On 6/5/20 4:56 PM, Markus Armbruster wrote:
> qdev_prop_set_netdev() fails when the property already has a non-null
> value. Seems to go back to commit 30c367ed44
> "qdev-properties-system.c: Allow vlan or netdev for -device, not
> both", v1.7.0. Board code doesn't expect failure, and crashes:
>
Public bug reported:
I have been doing some work cross compiling qemu for Windows using a
minimal Fedora container. Recently I started hitting some timeouts on
the CI service and noticed a build of all targets was going over 1 hour.
It seems like the 'cmp' utility from diffutils is used
** Changed in: qemu
Status: New => In Progress
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https://bugs.launchpad.net/bugs/1881004
Title:
fpu/softfloat.c: error: bitwise negation of a boolean expression
Status in QEMU:
Hi Aleksandar, Yoshinori, Aurelien.
On 6/1/20 12:34 PM, Aleksandar Markovic wrote:
> On Mon, Jun 1, 2020 at 12:23 PM Philippe Mathieu-Daudé
> wrote:
>>
>> +Peter +Markus as neutral and experienced contributors.
>>
>> On 6/1/20 11:56 AM, Aleksandar Markovic wrote:
>>> On Mon, Jun 1, 2020 at
On Tue, May 26, 2020 at 09:40:27PM +0100, David CARLIER wrote:
> From b24a6702beb2a4e2a9c1c03b69c6d1dd07d4cf08 Mon Sep 17 00:00:00 2001
> From: David Carlier
> Date: Tue, 26 May 2020 21:35:27 +0100
> Subject: [PATCH] util/oslib: current process full path resolution on MacOS
>
> Using existing
Emilio G. Cota writes:
> On Tue, Jun 02, 2020 at 16:46:22 +0100, Alex Bennée wrote:
>> This may well end up being anonymous but it should always be unique.
>>
>> Signed-off-by: Alex Bennée
>> ---
>> include/qemu/qemu-plugin.h | 5 +
>> plugins/api.c | 18 ++
On Jun 5 11:10, Andrzej Jakowski wrote:
> So far it was not possible to have CMB and PMR emulated on the same
> device, because BAR2 was used exclusively either of PMR or CMB. This
> patch places CMB at BAR4 offset so it not conflicts with MSI-X vectors.
>
Hi Andrzej,
Thanks for doing this,
On 6/6/20 11:03 AM, Erik Smit wrote:
> The hardware supports configurable descriptor sizes, configured in the DBLAC
> register.
>
> Most drivers use the default 4 word descriptor, which is currently hardcoded,
> but Aspeed SDK configures 8 words to store extra data.
>
> ---
> The implementation
Markus Armbruster writes:
> Peter Maydell writes:
>
>> On Fri, 29 May 2020 at 17:23, Christophe de Dinechin
>> wrote:
>>> On 2020-05-26 at 20:51 CEST, Eric Blake wrote...
>>> > diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
>>> > index d08ce6181199..95011a8015b4 100644
** Changed in: qemu
Status: New => Confirmed
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https://bugs.launchpad.net/bugs/1874073
Title:
openrisc_sim.c:87:42: error: 'cpu_irqs[0]' may be used uninitialized
in this
On Mon, 8 Jun 2020 03:46:09 +0800
Zhang Chen wrote:
> From: Zhang Chen
>
> No need to reuse MIGRATION_STATUS_ACTIVE boot COLO.
>
> Signed-off-by: Zhang Chen
> Reviewed-by: zhanghailiang
> ---
Looks good and works well in my tests.
Reviewed-by: Lukas Straub
Tested-by: Lukas Straub
** Changed in: qemu
Status: New => Opinion
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https://bugs.launchpad.net/bugs/1879672
Title:
QEMU installer with WHPX support
Status in QEMU:
Opinion
Bug description:
cmp is used in the makefiles.
And there is some kind of warning during build if it is missing:
/bin/sh: cmp: command not found
But perhaps it should abort the build in this case.
Something like that helps:
diff --git a/Makefile b/Makefile
index 40e4f7677bde..05e029bd99db 100644
--- a/Makefile
On 6/8/20 6:45 AM, Markus Armbruster wrote:
> Philippe Mathieu-Daudé writes:
>
>> On 2/28/20 6:32 PM, Markus Armbruster wrote:
[...]
>>> warn_reportf_err() is a convenience function to error_prepend(),
>>> warn_report() and free @local_err.
> [...]
>> Why warn_reportf_err() doesn't take a 'Error
Hi Aurelien,
On 6/1/20 11:41 PM, Aurelien Jarno wrote:
> On 2020-06-01 11:20, Philippe Mathieu-Daudé wrote:
>> I don't have much clue about the Renesas hardware, but at least
>> I know now the source files a little bit, so I volunteer to pick
>> up patches and send pull-requests for them during
When compiling with GCC 10 (Fedora 32) using CFLAGS=-O2 we get:
CC or1k-softmmu/hw/openrisc/openrisc_sim.o
hw/openrisc/openrisc_sim.c: In function ‘openrisc_sim_init’:
hw/openrisc/openrisc_sim.c:87:42: error: ‘cpu_irqs[0]’ may be used
uninitialized in this function
On Fri, 5 Jun 2020 17:47:08 +0200
Auger Eric wrote:
> Hi Stefan,
>
> On 6/5/20 5:25 PM, Stefan Berger wrote:
> > On 6/5/20 5:35 AM, Auger Eric wrote:
> >> Hi Stefan,
> >>
> >> On 6/2/20 6:17 PM, Stefan Berger wrote:
> >>> On 6/2/20 12:13 PM, Auger Eric wrote:
> Hi Stefan,
>
>
On 6/8/20 8:03 AM, Markus Armbruster wrote:
> Markus Armbruster writes:
>
>> Peter Maydell writes:
>>
>>> On Fri, 29 May 2020 at 17:23, Christophe de Dinechin
>>> wrote:
On 2020-05-26 at 20:51 CEST, Eric Blake wrote...
> diff --git a/hw/openrisc/openrisc_sim.c
On 6/8/20 5:45 AM, Emilio G. Cota wrote:
> On Tue, Jun 02, 2020 at 16:46:22 +0100, Alex Bennée wrote:
>> This may well end up being anonymous but it should always be unique.
>>
>> Signed-off-by: Alex Bennée
>> ---
>> include/qemu/qemu-plugin.h | 5 +
>> plugins/api.c | 18
On 08/06/2020 09.14, Philippe Mathieu-Daudé wrote:
> When compiling with GCC 10 (Fedora 32) using CFLAGS=-O2 we get:
>
> CC or1k-softmmu/hw/openrisc/openrisc_sim.o
> hw/openrisc/openrisc_sim.c: In function ‘openrisc_sim_init’:
> hw/openrisc/openrisc_sim.c:87:42: error: ‘cpu_irqs[0]’
On Mon, 8 Jun 2020 03:46:11 +0800
Zhang Chen wrote:
> From: Zhang Chen
>
> MIGRATION_STATUS_ACTIVE is invalid here, handle it by default case.
>
> Suggested-by: Lukas Straub
> Signed-off-by: Zhang Chen
> ---
Looks good and works well in my tests.
Reviewed-by: Lukas Straub
Tested-by:
Some bits of the CCM registers are non writable.
This was left undone in the initial commit (all bits of registers were
writable).
This patch adds the required code to protect the non writable bits.
Signed-off-by: Jean-Christophe Dubois
---
v2: simplify code after feedback on the first
On 5/28/20 1:04 PM, Markus Armbruster wrote:
> sm501_init() and ati_vga_realize() create an "i2c-ddc" device, but
> neglect to realize it. Affects machines sam460ex, shix, r2d, and
> fulong2e.
>
> In theory, a device becomes real only on realize. In practice, the
> transition from unreal to
From: Bin Meng
There is no need to retrieve all PLIC IRQ information in order to
just connect the GEM IRQ. Use qdev_get_gpio_in() directly like
what is done for other peripherals.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
From: Bin Meng
This was done in the virt & sifive_u codes, but sifive_e codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_e.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git
From: Bin Meng
This was done in the virt & sifive_u codes, but opentitan codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.
Signed-off-by: Bin Meng
---
hw/riscv/opentitan.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
From: Bin Meng
This series updates the 'sifive_u' machine support:
- Add GPIO controller support
- Support reboot functionality via GPIO pin#10
- Change SiFive E/U series CPU reset vector to 0x1004
- Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new
"msel" machine property
- Add a
On 6/5/20 5:26 AM, Kevin Wolf wrote:
> Am 04.06.2020 um 22:22 hat John Snow geschrieben:
>> Based-on: 20200604195252.20739-1-js...@redhat.com
>>
>> This series is extracted from my larger series that attempted to bundle
>> our python module as an installable module. These fixes don't require
The 06/05/2020 13:26, Richard Henderson wrote:
> That assert is just wrong -- it's attempting to sanity check a virtual address
> against a property associated with the physical address, and even doing that
> incorrectly.
>
> I've pushed a fixup to the branch to remove it, and I'll look into
The memory region is limited to 1 KiB, so the address is
garantied to be in that range. No need to mask.
711 static const MemoryRegionOps open_eth_desc_ops = {
712 .read = open_eth_desc_read,
713 .write = open_eth_desc_write,
714 };
...
725 memory_region_init_io(>desc_io,
lo_setattr() invokes fchmod() in a rarely used code path, so it should
be whitelisted or virtiofsd will crash with EBADSYS.
Said code path can be triggered for example as follows:
On the host, in the shared directory, create a file with the sticky bit
set and a security.capability xattr:
(1) #
Note that you can start QEMU with the "-S" flag which means CPUS are
paused. This gives you ability to run the "set_link" monitor command
above, and then run "cont" to actually start the VM. Less convenient
that a CLI flag, but functionally it is eqivalent.
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On Sun, Jun 07, 2020 at 08:53:52AM +0200, Thomas Huth wrote:
> Hi David,
>
> could you maybe take this through your ppc tree?
Sounds reasonable, but this version doesn't seem to apply any more.
>
> Thanks,
> Thomas
>
>
> On 01/06/2020 13.28, Claudio Fontana wrote:
> > Hello all,
> >
> >
08.06.2020 12:21, Kevin Wolf wrote:
Am 06.06.2020 um 08:55 hat Vladimir Sementsov-Ogievskiy geschrieben:
05.06.2020 13:59, Peter Krempa wrote:
On Fri, Jun 05, 2020 at 12:07:47 +0200, Kevin Wolf wrote:
Am 05.06.2020 um 11:58 hat Peter Krempa geschrieben:
On Fri, Jun 05, 2020 at 11:44:07
On Fri, 5 Jun 2020 18:47:58 +0200
Greg Kurz wrote:
> On Fri, 5 Jun 2020 12:03:21 -0400
> Igor Mammedov wrote:
>
> > Deprecation period is run out and it's a time to flip the switch
> > introduced by cd5ff8333a. Disable legacy option for new machine
> > types (since 5.1) and amend
Philippe Mathieu-Daudé writes:
> Expose the CONFIG_TCG selector to let minikconf.py uses it.
>
> When building with --disable-tcg build, this helps to deselect
> devices that are TCG-dependent.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex
Philippe Mathieu-Daudé writes:
> Having one entry per line helps reviews/refactors. As we are
> going to modify the MINIKCONF variables, split them now to
> ease further review.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
--
Alex
On Sun, May 24, 2020 at 10:21 PM Philippe Mathieu-Daudé wrote:
>
> On 5/24/20 9:37 PM, Aleksandar Markovic wrote:
> > нед, 24. мај 2020. у 18:58 Philippe Mathieu-Daudé
> > је написао/ла:
> >>
> >> ping?
> >>
> >
> > I agree with all of your patches, they absolutely make sense to me,
> > but I
On 27/05/2020 09:47, Markus Armbruster wrote:
> Extracted from my '[PATCH not-for-merge 0/5] Instrumentation for
> "Fixes around device realization"' on reviewer's advice.
>
> Markus Armbruster (2):
> qom: Constify object_get_canonical_path{,_component}()'s parameter
> qom: Make "info
On Mon, 8 Jun 2020 at 12:40, Leif Lindholm wrote:
>
> Some basic options will be set by all aarch64 platforms.
> Break those out into a separate aarch64_cpu_common_init function, which
> also takes implementer, partnum, variant, and revision as arguments to
> set up MIDR.
>
> Invoke this to
On Sat, 6 Jun 2020 at 14:19, Laurent Vivier wrote:
>
> The following changes since commit ddc760832fa8cf5e93b9d9e6e854a5114ac63510:
>
> Merge remote-tracking branch 'remotes/gkurz/tags/9p-next-2020-05-26' into s=
> taging (2020-05-26 14:05:53 +0100)
>
> are available in the Git repository at:
>
Hi Richard,
I am doing bfloat16 support on QEMU.
Once I tried to reuse float32 interface, but I couldn't properly process
rounding in some insns like fadd.
What's your opinion about it? Should I expand the fpu/softfloat?
Best Regards,
Zhiwei
Robert Foley writes:
> From: Lingfeng Yang
>
> We tried running QEMU under tsan in 2016, but tsan's lack of support for
> longjmp-based fibers was a blocker:
> https://groups.google.com/forum/#!topic/thread-sanitizer/se0YuzfWazw
>
> Fortunately, thread sanitizer gained fiber support in
> From: Igor Mammedov [mailto:imamm...@redhat.com]
> Sent: Monday, June 8, 2020 1:00 PM
>
> On Fri, 5 Jun 2020 16:38:37 +
> Salil Mehta wrote:
>
> > > From: Igor Mammedov [mailto:imamm...@redhat.com]
> > > Sent: Friday, June 5, 2020 4:31 PM
> > > To: Andrew Jones
> > > Cc: Salil Mehta ;
On 5/28/20 1:04 PM, Markus Armbruster wrote:
> pxa2xx_mmci_init() creates a "pxa2xx-mmci" device, but neglects to
> realize it. Affects machines akita, borzoi, connex, mainstone, spitz,
> terrier, tosa, verdex, and z2.
>
> In theory, a device becomes real only on realize. In practice, the
>
On 5/28/20 1:04 PM, Markus Armbruster wrote:
> macio_oldworld_init() creates a "macio-nvram", sysbus device, but
> neglects to but it on a bus.
>
> Put it on the macio bus. Affects machine g3beige. Visible in "info
> qtree":
>
> bus: macio.0
>type macio-bus
>
On 5/28/20 1:04 PM, Markus Armbruster wrote:
> cuda_init() creates a "mos6522-cuda" device, but it's never realized.
> Affects machines mac99 with via=cuda (default) and g3beige.
>
> pmu_init() creates a "mos6522-pmu" device, but it's never realized.
> Affects machine mac99 with via=pmu and
From: Bin Meng
The HiFive Unleashed board wires GPIO pin#10 to the input of the
system reset signal. Let's set up the GPIO pin#10 and insert a
"gpio-restart" device tree node so that reboot is now functional
with QEMU 'sifive_u' machine.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 24
> Am 08.06.2020 um 16:16 schrieb Paolo Bonzini :
>
> On 08/06/20 16:06, David Hildenbrand wrote:
>> {
>> .name = "qom-set",
>> -.args_type = "path:s,property:s,value:S",
>> -.params = "path property value",
>> -.help = "set QOM property",
From: Bin Meng
Add a new property to represent the number of GPIO pins supported
by the GPIO controller.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_gpio.c | 30 +++---
include/hw/riscv/sifive_gpio.h | 3 +++
2 files changed, 22 insertions(+), 11 deletions(-)
From: Bin Meng
At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_gpio.c | 4 +++-
1 file changed, 3
On Thu, 28 May 2020 at 12:04, Markus Armbruster wrote:
>
> These devices are optional, and enabled by property "enable-bitband".
> armv7m_instance_init() creates them unconditionally, because the
> property has not been set then. armv7m_realize() realizes them only
> when the property is true.
On 5/28/20 1:04 PM, Markus Armbruster wrote:
> Commit 260bc9d8aa "hw/sd/sd.c: QOMify" QOMified only the device
> itself, not its users. It kept sd_init() around for non-QOMified
> users.
>
> More than four years later, three such users remain: omap1 (machines
> cheetah, sx1, sx1-v1) and omap2
David Gibson writes:
> On Fri, Jun 05, 2020 at 05:01:07PM -0300, Thiago Jung Bauermann wrote:
>>
>> Paolo Bonzini writes:
>>
>> > On 05/06/20 01:30, Thiago Jung Bauermann wrote:
>> >> Paolo Bonzini writes:
>> >>> On 04/06/20 23:54, Thiago Jung Bauermann wrote:
>> QEMU could always
On 6/8/20 11:27 AM, Wang, Wenchao wrote:
> Hi, Philippe,
>
> Sorry for missing your mail.
>
> We are still maintaining HAX accelerator in QEMU. The status had been added
> as below in MAINTAINERS line 458. I noticed that the only difference with
> your commit is the last third line. The file
Am 08.06.2020 um 17:19 hat John Snow geschrieben:
>
>
> On 6/5/20 5:26 AM, Kevin Wolf wrote:
> > Am 04.06.2020 um 22:22 hat John Snow geschrieben:
> >> Based-on: 20200604195252.20739-1-js...@redhat.com
> >>
> >> This series is extracted from my larger series that attempted to bundle
> >> our
Robert Foley writes:
> Disable a few tests under CONFIG_TSAN, which
> run into a known TSan issue that results in a hang.
> https://github.com/google/sanitizers/issues/1116
>
> The disabled tests under TSan include all the qtests as well as
> the test-char, test-qga, and
When built with --enable-qdev-deprecation-warning, calling
qdev_warn_deprecated_function_used() will emit a warning such:
$ qemu-system-arm -M verdex ...
qemu-system-arm: warning: use of deprecated non-qdev/non-qom code in
pxa2xx_lcdc_init()
qemu-system-arm: warning: use of deprecated
Based on today's IRC chat, this is a trivial RFC series
to anotate pre-qdev/QOM devices so developers using them
without knowing they are not QOM'ified yet can realize
it and convert them if they have time.
qdev/QOM devices are introspectable, so easier to test
or even fuzz.
Philippe
On Fri, May 15, 2020 at 05:04:05PM +0200, Gerd Hoffmann wrote:
> First batch of microvm patches, some generic acpi stuff.
> Split the acpi-build.c monster, specifically split the
> pc and q35 and pci bits into a separate file which we
> can skip building at some point in the future.
>
> v2
On Mon, Jun 08, 2020 at 03:22:45PM +0200, Gerd Hoffmann wrote:
> On Fri, May 15, 2020 at 05:04:05PM +0200, Gerd Hoffmann wrote:
> > First batch of microvm patches, some generic acpi stuff.
> > Split the acpi-build.c monster, specifically split the
> > pc and q35 and pci bits into a separate file
On Fri, May 29, 2020 at 09:39:53AM +0200, Gerd Hoffmann wrote:
> With more microvm memory config tweaks split this into its owns series,
> the microvm acpi patch series is already big enough ...
>
> v2:
> - use 3G split.
> - add patch to move virtio-mmio region.
> - pick up acks & reviews.
>
On Fri, May 29, 2020 at 09:39:57AM +0200, Gerd Hoffmann wrote:
> Place virtio-mmio devices near the other mmio regions,
> next ioapic is at @ 0xfec0.
>
> Signed-off-by: Gerd Hoffmann
> ---
> include/hw/i386/microvm.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
Commit 7d2ef6dcc1cf ("hmp: Simplify qom-set") switched to the json
parser, making it possible to specify complex types. However, with this
change it is no longer possible to specify proper sizes (e.g., 2G, 128M),
turning the interface harder to use for properties that consume sizes.
Let's switch
On 6/6/20 1:53 AM, Vladimir Sementsov-Ogievskiy wrote:
> For patches 05-07:
>
> Reviewing such patch is a strange thing: Pipfile changes are obvious
> enough, just select some version (I can't be sure about correct version
> choice, just believe in your commit messages). But what for
>
From: Bin Meng
On SiFive FU540 SoC, the value stored at physical address 0x1000
stores the MSEL pin state that is used to control the next boot
location that ROM codes jump to.
Add a new property msel to sifive_u machine for this.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 7
On Mon, 8 Jun 2020 08:03:44 -0400
Igor Mammedov wrote:
> Deprecation period is run out and it's a time to flip the switch
> introduced by cd5ff8333a. Disable legacy option for new machine
> types (since 5.1) and amend documentation.
>
> '-numa node,memdev' shall be used instead of disabled
On 6/8/20 2:14 AM, Philippe Mathieu-Daudé wrote:
When compiling with GCC 10 (Fedora 32) using CFLAGS=-O2 we get:
In the subject: s/silent/silence/
CC or1k-softmmu/hw/openrisc/openrisc_sim.o
hw/openrisc/openrisc_sim.c: In function ‘openrisc_sim_init’:
On 6/8/20 4:15 AM, Markus Armbruster wrote:
Yes: openrisc_sim_machine_init() sets mc->max_cpus = 2.
My suggestion of adding an assert() is essentially telling the
compiler that indeed smp_cpus must always be in the range [1,2],
which we can tell but it can't.
Do we have a proper patch for
On 6/8/20 7:03 AM, Igor Mammedov wrote:
Deprecation period is run out and it's a time to flip the switch
introduced by cd5ff8333a. Disable legacy option for new machine
types (since 5.1) and amend documentation.
'-numa node,memdev' shall be used instead of disabled option
with new machine
Am 08.06.2020 um 12:00 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 08.06.2020 12:21, Kevin Wolf wrote:
> > Am 06.06.2020 um 08:55 hat Vladimir Sementsov-Ogievskiy geschrieben:
> > > Allowing to use one target for several populating job is an
> > > interesting idea. Current series does
> > >
On Fri, May 29, 2020 at 09:39:53AM +0200, Gerd Hoffmann wrote:
> With more microvm memory config tweaks split this into its owns series,
> the microvm acpi patch series is already big enough ...
Looks sane:
Acked-by: Michael S. Tsirkin
microvm things so should use that tree ...
> v2:
> - use
On 5/28/20 1:04 PM, Markus Armbruster wrote:
> These devices are optional, and enabled by property "enable-bitband".
> armv7m_instance_init() creates them unconditionally, because the
> property has not been set then. armv7m_realize() realizes them only
> when the property is true. Works,
On 5/28/20 1:04 PM, Markus Armbruster wrote:
> xlnx_dp_init() creates these two devices, but they're never realized.
> Affects machine xlnx-zcu102.
>
> In theory, a device becomes real only on realize. In practice, the
> transition from unreal to real is a fuzzy one. The work to make a
> device
On 08/06/20 16:06, David Hildenbrand wrote:
> {
> .name = "qom-set",
> -.args_type = "path:s,property:s,value:S",
> -.params = "path property value",
> -.help = "set QOM property",
> +.args_type = "json:-j,path:s,property:s,value:s",
From: Bin Meng
Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_e.c | 8 +---
hw/riscv/sifive_u.c | 6 +++---
target/riscv/cpu.c | 4 ++--
3 files changed, 10 insertions(+), 8
From: Bin Meng
SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines.
This hooks the exsiting SiFive GPIO model to the SoC, and adds its
device tree data as well.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 44 ++--
From: Bin Meng
Move the flash and DRAM to the end of the SoC memmap table.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f64aa52..c94ff6f 100644
--- a/hw/riscv/sifive_u.c
On Thu, 28 May 2020 at 12:13, Markus Armbruster wrote:
>
> cuda_init() creates a "mos6522-cuda" device, but it's never realized.
> Affects machines mac99 with via=cuda (default) and g3beige.
>
> pmu_init() creates a "mos6522-pmu" device, but it's never realized.
> Affects machine mac99 with
Robert Foley writes:
> From: "Emilio G. Cota"
>
> Signed-off-by: Emilio G. Cota
> Signed-off-by: Robert Foley
> [RF: Minor changes to fix some checkpatch errors]
> ---
> accel/tcg/translate-all.c | 10 +-
> include/tcg/tcg.h | 3 ++-
> tcg/tcg.c | 19
Robert Foley writes:
> From: "Emilio G. Cota"
>
> The radix tree is append-only, but we can fail to insert
> a PageDesc if the insertion races with another thread.
>
> Signed-off-by: Emilio G. Cota
> Signed-off-by: Robert Foley
> ---
> accel/tcg/translate-all.c | 9 +
> 1 file
Robert Foley writes:
> Adds TSan details to testing.rst.
> This includes background and reference details on TSan,
> and details on how to build and test with TSan
> both with and without docker.
>
> Signed-off-by: Robert Foley
> Reviewed-by: Emilio G. Cota
Yay docs \o/
Reviewed-by: Alex
On Mon, 8 Jun 2020 08:55:08 -0400
"Michael S. Tsirkin" wrote:
> On Mon, Jun 08, 2020 at 08:03:44AM -0400, Igor Mammedov wrote:
> > Deprecation period is run out and it's a time to flip the switch
> > introduced by cd5ff8333a. Disable legacy option for new machine
> > types (since 5.1) and amend
On 5/26/20 11:50 AM, Philippe Mathieu-Daudé wrote:
> On 5/25/20 1:02 PM, Fred Konrad wrote:
>> Sorry Philippe I missed that.
>>
>> Would be happy to do a PR if needed but:
>> * I never did that.
>> * Looking at https://wiki.qemu.org/Contribute/SubmitAPullRequest, I
>> don't have
>> the
It's been almost 2 weeks since I submitted this. Just thought I would
follow up and see if there is any ETA on when this might be applied,
or if I missed the need to fix something and resubmit.
Thanks.
- Alex
On Tue, May 26, 2020 at 9:13 PM Alexander Duyck
wrote:
>
> This series provides an
* Max Reitz (mre...@redhat.com) wrote:
> lo_setattr() invokes fchmod() in a rarely used code path, so it should
> be whitelisted or virtiofsd will crash with EBADSYS.
>
> Said code path can be triggered for example as follows:
>
> On the host, in the shared directory, create a file with the
Thomas Huth writes:
> On 05/06/2020 17.49, Alex Bennée wrote:
>> Hi,
>>
>> These are all the patches I've currently got which are ready for a
>> pull request next week. I've included some patches which are destined
>> to go in via other trees so I can keep the testing green on the CI.
>>
>>
пон, 8. јун 2020. у 15:05 Peter Maydell је
написао/ла:
>
> On Sun, 7 Jun 2020 at 20:46, Aleksandar Markovic
> wrote:
> >
> > The following changes since commit 175198ad91d8bac540159705873b4ffe4fb94eab:
> >
> > Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200605' into
> > staging
Robert Foley writes:
> Added a new docker for ubuntu 20.04.
> This docker has support for Thread Sanitizer
> including one patch we need in one of the header files.
> https://github.com/llvm/llvm-project/commit/a72dc86cd
>
> This command will build with tsan enabled:
> make
From: Bin Meng
Do various minor clean-ups to the exisiting codes for:
- coding convention conformance
- remove unnecessary blank lines
- spell SiFive correctly
Signed-off-by: Bin Meng
---
hw/riscv/sifive_gpio.c | 13 +
include/hw/riscv/sifive_gpio.h | 7 ---
2 files
From: Bin Meng
Upstream U-Boot v2020.07 codes switch to access SiFive FU540 OTP
based on device tree information. Let's generate the device tree
node for OTP.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/riscv/sifive_u.c
From: Bin Meng
In prepration to add more properties to this machine, rename the
existing serial property get/set functions to a generic name.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/sifive_u.c
From: Bin Meng
It is enough to simply map the SiFive FU540 DDR memory controller
into the MMIO space using create_unimplemented_device(), to make
the upstream U-Boot v2020.07 DDR memory initialization codes happy.
Note we do not generate device tree fragment for the DDR memory
controller. Since
From: Bin Meng
SiFive FU540 SoC supports booting from several sources, which are
controlled using the Mode Select (MSEL[3:0]) pins on the chip.
Typically, the boot process runs through several stages before it
begins execution of user-provided programs.
The SoC supports booting from
On Thu, Jun 4, 2020 at 7:34 PM Michael S. Tsirkin wrote:
>
> On Thu, Jun 04, 2020 at 12:39:34PM +0200, Eugenio Perez Martin wrote:
> > > +static int vhost_vdpa_set_config(struct vhost_dev *dev, const uint8_t
> > > *data,
> > > + uint32_t offset, uint32_t size,
>
Robert Foley writes:
> These annotations will allow us to give tsan
> additional hints. For example, we can inform
> tsan about reads/writes to ignore to silence certain
> classes of warnings.
> We can also annotate threads so that the proper thread
> naming shows up in tsan warning results.
On 6/6/20 2:03 AM, Vladimir Sementsov-Ogievskiy wrote:
05.06.2020 23:14, Eric Blake wrote:
On 6/4/20 12:41 PM, Vladimir Sementsov-Ogievskiy wrote:
We are going to enhance qcow2 format parsing by adding more structure
classes. Let's split format parsing from utility code.
Signed-off-by:
On 6/6/20 5:50 AM, marshell wrote:
Public bug reported:
I have configured 2 ide disks with name starting with hd, but when the
vm boots up, it shows disks whose name starting with sd.
This looks more like a libvirt question than a qemu one.
1. ide disks in vm xml:
Robert Foley writes:
> v1: https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg08302.html
>
> Changes in v2:
> - Fixed make check under TSan. With the below fixes, make check
> under TSan completes successfully, albeit with TSan warnings.
> - We found that several unit tests and the
LIU Zhiwei writes:
> Hi Richard,
>
> I am doing bfloat16 support on QEMU.
>
> Once I tried to reuse float32 interface, but I couldn't properly process
> rounding in some insns like fadd.
What do you mean by re-use the float32 interface? Isn't bfloat16 going
to be pretty much the same as
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