Your pipeline has failed.
Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )
Commit: d0c8b957 (
https://gitlab.com/qemu-project/qemu/-/commit/d0c8b957ae648f67e3ccb5a14e1edc4ae0bea5db
)
Commit Message: Merge remote-tr
When all we do with an Error we receive into a local variable is
propagating to somewhere else, we can just as well receive it there
right away. The previous commit did that with a Coccinelle script I
consider fairly trustworthy. This commit uses the same script with
the matching of return taken
On 7/2/20 10:49 AM, Markus Armbruster wrote:
The previous commit enables conversion of
foo(..., &err);
if (err) {
...
}
to
if (!foo(..., &err)) {
...
}
for QemuOpts functions that now return true / false on success /
error. Coccinelle script:
On 7/2/20 10:49 AM, Markus Armbruster wrote:
When creating an image fails because the format doesn't support option
"backing_file" or "backing_fmt", bdrv_img_create() first has
qemu_opt_set() put a generic error into @local_err, then puts the real
error into @errp with error_setg(), and then prop
On Thu, 2 Jul 2020 at 12:18, Markus Armbruster wrote:
>
> The following changes since commit fc1bff958998910ec8d25db86cd2f53ff125f7ab:
>
> hw/misc/pca9552: Add missing TypeInfo::class_size field (2020-06-29
> 21:16:10 +0100)
>
> are available in the Git repository at:
>
> git://repo.or.cz/qem
On 7/2/20 10:49 AM, Markus Armbruster wrote:
Convert
foo(..., &err);
if (err) {
...
}
to
if (!foo(..., &err)) {
...
}
for qdev_realize(), qdev_realize_and_unref(), qbus_realize() and their
wrappers isa_realize_and_unref(), pci_realize_and_unref(),
sy
Patchew URL: https://patchew.org/QEMU/20200702152710.84602-1-laur...@vivier.eu/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!
From: Jessica Clarke
Claiming an interrupt and changing the source priority both potentially
affect whether an interrupt is pending, thus we must re-compute xEIP.
Note that we don't put the sifive_plic_update inside sifive_plic_claim
so that the logging of a claim (and the resulting IRQ) happens
l-riscv-to-apply-20200702-1
for you to fetch changes up to 6bf91617f47c74efc99ef48236765d9677c0898e:
target/riscv: configure and turn on vector extension from command line
(2020-07-02 09:19:34 -0700)
This PR contains two patches to im
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-20-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode
From: Jessica Clarke
The source priorities can be used to order sources with respect to other
sources, not just as a way to enable/disable them based off a threshold.
We must therefore always claim the highest-priority source, rather than
the first source we find.
Signed-off-by: Jessica Clarke
From: LIU Zhiwei
The internals.h keeps things that are not relevant to the actual architecture,
only to the implementation, separate.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-6-zhiwei_...@c-sky.com>
Signed-off-by:
Commit 5d971f9e672507210e77d020d89e0e89165c8fc9
"memory: Revert "memory: accept mismatching sizes in
memory_region_access_valid"" broke most RISC-V boards as they do 64 bit
accesses to the CLINT and QEMU would trigger a fault. Fix this failure
by allowing 8 byte accesses.
Signed-off-by: Alistair F
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-12-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 49 +++
target/riscv/insn32.decode
From: LIU Zhiwei
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in me
From: LIU Zhiwei
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Re
From: LIU Zhiwei
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Franc
From: LIU Zhiwei
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-3-
From: LIU Zhiwei
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-4-zhiwei_.
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-19-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 33 +
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-16-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 13
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-11-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 25 ++
target/riscv/insn32.decode | 1
From: LIU Zhiwei
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-14-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 25
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-27-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-15-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 25
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-26-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 17
target/riscv/insn32.decode |
From: LIU Zhiwei
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
Reviewed
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-30-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-13-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-17-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 57 +++
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-45-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-32-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode |
From: LIU Zhiwei
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Fra
Patchew URL: https://patchew.org/QEMU/20200702152710.84602-1-laur...@vivier.eu/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PULL v2 00/12] Linux user for 5.1 patches
Type: series
Message-id: 20200702152710.84602-1-laur...@vivier.eu
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-51-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/tran
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-38-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 13
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-22-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-18-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 33
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-46-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-52-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/tran
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-24-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 17
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-21-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-23-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 22
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-48-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 10 +++
target/riscv/insn32.decode
Patchew URL:
https://patchew.org/QEMU/20200702160915.9517-1-filip.boz...@syrmia.com/
Hi,
This series failed build test on FreeBSD host. Please find the details below.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-25-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 1
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-34-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-55-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-28-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-29-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 17
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-57-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/internals.h| 6 +++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/tra
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-39-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 19 ++
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-31-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 16
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-37-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-40-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 37 +
target/riscv/insn32.decode |
Patchew URL:
https://patchew.org/QEMU/20200702155000.3455325-1-arm...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ==
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-41-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 4 ++
target/riscv/internals.h| 5
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-33-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 16
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-35-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 49 +
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-49-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 2
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-50-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 8 +
target/riscv/insn_tr
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-36-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode |
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-56-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 116
2 fi
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-42-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 2
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-59-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans
Le 26/06/2020 à 23:39, Filip Bozuta a écrit :
> This patch implements strace argument printing functionality for following
> syscalls:
>
> * truncate, ftruncate - truncate a file to a specified length
>
> int truncate(const char *path, off_t length)
> int ftruncate(int fd, of
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-44-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode |
On 7/2/20 10:49 AM, Markus Armbruster wrote:
See recent commit "error: Document Error API usage rules" for
rationale.
Signed-off-by: Markus Armbruster
---
Reviewed-by: Eric Blake
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3226
Virtualization: qemu.org | l
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-43-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 13 ++
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200701152549.1218-47-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 7 +++
target/riscv/insn32.decode
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-53-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/tra
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-54-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/t
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-58-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 49 +
2 fi
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-61-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 5
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/tr
Your pipeline has failed.
Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )
Commit: 64f0ad8a (
https://gitlab.com/qemu-project/qemu/-/commit/64f0ad8ad8e13257e7c912df470d46784b55c3fd
)
Commit Message: Merge remote-tr
From: LIU Zhiwei
Vector extension is default off. The only way to use vector extension is
1. use cpu rv32 or rv64
2. turn on it by command line
"-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1".
vlen is the vector register length, default value is 128 bit.
elen is the max operator size i
On 6/26/20 1:59 PM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/insn_trans/trans_rvd.inc.c | 8
> target/riscv/insn_trans/trans_rvf.inc.c | 8
> 2 files changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson
r~
On 6/26/20 1:59 PM, LIU Zhiwei wrote:
> An n-bit foating-point result is written to the n least-significant bits
> of the destination f register, with all 1s written to the uppermost
> FLEN - n bits to yield a legal NaN-boxed value
>
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/insn_trans/tr
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Message-Id: <20200701152549.1218-60-zhiwei_...@c-sky.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 3 +
target/riscv/insn_trans/tra
Le 26/06/2020 à 23:39, Filip Bozuta a écrit :
> This patch implements strace argument printing functionality for following
> syscalls:
>
> * mlock, munlock, mlockall, munlockall - lock and unlock memory
>
>int mlock(const void *addr, size_t len)
>int munlock(const void *addr,
Public bug reported:
QEMU Commit fc1bff958998910ec8d25db86cd2f53ff125f7ab
RISC-V PMP implementation is not correct on QEMU.
When an access is granted there is no more PMP check on the 4KB memory range of
the accessed location.
A cache flush is needed in order to force a PMP check on next acces
On Fri, Jun 26, 2020 at 6:15 AM Bin Meng wrote:
>
> List me as the maintainer for OpenSBI firmware related files.
>
> Signed-off-by: Bin Meng
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> MAINTAINERS | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MA
Patchew URL:
https://patchew.org/QEMU/20200702155000.3455325-1-arm...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v2 00/44] Less clumsy error checking
Type: series
Message-id: 20200702155000.3455325-1-arm...@redh
On 2020-07-02 11:53, Dr. David Alan Gilbert wrote:
* Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
From: Tobin Feldman-Fitzthum
AMD SEV allows a guest owner to inject a secret blob
into the memory of a virtual machine. The secret is
encrypted with the SEV Transport Encryption Key an
On Donnerstag, 2. Juli 2020 17:35:00 CEST Greg Kurz wrote:
> > > It isn't readdir only, most requests span over multiple v9fs_co_*()
> > > calls...>
> > Right, I know! And that's actually my root motivation to finally bring
> > this
> > patch set forward, since I am very aware that this patch set
Hi,
I noticed the [PULL V2 02/33] virtio-net: implement RX RSS processing
https://marc.info/?l=qemu-devel&m=159248675403246&w=2 and cloned
https://github.com/jasowang/qemu.git tags/net-pull-request for testing the
RX RSS feature, but I am not clear how to test this feature and see if it
mee
On 6/26/20 1:59 PM, LIU Zhiwei wrote:
> As this function will be used by fcvt.d.s in trans_rvd.inc.c,
> make it a visible function for RVF and RVD.
>
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/insn_trans/trans_rvf.inc.c | 14 --
> target/riscv/translate.c| 14 ++
Patchew URL:
https://patchew.org/QEMU/20200702162354.928528-1-alistair.fran...@wdc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PULL v2 00/64] riscv-to-apply queue
Type: series
Message-id: 20200702162354.928528-1-alistair.fran
On 7/2/20 10:49 AM, Markus Armbruster wrote:
The previous commit enables conversion of
visit_foo(..., &err);
if (err) {
...
}
to
if (!visit_foo(..., errp)) {
...
}
for visitor functions that now return true / false on success / error.
Coccinelle script
On 7/2/20 10:49 AM, Markus Armbruster wrote:
Pass &error_abort instead of NULL where the returned value is
dereferenced or asserted to be non-null. Drop a now redundant
assertion.
Signed-off-by: Markus Armbruster
---
hw/core/platform-bus.c | 6 +++---
Reviewed-by: Eric Blake
--
Eric Bl
On 7/2/20 10:49 AM, Markus Armbruster wrote:
The previous commit enables conversion of
foo(..., &err);
if (err) {
...
}
to
if (!foo(..., errp)) {
...
}
for QOM functions that now return true / false on success / error.
Coccinelle script:
@@
On 7/2/20 10:49 AM, Markus Armbruster wrote:
The previous commit enables conversion of
qdev_prop_set_drive_err(..., &err);
if (err) {
...
}
to
if (!qdev_prop_set_drive_err(..., errp)) {
...
}
Coccinelle script:
Reviewed-by: Eric Blake
--
Eric Blake, Prin
On 7/2/20 10:49 AM, Markus Armbruster wrote:
The previous commit used Coccinelle to convert from checking the Error
object to checking the return value. Convert a few more manually.
Signed-off-by: Markus Armbruster
---
hw/core/bus.c | 6 +-
hw/core/qdev.c | 7
On 02/07/2020 18.13, Michele Denber wrote:
On 07/02/20 10:39, Thomas Huth wrote:
Recent versions of Solaris (v11.4) now feature an openpty() function,
too, causing a build failure since we ship our own implementation of
openpty() for Solaris in util/qemu-openpty.c so far. Since there are
now b
On 6/26/20 1:59 PM, LIU Zhiwei wrote:
> Multiple precison shoule be supported by NaN-boxing. That means, we should
> flush not valid NaN-boxing input to canonical NaN before effective
> calculation and we should NaN-boxing the result after the effective
> calculation.
>
> In this patch set, split
Most of these developers have the Signed-off-by tag properly
written, but not the author/committer name. Fix this.
Also we incorrectly wrote Arei Gonglei name, update and reorder.
The committer name/email is displayed when using:
$ git log --format=fuller
(which can be set in git-config settin
Fix Andreas Färber name in the following commits:
$ git log --format=fuller --author='Andreas Faerber '
--oneline
165ceac095 qemu-timer: Move include for __FreeBSD_version to header
5d7ff5bbde TCG: Mac OS X support for ppc64 target
ea5ad306ba Suppress optionrom build on Solaris x86
Cc: F
Fix Arei Gonglei email address in the following commits:
$ git log --committer='' --oneline
ddcd55316f bootdevice: add Error **errp argument for QEMUBootSetHandler
3b08098b40 bootdevice: add validate check for qemu_boot_set()
f1839938b0 bootdevice: add Error **errp argument for qemu_boot_s
Update Alexander Graf email address to avoid emails bouncing.
Suggested-by: Alexander Graf
Signed-off-by: Philippe Mathieu-Daudé
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index 926cac6bb8..e46e6c7302 100644
--- a/.mailmap
+++ b/.mailmap
@@ -44,6 +44,7
301 - 400 of 559 matches
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