[PATCH v6 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev --- target/riscv/cpu.h | 19 +++ target/riscv/translate.c | 34 -- 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH] i386/cpu: Expose the PTWRITE to the guest

PTWRITE provides a mechanism by which software can instrument the Intel PT trace. The current implementation will mask off this feature when the PTWRITE is supported on the host because of the Intel PT CPUID is a constant value(ICX CPUID) in qemu. This patch will expose the PTWRITE feature to the

[PATCH v6 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/translate.c| 14 ++ 5

[PATCH v6 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db72f5cf59..1c00d9ea26 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -255,6 +255,31 @@ static void

[PATCH v6 0/6] RISC-V Pointer Masking implementation

Hi, Added missing sign-off on the first patch. Thanks Alexey Baturo (5): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode [RISCV_PM] Print new PM CSRs in QEMU logs [RISCV_PM] Support pointer masking

[PATCH v6 1/6] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..4e305249b3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -516,6 +516,7 @@ static Property

[PATCH v6 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 3 + target/riscv/cpu.h | 12 ++ target/riscv/cpu_bits.h | 66 ++ target/riscv/csr.c | 271 4 files changed, 352 insertions(+) diff --git a/target/riscv/cpu.c

Re: [PATCH v5 0/6] RISC-V Pointer Masking implementation

Patchew URL: https://patchew.org/QEMU/20201022074309.3210-1-space.monkey.deliv...@gmail.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20201022074309.3210-1-space.monkey.deliv...@gmail.com Subject: [PATCH v5 0/6]

Re: [PATCH v11 09/13] copy-on-read: skip non-guest reads if no copy needed

On 21.10.2020 23:43, Andrey Shinkevich wrote: On 14.10.2020 18:22, Vladimir Sementsov-Ogievskiy wrote: 14.10.2020 15:51, Max Reitz wrote: On 12.10.20 19:43, Andrey Shinkevich wrote: If the flag BDRV_REQ_PREFETCH was set, pass it further to the COR-driver to skip unneeded reading. It can be

Re: [PATCH] migration/block-dirty-bitmap: fix larger granularity bitmaps

On 10/21/20 5:17 PM, Vladimir Sementsov-Ogievskiy wrote: 21.10.2020 17:44, Stefan Reiter wrote: sectors_per_chunk is a 64 bit integer, but the calculation is done in 32 bits, leading to an overflow for coarse bitmap granularities. If that results in the value 0, it leads to a hang where no

[PATCH v5 0/6] RISC-V Pointer Masking implementation

Hi, Addressing Alistair comment: J-ext enabling patch is now the last one in the series. Thanks Alexey Baturo (5): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode [RISCV_PM] Print new PM CSRs in QEMU

Re: [PATCH v26 05/17] vfio: Add VM state change handler to know state of VM

On Wed, 21 Oct 2020 11:03:23 +0530 Kirti Wankhede wrote: > On 10/20/2020 4:21 PM, Cornelia Huck wrote: > > On Sun, 18 Oct 2020 01:54:56 +0530 > > Kirti Wankhede wrote: > > > >> On 9/29/2020 4:33 PM, Dr. David Alan Gilbert wrote: > >>> * Cornelia Huck (coh...@redhat.com) wrote: > On

[PATCH v4 2/2] hw/block/nvme: add the dataset management command

From: Klaus Jensen Add support for the Dataset Management command and the Deallocate attribute. Deallocation results in discards being sent to the underlying block device. Whether of not the blocks are actually deallocated is affected by the same factors as Write Zeroes (see previous commit).

[PATCH v5 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db72f5cf59..1c00d9ea26 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -255,6 +255,31 @@ static void

[PATCH v5 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev --- target/riscv/cpu.h | 19 +++ target/riscv/translate.c | 34 -- 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v5 6/6] [RISCV_PM] Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1c00d9ea26..56633c14eb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -465,6 +465,7 @@ static void riscv_cpu_realize(DeviceState

[PATCH v5 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/translate.c| 14 ++ 5

[PATCH v5 1/6] [RISCV_PM] Add J-extension into RISC-V

--- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..4e305249b3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -516,6 +516,7 @@ static Property riscv_cpu_properties[] = {

[PATCH v5 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 3 + target/riscv/cpu.h | 12 ++ target/riscv/cpu_bits.h | 66 ++ target/riscv/csr.c | 271 4 files changed, 352 insertions(+) diff --git a/target/riscv/cpu.c

[PATCH v4 1/2] hw/block/nvme: add dulbe support

From: Klaus Jensen Add support for reporting the Deallocated or Unwritten Logical Block Error (DULBE). Rely on the block status flags reported by the block layer and consider any block with the BDRV_BLOCK_ZERO flag to be deallocated. Multiple factors affect when a Write Zeroes command result

Re: [PATCH v3 2/2] hw/block/nvme: add the dataset management command

On Oct 21 17:59, Keith Busch wrote: > On Thu, Oct 22, 2020 at 12:17:36AM +0200, Klaus Jensen wrote: > > +static void nvme_aio_discard_cb(void *opaque, int ret) > > +{ > > +NvmeRequest *req = opaque; > > +int *discards = req->opaque; > > + > > +

[PATCH v4 0/2] hw/block/nvme: dulbe and dsm support

From: Klaus Jensen This adds support for the Deallocated or Unwritten Logical Block error recovery feature as well as the Dataset Management command. I wanted to add support for the NPDG and NPDA fields such that the host could get a hint on how many blocks to request deallocation of for the

Re: [PATCH 20/22] vl: move CHECKPOINT_INIT after preconfig

On 10/21/20 10:57 PM, Paolo Bonzini wrote: Move CHECKPOINT_INIT right before the machine initialization is completed. Everything before is essentially an extension of command line parsing. Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé --- softmmu/vl.c | 10 +-

Re: [PATCH 17/22] vl: load plugins as late as possible

On 10/21/20 10:57 PM, Paolo Bonzini wrote: There is no need to load plugins in the middle of default device processing, move -plugin handling just before preconfig is entered. Signed-off-by: Paolo Bonzini --- softmmu/vl.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-)

Re: [PATCH 12/22] vl: move bios_name out of softmmu/vl.c

On 10/21/20 10:57 PM, Paolo Bonzini wrote: bios_name is a legacy variable used by machine code. Hide it from softmmu/vl.c. Signed-off-by: Paolo Bonzini --- hw/core/machine.c | 5 + softmmu/vl.c | 2 -- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git

Re: [PATCH 04/22] machine: move SMP initialization from vl.c

On 10/21/20 10:56 PM, Paolo Bonzini wrote: Initialize the object's values from the class when the object is created, no need to have vl.c do it for us. Signed-off-by: Paolo Bonzini --- hw/core/machine.c | 7 +++ softmmu/vl.c | 7 --- 2 files changed, 7 insertions(+), 7

Re: [PATCH 02/22] machine: remove deprecated -machine enforce-config-section option

On 22/10/20 07:09, Thomas Huth wrote: >> +#include "migration/misc.h" > This new include does not make much sense to me, if all you did was removing > code from this file. Why did you add this here? Yeah, it's not needed anymore. It's part of a different patch that I threw away when I noticed

答复: 答复: [PATCH 1/1] Skip flatview_simplify() for cpu vendor zhaoxin

hi paolo, >So removing flatview_simplify() works because the higher area (0x1 >and above) remains the same. I guess the simplest thing to do is to >apply flatview_simplify() only to I/O areas, though we can also consider >removing it completely. I'm not sure in which case it would provide

Re: [PATCH v1 6/6] tests/acceptance: pick a random gdb port for reverse debugging

On 21.10.2020 19:31, Alex Bennée wrote: Currently the test randomly fails if you are using a shared machine due to contention on the well known port 1234. We can ameliorate this a bit by picking a random non-ephemeral port although it doesn't totally avoid the problem. While we could use a

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