[PULL 03/11] configure: move gettext detection to meson.build

This will allow meson to honour -Dauto_features=disabled later. Suggested-by: Paolo Bonzini Signed-off-by: Alex Bennée Acked-by: Paolo Bonzini Message-Id: <20201210190417.31673-4-alex.ben...@linaro.org> diff --git a/configure b/configure index d37ec98aa9..f9b1e4fbb0 100755 --- a/configure +++

[PULL 06/11] gitlab: move --without-default-devices build from Travis

Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth Reviewed-by: Wainer dos Santos Moschetta Message-Id: <20201210190417.31673-7-alex.ben...@linaro.org> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b3bcaacf7b..2134453717 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -514,6 +514,13

[PULL 02/11] gitlab: include aarch64-softmmu and ppc64-softmmu cross-system-build

Otherwise we miss coverage of KVM support in the cross build. To balance it out add arm-softmmu (no kvm, subset of aarch64), cris-softmmu and ppc-softmmu to the exclude list which do get coverage elsewhere. Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth Reviewed-by: Wainer dos Santos

[PATCH v2 11/12] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5

The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 4 ++-- target/mips/translate.c | 2 +- 2 files changed, 3 insertions(+), 3

[PULL 04/11] configure: add --without-default-features

By default QEMU enables a lot of features if it can probe and find the support libraries. It also enables a bunch of features by default. This patch adds the ability to build --without-default-features which can be paired with a --without-default-devices for a barely functional build. The main

[PULL 01/11] configure: include moxie-softmmu in deprecated_targets_list

We still build it but there is no point including it in the normal builds as it is ushered out of the door. Fixes: 4258c8e221 ("docs/system/deprecated: Mark the 'moxie' CPU as deprecated") Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth Reviewed-by: Wainer dos Santos Moschetta Message-Id:

[PATCH v2 10/12] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3

The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [RFC v2 08/15] target/riscv: rvb: single-bit instructions

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > +static bool gen_shifti(DisasContext *ctx, arg_shift *a, > +void(*func)(TCGv, TCGv, TCGv)) > +{ > +TCGv source1 = tcg_temp_new(); > +TCGv source2 = tcg_temp_new(); > + > +gen_get_gpr(source1, a->rs1); > +

[PATCH v2 06/12] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5

Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 3 +-- 1 file

[PATCH v2 12/12] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6

The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 4 +- target/mips/mips-defs.h| 4 +- linux-user/elfload.c | 2 +-

Re: [PATCH 03/11] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2

On 12/16/20 4:16 PM, Jiaxun Yang wrote: > 在 2020/12/16 21:43, Philippe Mathieu-Daudé 写道: >> Use the single ISA_MIPS32R2 definition to check if the Release 2 >> ISA is supported, whether the CPU support 32/64-bit. >> >> For now we keep '32' in the definition name, we will rename it >> as

[PATCH v2 07/12] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6

Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 2 +-

Re: [RFC v2 10/15] target/riscv: rvb: rotate (left/right)

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > +static bool trans_ror(DisasContext *ctx, arg_ror *a) > { > +REQUIRE_EXT(ctx, RVB); > +return gen_arith(ctx, a, _gen_rotr_tl); > +} Use gen_shift. > +static bool trans_rori(DisasContext *ctx, arg_rori *a) > +{ > +REQUIRE_EXT(ctx,

[PATCH v2 09/12] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2

The MIPS ISA release 2 is common to 32/64-bit CPUs. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 2 +- target/mips/mips-defs.h| 6 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cp0_timer.c| 4 +- target/mips/cpu.c | 2 +-

[PATCH v2 05/12] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3

Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 3 +-- 1 file

[PATCH v2 03/12] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1

Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 3 +--

[PATCH v2 00/12] target/mips/mips-defs: Simplify ISA definitions

v2: Do not use MIPS3 for 64R1 (Jiaxun) As we don't need to duplicate 32/64-bit ISA defititions, this series remove the duplicated 64-bit variants, simplifying the overall. Changes done automatically with my editor using "find and replace". While the 'ISA_MIPS_Rx' form is shorter than

[PATCH v2 08/12] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1

The MIPS ISA release '1' is common to 32/64-bit CPUs. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 4 +-- target/mips/translate.c | 54 - 3 files changed, 30 insertions(+), 30 deletions(-) diff

[PATCH v2 04/12] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2

Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h| 3 +--

[PATCH v2 02/12] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64

MIPS 64-bit ISA is introduced with MIPS3. No need for another bit/definition to check for 64-bit. Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 2 +- hw/mips/boston.c| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [PATCH v3 1/3] docs: generate qemu-storage-daemon-qmp-ref(7) man page

On Wed, 16 Dec 2020 at 16:21, Stefan Hajnoczi wrote: > > On Tue, Dec 15, 2020 at 05:11:06PM +0100, Kevin Wolf wrote: > > > diff --git a/docs/interop/qemu-storage-daemon-qmp-ref.rst > > > b/docs/interop/qemu-storage-daemon-qmp-ref.rst > > > new file mode 100644 > > > index 00..caf9dad23a

[PATCH v2 01/12] target/mips/mips-defs: Reorder CPU_MIPS5 definition

Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 805034b8956..f4d76e562d1 100644 ---

Re: [RFC v2 05/15] target/riscv: rvb: pack two words into one register

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Frank Chang > --- > target/riscv/insn32-64.decode | 3 ++ > target/riscv/insn32.decode | 3 ++ > target/riscv/insn_trans/trans_rvb.c.inc | 30

Re: [PATCH v3 1/3] docs: generate qemu-storage-daemon-qmp-ref(7) man page

On Tue, Dec 15, 2020 at 05:11:06PM +0100, Kevin Wolf wrote: > > diff --git a/docs/interop/qemu-storage-daemon-qmp-ref.rst > > b/docs/interop/qemu-storage-daemon-qmp-ref.rst > > new file mode 100644 > > index 00..caf9dad23a > > --- /dev/null > > +++

[PATCH 5/7] meson: use pkg-config method for libudev

Do not bother asking CMake, this is a pkg-config dependency. Signed-off-by: Paolo Bonzini --- meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/meson.build b/meson.build index ab622ae8bd..0b36fb38f1 100644 --- a/meson.build +++ b/meson.build @@ -399,6 +399,7 @@ endif libudev =

Re: [RFC v2 06/15] target/riscv: rvb: min/max instructions

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Frank Chang > --- > target/riscv/insn32.decode | 4 > target/riscv/insn_trans/trans_rvb.c.inc | 24 > 2 files changed, 28

[PATCH 1/7] Makefile: add dummy target for build.ninja dependencies

The dummy targets ensure that incremental build can be done after deleting a meson.build file. Signed-off-by: Paolo Bonzini --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 76dbb917f5..fb9923ff22 100644 --- a/Makefile +++ b/Makefile @@ -133,6 +133,7 @@

[PATCH 6/7] meson: use dependency to gate block modules

This will allow converting the dependencies to meson options one by one, because moving the tests to meson.build will get rid of the symbols in config-host.mak. Signed-off-by: Paolo Bonzini --- block/meson.build | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff

[PATCH 7/7] meson: cleanup Kconfig.host handling

Build the array of command line arguments coming from config_host once for all targets. Add all accelerators to accel/Kconfig so that the command line arguments for accelerators can be computed easily in the existing "foreach sym: accelerators" loop. Signed-off-by: Paolo Bonzini ---

Re: [RFC v2 07/15] target/riscv: rvb: sign-extend instructions

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > +static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) > +{ > +REQUIRE_EXT(ctx, RVB); > +return gen_unary(ctx, a, _gen_ext16s_tl); > +} > + > +{ Stray "{". Presumably a rebase error fixed up in a later patch? Anyway, with that

[PATCH 2/7] meson: update submodule to 0.56.0

Signed-off-by: Paolo Bonzini --- configure | 2 +- meson | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 6317964997..8d12b715e3 100755 --- a/configure +++ b/configure @@ -1938,7 +1938,7 @@ python_version=$($python -c 'import sys;

[PATCH 3/7] meson: switch minimum meson version to 0.56.0

Meson 0.56.0 does not need b_staticpic=$pie anymore, and has stabilized the keyval module. Remove the workaround and use a few replacements for features deprecated in that release cycle. Signed-off-by: Paolo Bonzini --- configure | 5 docs/meson.build |

[PATCH 4/7] meson: fix detection of curses with pkgconfig

Signed-off-by: Paolo Bonzini --- meson.build | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index 39fc9b7143..ab622ae8bd 100644 --- a/meson.build +++ b/meson.build @@ -500,16 +500,16 @@ if have_system and not get_option('curses').disabled()

Re: [PATCH] tests: update for rename of CentOS8 PowerTools repo

On Wed, Dec 16, 2020 at 04:10:56PM +, Peter Maydell wrote: > On Wed, 16 Dec 2020 at 14:21, Daniel P. Berrangé wrote: > > > > This was intentionally renamed recently to be all lowercase: > > > > https://bugs.centos.org/view.php?id=17920 > >

[PATCH 0/7] First round of meson bugfixes and cleanups for 6.0

Mostly switching to 0.56.0 in order to remove the b_staticpic version-dependent hack. Paolo Bonzini (7): Makefile: add dummy target for build.ninja dependencies meson: update submodule to 0.56.0 meson: switch minimum meson version to 0.56.0 meson: fix detection of curses with pkgconfig

Re: [PATCH] tests: update for rename of CentOS8 PowerTools repo

Daniel P. Berrangé writes: > This was intentionally renamed recently to be all lowercase: > > https://bugs.centos.org/view.php?id=17920 > https://wiki.centos.org/Manuals/ReleaseNotes/CentOS8.2011#Yum_repo_file_and_repoid_changes > > Signed-off-by: Daniel P. Berrangé > --- > > This needs to be

Re: [PATCH] x86/cpu: Add AVX512_FP16 cpu feature

On 2020-12-16 at 23:40 CET, Cathy Zhang wrote... > AVX512 Half-precision floating point (FP16) has better performance > compared to FP32 if the presicion or magnitude requirements are met. spelling: precision > It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23]. > > Refer to >

Re: [PATCH 2/2] qom: Assert that objects being destroyed have no parent

Paolo Bonzini writes: > On 16/12/20 08:53, Marc-André Lureau wrote: >> >> On the principle, I fully agree. But the risk is high to introduce >> regression if objects are manipulated in strange ways. >> >> I remember I wanted object_unref() to automatically remove itself from >> the parent

[PATCH v2 3/3] trace: recommend "log" backend for getting started with tracing

The "simple" backend is actually more complicated to use than the "log" backend. Update the quickstart documentation to feature the "log" backend instead of the "simple" backend. Suggested-by: Peter Maydell Signed-off-by: Stefan Hajnoczi --- docs/devel/tracing.rst | 35

[PATCH v2 1/3] trace: fix simpletrace doc mismerge

The simpletrace documentation section was accidentally split when the ftrace section was introduced. Move the simpletrace-specific documentation back into the simpletrace section. Fixes: e64dd5efb2c6d522a3bc9d096cd49a4e53f0ae10 ("trace: document ftrace backend") Reviewed-by: Peter Maydell

Re: [PATCH] tests: update for rename of CentOS8 PowerTools repo

On Wed, 16 Dec 2020 at 14:21, Daniel P. Berrangé wrote: > > This was intentionally renamed recently to be all lowercase: > > https://bugs.centos.org/view.php?id=17920 > https://wiki.centos.org/Manuals/ReleaseNotes/CentOS8.2011#Yum_repo_file_and_repoid_changes > > Signed-off-by: Daniel P. Berrangé

Re: [PATCH] tcg,riscv: Fix illegal shift instructions

On 12/16/20 2:12 AM, Zihao Yu wrote: > * This bug can be reproduced by running the following guest instructions > on a RISC-V host. > > (1) xor %ecx,%ecx > (2) sar %cl,%eax > (3) cmovne %edi,%eax > > After optimization, the tcg instructions of (2) are > > movi_i32

[PATCH v2 2/3] tracing: convert documentation to rST

This is a simple rST conversion of the documentation. Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi --- docs/devel/index.rst| 1 + docs/devel/{tracing.txt => tracing.rst} | 134 ++-- 2 files changed, 81 insertions(+), 54 deletions(-)

[PATCH v2 0/3] trace: convert docs to rST and feature "log" backend in quickstart

v2: * Simplify quickstart for the "log" trace backend that is enabled by default [Peter] * Don't show ./configure --enable-trace-backends=log example since it's built by default (changed to --enable-trace-backends=simple,dtrace) [Peter] Convert tracing.txt to rST and add it to the

Re: [PATCH 02/11] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64

On 12/16/20 4:06 PM, Jiaxun Yang wrote: > 在 2020/12/16 21:43, Philippe Mathieu-Daudé 写道: >> MIPS 64-bit ISA is introduced with MIPS3. >> No need for another bit/definition to check for 64-bit. >> >> Simplify CPU_MIPS64 definition as CPU_MIPS5 contains >> CPU_MIPS4 which contains CPU_MIPS3 which

Re: CXL support in QEMU

On 20-12-16 13:42:51, Jonathan Cameron wrote: > On Wed, 16 Dec 2020 10:53:34 +0100 > Thomas Huth wrote: > > > On 16/12/2020 06.05, Prashant V Agarwal wrote: > > > Hi, > > > Is there a way to know the support plans for CXL protocol in QEMU? > > > I see that there is side branch development going

Re: tests/test-char hangs in CI (Centos7 with check-crypto-old-nettle)

Alex Bennée writes: > Hi, > > Over the last few weeks we've seen a steadily more common failure in > test-char on CI. It seems to only manifest itself on the > check-crypto-old-nettle build set and fails with a message like: > > Running test test-char > Unexpected error in

Re: [PATCH v2 3/8] configure: move gettext detection to meson.build

On 16/12/20 16:27, Alex Bennée wrote: Paolo Bonzini writes: On 16/12/20 15:19, Alex Bennée wrote: Alex Bennée writes: This will allow meson to honour -Dauto_features=disabled later. Suggested-by: Paolo Bonzini Signed-off-by: Alex Bennée ping Paolo, are you happy with this bit?

Re: [PATCH 3/3] trace: do not include TCG helper tracepoints in no-TCG builds

On 16/12/20 16:25, Richard Henderson wrote: On 12/16/20 9:22 AM, Paolo Bonzini wrote: On 16/12/20 16:13, Richard Henderson wrote: @@ -71,7 +71,7 @@ foreach d : [   input: meson.project_source_root() / 'trace-events',   command: [ tracetool, '--group=root',

Re: [PATCH v2 3/8] configure: move gettext detection to meson.build

Paolo Bonzini writes: > On 16/12/20 15:19, Alex Bennée wrote: >> >> Alex Bennée writes: >> >>> This will allow meson to honour -Dauto_features=disabled later. >>> >>> Suggested-by: Paolo Bonzini >>> Signed-off-by: Alex Bennée >> >> ping Paolo, are you happy with this bit? > > Yes, I'm so

Re: [RFC v2 04/15] target/riscv: rvb: logic-with-negate

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > +static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2) > +{ > +TCGv t = tcg_temp_new(); > +tcg_gen_andc_tl(ret, arg1, arg2); > +tcg_temp_free(t); > +} > + > +static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2) > +{ > +TCGv t =

Re: [PATCH 1/3] remove TCG includes from common code

On 12/16/20 2:55 PM, Paolo Bonzini wrote: > Enable removing tcg/$tcg_arch from the include path when TCG is disabled. > Move translate-all.h to include/exec, since stubs exist for the functions > defined therein. > > Signed-off-by: Paolo Bonzini > --- > accel/stubs/tcg-stub.c

Re: [RFC PATCH 0/9] Support for Virtio-fs daemon crash reconnection

Hi On Tue, Dec 15, 2020 at 8:22 PM Jiachen Zhang < zhangjiachen.jay...@bytedance.com> wrote: > Hi, all > > We implement virtio-fs crash reconnection in this patchset. The crash > reconnection of virtiofsd here is completely transparent to guest, no > remount in guest is needed, even the inflight

Re: [PATCH] tests: update for rename of CentOS8 PowerTools repo

On Wed, Dec 16, 2020 at 11:21 AM Daniel P. Berrangé wrote: > > This was intentionally renamed recently to be all lowercase: > > https://bugs.centos.org/view.php?id=17920 > https://wiki.centos.org/Manuals/ReleaseNotes/CentOS8.2011#Yum_repo_file_and_repoid_changes > > Signed-off-by: Daniel P.

Re: [PATCH 03/11] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2

在 2020/12/16 21:43, Philippe Mathieu-Daudé 写道: Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Signed-off-by: Philippe

Re: [PATCH v2] qga/commands-posix: Send CCW address on s390x with the fsinfo data

On Fri, 27 Nov 2020 09:23:53 +0100 Thomas Huth wrote: > We need the CCW address on the libvirt side to correctly identify > the disk, so add this information to the GuestDiskAddress on s390x. > > Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1755075 > Signed-off-by: Thomas Huth > --- >

Re: [PATCH 3/3] trace: do not include TCG helper tracepoints in no-TCG builds

On 12/16/20 7:55 AM, Paolo Bonzini wrote: > diff --git a/trace/meson.build b/trace/meson.build > index 3fa760f568..012d0dbceb 100644 > --- a/trace/meson.build > +++ b/trace/meson.build > @@ -71,7 +71,7 @@ foreach d : [ > input: meson.project_source_root() / 'trace-events', >

Re: [PATCH 1/3] remove TCG includes from common code

On 12/16/20 7:55 AM, Paolo Bonzini wrote: > Enable removing tcg/$tcg_arch from the include path when TCG is disabled. > Move translate-all.h to include/exec, since stubs exist for the functions > defined therein. > > Signed-off-by: Paolo Bonzini > --- > accel/stubs/tcg-stub.c

Re: [PATCH 3/3] trace: do not include TCG helper tracepoints in no-TCG builds

On 12/16/20 9:22 AM, Paolo Bonzini wrote: > On 16/12/20 16:13, Richard Henderson wrote: >>> @@ -71,7 +71,7 @@ foreach d : [ >>>   input: meson.project_source_root() / 'trace-events', >>>   command: [ tracetool, '--group=root', >>> '--format=@0@'.format(d[1]),

Re: [RFC v2 03/15] target/riscv: rvb: count bits set

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > From: Frank Chang > > Signed-off-by: Kito Cheng > Signed-off-by: Frank Chang Reviewed-by: Richard Henderson > +return gen_unary(ctx, a, _gen_ctpop_tl); ... > +return gen_unary(ctx, a, _pcntw); You can drop all of the unnecessary

Re: [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Frank Chang > --- > target/riscv/insn32-64.decode | 4 +++ > target/riscv/insn32.decode | 7 +++- > target/riscv/insn_trans/trans_rvb.c.inc | 47

Re: [PATCH 3/3] trace: do not include TCG helper tracepoints in no-TCG builds

On 16/12/20 16:13, Richard Henderson wrote: @@ -71,7 +71,7 @@ foreach d : [ input: meson.project_source_root() / 'trace-events', command: [ tracetool, '--group=root', '--format=@0@'.format(d[1]), '@INPUT@' ], capture: true) -

Re: [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Frank Chang > --- > target/riscv/insn32.decode | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Richard Henderson r~

[ANNOUNCE] qemu-security mailing list

Hello, * QEMU project has set-up a dedicated mailing list to receive and triage all its security issues. Please see: -> https://www.qemu.org/contribute/security-process/ -> https://lists.nongnu.org/mailman/listinfo/qemu-security * If you are a security researcher OR think you've

[PATCH 5/7] meson: use pkg-config method for libudev

Do not bother asking CMake, this is a pkg-config dependency. Signed-off-by: Paolo Bonzini --- meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/meson.build b/meson.build index ab622ae8bd..0b36fb38f1 100644 --- a/meson.build +++ b/meson.build @@ -399,6 +399,7 @@ endif libudev =

[PATCH 7/7] meson: cleanup Kconfig.host handling

Build the array of command line arguments coming from config_host once for all targets. Add all accelerators to accel/Kconfig so that the command line arguments for accelerators can be computed easily in the existing "foreach sym: accelerators" loop. Signed-off-by: Paolo Bonzini ---

Re: [PATCH 02/11] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64

在 2020/12/16 21:43, Philippe Mathieu-Daudé 写道: MIPS 64-bit ISA is introduced with MIPS3. No need for another bit/definition to check for 64-bit. Simplify CPU_MIPS64 definition as CPU_MIPS5 contains CPU_MIPS4 which contains CPU_MIPS3 which contains ISA_MIPS3. Oops, I shall amend my reviewed

[PATCH 3/7] meson: switch minimum meson version to 0.56.0

Meson 0.56.0 does not need b_staticpic=$pie anymore, and has stabilized the keyval module. Remove the workaround and use a few replacements for features deprecated in that release cycle. Signed-off-by: Paolo Bonzini --- configure | 5 docs/meson.build |

[PATCH 2/7] meson: update submodule to 0.56.0

Signed-off-by: Paolo Bonzini --- configure | 2 +- meson | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 6317964997..8d12b715e3 100755 --- a/configure +++ b/configure @@ -1938,7 +1938,7 @@ python_version=$($python -c 'import sys;

[PATCH 6/7] meson: use dependency to gate block modules

This will allow converting the dependencies to meson options one by one, because moving the tests to meson.build will get rid of the symbols in config-host.mak. Signed-off-by: Paolo Bonzini --- block/meson.build | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff

[PATCH 1/7] Makefile: add dummy target for build.ninja dependencies

The dummy targets ensure that incremental build can be done after deleting a meson.build file. Signed-off-by: Paolo Bonzini --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 76dbb917f5..fb9923ff22 100644 --- a/Makefile +++ b/Makefile @@ -133,6 +133,7 @@

[PATCH 0/7] First round of meson bugfixes and cleanups for 6.0

Mostly switching to 0.56.0 in order to remove the b_staticpic version-dependent hack. Paolo Bonzini (7): Makefile: add dummy target for build.ninja dependencies meson: update submodule to 0.56.0 meson: switch minimum meson version to 0.56.0 meson: fix detection of curses with pkgconfig

[Bug 1908416] Re: qemu-system-aarch64 can't run Windows 10 for ARM version 2004

** Attachment added: "UEFI img files (QEMU_VARS and QEMU_EFI)" https://bugs.launchpad.net/qemu/+bug/1908416/+attachment/5444215/+files/uefi.7z -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

[PATCH 4/7] meson: fix detection of curses with pkgconfig

Signed-off-by: Paolo Bonzini --- meson.build | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index 39fc9b7143..ab622ae8bd 100644 --- a/meson.build +++ b/meson.build @@ -500,16 +500,16 @@ if have_system and not get_option('curses').disabled()

[Bug 1908416] [NEW] qemu-system-aarch64 can't run Windows 10 for ARM version 2004

Public bug reported: Problem: qemu-system-aarch64 can't run Windows 10 for ARM version 2004 (20H2) or newer Host OS: Windows 10 x64 version 20H2 CPU: Intel Pentium Dual-core T4300 (no vt-x) QEMU : QEMU version 5.1.0 from qemu.org cmdline: qemu-system-aarch64.exe -M virt -cpu cortex-a72

Re: [PATCH 02/11] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64

在 2020/12/16 21:43, Philippe Mathieu-Daudé 写道: MIPS 64-bit ISA is introduced with MIPS3. No need for another bit/definition to check for 64-bit. Simplify CPU_MIPS64 definition as CPU_MIPS5 contains CPU_MIPS4 which contains CPU_MIPS3 which contains ISA_MIPS3. Suggested-by: Jiaxun Yang

Re: [PATCH 2/3] move icache flush out of tcg.h

On 16/12/20 15:52, Richard Henderson wrote: On 12/16/20 7:55 AM, Paolo Bonzini wrote: icache flush is also used by non-TCG accelerators. Do not require users such as physmem.c to include tcg/tcg.h. Signed-off-by: Paolo Bonzini --- See also

Re: [PATCH 01/11] target/mips/mips-defs: Reorder CPU_MIPS5 definition

在 2020/12/16 21:43, Philippe Mathieu-Daudé 写道: Move CPU_MIPS5 after CPU_MIPS4 :) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)- - Jiaxun

Re: [PATCH v2 2/4] block: Avoid processing BDS twice in bdrv_set_aio_context_ignore()

On Wed, Dec 16, 2020 at 01:35:14PM +0100, Kevin Wolf wrote: > Am 15.12.2020 um 18:23 hat Sergio Lopez geschrieben: > > On Tue, Dec 15, 2020 at 04:01:19PM +0100, Kevin Wolf wrote: > > > Am 15.12.2020 um 14:15 hat Sergio Lopez geschrieben: > > > > On Tue, Dec 15, 2020 at 01:12:33PM +0100, Kevin Wolf

Re: [PATCH 00/11] target/mips/mips-defs: Simplify ISA definitions

在 2020/12/16 21:43, Philippe Mathieu-Daudé 写道: As we don't need to duplicate 32/64-bit ISA defititions, this series remove the duplicated 64-bit variants, simplifying the overall. Thanks, that makes things much more clear! Changes done automatically with my editor using "find and

Re: [PATCH 2/3] move icache flush out of tcg.h

On 12/16/20 7:55 AM, Paolo Bonzini wrote: > icache flush is also used by non-TCG accelerators. Do not require users > such as physmem.c to include tcg/tcg.h. > > Signed-off-by: Paolo Bonzini > --- See also https://lists.gnu.org/archive/html/qemu-devel/2020-12/msg03623.html I moved it to a

Re: [PATCH v3 0/4] target/s390x: Improve carry computation

On 14.12.20 23:13, Richard Henderson wrote: > While testing the float128_muladd changes for s390x host, > emulating under x86_64 of course, I noticed that the code > we generate for strings of ALCGR and SLBGR is pretty awful. > > I realized that we were missing a trick: the output cc is > based

Re: [PATCH 3/3] trace: recommend "log" backend for getting started with tracing

On Fri, Dec 11, 2020 at 03:06:17PM +, Peter Maydell wrote: > On Wed, 9 Dec 2020 at 17:42, Stefan Hajnoczi wrote: > > > > The "simple" backend is actually more complicated to use than the "log" > > backend. Update the quickstart documentation to feature the "log" > > backend instead of the

Re: [PATCH v2 3/8] configure: move gettext detection to meson.build

Alex Bennée writes: > This will allow meson to honour -Dauto_features=disabled later. > > Suggested-by: Paolo Bonzini > Signed-off-by: Alex Bennée ping Paolo, are you happy with this bit? > --- > configure | 19 +++ > meson_options.txt | 2 +- > po/meson.build

Re: Are user static builds really dynamically linked ?

On 16/12/2020 11:39, Paolo Bonzini wrote: > On 16/12/20 12:07, Peter Maydell wrote: >> Something has definitely changed here. What you had with 4.2.1 >> is what you should be getting. The obvious suspect is that >> something weird happened in the meson conversion... Ubuntu/Debian maintainer

[PATCH v3 10/10] vfio: Disable only uncoordinated discards

We support coordinated discarding of RAM using the RamDiscardMgr. Let's unlock support for coordinated discards, keeping uncoordinated discards (e.g., via virtio-balloon) disabled. This unlocks virtio-mem + vfio. Note that vfio used via "nvme://" by the block layer has to be implemented/unlocked

[PATCH v3 07/10] softmmu/physmem: Don't use atomic operations in ram_block_discard_(disable|require)

We have users in migration context that don't hold the BQL (when finishing migration). To prepare for further changes, use a dedicated mutex instead of atomic operations. Keep using qatomic_read ("READ_ONCE") for the functions that only extract the current state (e.g., used by virtio-balloon),

[PATCH v3 03/10] virtio-mem: Implement RamDiscardMgr interface

Let's properly notify when (un)plugging blocks, after discarding memory and before allowing the guest to consume memory. Handle errors from notifiers gracefully (e.g., no remaining VFIO mappings) when plugging, rolling back the change and telling the guest that the VM is busy. One special case to

Re: [PATCH v2 3/8] configure: move gettext detection to meson.build

On 16/12/20 15:19, Alex Bennée wrote: Alex Bennée writes: This will allow meson to honour -Dauto_features=disabled later. Suggested-by: Paolo Bonzini Signed-off-by: Alex Bennée ping Paolo, are you happy with this bit? Yes, I'm so happy with this and the --with-default-features parts

Re: [PATCH] tcg: Use memset for large vector byte replication

On 12/15/20 5:38 PM, Philippe Mathieu-Daudé wrote: > BTW (nitpicking) I'd rewrite the epilogue as: > > if (!in_32) { > tcg_temp_free_i32(t_val); > } > tcg_temp_free_ptr(t_size); > > tcg_temp_free_ptr(t_ptr); > return; > > t_val first, because

Re: [PATCH] block: report errno when flock fcntl fails

16.12.2020 16:53, Kevin Wolf wrote: Am 16.12.2020 um 14:06 hat David Edmondson geschrieben: On Wednesday, 2020-12-16 at 12:57:46 +01, Kevin Wolf wrote: Am 16.12.2020 um 12:38 hat David Edmondson geschrieben: On Wednesday, 2020-12-16 at 12:29:40 +01, Kevin Wolf wrote: Am 15.12.2020 um 20:01

[PATCH v3 09/10] virtio-mem: Require only coordinated discards

We implement the RamDiscardMgr interface and only require coordinated discarding of RAM to work. Reviewed-by: Dr. David Alan Gilbert Reviewed-by: Pankaj Gupta Cc: Paolo Bonzini Cc: "Michael S. Tsirkin" Cc: Alex Williamson Cc: Dr. David Alan Gilbert Cc: Igor Mammedov Cc: Pankaj Gupta Cc:

[PATCH v3 06/10] vfio: Support for RamDiscardMgr in the vIOMMU case

vIOMMU support works already with RamDiscardMgr as long as guests only map populated memory. Both, populated and discarded memory is mapped into _space_memory, where vfio_get_xlat_addr() will find that memory, to create the vfio mapping. Sane guests will never map discarded memory (e.g.,

[PATCH] tests: update for rename of CentOS8 PowerTools repo

This was intentionally renamed recently to be all lowercase: https://bugs.centos.org/view.php?id=17920 https://wiki.centos.org/Manuals/ReleaseNotes/CentOS8.2011#Yum_repo_file_and_repoid_changes Signed-off-by: Daniel P. Berrangé --- This needs to be merged asap, as CI will break for anyone

[PATCH v3 05/10] vfio: Support for RamDiscardMgr in the !vIOMMU case

Implement support for RamDiscardMgr, to prepare for virtio-mem support. Instead of mapping the whole memory section, we only map "populated" parts and update the mapping when notified about discarding/population of memory via the RamDiscardListener. Similarly, when syncing the dirty bitmaps, sync

[PATCH v3 04/10] vfio: Query and store the maximum number of DMA mappings

Let's query the maximum number of DMA mappings by querying the available mappings when creating the container. In addition, count the number of DMA mappings and warn when we would exceed it. This is a preparation for RamDiscardMgr which might create quite some DMA mappings over time, and we at

[PATCH v3 01/10] memory: Introduce RamDiscardMgr for RAM memory regions

We have some special RAM memory regions (managed by virtio-mem), whereby the guest agreed to only use selected memory ranges. "unused" parts are discarded so they won't consume memory - to logically unplug these memory ranges. Before the VM is allowed to use such logically unplugged memory again,

[PATCH v3 08/10] softmmu/physmem: Extend ram_block_discard_(require|disable) by two discard types

We want to separate the two cases whereby we discard ram - uncoordinated: e.g., virito-balloon - coordinated: e.g., virtio-mem coordinated via the RamDiscardMgr Reviewed-by: Pankaj Gupta Cc: Paolo Bonzini Cc: "Michael S. Tsirkin" Cc: Alex Williamson Cc: Dr. David Alan Gilbert Cc: Igor

[PATCH v3 02/10] virtio-mem: Factor out traversing unplugged ranges

Let's factor out the core logic, to be reused soon. Reviewed-by: Pankaj Gupta Cc: Paolo Bonzini Cc: "Michael S. Tsirkin" Cc: Alex Williamson Cc: Dr. David Alan Gilbert Cc: Igor Mammedov Cc: Pankaj Gupta Cc: Peter Xu Cc: Auger Eric Cc: Wei Yang Cc: teawater Cc: Marek Kedzierski

[PATCH v3 00/10] virtio-mem: vfio support

A virtio-mem device manages a memory region in guest physical address space, represented as a single (currently large) memory region in QEMU, mapped into system memory address space. Before the guest is allowed to use memory blocks, it must coordinate with the hypervisor (plug blocks). After a

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