[PULL 63/66] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree

LDL/LDR/SDL/SDR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <202012

[PULL 41/66] target/mips: Remove now unused ASE_MSA definition

We don't use ASE_MSA anymore (replaced by ase_msa_available() checking MSAP bit from CP0_Config3). Remove it. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-6-f4...@amsat.org> --- target/

[PULL 59/66] target/mips: Convert Rel6 COP1X opcode to decodetree

COP1x opcode has been removed from the Release 6. Add a single decodetree entry for it, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-8-f4..

[PULL 37/66] target/mips: Introduce ase_msa_available() helper

Instead of accessing CP0_Config3 directly and checking the 'MSA Present' bit, introduce an explicit helper, making the code easier to read. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-2

[PULL 47/66] target/mips: Extract MSA helpers from op_helper.c

We have ~400 lines of MSA helpers in the generic op_helper.c, move them with the other helpers in 'msa_helper.c'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201123204448.3260804-5-f4...@amsat.org> Tested-by: Jiaxun Yang --- target/mips/msa_helper.c | 39

[PULL 58/66] target/mips: Convert Rel6 Special2 opcode to decodetree

Special2 opcode have been removed from the Release 6. Add a single decodetree entry for all the opcode class, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <202012

[PULL 36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode

To allow compiling 64-bit specific translation code more generically (and removing #ifdef'ry), allow compiling check_mips_64() on 32-bit targets. If ever called on 32-bit, we obviously emit a reserved instruction exception. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Message-I

[PULL 44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods

The gen_msa*() methods don't use the "CPUMIPSState *env" argument. Remove it to simplify. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-9-f4...@amsat.org> --- target/mips/translate.c | 5

[PULL 55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes

Add the LSA opcode to the MSA32 decodetree config, add DLSA to a new config for the MSA64 ASE, and call decode_msa64() in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-23-f4...@amsat.org> --- target/mips/msa32

[PULL 35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc()

As we will slowly move to decodetree generated decoders, extract the legacy decoding from decode_opc(), so new decoders are added in decode_opc() while old code is removed from decode_opc_legacy(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201215225757.7

[PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h'

Make gen_msa() and gen_msa_branch() public declarations so we can keep calling them once extracted from the big translate.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-18-f4...@amsat.org> Tested-by: Jiaxun Yang ---

[PULL 43/66] target/mips: Extract msa_translate_init() from mips_tcg_init()

The msa_wr_d[] registers are only initialized/used by MSA. They are declared static. We want to move them to the new 'msa_translate.c' unit in few commits, without having to declare them global (with extern). Extract first the logic initialization of the MSA registers from the generic initializat

[PULL 54/66] target/mips: Extract LSA/DLSA translation generators

Extract gen_lsa() from translate.c and explode it as gen_LSA() and gen_DLSA(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-22-f4...@amsat.org> --- target/mips/translate.h| 6 +++ target/mips/translate.c| 35 ++-

[PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h'

Some FPU translation functions / registers can be used by ISA / ASE / extensions out of the big translate.c file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-15-f4...@amsat.org> --- target/mips/translate.h | 7 +++ target/mips/tra

[PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-20-f4...@amsat.org> --- target/mips/meson.build | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 5a49951c6d7

[PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA

MSA presence is expressed by the MSAP bit of CP0_Config3. We don't need to check anything else. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-4-f4...@amsat.org> --- target/mips/internal.

[PULL 53/66] target/mips: Use decode_ase_msa() generated from decodetree

Now that we can decode the MSA ASE with decode_ase_msa(), use it and remove the previous code, now unreachable. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-21-f4...@amsat.org> Tested-by: Jiaxun Yang --- target/mips/translate.h | 1

[PULL 33/66] target/mips: Extract FPU specific definitions to translate.h

Extract FPU specific definitions that can be used by ISA / ASE / extensions to translate.h header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-16-f4...@amsat.org> --- target/mips/translate.h | 71 +++

[PULL 38/66] target/mips: Simplify msa_reset()

Call msa_reset() unconditionally, but only reset the MSA registers if MSA is implemented. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-3-f4...@amsat.org> --- target/mips/cpu.c

[PULL 31/66] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction

gen_reserved_instruction() is easier to read than generate_exception_end(ctx, EXCP_RI), replace it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-12-f4...@amsat.org> --- target/mips/translate.h | 1 + target/mips/translate.c | 729

[PULL 28/66] target/mips/translate: Extract DisasContext structure

Extract DisasContext to a new 'translate.h' header so different translation files (ISA, ASE, extensions) can use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-2-f4...@amsat.org> --- target/mips/translate.h | 50 +

[PULL 52/66] target/mips: Introduce decode tree bindings for MSA ASE

Introduce the 'msa32' decodetree config for the 32-bit MSA ASE. We start by decoding: - the branch instructions, - all instructions based on the MSA opcode. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-20-f4...@amsat.org> Reviewed-by: J

[PULL 30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end()

generate_exception_err(err=0) is simply generate_exception_end(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-11-f4...@amsat.org> --- target/mips/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tar

[PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element()

Simplify gen_check_zero_element() by passing the TCGCond argument along. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-25-f4...@amsat.org> --- target/mips/msa_translate.c | 10 -- 1 file changed,

[PULL 25/66] target/mips: Fix code style for checkpatch.pl

We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-14-f4...@amsat.org> --- target/mips/translate_init.c.inc | 36 1 file changed, 18 insertions(+), 18 dele

[PULL 26/66] target/mips: Move mmu_init() functions to tlb_helper.c

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-15-f4...@amsat.org> --- target/mips/internal.h | 1 + target/mips/tlb_helper.c | 46 ++ target/mips/translate_init.c.inc | 48 --

[PULL 20/66] target/mips: Extract FPU helpers to 'fpu_helper.h'

Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201120210844.2625602-2-f4...@amsat.org> --- target/mips/fpu_helper.h | 59 target/mips/internal.h

[PULL 29/66] target/mips/translate: Add declarations for generic code

Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-3-f4...@amsat.org> --

[PULL 48/66] target/mips: Extract MSA helper definitions

Keep all MSA-related code altogether. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201120210844.2625602-4-f4...@amsat.org> Tested-by: Jiaxun Yang --- target/mips/helper.h | 436 +- target/mips/msa_helper.h.inc | 443

[PULL 24/66] target/mips: Rename helper.c as tlb_helper.c

This file contains functions related to TLB management, rename it as 'tlb_helper.c'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-13-f4...@amsat.org> --- target/mips/{helper.c => tlb_helper.c} | 2 +- target/mips/meson.build

[PULL 23/66] target/mips: Move common helpers from helper.c to cpu.c

The rest of helper.c is TLB related. Extract the non TLB specific functions to cpu.c, so we can rename helper.c as tlb_helper.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-6-f4...@amsat.org> --- target/mips/internal

[PULL 21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif

To help understand ifdef'ry, add comment after #endif. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-4-f4...@amsat.org> --- target/mips/helper.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mip

[PULL 46/66] target/mips: Move msa_reset() to msa_helper.c

translate_init.c.inc mostly contains CPU definitions. msa_reset() doesn't belong here, move it with the MSA helpers. One comment style is updated to avoid checkpatch.pl warning. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-15-f4...@amsa

[PULL 15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2

The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210104221154.3127610-13-f4...@amsat.org> --- target/mips/internal.h | 2 +- target/mips/mips-defs.h| 4 +- linux-user/mips/cpu_loop.c | 2 +- tar

[PULL 22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-5-f4...@amsat.org> --- target/mips/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 92bd3fb8550..cfb6d82fd33 100644 --- a/target/

[PULL 45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()

In preparation of using the decodetree script, explode gen_msa_branch() as following: - OPC_BZ_V -> BxZ_V(EQ) - OPC_BNZ_V -> BxZ_V(NE) - OPC_BZ_[BHWD] -> BxZ(false) - OPC_BNZ_[BHWD]-> BxZ(true) Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Sign

[PULL 14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1

The MIPS ISA release '1' is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210104221154.3127610-12-f4...@amsat.org> --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 4 +-- target/mips/translate.c | 54

[PULL 17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5

The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210104221154.3127610-15-f4...@amsat.org> --- target/mips/mips-defs.h

[PULL 18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6

The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210104221154.3127610-16-f4...@amsat.org> --- target/mips/internal.h

[PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers

Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. It is not very clear to have FPU registers displayed with MSA register names, ev

[PULL 10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2

Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <2

[PULL 16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3

The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210104221154.3127610-14-f4...@amsat.org> --- target/mips/mips-defs.h

[PULL 19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset()

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-2-f4...@amsat.org> --- target/mips/cpu.c | 26 +- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 12126d37f16

[PULL 40/66] target/mips: Simplify MSA TCG logic

Only decode MSA opcodes if MSA is present (implemented). Now than check_msa_access() will only be called if MSA is present, the only way to have MIPS_HFLAG_MSA unset is if MSA is disabled (bit CP0C5_MSAEn cleared, see previous commit). Therefore we can remove the 'reserved instruction' exception.

[PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()

MIPS 64-bit ISA is introduced with MIPS3. Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, and the cpu_type_is_64bit() method to check if a CPU supports this ISA (thus is 64-bit). Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Messag

[PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3

Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <2

[PULL 12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5

Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <2

[PULL 08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()

Directly check if the CPU supports 64-bit with the recently added cpu_type_is_64bit() helper (inlined). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210104221154.3127610-6-f4...@amsat.org> --- hw/mips/boston.c | 6 ++ 1 file changed, 2 insertions(+), 4

[PULL 27/66] target/mips: Rename translate_init.c as cpu-defs.c

This file is not TCG specific, contains CPU definitions and is consumed by cpu.c. Rename it as such. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-10-f4...@amsat.org> --- target/mips/cpu.c| 2 +- targe

[PULL 06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1

'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing the "Release 1" ISA. Rename it with the 'R1' suffix, as the other CPU definitions do. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210104221154.3127610-4-f4...@amsat.org> --- target/mips/m

[PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1

Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <202

[PULL 13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6

Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <2

[PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment

Remove a comment added 12 years ago but never used (commit b6d96beda3a: "Use temporary registers for the MIPS FPU emulation"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210104221154.3127610-2-f4...@amsat.org> --- target/mips/mips-defs.h | 6 -- 1 fi

[PULL 01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA

The MIPS3 and MIPS32/64 ISA use different definitions for the CP0 Config0 register. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201201132817.2863301-2-f4...@amsat.org> --- target/mips/cpu.h | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-)

[PULL 05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition

Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210104221154.3127610-3-f4...@amsat.org> --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/m

[PULL 03/66] target/mips/addr: Add translation helpers for KSEG1

From: Jiaxun Yang It's useful for bootloader to do I/O operations. Signed-off-by: Jiaxun Yang Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Huacai Chen Message-Id: <20201215064507.30148-3-jiaxun.y...@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé ---

[PULL 02/66] target/mips: Replace CP0_Config0 magic values by proper definitions

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201201132817.2863301-3-f4...@amsat.org> --- target/mips/translate_init.c.inc | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/trans

[PULL 00/66] MIPS patches for 2021-01-07

The following changes since commit 470dd6bd360782f5137f7e3376af6a44658eb1d3: Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-060121-4' into staging (2021-01-06 22:18:36 +) are available in the Git repository at: https://gitlab.com/philmd/qemu.git tags/mips-202

Re: [Bug 1910586] [NEW] SD card size constraint conceptually wrong

On 1/7/21 8:24 PM, - wrote: > Public bug reported: > > The patch discussed here: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg720833.html > introduces an artificial size constraint for SD cards > that has no relation to reality. > > I'm trying to use an _actual_ **physical** SD card, >

Re: [PATCH v2 24/24] target/arm: Enforce alignment for sve unpredicated LDR/STR

On 1/7/21 7:39 AM, Peter Maydell wrote: >> +if (align > MO_ALIGN_8) { >> +t0 = tcg_temp_new_i64(); >> +tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ | align); >> +tcg_gen_addi_i64(clean_addr, clean_addr, 8); >> +tcg_gen_addi_ptr(i, i, 8); >

Re: [PATCH v4 3/6] hw/adc: Add an ADC module for NPCM7XX

Thanks for your review. We'll apply your suggestions. On Thu, Jan 7, 2021 at 1:07 PM Peter Maydell wrote: > On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > > > The ADC is part of NPCM7XX Module. Its behavior is controled by the > > ADC_CON register. It converts one of the eight analog inputs in

Re: What's the correct way to implement rfi and related instruction.

On 1/7/21 8:14 PM, 罗勇刚(Yonggang Luo) wrote: > This is the first patch,: > It's store MSR bits differntly for different rfi instructions: > [Qemu-devel] [PATCH] target-ppc: fix RFI by clearing some bits of MSR > https://lists.gnu.org/archive/html/qemu-devel/2010-05/msg02999.html >

Re: [PATCH v4 2/6] hw/timer: Refactor NPCM7XX Timer to use CLK clock

On Thu, Jan 7, 2021 at 12:51 PM Peter Maydell wrote: > On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > > > This patch makes NPCM7XX Timer to use a the timer clock generated by the > > CLK module instead of the magic number TIMER_REF_HZ. > > > > Reviewed-by: Havard Skinnemoen > > Reviewed-by: Ty

[PATCH] configure: Add flags for MinGW32 standalone build

There are two cases that need to be accounted for when compiling QEMU for MinGW32: 1) A standalone distribution, where QEMU is self contained and extracted by the user, such as a user would download from the QEMU website. In this case, all of the QEMU files should be rooted in $prefix

Re: [PATCH v2 0/4] qemu-timer: Make timer_free() imply timer_del()

On Tue, 15 Dec 2020 at 15:41, Peter Maydell wrote: > > Currently timer_free() is a simple wrapper for g_free(). This means > that the timer being freed must not be currently active, as otherwise > QEMU might crash later when the active list is processed and still > has a pointer to freed memory o

Re: [PATCH v4 5/6] hw/misc: Add QTest for NPCM7XX PWM Module

On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > We add a qtest for the PWM in the previous patch. It proves it works as > expected. > > Reviewed-by: Havard Skinnemoen > Reviewed-by: Tyrone Ting > Signed-off-by: Hao Wu Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v4 6/6] hw/*: Use type casting for SysBusDevice in NPCM7XX

On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > A device shouldn't access its parent object which is QOM internal. > Instead it should use type cast for this purporse. This patch fixes this > issue for all NPCM7XX Devices. > > Signed-off-by: Hao Wu Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v4 3/6] hw/adc: Add an ADC module for NPCM7XX

On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > The ADC is part of NPCM7XX Module. Its behavior is controled by the > ADC_CON register. It converts one of the eight analog inputs into a > digital input and stores it in the ADC_DATA register when enabled. > > Users can alter input value by using qo

Re: [PULL 00/47] tcg patch queue

Patchew URL: https://patchew.org/QEMU/20210107201448.1152301-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210107201448.1152301-1-richard.hender...@linaro.org Subject: [PULL 00/47] tc

Re: [PATCH v4 2/6] hw/timer: Refactor NPCM7XX Timer to use CLK clock

On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > This patch makes NPCM7XX Timer to use a the timer clock generated by the > CLK module instead of the magic number TIMER_REF_HZ. > > Reviewed-by: Havard Skinnemoen > Reviewed-by: Tyrone Ting > Signed-off-by: Hao Wu > --- > hw/arm/npcm7xx.c

Re: Plugin Register Accesses

On Jan 07 16:49, Alex Bennée wrote: > > Aaron Lindsay writes: > > > On Dec 08 14:44, Aaron Lindsay wrote: > >> On Dec 08 17:56, Alex Bennée wrote: > >> > Aaron Lindsay writes: > >> > > On Dec 08 12:17, Alex Bennée wrote: > >> > >> Aaron Lindsay writes: > >> > >> Memory is a little trickier b

[PATCH] target/s390x: Fix ALGSI

Looks like something went wrong while touching that line. Instead of "r1" we need a new temporary. Also, we have to pass MO_TEQ, to indicate that we are working with 64-bit values. Let's revert these changes. Fixes: ff26d287bddc ("target/s390x: Improve cc computation for ADD LOGICAL") Signed-off-b

[PULL 41/47] accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd

Re-use the 256MiB region handling from alloc_code_gen_buffer_anon, and replace that with the shared file mapping. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 46 --- 1 file changed, 38 insertions(+), 8 deletions(-) diff --git a/accel/tcg/

Re: [PATCH v4 1/6] hw/misc: Add clock converter in NPCM7XX CLK module

On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > This patch allows NPCM7XX CLK module to compute clocks that are used by > other NPCM7XX modules. > > Add a new struct NPCM7xxClockConverterState which represents a > single converter. Each clock converter in CLK module represents one > converter in

[PULL 42/47] tcg/mips: Do not assert on relocation overflow

This target was not updated with 7ecd02a06f8, and so did not allow re-compilation with relocation overflow. Remove reloc_26 and reloc_26_val as unused. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 53 ++- 1 file changed, 19 insertions(+),

Re: [PATCH v2 05/24] target/arm: Fix SCTLR_B test for TCGv_i64 load/store

On 1/7/21 6:00 AM, Peter Maydell wrote: > On Tue, 8 Dec 2020 at 18:01, Richard Henderson > wrote: >> >> Just because operating on a TCGv_i64 temporary does not >> mean that we're performing a 64-bit operation. Restrict >> the frobbing to actual 64-bit operations. > > If I understand correctly, t

[PULL 38/47] tcg/riscv: Fix branch range checks

The offset even checks were folded into the range check incorrectly. By offsetting by 1, and not decrementing the width, we silently allowed out of range branches. Assert that the offset is always even instead. Move tcg_out_goto down into the CONFIG_SOFTMMU block so that it is not unused. Review

[PULL 37/47] tcg/s390: Support split-wx code generation

Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.c.inc | 69 +-- 2 files changed, 31 insertions(+), 40 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index b8f4296e4b..4edcb06044 100644 --- a/

[PULL 43/47] tcg/mips: Support split-wx code generation

Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 +- tcg/mips/tcg-target.c.inc | 43 ++- 2 files changed, 25 insertions(+), 20 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index fbfe775fb4..ed5c347374 100644 --- a/

[PULL 40/47] tcg/riscv: Support split-wx code generation

Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 +- tcg/riscv/tcg-target.c.inc | 41 +- 2 files changed, 24 insertions(+), 19 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 62

[PULL 36/47] tcg/s390: Use tcg_tbrel_diff

Use tcg_tbrel_diff when we need a displacement to a label, and with a NULL argument when we need the normalizing addend. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c.inc | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/s390/tcg-target.c.inc b

[PULL 28/47] disas: Push const down through host disassembly

Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/disas/dis-asm.h | 4 ++-- disas.c | 4 +--- disas/capstone.c| 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/include/disas/dis-asm.h b/incl

[PULL 46/47] tcg: Constify tcg_code_gen_epilogue

Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h| 2 +- tcg/tcg.c| 2 +- tcg/aarch64/tcg-target.c.inc | 3 +-- tcg/arm/

[PULL 39/47] tcg/riscv: Remove branch-over-branch fallback

Since 7ecd02a06f8, we are prepared to re-start code generation with a smaller TB if a relocation is out of range. We no longer need to leave a nop in the stream Just In Case. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 56

[PULL 27/47] tcg/aarch64: Support split-wx code generation

Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.c.inc | 57 2 files changed, 33 insertions(+), 26 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h ind

[PULL 47/47] tcg: Constify TCGLabelQemuLdst.raddr

Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 3 +-- tcg/arm/tcg-target.c.inc | 3 +-- tcg/i386/tcg-target.c.inc| 3 +-- tcg/mi

[PULL 32/47] tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB

The maximum TB code gen size is UINT16_MAX, which the current code does not support. Use our utility function to optimally add an arbitrary constant. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tc

[PULL 35/47] tcg/sparc: Support split-wx code generation

Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.h | 2 +- tcg/sparc/tcg-target.c.inc | 24 +--- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 6f6cefaa15..6426e24f17 100644 --- a/tcg/sparc/t

[PULL 26/47] tcg/aarch64: Use B not BL for tcg_out_goto_long

A typo generated a branch-and-link insn instead of plain branch. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index f

[PULL 33/47] tcg/ppc: Support split-wx code generation

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.c.inc | 53 +++- 2 files changed, 31 insertions(+), 24 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index ba61a31b3e..ec51f474a7 100644 --- a/tcg

[PULL 31/47] tcg/ppc: Use tcg_tbrel_diff

Use tcg_tbrel_diff when we need a displacement to a label, and with a NULL argument when we need the normalizing addend. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-

[PULL 25/47] tcg/i386: Support split-wx code generation

Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 20 +++- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 73aa45a665..cb1b138b66 10

[PULL 29/47] tcg/tci: Push const down through bytecode reading

Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 60 +++ 1 file changed, 34 insertions(+), 26 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 017887bbc9..2bcc4409be 100644

[PULL 21/47] tcg: Add --accel tcg,split-wx property

Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend, so for now enabling it will result in an error. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- include/sysemu/tcg.h | 3 ++- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-

[PULL 30/47] tcg: Introduce tcg_tbrel_diff

Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 13 + 1 file changed, 13 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e744a1ce02..e6fce9a049 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1146,6 +1146,19 @@

[PULL 22/47] accel/tcg: Support split-wx for linux with memfd

We cannot use a real temp file, because we would need to find a filesystem that does not have noexec enabled. However, a memfd is not associated with any filesystem. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 84 +++

[PULL 23/47] accel/tcg: Support split-wx for darwin/iOS with vm_remap

Cribbed from code posted by Joelle van Dyne , and rearranged to a cleaner structure. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 67 +++ 1 file changed, 67 insertions(+) diff --git a/accel/tcg/translate-all.c

[PULL 14/47] tcg: Adjust tcg_out_call for const

We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c| 2 +- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +-

[PULL 45/47] tcg: Remove TCG_TARGET_SUPPORT_MIRROR

Now that all native tcg hosts support splitwx, remove the define. Replace the one use with a test for CONFIG_TCG_INTERPRETER. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - t

[PULL 19/47] tcg: Make tb arg to synchronize_from_tb const

There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx region. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Ri

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