On 12/18/20 12:37 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> Signed-off-by: Rémi Denis-Courmont
> ---
> target/arm/helper.c | 25 +++--
> 1 file changed, 11 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/18/20 12:37 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> The stage_1_mmu_idx() already effectively keeps track of which
> translation regimes have two stages. Don't hard-code another test.
>
> Signed-off-by: Rémi Denis-Courmont
> ---
> target/arm/helper.c |
On 12/18/20 12:37 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> Signed-off-by: Rémi Denis-Courmont
> ---
> target/arm/cpu.h| 7 +++
> target/arm/helper.c | 24
> 2 files changed, 31 insertions(+)
Reviewed-by: Richard Henderson
On 12/18/20 12:37 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> Signed-off-by: Rémi Denis-Courmont
> ---
> target/arm/helper.c | 12
> 1 file changed, 12 insertions(+)
Reviewed-by: Richard Henderson
r~
On 12/18/20 12:37 AM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in
> secure mode, though it can only be AArch64.
>
> This patch adds the target EL for exceptions from 64-bit S-EL2.
>
> It also fixes the
The crypto overhead of emulating pauth can be significant for
some workloads. Add two boolean properties that allows the
feature to be turned off, on with the architected algorithm,
or on with an implementation defined algorithm.
We need two intermediate booleans to control the state while
On 1/7/21 11:08 PM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> This adds for the Small Translation tables extension in AArch64 state.
>
> Signed-off-by: Rémi Denis-Courmont
> ---
> target/arm/cpu.h| 5 +
> target/arm/helper.c | 15 +--
> 2 files
On 1/7/21 11:08 PM, remi.denis.courm...@huawei.com wrote:
> From: Rémi Denis-Courmont
>
> Signed-off-by: Rémi Denis-Courmont
> ---
> target/arm/cpu64.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
The architected pauth algorithm is quite slow without
hardware support, and boot times for kernels that enable
use of the feature have been significantly impacted.
Version 7 changes:
* Fix rebase error (drjones).
Version 6 changes:
* Rearrange xxhash64 (pmm).
* Add documentation (pmm).
Without hardware acceleration, a cryptographically strong
algorithm is too expensive for pauth_computepac.
Even with hardware accel, we are not currently expecting
to link the linux-user binaries to any crypto libraries,
and doing so would generally make the --static build fail.
So choose XXH64
The interface for object_property_add_bool is simpler,
making the code easier to understand.
Reviewed-by: Andrew Jones
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu64.c
On 1/11/21 1:53 PM, Andrew Jones wrote:
>> -"kvm-no-adjvtime", "kvm-steal-time",
>> +"kvm-no-adjvtime",
> Looks like a rebase error; kvm-steal-time is getting dropped.
>
Whoops. Will fix.
r~
On Mon, Jan 11, 2021 at 01:11:07PM -1000, Richard Henderson wrote:
> The crypto overhead of emulating pauth can be significant for
> some workloads. Add two boolean properties that allows the
> feature to be turned off, on with the architected algorithm,
> or on with an implementation defined
On 1/11/21 11:35 PM, Eduardo Habkost wrote:
> On Mon, Jan 11, 2021 at 05:13:27PM +0100, Claudio Fontana wrote:
>> Happy new year,
>
> Hi!
>
>>
>> picking up this topic again, i am looking at at now a different aspect of
>> this problem, of setting the right tcg ops for the right cpu class.
>>
Without hardware acceleration, a cryptographically strong
algorithm is too expensive for pauth_computepac.
Even with hardware accel, we are not currently expecting
to link the linux-user binaries to any crypto libraries,
and doing so would generally make the --static build fail.
So choose XXH64
The architected pauth algorithm is quite slow without
hardware support, and boot times for kernels that enable
use of the feature have been significantly impacted.
Version 6 changes:
* Rearrange xxhash64 (pmm).
* Add documentation (pmm).
r~
Richard Henderson (3):
target/arm: Implement
The crypto overhead of emulating pauth can be significant for
some workloads. Add two boolean properties that allows the
feature to be turned off, on with the architected algorithm,
or on with an implementation defined algorithm.
We need two intermediate booleans to control the state while
The interface for object_property_add_bool is simpler,
making the code easier to understand.
Reviewed-by: Andrew Jones
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu64.c
On Mon, Jan 11, 2021 at 05:13:27PM +0100, Claudio Fontana wrote:
> Happy new year,
Hi!
>
> picking up this topic again, i am looking at at now a different aspect of
> this problem, of setting the right tcg ops for the right cpu class.
>
> This issue I am highlighting is present because
Add documentation for '-machine memory-backend' CLI option and
how to use it.
PS:
While at it add a comment to x-use-canonical-path-for-ramblock-id,
to make sure it won't go away by accident.
Signed-off-by: Igor Mammedov
---
backends/hostmem.c | 8
qemu-options.hx| 25
+Thomas/Daniel/Peter.
On 1/11/21 10:14 PM, Taylor Simpson wrote:
>> -Original Message-
>> From: Qemu-devel > bounces+tsimpson=quicinc@nongnu.org> On Behalf Of Philippe
>> Mathieu-Daudé
>> Sent: Saturday, January 9, 2021 3:38 PM
>> To: Taylor Simpson ; qemu-devel@nongnu.org
>> Cc:
In commit 34d0831f38fd8 the ppc-uic device was added, with a dcr-base
property. The intention was that the default value of dcr-base should be
the one that most of our boards need, so that in the common case they
don't need to specify a property value.
All QEMU boards with a UIC use a dcr-base of
11.01.2021 19:08, Alberto Garcia wrote:
On Sat 09 Jan 2021 01:58:11 PM CET, Vladimir Sementsov-Ogievskiy wrote:
Keep setting ret close to setting errp and don't merge different error
paths into one. This way it's more obvious that we don't return
error without setting errp.
Signed-off-by:
> -Original Message-
> From: Qemu-devel bounces+tsimpson=quicinc@nongnu.org> On Behalf Of Philippe
> Mathieu-Daudé
> Sent: Saturday, January 9, 2021 3:38 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: a...@rev.ng; Brian Cain ;
> richard.hender...@linaro.org; laur...@vivier.eu
On Mon, 11 Jan 2021 at 19:19, BALATON Zoltan wrote:
>
> On Mon, 11 Jan 2021, Peter Maydell wrote:
> > In commit 0270d74ef8862350 we switched from ppcuic_init() to directly
> > creating the UIC device, but I missed that the Bamboo's UIC has a
> > non-standard DCR base register value (0xc0 rather
It is not safe to pretend that emulated NVDIMM supports
persistence while backend actually failed to enable it
and used non-persistent mapping as fall back.
Instead of falling-back, QEMU should be more strict and
error out with clear message that it's not supported.
So if user asks for persistence
I know it does not answer your question directly, but you might find useful to
take a look at the solution used in the xPack QEMU Arm (formerly GNU ARM
Eclipse QEMU).
In this fork I dynamically create the peripheral registers when QEMU starts, by
reading a JSON file, converted from the CMSIS
On Mon, Jan 11, 2021 at 6:34 PM Thomas Huth wrote:
>
> The mingw-w64-x86_64-python-sphinx-2.3.1 package has been removed from
> the server, so the windows_msys2_task is currently failing. Replace the
> old version with the current generic one to fix the issue (the current
> version seems to work
On Tue, Jan 12, 2021 at 2:02 AM Jag Raman wrote:
>
>
>
> > On Jan 11, 2021, at 12:20 AM, 罗勇刚(Yonggang Luo)
wrote:
> >
> > I have a question, does this support/test on Windows?
>
> Hi Yonggang, we have not tested this on Windows. The project only builds
on Linux for now.
>
> Thank you!
I may
On Mon, 11 Jan 2021, Luc Michel wrote:
Hi,
We would like to work on improving QEMU to be able to create custom machines
from the command line. The goal here is to get feedback from the community
and shape the future developments.
The use case mainly comes from people working with tools to
On Mon, Jan 11, 2021 at 05:59:14PM +0100, Cornelia Huck wrote:
> On Tue, 5 Jan 2021 12:41:25 -0800
> Ram Pai wrote:
>
> > On Tue, Jan 05, 2021 at 11:56:14AM +0100, Halil Pasic wrote:
> > > On Mon, 4 Jan 2021 10:40:26 -0800
> > > Ram Pai wrote:
>
> > > > The main difference between my proposal
On Mon, 11 Jan 2021, Peter Maydell wrote:
In commit 0270d74ef8862350 we switched from ppcuic_init() to directly
creating the UIC device, but I missed that the Bamboo's UIC has a
non-standard DCR base register value (0xc0 rather than the default
of 0x30). This made Linux panic early in the boot
On Mon, 11 Jan 2021 16:59:54 +0200
Marian Posteuca wrote:
> Igor Mammedov writes:
>
> > overall looks good.
> > Please add a test case for it, see
> > tests/qtest/bios-tables-test.c for description how to do it
> > an/or at
> > "[PATCH v3 08/12] tests/acpi: allow updates for expected data
Hi:
Sorry to bother you~
I have read the discussions about CVE--2019-12928 (
https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg01153.html).
But, for the scenario of PC users, which is no requirement of network access to
QMP, there are some mitigating proposes.
I want to have your
On Sat, 12 Dec 2020, Peter Maydell wrote:
Switch the ppc405_uc boards to directly creating and configuring the
UIC, rather than doing it via the old ppcuic_init() helper function.
We retain the API feature of ppc405ep_init() where it passes back
something allowing the callers to wire up devices
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7765c15e0c..ec8e488b11 100644
--- a/target/arm/translate-a64.c
On Sat, 12 Dec 2020, Peter Maydell wrote:
Switch the virtex_ml507 board to directly creating and
configuring the UIC, rather than doing it via the old
ppcuic_init() helper function.
This fixes a trivial Coverity-detected memory leak where
we were leaking the array of IRQs returned by
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7f37f8bb12..296cd430ab 100644
---
In the case of gpr load, merge the size and is_signed arguments;
otherwise, simply convert size to memop.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 78 --
1 file changed, 33 insertions(+), 45 deletions(-)
Hi:
Sorry to bother you~
I have read the discussions about CVE--2019-12928 (
https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg01153.html).
But, for the scenario of PC users, which is no requirement of network access to
QMP, there are some mitigating proposes.
1. Modify the
For 128-bit load/store, use 16-byte alignment. This
requires that we perform the two operations in the
correct order so that we generate the alignment fault
before modifying memory.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 42
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-neon.c.inc | 48 -
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index e706c37c80..a02b8369a1
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9255763ea7..7f37f8bb12 100644
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 0c3a6d2121..6125e734af 100644
--- a/target/arm/translate-sve.c
+++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a0d543ec1f..3057d102f2 100644
--- a/target/arm/translate.c
+++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 296cd430ab..7765c15e0c 100644
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index dbe74e2c34..a0d543ec1f 100644
--- a/target/arm/translate.c
+++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ba68d4d7f4..dbe74e2c34 100644
--- a/target/arm/translate.c
+++
Signed-off-by: Richard Henderson
---
v2: Fix alignment for n in {2, 4}.
---
target/arm/translate.h | 1 +
target/arm/translate.c | 15 +
target/arm/translate-neon.c.inc | 37 +
3 files changed, 44 insertions(+), 9 deletions(-)
diff
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-neon.c.inc | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 9c2b076027..e706c37c80 100644
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-vfp.c.inc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 10766f210c..f50afb23e7 100644
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-vfp.c.inc | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index f50afb23e7..e20d9c7ba6 100644
---
Adjust the interface to match what has been done to the
TCGv_i32 load/store functions.
This is less obvious, because at present the only user of
these functions, trans_VLDST_multiple, also wants to manipulate
the endianness to speed up loading multiple bytes. Thus we
retain an "internal"
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9cc6a9f83d..ba68d4d7f4 100644
--- a/target/arm/translate.c
+++
Create a finalize_memop function that computes alignment and
endianness and returns the final MemOp for the operation.
Split out gen_aa32_{ld,st}_internal_i32 which bypasses any special
handling of endianness or alignment. Adjust gen_aa32_{ld,st}_i32
so that s->be_data is not added by the
Just because operating on a TCGv_i64 temporary does not
mean that we're performing a 64-bit operation. Restrict
the frobbing to actual 64-bit operations.
This bug is not currently visible because all current
users of these two functions always pass MO_64.
Reviewed-by: Peter Maydell
Use this to signal when memory access alignment is required.
This value comes from the CCR register for M-profile, and
from the SCTLR register for A-profile.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 2 ++
target/arm/helper.c|
Buglink: https://bugs.launchpad.net/qemu/+bug/1905356
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Now that these bits have been moved out of tb->flags,
where TBFLAG_ANY was filling from the top, move AM32
to fill from the top, and A32 and M32 to fill from the
bottom. This means fewer changes when adding new bits.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 42
We're about to rearrange the macro expansion surrounding tbflags,
and this field name will be expanded using the bit definition of
the same name, resulting in a token pasting error.
So PSTATE_SS -> PSTATE__SS in the uses, and document it.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h
Now that other bits have been moved out of tb->flags,
there's no point in filling from the top.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
This is the only caller. Adjust some commentary to talk
about SCTLR_B instead of the vanishing function.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 37 -
1 file changed, 16 insertions(+), 21 deletions(-)
diff
We're about to rearrange the macro expansion surrounding tbflags,
and this field name will be expanded using the bit definition of
the same name, resulting in a token pasting error.
So SCTLR_B -> SCTLR__B in the 3 uses, and document it.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h
Now that we have all of the proper macros defined, expanding
the CPUARMTBFlags structure and populating the two TB fields
is relatively simple.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 49 --
target/arm/translate.h | 2 +-
In preparation for splitting tb->flags across multiple
fields, introduce a structure to hold the value(s).
So far this only migrates the one uint32_t and fixes
all of the places that require adjustment to match.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 26
As reported in https://bugs.launchpad.net/bugs/1905356
Changes for v3:
* Move TBFLAG_{A64,A32,M32,AM32} to tb->cs_base, leaving only
TBFLAG_ANY in tb->flags. This solves our current problem of
running out of bits in tb->flags.
* Dropped "Enforce alignment for sve unpredicated LDR/STR";
We're about to split tbflags into two parts. These macros
will ensure that the correct part is used with the correct
set of bits.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 22 +-
target/arm/helper-a64.c| 2 +-
target/arm/helper.c| 85
The encoding of size = 2 and size = 3 had the incorrect decode
for align, overlapping the stride field. This error was hidden
by what should have been unnecessary masking in translate.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/neon-ls.decode | 4 ++--
Hi Richard,
happy new year,
this change of mine breaks with --enable-debug, after your changes related to
"splitrw" in tcg/,
I am a bit at a loss at what could be going wrong.. any hints?
I am getting assertion failures with --enable-debug in make check-tcg,
in particular in tcg/tcg.c:768
On 1/9/21 2:02 PM, Philippe Mathieu-Daudé wrote:
> When decodetree.py was added in commit 568ae7efae7, QEMU was
> using Python 2 which happily reads UTF-8 files in text mode.
> Python 3 requires either UTF-8 locale or an explicit encoding
> passed to open(). Now that Python 3 is required, explicit
On 11/01/2021 17:14, Peter Maydell wrote:
On Sat, Dec 12, 2020 at 12:15:33AM +, Peter Maydell wrote:
Switch the bamboo board to directly creating and configuring the UIC,
rather than doing it via the old ppcuic_init() helper function.
Hopefully reporting this here is okay, I find
On 12/4/20 6:44 AM, David Gibson wrote:
> The kvm_memcrypt_enabled() and kvm_memcrypt_encrypt_data() helper functions
> don't conceptually have any connection to KVM (although it's not possible
> in practice to use them without it).
>
> They also rely on looking at the global KVMState. But the
From: Klaus Jensen
The device uses the BDRV_BLOCK_ZERO flag to determine the "deallocated"
status of logical blocks. Since the zoned namespaces command set
specification defines that logical blocks SHALL be marked as deallocated
when the zone is in the Empty or Offline states, DULBE can only be
On 12/4/20 6:44 AM, David Gibson wrote:
> Currently the "memory-encryption" property is only looked at once we
> get to kvm_init(). Although protection of guest memory from the
> hypervisor isn't something that could really ever work with TCG, it's
> not conceptually tied to the KVM accelerator.
On 1/11/21 5:13 PM, Claudio Fontana wrote:
> On 12/19/20 12:00 AM, Claudio Fontana wrote:
>> On 12/18/20 11:30 PM, Claudio Fontana wrote:
>>> On 12/18/20 10:55 PM, Claudio Fontana wrote:
On 12/18/20 7:04 PM, Claudio Fontana wrote:
> On 12/18/20 7:01 PM, Paolo Bonzini wrote:
>> On
On 12/4/20 6:44 AM, David Gibson wrote:
> From: Greg Kurz
>
> Global properties have an @optional field, which allows to apply a given
> property to a given type even if one of its subclasses doesn't support
> it. This is especially used in the compat code when dealing with the
>
> On Jan 11, 2021, at 12:20 AM, 罗勇刚(Yonggang Luo) wrote:
>
> I have a question, does this support/test on Windows?
Hi Yonggang, we have not tested this on Windows. The project only builds on
Linux for now.
Thank you!
—
Jag
>
> On Mon, Jan 11, 2021 at 1:08 PM Jagannathan Raman
> wrote:
On 1/11/21 6:09 PM, Miroslav Rezanina wrote:
> When using strncpy with lenght equal to size of target array,
Typo "length".
> GCC 11 produce following warning:
>
>warning: '__builtin_strncpy' specified bound 256 equals destination size
> [-Wstringop-truncation]
>
> To prevent this
Philippe Mathieu-Daudé writes:
> The 'running' argument from VMChangeStateHandler does not require
> other value than 0 / 1. Make it a plain boolean.
>
> Signed-off-by: Philippe Mathieu-Daudé
Seems reasonable
Reviewed-by: Alex Bennée
--
Alex Bennée
Philippe Mathieu-Daudé writes:
> runstate_check() returns a boolean. runstate_is_running()
> returns what runstate_check() returns, also a boolean.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
--
Alex Bennée
On Mon, 11 Jan 2021 at 14:06, Thomas Huth wrote:
>
> The following changes since commit 7b09f127738ae3d0e71716cea086fc8f847a5686:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20210108' into staging (2021-01-08
> 15:37:04 +)
>
> are available in the Git
On 1/11/21 5:01 AM, Philippe Mathieu-Daudé wrote:
> Attempt to fix the warning reported by Miroslav using GCC 10:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg771520.html
>
> Philippe Mathieu-Daudé (5):
> tcg/arm: Hoist common argument loads in tcg_out_op()
> tcg/ppc: Hoist common
On Mon, 11 Jan 2021 at 01:11, Nathan Chancellor
wrote:
>
> On Tue, Sep 01, 2020 at 12:40:42PM +0200, Philippe Mathieu-Daudé wrote:
> > We call pci_register_root_bus() to register 4 IRQs with the
> > ppc4xx_pci_set_irq() handler. As it can only be called with
> > values in the [0-4[ range, replace
Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to
"t1 = -v2, t2 = c - v2". This avoids a serial dependency
between t1 and t2.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 1706b7c776..050f3cb0b1 100644
---
We must do this before we adjust tcg_out_movi_i32, lest the
under-the-hood poking that we do for icount be broken.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/gen-icount.h | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff
* Laszlo Ersek (ler...@redhat.com) wrote:
> virtio-fs qualifies as a bootable device minimally under OVMF, but
> currently the necessary "bootindex" property is missing (fw_cfg kernel
> boot notwithstanding).
>
> Add the property. For completeness, add it to the CCW device as well;
> other
The normal movi opcodes are going away. We need something
for TCI to use internally.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 8
tcg/tci.c| 4 ++--
tcg/tci/tcg-target.c.inc | 4 ++--
3 files changed, 12 insertions(+), 4
There are several ways we can expand a vector dup of a 64-bit
element on a 32-bit host.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 97 +++
1 file changed, 97 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5b0e42be91..8f8badb61c
These interfaces have been replaced by tcg_gen_dupi_vec
and tcg_constant_vec.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 4
tcg/tcg-op-vec.c | 20
2 files changed, 24 deletions(-)
diff --git a/include/tcg/tcg-op.h
These are now completely covered by mov from a
TYPE_CONST temporary.
Reviewed-by: Alex Bennée
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 3 ---
tcg/optimize.c | 4
tcg/tcg-op-vec.c | 1 -
tcg/tcg.c
On 11/01/21 17:01, Joshua Watt wrote:
I agree, it was an issue before 5.2 but now we have relocatable
installations. So it would be better to remove all the special casing
of mingw, except that (for backwards compatibility) on mingw bindir
defaults to $prefix instead of $prefix/bin. Then
Improve expand_vec_shi to use sign-extraction for MO_32.
This allows a single VSPLTISB instruction to load all of
the valid shift constants.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 44
1 file changed, 27 insertions(+), 17
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
tcg/tcg-op-gvec.c | 129 ++
tcg/tcg.c | 8 +++
3 files changed, 60 insertions(+), 78 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index eeeb70ad43..504c5e9bb0
Because we now store uint64_t in TCGTemp, we can now always
store the full 64-bit duplicate immediate. So remove the
difference between 32- and 64-bit hosts.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 9 -
tcg/tcg-op-vec.c | 39 ++-
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 13 +--
tcg/tcg-op.c | 227 ---
2 files changed, 109 insertions(+), 131 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 901b19f32a..ed8de045e2 100644
---
These will hold a single constant for the duration of the TB.
They are hashed, so that each value has one temp across the TB.
Not used yet, this is all infrastructure.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 24 -
tcg/optimize.c| 13 ++-
tcg/tcg.c | 224
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 108 ++---
1 file changed, 49 insertions(+), 59 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 49bf1386c7..bda727d5ed 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -178,37
This will reduce the differences between 32-bit and 64-bit hosts,
allowing full 64-bit constants to be created with the same interface.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +-
tcg/tcg.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 49 +++---
1 file changed, 22 insertions(+), 27 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 51580d51a0..e5dc9d0ca9 100644
---
101 - 200 of 362 matches
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