Re: [PATCH v4 00/12] hw/block/nvme: metadata and end-to-end data protection support

On Mon, Mar 01, 2021 at 03:00:35PM +0100, Klaus Jensen wrote: > From: Klaus Jensen > > This is v4 (RFC removed) of a series that adds support for metadata and > end-to-end data protection. > > First, on the subject of metadata, in v1, support was restricted to > extended logical blocks, which

Re: [PATCH v3 2/2] docs: replace insecure /tmp examples in qsd docs

For the series: Reviewed-by: Richard W.M. Jones Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones Read my programming and virtualization blog: http://rwmj.wordpress.com Fedora Windows cross-compiler. Compile Windows programs, test, and build Windows

Re: [PATCH v2 0/7] acpi: Error Record Serialization Table, ERST, support for QEMU

Hi, A friendly request to review and/or provide feedback on this patchset. Thanks, eric From: Eric Devolder Sent: Monday, February 8, 2021 2:58 PM To: m...@redhat.com ; imamm...@redhat.com ; marcel.apfelb...@gmail.com ; pbonz...@redhat.com ; r...@twiddle.net ;

Re: [PATCH 1/2] i386/acpi: fix inconsistent QEMU/OVMF device paths

On Mon, 1 Mar 2021 17:28:05 +0100 Laszlo Ersek wrote: > On 03/01/21 17:14, Michael S. Tsirkin wrote: > > On Mon, Mar 01, 2021 at 02:28:19PM +0100, Igor Mammedov wrote: > > >> How about: > >> * buggy ACPI for 5.1 machine types and older > >> * fixed ACPI for 5.2 and newer? > > > >

Re: [PATCH] pcnet: switch to use qemu_receive_packet() for loopback

On 3/1/21 4:33 PM, Alexander Bulekov wrote: > This patch switches to use qemu_receive_packet() which can detect > reentrancy and return early. > > Buglink: https://bugs.launchpad.net/qemu/+bug/1917085 > Signed-off-by: Alexander Bulekov > --- > > Here's another one, that looks like the same

[Bug 1913341] Re: Chardev behavior breaks polling based devices

** Changed in: qemu Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1913341 Title: Chardev behavior breaks polling based devices Status in QEMU: Fix Committed

[Bug 1913344] Re: Exynos4210 UART peripheral data loss

** Changed in: qemu Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1913344 Title: Exynos4210 UART peripheral data loss Status in QEMU: Fix Committed Bug

[PATCH v2 1/1] i386: Add support for AMD new-style boot mechanism.

This introduces a new generic-loader setting "csbaseaddr" that allows you to set the segment base address of CS. Signed-off-by: Danny Milosavljevic --- hw/core/generic-loader.c | 6 +- include/hw/core/cpu.h| 1 + include/hw/core/generic-loader.h | 1 +

[PATCH v2 0/1] Add support for AMD new-style boot mechanism.

A lot of AMD CPUs boot the bootstrap processor using a new mechanism. According to https://doc.coreboot.org/soc/amd/family17h.html [1] that means that the flash header specifies a destination and size in RAM (!), and the bootstrap processor will start using a CS segment descriptor set up in such

[Bug 1914117] Re: Short files returned via FTP on Qemu with various architectures and OSes

libslirp now has a workaround for this in slirp.c. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1914117 Title: Short files returned via FTP on Qemu with various architectures and OSes Status

[PATCH] cadence_gem: switch to use qemu_receive_packet() for loopback

This patch switches to use qemu_receive_packet() which can detect reentrancy and return early. Signed-off-by: Alexander Bulekov --- hw/net/cadence_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 9a4474a084..1c576a130c

[PATCH] lan9118: switch to use qemu_receive_packet() for loopback

This patch switches to use qemu_receive_packet() which can detect reentrancy and return early. Signed-off-by: Alexander Bulekov --- I think this is the last one that directly calls its own receive function to do loopback (or the last one within my grepping capapbilities). -Alex

[PATCH] vfio-ccw: Do not read region ret_code after write

A pwrite() call returns the number of bytes written (or -1 on error), and vfio-ccw compares this number with the size of the region to determine if an error had occurred or not. If they are equal, the code reads the ret_code field from the region. However, while the kernel sets the ret_code field

Re: [PATCH v2 02/42] esp: rename existing ESP QOM type to SYSBUS_ESP

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > The existing ESP QOM type currently represents a sysbus device with an > embedded > ESP state. Rename the type to SYSBUS_ESP accordingly. > > Signed-off-by: Mark Cave-Ayland > --- > hw/dma/sparc32_dma.c | 4 ++-- > hw/m68k/q800.c| 4

Re: [PATCH 1/2] i386/acpi: fix inconsistent QEMU/OVMF device paths

I provided the initial version of the patch to the mailing list: [PATCH] i386/acpi: restore device paths for pre-5.1 vms Unfortunately I do not have easy access to a VM where I can test it at the moment. Please make sure that it works for you and reply with `Tested-by`. Thanks, Vitaly > 1

Re: [PATCH 1/2] i386/acpi: fix inconsistent QEMU/OVMF device paths

On Mon, 1 Mar 2021 15:27:38 +0100 Thomas Lamprecht wrote: > On 01.03.21 15:20, Igor Mammedov wrote: > > On Mon, 1 Mar 2021 08:45:53 +0100 > > Thomas Lamprecht wrote: > >> On 01.03.21 08:20, Michael S. Tsirkin wrote: > >>> There are various testing efforts the reason this got undetected is >

Re: [PATCH 1/2] acpi: Move setters/getters of oem fields to X86MachineState

On Sun, 21 Feb 2021 02:17:36 +0200 Marian Postevca wrote: > The code that sets/gets oem fields is duplicated in both PC and MICROVM > variants. This commit moves it to X86MachineState so that all x86 > variants can use it and duplication is removed. > > Signed-off-by: Marian Postevca nice

[PATCH v2 04/17] cpu: Directly use cpu_write_elf*() fallback handlers in place

No code directly accesses CPUClass::write_elf*() handlers out of hw/core/cpu.c (the rest are assignation in target/ code): $ git grep -F -- '->write_elf' hw/core/cpu.c:157:return (*cc->write_elf32_qemunote)(f, cpu, opaque); hw/core/cpu.c:171:return (*cc->write_elf32_note)(f, cpu,

[PATCH v2 16/17] cpu: Restrict cpu_paging_enabled / cpu_get_memory_mapping to sysemu

Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 960846d2b64..d99d3c830dc 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -427,6 +427,8 @@

[PATCH v2 03/17] cpu: Introduce cpu_virtio_is_big_endian()

Introduce the cpu_virtio_is_big_endian() generic helper to avoid calling CPUClass internal virtio_is_big_endian() one. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 9 + hw/core/cpu.c | 8 ++-- hw/virtio/virtio.c| 4 +--- 3 files changed, 16

RE: [PATCH 0/4] hexagon: Add Docker image & testing to gitlab-ci

> -Original Message- > From: Philippe Mathieu-Daudé On > Behalf Of Philippe Mathieu-Daudé > Sent: Sunday, February 28, 2021 4:23 PM > To: qemu-devel@nongnu.org > Cc: Fam Zheng ; Taylor Simpson > ; Philippe Mathieu-Daudé ; > Alex Bennée ; Alessandro Di Federico > ; Brian Cain ; Philippe

RE: [PATCH 1/4] docker: Add Hexagon image

Reviewed-by: Brian Cain > -Original Message- > From: Philippe Mathieu-Daudé On > Behalf Of Philippe Mathieu-Daudé > Sent: Sunday, February 28, 2021 4:23 PM > To: qemu-devel@nongnu.org > Cc: Fam Zheng ; Taylor Simpson > ; Philippe Mathieu-Daudé ; > Alex Bennée ; Alessandro Di Federico >

Re: [PATCH v2 12/42] esp: remove dma_counter from ESPState

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > The value of dma_counter is set once at the start of the transfer and remains > the same until the transfer is complete. This allows the check in > esp_transfer_data > to be simplified since dma_left will always be non-zero until the transfer is

[PATCH v2 02/17] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs

To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 33 - hw/core/cpu.c | 32

[PATCH v2 08/17] cpu: Move CPUClass::vmsd to SysemuCPUOps

Migration is specific to system emulation. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 2 -- include/hw/core/sysemu-cpu-ops.h | 4 cpu.c| 18 -- target/alpha/cpu.c | 2 +- target/arm/cpu.c

Re: [PATCH v2 14/42] esp: remove minlen restriction in handle_ti

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > The limiting of DMA transfers to the maximum size of the available data is > already > handled by esp_do_dma() and do_dma_pdma_cb(). > > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c | 12 ++-- > 1 file changed, 2

[PATCH v2 14/17] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 3 --- include/hw/core/sysemu-cpu-ops.h | 5 + hw/core/cpu.c| 4 ++-- target/i386/cpu.c| 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h

Re: [PATCH v2 15/42] esp: introduce esp_pdma_read() and esp_pdma_write() functions

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c | 28 > 1 file changed, 20 insertions(+), 8 deletions(-) > > diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c > index e7cf36f4b8..b0cba889a9 100644 > ---

[PATCH 1/2] block: Clarify error messages pertaining to 'node-name'

Reported-by: Tingting Mao Fixes: https://bugzilla.redhat.com/1651437 Signed-off-by: Connor Kuehl --- block.c| 8 tests/qemu-iotests/040 | 4 ++-- tests/qemu-iotests/249.out | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/block.c b/block.c

Re: [PATCH v2 03/42] esp: QOMify the internal ESP device state

Le 15/02/2021 à 23:29, Mark Cave-Ayland a écrit : > On 12/02/2021 18:51, Philippe Mathieu-Daudé wrote: > >> On 2/9/21 8:29 PM, Mark Cave-Ayland wrote: >>> Make this new QOM device state a child device of both the sysbus-esp and >>> esp-pci >>> implementations. >>> >>> Signed-off-by: Mark

Re: [PATCH v2 08/42] esp: determine transfer direction directly from SCSI phase

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > The transfer direction is currently determined by checking the sign of ti_size > but as this series progresses ti_size can be zero at the end of the transfer. > > Use the SCSI phase to determine the transfer direction as used in other SCSI >

Re: [PATCH v2 13/42] esp: remove dma_left from ESPState

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > The ESP device already keeps track of the remaining bytes left to transfer via > its TC (transfer counter) register which is decremented for each byte that > is transferred across the SCSI bus. > > Switch the transfer logic to use the value of

[PATCH v2 11/17] cpu: Move CPUClass::write_elf* to SysemuCPUOps

The write_elf*() handlers are used to dump vmcore images. This feature is only meaningful for system emulation. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 17 - include/hw/core/sysemu-cpu-ops.h | 24 hw/core/cpu.c

Re: [PATCH v2 17/42] esp: move pdma_len and TC logic into esp_pdma_read()/esp_pdma_write()

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c | 50 -- > 1 file changed, 32 insertions(+), 18 deletions(-) > > diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c > index cfeba2feb0..7134c0aff4

Re: [PATCH v2 01/42] esp: checkpatch fixes

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > Signed-off-by: Mark Cave-Ayland > Reviewed-by: Philippe Mathieu-Daudé > --- > hw/scsi/esp.c | 52 ++- > 1 file changed, 31 insertions(+), 21 deletions(-) > > diff --git a/hw/scsi/esp.c

Re: [PATCH v2 09/42] esp: introduce esp_get_tc() and esp_set_tc()

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > This simplifies reading and writing the TC register value without having to > manually shift each individual 8-bit value. > > Signed-off-by: Mark Cave-Ayland > Reviewed-by: Philippe Mathieu-Daudé > --- > hw/scsi/esp.c | 38

[PATCH v2 09/17] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps

VirtIO devices are only meaningful with system emulation. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 5 - include/hw/core/sysemu-cpu-ops.h | 8 hw/core/cpu.c| 4 ++-- target/arm/cpu.c | 2 +-

[PATCH v2 12/17] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 3 --- include/hw/core/sysemu-cpu-ops.h | 5 + hw/core/cpu.c| 4 ++-- target/arm/cpu.c | 2 +- target/i386/cpu.c| 2 +- 5 files changed, 9 insertions(+), 7

[PATCH 0/2] Clarify error messages pertaining to 'node-name'

Some error messages contain ambiguous representations of the 'node-name' parameter. This can be particularly confusing when exchanging QMP messages (C = client, S = server): C: {"execute": "block_resize", "arguments": { "device": "my_file", "size": 26843545600 }} S: {"error": {"class":

Re: [PATCH v2 05/42] esp: add trace event when receiving a TI command

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > This enables us to determine whether the command being issued is for a DMA or > a > non-DMA transfer. > > Signed-off-by: Mark Cave-Ayland > Reviewed-by: Philippe Mathieu-Daudé > --- > hw/scsi/esp.c| 1 + > hw/scsi/trace-events | 1 +

[PATCH] target/ppc: fix icount support on Book-e vms accessing SPRs

Failing to guard SPR access with gen_io_start/gen_stop_exception causes "Bad icount read" exceptions when running VMs with e500mc and e500v2 CPUs with an icount parameter. Cc: qemu-devel@nongnu.org Signed-off-by: Vitaly Cheptsov --- target/ppc/translate_init.c.inc | 36

[PATCH v2 07/17] cpu: Introduce SysemuCPUOps structure

Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 5 + include/hw/core/sysemu-cpu-ops.h | 21 + target/alpha/cpu.c | 6 ++ target/arm/cpu.c | 6

Re: [PATCH v2 16/42] esp: use pdma_origin directly in esp_pdma_read()/esp_pdma_write()

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > This is the first step in removing get_pdma_buf() from esp.c. > > Signed-off-by: Mark Cave-Ayland > --- > hw/scsi/esp.c | 34 -- > 1 file changed, 28 insertions(+), 6 deletions(-) > > diff --git a/hw/scsi/esp.c

[PATCH 2/2] blockdev: Clarify error messages pertaining to 'node-name'

Signed-off-by: Connor Kuehl --- blockdev.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/blockdev.c b/blockdev.c index cd438e60e3..7c7ab2b386 100644 --- a/blockdev.c +++ b/blockdev.c @@ -1515,13 +1515,13 @@ static void external_snapshot_prepare(BlkActionState

Re: [PATCH 2/2] acpi: Consolidate the handling of OEM ID and OEM Table ID fields

On Sun, 21 Feb 2021 02:17:37 +0200 Marian Postevca wrote: > Introduces structure AcpiBuildOem to hold the value of OEM fields and > uses dedicated macros to initialize/set the values. > Unnecessary dynamically allocated OEM fields are re-factored to static > allocation. looks fine to me.

Re: [PATCH v2 06/42] esp: fix esp_reg_read() trace event

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > Move the trace event to the end of the function so that it correctly reports > the returned value if it doesn't come directly from the rregs array. > > Signed-off-by: Mark Cave-Ayland > Reviewed-by: Philippe Mathieu-Daudé > --- >

[PATCH v2 10/17] cpu: Move CPUClass::get_crash_info to SysemuCPUOps

cpu_get_crash_info() is called on GUEST_PANICKED events, which only occur in system emulation. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 1 - include/hw/core/sysemu-cpu-ops.h | 5 + hw/core/cpu.c| 4 ++-- target/i386/cpu.c

Re: [PATCH v2 04/42] esp: add vmstate_esp version to embedded ESPState

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > The QOM object representing ESPState is currently embedded within both the > SYSBUS_ESP and PCI_ESP devices with migration state handled by embedding > vmstate_esp within each device using VMSTATE_STRUCT. > > Since the vmstate_esp fields are

Re: [PATCH v2 07/42] esp: add PDMA trace events

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > This will become more useful later when trying to debug mixed FIFO and PDMA > requests. > > Signed-off-by: Mark Cave-Ayland > Reviewed-by: Philippe Mathieu-Daudé > --- > hw/scsi/esp.c| 6 ++ > hw/scsi/trace-events | 4 > 2

RE: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

> -Original Message- > From: Pankaj Gupta > Sent: Monday, March 1, 2021 2:22 PM > To: Moger, Babu > Cc: Pankaj Gupta ; Paolo Bonzini > ; richard.hender...@linaro.org; Eduardo Habkost > ; Qemu Developers > Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation >

Re: [PATCH v4 2/4] util/qemu-sockets.c: Split host:port parsing out of inet_parse

Samuel Thibault, le lun. 01 mars 2021 17:27:47 +0100, a ecrit: > Doug Evans, le lun. 01 mars 2021 08:23:03 -0800, a ecrit: > > On Sun, Feb 28, 2021 at 1:40 PM Samuel Thibault <[1]samuel.thiba...@gnu.org> > > wrote: > > > > [...] > > > Note that one issue I am leaving for later (i.e., I

Re: [PATCH v2 11/42] esp: apply transfer length adjustment when STC is zero at TC load time

Le 09/02/2021 à 20:29, Mark Cave-Ayland a écrit : > Perform the length adjustment whereby a value of 0 in the STC represents > a transfer length of 0x1 at the point where the TC is loaded at the > start of a DMA command rather than just when a TI (Transfer Information) > command is executed.

Re: [PATCH v2 4/5] hw/misc: Add a basic Aspeed LPC controller model

On Mon, 1 Mar 2021, at 11:36, Andrew Jeffery wrote: > From: Cédric Le Goater > > This is a very minimal framework to access registers which are used to > configure the AHB memory mapping of the flash chips on the LPC HC > Firmware address space. > > Signed-off-by: Cédric Le Goater >

[PATCH v2 06/17] cpu: Directly use get_memory_mapping() fallback handlers in place

No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c: $ git grep -F -- '->get_memory_mapping' hw/core/cpu.c:87:cc->get_memory_mapping(cpu, list, errp); hw/core/cpu.c:439:k->get_memory_mapping = cpu_common_get_memory_mapping; target/i386/cpu.c:7422:

[PATCH v2 05/17] cpu: Directly use get_paging_enabled() fallback handlers in place

No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c: $ git grep -F -- '->get_paging_enabled' hw/core/cpu.c:74:return cc->get_paging_enabled(cpu); hw/core/cpu.c:438:k->get_paging_enabled = cpu_common_get_paging_enabled; target/i386/cpu.c:7418:

[RFC PATCH v2 17/17] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c

Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"): We cannot in principle make the SysEmu Operations field definitions conditional on CONFIG_SOFTMMU in code that is included by both common_ss and specific_ss modules. Therefore, what we can

[PATCH v2 15/17] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 2 -- include/hw/core/sysemu-cpu-ops.h | 4 hw/core/cpu.c| 4 ++-- target/i386/cpu.c| 4 +++- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h

RE: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

Pankaj, > -Original Message- > From: Pankaj Gupta > Sent: Monday, March 1, 2021 10:46 AM > To: Pankaj Gupta > Cc: Moger, Babu ; Paolo Bonzini > ; richard.hender...@linaro.org; Eduardo Habkost > ; Qemu Developers > Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd

Re: [PATCH v2 0/2] gitlab-ci.yml: Add jobs to test CFI

Hi Daniel, On 3/1/2021 10:08 AM, Daniel P. Berrangé wrote: What are the unique failure scenarios for CFI that these jobs are likely to expose ? Is it likely that we'll have cases where CFI succeeds in say, x86_64 target, but fails in aarch64 target ? For CFI to fail (even if it shouldn't)

Re: [PATCH v4 2/4] util/qemu-sockets.c: Split host:port parsing out of inet_parse

Samuel Thibault, le lun. 01 mars 2021 17:26:23 +0100, a ecrit: > We could make libslirp enable the IPV6ONLY flag to avoid that, and > make qemu pass an AF_UNSPEC address for the ipv4+ipv6 case, in which > case libslirp wouldn't set IPV6ONLY. Ah, no, AF_UNSPEC would not allow to specify the port.

[PATCH] i386/acpi: restore device paths for pre-5.1 vms

After fixing the _UID value for the primary PCI root bridge in af1b80ae it was discovered that this change updates Windows configuration in an incompatible way causing network configuration failure unless DHCP is used. More details provided on the list:

[PATCH v2 01/17] target: Set CPUClass::vmsd instead of DeviceClass::vmsd

The cpu model is the single device available in user-mode. Since we want to restrict some fields to user-mode emulation, we prefer to set the vmsd field of CPUClass, rather than the DeviceClass one. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 2 +- target/cris/cpu.c

[PATCH v2 00/17] cpu: Introduce SysemuCPUOps structure

Hi, This series is inspired on Claudio TCG work. Instead of separate TCG from other accelerators, here we separate sysemu operations (system VS user). Patches 1-6 are generic cleanups. Patches 7-15 move from CPUClass to SysemuCPUOps Patches 16-17 restrict SysemuCPUOps to sysemu Since v1: -

[PATCH v2 13/17] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h| 8 include/hw/core/sysemu-cpu-ops.h | 13 + hw/core/cpu.c| 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c

Re: [RFC v2 08/24] target/arm: split cpregs from tcg/helper.c

On 3/1/21 8:49 AM, Claudio Fontana wrote: +uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri); +void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value); These shouldn't go in cpu.h; the new cpregs.h seems reasonable. Otherwise, LGTM. r~

[PATCH v3 0/5] aspeed: LPC peripheral controller devices

Hello, This series adds support for some of the LPC[1] peripherals found in Aspeed BMC SoCs. [1] https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf v3 fixes a copy/paste error hooking up the LPC IRQ for the AST2600, identified

[PATCH v3 4/5] hw/misc: Add a basic Aspeed LPC controller model

From: Cédric Le Goater This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery --- docs/system/arm/aspeed.rst | 2 +-

Re: [PATCH 3/5] spapr.c: add 'unplug already in progress' message for PHB unplug

On Fri, Feb 26, 2021 at 01:32:59PM -0300, Daniel Henrique Barboza wrote: > Both CPU hotunplug and PC_DIMM unplug reports an user warning, > mentioning that the hotunplug is in progress, if consecutive > 'device_del' are issued in quick succession. > > Do the same for PHBs in

Re: [PATCH 4/5] spapr_pci.c: add 'unplug already in progress' message for PCI unplug

On Fri, Feb 26, 2021 at 01:33:00PM -0300, Daniel Henrique Barboza wrote: > Hotunplug for all other devices are warning the user when the hotunplug > is already in progress. Do the same for PCI devices in > spapr_pci_unplug_request(). > > Signed-off-by: Daniel Henrique Barboza Applied to

Re: [PATCH 5/5] spapr.c: send QAPI event when memory hotunplug fails

On Fri, Feb 26, 2021 at 01:33:01PM -0300, Daniel Henrique Barboza wrote: > Recent changes allowed the pSeries machine to rollback the hotunplug > process for the DIMM when the guest kernel signals, via a > reconfiguration of the DR connector, that it's not going to release the > LMBs. > > Let's

Re: [PATCH v3 08/16] qapi/expr.py: add type hint annotations

John Snow writes: > On 2/25/21 8:56 AM, Markus Armbruster wrote: >> John Snow writes: >> >>> Annotations do not change runtime behavior. >>> This commit *only* adds annotations. >>> >>> Signed-off-by: John Snow >>> Reviewed-by: Eduardo Habkost >>> Reviewed-by: Cleber Rosa >>> --- >>>

[PATCH v3 2/5] hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet

The datasheet says we have 197 IRQs allocated, and we need more than 128 to describe IRQs from LPC devices. Raise the value now to allow modelling of the LPC devices. Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast2600.c |

[PATCH] block: Change write_threshold to uint64 in BlockDeviceInfo

From: renlei4 write_threshold is saved as uint64, but BlockDeviceInfo use int to describe it. normally it works well if threshold less than max int: # virsh domblkthreshold v6_163 sda 9223372036854775807 # virsh qemu-monitor-command v6_163 '{ "execute": "query-named-block-nodes" }' |grep

Re: [PATCH 2/5] spapr.c: check unplug_request flag in spapr_memory_unplug_request()

On Fri, Feb 26, 2021 at 01:32:58PM -0300, Daniel Henrique Barboza wrote: > Now that we're asserting the first DRC LMB earlier, use it to query if > the DRC is already pending unplug and, in this case, issue the same > error we already do. > > The previous check was introduced in commit

[Bug 1917394] [NEW] command lspci does not show the IVSHMEM device

Public bug reported: qeum version: QEMU emulator version 4.2.1 I met a problem when I tried to use IVSHMEM. Command lspci does not show the IVSHMEM device. Below is the configuration from my side: 1. guest vm xml configuration. 2 2. after the booting up and I

Re: [RFC v2 10/24] target/arm: only perform TCG cpu and machine inits if tcg enabled

On 3/1/21 8:49 AM, Claudio Fontana wrote: @@ -1321,6 +1323,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } } +#ifdef CONFIG_TCG { uint64_t scale; @@ -1346,7 +1349,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

Re: [PATCH] docs: show how to spawn qemu-storage-daemon with fd passing

Daniel P. Berrangé writes: > On Mon, Mar 01, 2021 at 09:49:21AM -0600, Eric Blake wrote: >> On 3/1/21 9:41 AM, Daniel P. Berrangé wrote: >> > On Mon, Mar 01, 2021 at 03:31:59PM +, Stefan Hajnoczi wrote: >> >> The QMP monitor, NBD server, and vhost-user-blk export all support file >> >>

[PATCH v3 1/5] hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC

This appears to be a requirement of the GIC model. The AST2600 allocates 197 GIC IRQs, which we will adjust shortly. Signed-off-by: Andrew Jeffery Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast2600.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [PATCH v3 03/16] qapi/expr.py: constrain incoming expression types

John Snow writes: > On 2/25/21 6:56 AM, Markus Armbruster wrote: >> John Snow writes: >> >>> On 2/24/21 5:01 AM, Markus Armbruster wrote: John Snow writes: > mypy does not know the types of values stored in Dicts that masquerade > as objects. Help the type checker out by

[PATCH] file-posix: allow -EBUSY errors during write zeros on block

After Linux 5.10, write zeros to a multipath device using ioctl(fd, BLKZEROOUT, range) with cache none or directsync will return EBUSY. Similar to handle_aiocb_write_zeroes_unmap, handle_aiocb_write_zeroes_block allow -EBUSY errors during ioctl(fd, BLKZEROOUT, range). Reference commit in Linux

Re: [PATCH v4 0/6] Pegasos2 emulation

On Thu, Feb 25, 2021 at 12:10:55PM -0800, no-re...@patchew.org wrote: > Patchew URL: https://patchew.org/QEMU/cover.1614282456.git.bala...@eik.bme.hu/ > > > > Hi, > > This series seems to have some coding style problems. See output below for > more information: > > Type: series > Message-id:

Re: [PATCH v4 0/6] Pegasos2 emulation

On Thu, Feb 25, 2021 at 08:47:36PM +0100, BALATON Zoltan wrote: > Hello, > > This is adding a new PPC board called pegasos2. More info on it can be > found at: > > https://osdn.net/projects/qmiga/wiki/SubprojectPegasos2 > > Currently it needs a firmware ROM image that I cannot include due to >

Re: [RFC v2 13/24] target/arm: add temporary stub for arm_rebuild_hflags

On 3/1/21 8:49 AM, Claudio Fontana wrote: +#ifdef CONFIG_TCG /* CP15 update requires rebuilding hflags */ arm_rebuild_hflags(_cpu->env); +#endif /* CONFIG_TCG */ ... +/* XXX this is used all over in hw/arm, needs Philippe's work to remove */ +void arm_rebuild_hflags(CPUARMState

Re: [RFC v2 16/24] target/arm: move sve_zcr_len_for_el to common_cpu

On 3/1/21 8:49 AM, Claudio Fontana wrote: it is required by arch-dump.c and cpu.c, so apparently we need this for KVM too? Signed-off-by: Claudio Fontana --- target/arm/cpu-common.c | 33 + target/arm/tcg/helper.c | 33 - 2

Re: [RFC v2 11/24] target/arm: kvm: add stubs for some helpers

On 3/1/21 8:49 AM, Claudio Fontana wrote: --- /dev/null +++ b/target/arm/kvm/helper-stubs.c @@ -0,0 +1,18 @@ +#include "qemu/osdep.h" +#include "cpu.h" Need license boilerplate. Otherwise looks fine. r~

Re: [RFC v2 12/24] target/arm: move cpsr_read, cpsr_write to cpu_common

On 3/1/21 8:49 AM, Claudio Fontana wrote: we need as a result to move switch_mode too, so we put an implementation into cpu_user and cpu_sysemu. Signed-off-by: Claudio Fontana --- target/arm/cpu.h| 2 + target/arm/cpu-common.c | 182 +

Re: [RFC v2 14/24] target/arm: split vfp state setting from tcg helpers

On 3/1/21 8:49 AM, Claudio Fontana wrote: vfp_get_fpsr and vfp_set_fpsr are needed also for KVM. Signed-off-by: Claudio Fontana --- target/arm/cpu-vfp.h | 29 + target/arm/cpu-vfp.c | 92 +++ target/arm/kvm/helper-stubs.c | 10 ++

Re: [PATCH qemu v13] spapr: Implement Open Firmware client interface

On Tue, Feb 23, 2021 at 11:19:38PM +1100, Alexey Kardashevskiy wrote: > > > On 23/02/2021 14:07, David Gibson wrote: > > On Tue, Feb 09, 2021 at 10:02:52PM +1100, Alexey Kardashevskiy wrote: > > > The PAPR platform which describes an OS environment that's presented by > > > a combination of a

Re: [PATCH v2 1/1] qemu_timer.c: add timer_deadline_ms() helper

On Mon, Mar 01, 2021 at 09:41:33AM -0300, Daniel Henrique Barboza wrote: > The pSeries machine is using QEMUTimer internals to return the timeout > in seconds for a timer object, in hw/ppc/spapr.c, function > spapr_drc_unplug_timeout_remaining_sec(). > > Create a helper in qemu-timer.c to

Re: [PATCH qemu v14] spapr: Implement Open Firmware client interface

On Wed, Feb 24, 2021 at 04:41:30PM +1100, Alexey Kardashevskiy wrote: > The PAPR platform which describes an OS environment that's presented by > a combination of a hypervisor and firmware. The features it specifies > require collaboration between the firmware and the hypervisor. > > Since the

Re: [RFC v2 15/24] target/arm: move arm_mmu_idx* to get-phys-addr

On 3/1/21 8:49 AM, Claudio Fontana wrote: Signed-off-by: Claudio Fontana --- target/arm/get-phys-addr.c | 95 ++ target/arm/tcg/helper.c| 95 -- 2 files changed, 95 insertions(+), 95 deletions(-) So...

Re: CI with --enable-debug?

On 01/03/2021 15.06, Markus Armbruster wrote: Today I debugged why Paolo couldn't reproduce an assertion failure I found in review. Turns out compiling with optimization masks it for both of us. This made me wonder whether our CI tests with and without optimization. I quick grep finds

Re: [RFC PATCH] docs/system: add a gentle prompt for the complexity to come

On 01/03/2021 12.27, Alex Bennée wrote: We all know the QEMU command line can become a fiendishly complex beast. Lets gently prepare our user for the horrors to come by referencing where other example command lines can be found in the manual. Signed-off-by: Alex Bennée ---

[PATCH v3 3/5] hw/arm: ast2600: Correct the iBT interrupt ID

The AST2600 allocates distinct GIC IRQs for the LPC subdevices such as the iBT device. Previously on the AST2400 and AST2500 the LPC subdevices shared a single LPC IRQ. Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast2600.c

[PATCH v3 5/5] hw/misc: Model KCS devices in the Aspeed LPC controller

Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC IO cycles from the BMC to the host. Expose support on the BMC side by implementing the usual MMIO behaviours, and expose the ability to inspect the KCS registers in "host" style by accessing QOM properties associated with

Re: [PATCH qemu v14] spapr: Implement Open Firmware client interface

On Tue, Feb 23, 2021 at 09:48:56PM -0800, no-re...@patchew.org wrote: > Patchew URL: https://patchew.org/QEMU/20210224054130.4540-1-...@ozlabs.ru/ > > > > Hi, > > This series seems to have some coding style problems. See output below for > more information: > > Type: series > Message-id:

m...@redhat.com

Hi Team, Sorry for the disturbance. I have to ask for your help since I can't solve the problem by googling. *Below is the problem:* I met a problem when I tried to use IVSHMEM. Command lspci does not show the IVSHMEM device. Below is the configuration from my side: *1. guest vm xml

Re: [PATCH v2 2/5] hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet

On 3/1/21 2:06 AM, Andrew Jeffery wrote: > The datasheet says we have 197 IRQs allocated, and we need more than 128 > to describe IRQs from LPC devices. Raise the value now to allow > modelling of the LPC devices. > > Signed-off-by: Andrew Jeffery > --- > hw/arm/aspeed_ast2600.c | 2 +- > 1

Re: issue with meson and recursion: negation missing in add?

On 2/27/21 11:23 PM, Claudio Fontana wrote: > Hi Paolo, > > I don't know how to handle an issue in the current way we are using meson > with recursion, ie always recursing, > and testing multiple options inside the recursed directory. > > In the case of ARM, we have: > >

Re: [PATCH] gitlab-ci: Disable vhost-kernel in build-disable job

ping? On 1/31/21 11:46 AM, Philippe Mathieu-Daudé wrote: > Commit 299e6f19b3e ("vhost-net: revamp configure logic") added > the --enable-vhost-kernel option. > Disable it in the build-disable job. > > Signed-off-by: Philippe Mathieu-Daudé > --- > .gitlab-ci.yml | 1 + > 1 file changed, 1

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