Excerpts from Cédric Le Goater's message of April 15, 2021 1:24 am:
> On 4/14/21 5:23 AM, Nicholas Piggin wrote:
>> The AIL logic is becoming unmanageable spread all over powerpc_excp(),
>> and it is slated to get even worse with POWER10 support.
>>
>> Move it all to a new helper function.
>
>
Peter Maydell writes:
> On Tue, 13 Apr 2021 at 17:18, Paolo Bonzini wrote:
>>
>> The following changes since commit c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620:
>>
>> Merge remote-tracking branch
>> 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging (2021-04-12
>> 12:12:09 +0100)
>>
This patchset takes the original patch from Maxim,
https://www.mail-archive.com/qemu-devel@nongnu.org/msg569573.html
and updates it.
Option hostfwd is extended to support ipv6 addresses.
Commands hostfwd_add, hostfwd_remove are extended as well.
The libslirp part of the patch has been committed
5eraph (2):
disable_dns option
limit vnameserver_addr to port 53
Akihiro Suda (1):
libslirp.h: fix SlirpConfig v3 documentation
Doug Evans (11):
Add ipv6 host forward support
tcpx_listen: Pass sizeof(addr) to memset
Reject host forwarding to ipv6 "addr-any"
The parsing is moved into new function inet_parse_host_port.
Also split out is ipv4=flag, ipv6=flag processing into inet_parse_ipv46.
This is done in preparation for using these functions in net/slirp.c.
Signed-off-by: Doug Evans
---
Changes from v5:
Also split out parsing of ipv4=on|off,
Add Frank, he is the SiFive's qemu maintainer.
On Thu, Apr 15, 2021 at 11:57 AM Alistair Francis wrote:
>
> + LIU Zhiwei and Kito Cheng
>
> Alistair
>
> On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923...@bugs.launchpad.net> wrote:
> >
> > Public bug reported:
> >
> > I noticed doing a negate ( 0
On Thu, Apr 15, 2021 at 2:18 PM LIU Zhiwei wrote:
>
> Hi Alistair,
>
> I think that this bug has been resolved in my packed-extension patch set[1].
>
> Would you mind to have a test and merge it before the whole patch set?
Great! Thanks
I have applied patch 3 for the next PR.
Alistair
>
>
Excerpts from Cédric Le Goater's message of April 15, 2021 1:54 am:
> On 4/14/21 5:23 AM, Nicholas Piggin wrote:
>> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
>> and it removes support for the LPCR[AIL]=0b10 mode.
>
> This looks good but it's missing the MSR_LE setting.
Hi Eric,
On 2021/4/14 16:05, Auger Eric wrote:
Hi Kunkun,
On 4/14/21 3:45 AM, Kunkun Jiang wrote:
On 2021/4/13 20:57, Auger Eric wrote:
Hi Kunkun,
On 4/13/21 2:10 PM, Kunkun Jiang wrote:
Hi Eric,
On 2021/4/11 20:08, Eric Auger wrote:
In nested mode, legacy vfio_iommu_map_notify cannot be
On Tue, Apr 13, 2021 at 3:44 AM Vijai Kumar K wrote:
>
> Add documentation for Shakti C reference platform.
>
> Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Alistair
> ---
> docs/system/riscv/shakti-c.rst | 82 ++
> 1 file changed, 82
The AIL logic is becoming unmanageable spread all over powerpc_excp(),
and it is slated to get even worse with POWER10 support.
Move it all to a new helper function.
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_hcall.c|
Net option "-hostfwd" now supports IPv6 addresses.
Commands hostfwd_add, hostfwd_remove now support IPv6 addresses.
Tested:
avocado run tests/acceptance/hostfwd.py
Signed-off-by: Doug Evans
---
Changes from v5:
Recognize ipv4=,ipv6= options.
hmp-commands.hx | 18 ++-
+ LIU Zhiwei and Kito Cheng
Alistair
On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923...@bugs.launchpad.net> wrote:
>
> Public bug reported:
>
> I noticed doing a negate ( 0 – 0x8000 ) using vssub.vv produces an
> incorrect result of 0x8000 (should saturate to 0x7FFF).
>
> Here is the
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fourth release candidate for the QEMU 6.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-6.0.0-rc3.tar.xz
Hi Alistair,
I think that this bug has been resolved in my packed-extension patch set[1].
Would you mind to have a test and merge it before the whole patch set?
Thanks.
Best Regards,
Zhiwei
[1]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg782125.html
On 2021/4/15 上午11:57,
Hi:
When I tested RDMA live migration, I found that the downtime increased as the
VM's memory increased.
My Mellanox network card is [ConnectX-4 LX] and the driver is MLNX-5.2, My VM
memory size is 64GB, downtime is 430ms when I migrate using the following
parameters:
virsh migrate --live
Thanks for raising this bug case. A fix should be available soon.
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https://bugs.launchpad.net/bugs/1923629
Title:
RISC-V Vector Instruction vssub.vv not saturating
Status in QEMU:
I'm guessing that this is a bug in your guest as it hasn't configured
PMP regions.
>From the RISC-V spec:
"
If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry
matches an
S-mode or U-mode access, but at least one PMP entry is implemented, the access
fails.
"
You can check this by reverting this QEMU commit:
commit d102f19a2085ac931cb998e6153b73248cca49f1
Author: Atish Patra
Date: Wed Dec 23 11:25:53 2020 -0800
target/riscv/pmp: Raise exception if no PMP entry is configured
As per the privilege specification, any access from S/U mode
... in preparation for adding ipv6 host forwarding support.
Tested:
avocado run tests/acceptance/hostfwd.py
Signed-off-by: Doug Evans
---
Changes from v5:
Use InetSocketAddress and getaddrinfo().
Use new libslirp calls: slirp_remove_hostxfwd, slirp_add_hostxfwd.
include/qemu/sockets.h
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_hcall.c| 7 -
target/ppc/cpu-qom.h|
ISA v3.0 radix guest execution has a quirk in AIL behaviour such that
the LPCR[AIL] value can apply to hypervisor interrupts.
This affects machines that emulate HV=1 mode (i.e., powernv9).
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 17 +
1 file changed, 13
This must have slipped through the cracks between adding POWER10 support
and scv support.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate_init.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
Here's a rollup of where this ended up, hopefully it suits everyone's
preference. Thanks for the review and catching several issues.
Patches 1-3 are unchanged except for minor comment and changelog tweaks,
patch 4 contains fixes for the issues Cedric noticed.
Thanks,
Nick
Nicholas Piggin (4):
On Wed, Apr 14, 2021 at 12:43 PM Richard Henderson
wrote:
>
> On 4/14/21 11:03 AM, Max Filippov wrote:
> > On Wed, Apr 14, 2021 at 9:51 AM Ilya Leoshkevich wrote:
> >> On Wed, 2021-04-14 at 16:48 +0200, David Hildenbrand wrote:
> >>> Did you double-check the xtensa issue?
> >>
> >> Oh, I'm
On Wed, Apr 14, 2021 at 5:35 PM Bin Meng wrote:
>
> Hi Alistair,
>
> On Tue, Apr 13, 2021 at 10:42 AM Alistair Francis
> wrote:
> >
> > From: Hou Weiying
> >
> > This commit adds support for ePMP v0.9.1.
> >
> > The ePMP spec can be found in:
> >
On Tue, Apr 13, 2021 at 1:28 PM LIU Zhiwei wrote:
>
> ping +1.
>
> On 2021/2/12 下午11:02, LIU Zhiwei wrote:
> > This patchset implements the packed extension for RISC-V on QEMU.
> >
> > This patchset have passed all my direct Linux user mode cases(RV64) and
> > bare metal cases(RV32) on X86-64
On 2021/4/15 下午12:46, Alistair Francis wrote:
On Tue, Apr 13, 2021 at 1:28 PM LIU Zhiwei wrote:
ping +1.
On 2021/2/12 下午11:02, LIU Zhiwei wrote:
This patchset implements the packed extension for RISC-V on QEMU.
This patchset have passed all my direct Linux user mode cases(RV64) and
bare
On Fri, 9 Apr 2021 15:54:47 +
Eric DeVolder wrote:
> Hi Igor,
> Thank you for reviewing. I've responded inline below.
> eric
>
>
> From: Igor Mammedov
> Sent: Tuesday, April 6, 2021 2:31 PM
> To: Eric DeVolder
> Cc: m...@redhat.com ;
Please install debuginfo and run "p *ctx" in GDB from the
aio_ctx_finalize frame. That should show ctx->scheduled_coroutines,
ctx->bh_slice_list, etc.
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As java -version passes few times, further also checked behaviour of Maven.
Observed that mvn -v crashes in a similar fashion, however after setting below:
export MAVEN_OPTS="-XX:-TieredCompilation -XX:+UseG1GC -Dcount=100"
mvn -v always passes.
root@XX:/# mvn -v
OpenJDK 64-Bit Server VM
On 4/14/21 10:19 AM, Thomas Huth wrote:
> For some reasons, the "cc" symlink is missing in Ubuntu 20.04.
> Add it manually.
>
> Signed-off-by: Thomas Huth
> ---
> tests/docker/dockerfiles/ubuntu2004.docker | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git
On Wed, 14 Apr 2021 12:39:36 +0200
Cornelia Huck wrote:
> On Wed, 14 Apr 2021 12:27:03 +0200
> Ilya Leoshkevich wrote:
>
> > On Wed, 2021-04-14 at 11:19 +0200, Ilya Leoshkevich wrote:
> > > On Wed, 2021-04-14 at 10:38 +0200, Cornelia Huck wrote:
> > > > On Tue, 13 Apr 2021 18:52:57 +0200
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/meson.build| 3 +++
target/arm/tcg/sysemu/meson.build | 2 ++
target/arm/tcg/user/meson.build | 2 ++
3 files changed, 7 insertions(+)
create mode 100644 target/arm/tcg/sysemu/meson.build
create mode
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-common.c | 41 +
target/arm/tcg/helper.c | 29 -
target/arm/meson.build | 1 +
3 files changed, 42 insertions(+), 29 deletions(-)
create mode
we need as a result to move switch_mode too,
so we put an implementation into cpu_user and cpu_sysemu.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu.h| 2 +
target/arm/cpu-common.c | 192 +++
target/arm/cpu-sysemu.c |
move work is needed later on to split things into
tcg-specific portions and kvm-specific portions of this
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/internals.h | 8 ++-
target/arm/cpu-sysemu.c | 105
and arm_phys_excp_target_el since it is tied up inside the
same #ifdef block.
aarch64_sync_32_to_64 and aarch64_sync_64_to_32 are
mixed in with the TCG helpers, but they shouldn't, as they
are needed for KVM too.
kvm_arch_get_registers()
{
if (!is_a64(env)) {
it is required by arch-dump.c and cpu.c, so apparently
we need this for KVM too
Signed-off-by: Claudio Fontana
---
target/arm/cpu-common.c | 43 +
target/arm/tcg/helper.c | 33 ---
2 files changed, 43 insertions(+), 33
After this patch it is possible to build only kvm:
./configure --disable-tcg --enable-kvm
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-sysemu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu-sysemu.c
Signed-off-by: Claudio Fontana
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7690efff71..10aafbf997 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -399,7 +399,7 @@ ARM KVM CPUs
M: Peter Maydell
L: qemu-...@nongnu.org
S:
this work is in preparation of making sve_zcr_len_for_el AARCH64-only.
Signed-off-by: Claudio Fontana
---
target/arm/helper-a64.h | 2 ++
target/arm/helper.h | 1 -
target/arm/tcg/helper.c | 12
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git
sve_tests_sve_max_vq_8,
sve_tests_sve_off,
test_query_cpu_model_expansion
all require TCG to run. Skip them for KVM-only builds.
Signed-off-by: Claudio Fontana
---
tests/qtest/arm-cpu-features.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/qtest/arm-cpu-features.c
external functions have the cpu_sve prefix,
while for static functions it can be omitted.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sve.h | 6 +++---
target/arm/cpu-sve.c | 32
target/arm/cpu.c | 2 +-
target/arm/cpu64.c | 4 ++--
move init, realizefn and reset code into it.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/internals.h | 1 -
target/arm/cpu-sysemu.c| 32 --
target/arm/cpu.c | 49 +++---
target/arm/kvm/kvm-cpu.c | 128
XXX Someone who really understands which properties should be added
where should review this attentively.
What goes into cpu leaf class initialization?
What goes into arm_post_init / accel_cpu?
What goes into arm_cpu_finalize_features / aarch64_cpu_finalize_features?
Should there be shift of
Hi,
> Any other ideas as to how to eliminate that Blit cleanly?
Well, "cleanly" pretty much implies "supported by toolkit".
gtk glarea for example sets up a framebuffer and expects the application
render to that framebuffer. So qemu glarea code does a fb-to-fb blit.
Other reasons are
Philippe Mathieu-Daudé writes:
> We used to run the TCG tests for various QEMU targets, but at
> some points it got restricted to base directories in tests/tcg/.
> For example, armeb/mipsel/mips64/... targets are currently skipped.
>
> The configuration Makefiles in default-configs/targets/
cpu-vfp.c: vfp_get_fpsr and vfp_set_fpsr are needed also for KVM,
so create a new cpu-vfp.c
tcg/cpu-vfp.c: vfp_get_fpscr_from_host and vv are TCG-only, so we
move the implementation to tcg/cpu-vfp.c
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
target/arm/tcg/tlb_helper.h| 17 ++
target/arm/tcg/sysemu/tlb_helper.c | 83 +
target/arm/tcg/tlb_helper.c| 97 ++
this first armv7m one should go away with proper
configuration changes (only enabling possible boards for KVM).
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/tcg-stubs.c | 16
target/arm/tcg/meson.build | 3 +++
2 files changed, 19
the functions used in machine.c are now protected via
if (kvm_enabled()), so the stub is not needed.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/kvm-stub.c | 24
1 file changed, 24 deletions(-)
delete mode 100644 target/arm/kvm-stub.c
we need to be careful not to use
if (tcg_enabled())
here, because of the VMSTATE definitions in machine.c,
which are only protected by CONFIG_TCG, and thus
it would break the --enable-tcg --enable-kvm build.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
restrict zcr_el1, zcr_el2, zcr_no_el2, zcr_el3 reginfo,
and the related SVE functions to TARGET_AARCH64.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/cpregs.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/cpregs.c
extract the SVE-related cpu object properties and functions,
and move them to a separate module.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sve.h | 37
target/arm/cpu.h | 14 +-
target/arm/cpu-sve.c | 358 +++
target/arm/cpu.c
make them canonical for the module name.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/tcg-sve.h | 6 +++---
linux-user/syscall.c | 2 +-
target/arm/cpu-exceptions-aa64.c | 2 +-
target/arm/tcg/cpregs.c | 2 +-
On Wed, 14 Apr 2021 04:43:56 -0400
Igor Mammedov wrote:
> Do the same as in commit
> (4d027afeb3a97 Virt: ACPI: fix qemu assert due to re-assigned table data
> address)
> for remaining tables that happen to use saved at
> the beginning pointer to build header to avoid assert
> when table_data
We are already poisoning CONFIG_KVM since this switch is not working
in common code. Do the same with the other accelerator switches, too
(except for CONFIG_TCG, which is special, since it is also defined in
config-host.h).
Signed-off-by: Thomas Huth
---
include/exec/poison.h | 4
Using target-specific CONFIG_xxx switches in common code via "#ifdef"s
is wrong, since these macros are only defined for target-specific code.
We already poison many switches in common code to avoid the bugs with
dead code here, but these problems still keep creeping in ...
This series now
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
target/arm/{ => tcg}/translate-a64.h | 0
target/arm/{ => tcg}/translate.h | 0
target/arm/{ => tcg}/a32-uncond.decode| 0
target/arm/{ => tcg}/a32.decode | 0
allocation_tag_mem has a different implementation for
user-only and sysemu, so move the two implementations into
the dedicated subdirs.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
target/arm/tcg/mte_helper.h| 53
in preparation of the creation of a new cpregs module,
fix the style for the to-be-exported code.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu.h| 54 ---
target/arm/tcg/helper.c | 310 ++--
2 files changed,
before moving over sve_exception_el from the helper code,
cleanup the style.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sysemu.c | 100
target/arm/cpu-user.c | 5 ++
target/arm/tcg/helper.c | 100
3 files changed, 105 insertions(+), 100 deletions(-)
diff --git
Signed-off-by: Claudio Fontana
---
target/arm/cpu32.h | 2 +-
target/arm/cpu.c | 225 -
target/arm/cpu32.c | 85 -
target/arm/cpu64.c | 142
4 files changed, 227 insertions(+), 227 deletions(-)
diff
we will need this for KVM too, especially for Nested support.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-common.c | 68 +
target/arm/tcg/helper.c | 68 -
2 files changed, 68
before refactoring the exception code, fix the style of the
functions being moved.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/arm/tcg/helper.c
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/{cpu_tcg.c => tcg/tcg-cpu-models.c} | 9 +
target/arm/meson.build | 4
This reverts commit 6e937ba7f8fb90d66cb3781f7fed32fb4239556a
This change breaks quickly at startup, as all interfaces in boards
are checked in vl.c in select_machine():
{
GSList *machines = object_class_get_list(TYPE_MACHINE, false);
}
In order to restrict v8M IDAU to TCG,
we need to first
make it clearer from the name that this is a tcg-only function.
Signed-off-by: Claudio Fontana
---
target/arm/tcg/tcg-cpu.h| 2 +-
target/arm/cpu-sysemu.c | 2 +-
target/arm/tcg/sysemu/tcg-cpu.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git
This patch introduces the vfio-user protocol specification (formerly
known as VFIO-over-socket), which is designed to allow devices to be
emulated outside QEMU, in a separate process. vfio-user reuses the
existing VFIO defines, structs and concepts.
It has been earlier discussed as an RFC in:
On Tue, Apr 13, 2021 at 09:37:37PM +0800, Zenghui Yu wrote:
As it's only used inside hw/virtio/vhost-vdpa.c.
Signed-off-by: Zenghui Yu
---
hw/virtio/vhost-vdpa.c | 4 ++--
include/hw/virtio/vhost-vdpa.h | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Stefano
On Tue, 13 Apr 2021 at 23:44, Devin Hussey wrote:
>
> In a toy project I was doing
> (https://github.com/easyaspi314/ThumbGolf), I found that qemu will
> incorrectly handle modifying pc in a handler.
>
> Specifically, on platforms with instruction alignment requirements
> (most notably ARM), if
On 4/13/21 3:37 PM, Zenghui Yu wrote:
> As it's only used inside hw/virtio/vhost-vdpa.c.
>
> Signed-off-by: Zenghui Yu
> ---
> hw/virtio/vhost-vdpa.c | 4 ++--
> include/hw/virtio/vhost-vdpa.h | 2 --
> 2 files changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Philippe
On Wed, 2021-04-14 at 11:19 +0200, Ilya Leoshkevich wrote:
> On Wed, 2021-04-14 at 10:38 +0200, Cornelia Huck wrote:
> > On Tue, 13 Apr 2021 18:52:57 +0200
> > Ilya Leoshkevich wrote:
> >
> > > Hitting an uretprobe in a s390x TCG guest causes a SIGSEGV. What
> > > happens is:
> > >
> > > *
On Tue, Apr 13, 2021 at 06:56:54PM +0200, Kevin Wolf wrote:
> virtio_add_queue() aborts when queue_size > VIRTQUEUE_MAX_SIZE, so
> vhost_user_blk_device_realize() should check this before calling it.
>
> Simple reproducer:
>
> qemu-system-x86_64 \
> -chardev null,id=foo \
> -device
On Wed, 14 Apr 2021 12:27:03 +0200
Ilya Leoshkevich wrote:
> On Wed, 2021-04-14 at 11:19 +0200, Ilya Leoshkevich wrote:
> > On Wed, 2021-04-14 at 10:38 +0200, Cornelia Huck wrote:
> > > On Tue, 13 Apr 2021 18:52:57 +0200
> > > Ilya Leoshkevich wrote:
> > >
> > > > Hitting an uretprobe in a
We are generating a lot of target-specific defines in the *-config-devices.h
and *-config-target.h files. Using them in common code is wrong and leads
to very subtle bugs since a "#ifdef CONFIG_SOMETHING" is not working there
as expected. To avoid these issues, we are already poisoning many of the
The ObjectType enum and ObjectOptions are included from qapi-types-qom.h
into common code. We should not use target-specific config switches like
CONFIG_VIRTIO_CRYPTO here, since this is not defined in common code and
thus the enum will look differently between common and target specific
code. For
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
meson.build | 1 +
target/arm/{ => tcg}/op_addsub.h | 0
target/arm/tcg/trace.h | 1 +
target/arm/{ => tcg}/vec_internal.h | 0
target/arm/{ =>
We do not move psci.c to tcg/ because we expect other
hypervisors to use it (waiting for HVF enablement).
Signed-off-by: Claudio Fontana
Cc: Alexander Graf
Reviewed-by: Richard Henderson
---
target/arm/meson.build | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/meson.build
move sysemu-only parts of debug_helper to sysemu/
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
target/arm/tcg/debug_helper.c| 27 ---
target/arm/tcg/sysemu/debug_helper.c | 33
Skip the test_device_intro_concrete for now for ARM KVM-only build,
as on ARM we currently build devices for ARM that are not
compatible with a KVM-only build.
We can remove this workaround when we fix this in KConfig etc,
and we only list and build machines that are compatible with KVM
for
The QEMU PSCI implementation is not used for KVM,
we do not need the kvm constants header.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/arm-powerctl.h | 2 --
target/arm/psci.c | 1 -
2 files changed, 3 deletions(-)
diff --git
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this case.
Signed-off-by: Claudio Fontana
Cc: Philippe
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 4
target/arm/kvm/kvm-cpu.c | 1 +
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 82856ffdb9..11a1e1cb66 100644
--- a/target/arm/cpu.c
+++
use a canonical module prefix followed by the get_zcr_len_for_el()
method name. Also rename the static internal auxiliary function,
where the module prefix is not necessary.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-sve.h | 2 +-
bail out immediately if ARM_FEATURE_AARCH64 is not set,
and add an else statement when checking for accelerators.
Signed-off-by: Claudio Fontana
---
target/arm/cpu64.c | 33 -
1 file changed, 16 insertions(+), 17 deletions(-)
diff --git a/target/arm/cpu64.c
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this case.
Signed-off-by: Claudio Fontana
Cc: Philippe
this will allow us to restrict more code to TARGET_AARCH64
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/arch_dump.c | 12 +++-
target/arm/cpu.c | 1 -
target/arm/cpu64.c | 4
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git
put the KVM-specific and TCG-specific functionality
in the respective subdirectories kvm/ and tcg/
Signed-off-by: Claudio Fontana
---
target/arm/kvm/kvm-sve.h | 28 +++
target/arm/tcg/tcg-sve.h | 24 ++
target/arm/cpu-sve.c | 155 ++---
On Tue, 13 Apr 2021 at 16:25, Dr. David Alan Gilbert (git)
wrote:
>
> From: "Dr. David Alan Gilbert"
>
> The following changes since commit dce628a97fde2594f99d738883a157f05aa0a14f:
>
> Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210412'
> into staging (2021-04-13
On 4/14/21 12:29 PM, Philippe Mathieu-Daudé wrote:
> On 4/14/21 10:19 AM, Thomas Huth wrote:
>> Ccache can speed up the compilation in some cases, so enable it for
>> our cross-compilation CI builds, too.
>>
>> Signed-off-by: Thomas Huth
>> ---
>> .gitlab-ci.d/crossbuilds.yml | 28
On 13/04/2021 14:55, Paolo Bonzini wrote:
Right now, rate limiting is protected by the AioContext mutex, which is
taken for example both by the block jobs and by qmp_block_job_set_speed
(via find_block_job).
We would like to remove the dependency of block layer code on the
AioContext mutex,
before exporting some functionality from helper.c into a new module,
fix the comment style of those functions.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper.c | 152 ++--
1 file changed, 101 insertions(+), 51
of note, cpreg lists were previously initialized by TCG first,
and then thrown away and replaced with the data coming from KVM.
Now we just initialize once, either for TCG or for KVM.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 32
this function is used for kvm too, add it to the
cpu-common module.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-common.c | 11 +++
target/arm/tcg/helper.c | 11 ---
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu-common.c
we need this for KVM too.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-sysemu.c | 62 +++
target/arm/cpu-user.c | 5
target/arm/tcg/helper.c | 64 -
3 files changed, 67
Signed-off-by: Claudio Fontana
---
target/arm/tcg/helper.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index aaa307daca..4e027b98fe 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@
cpu.c,
cpu32.c,
cpu64.c,
tcg/sysemu/tcg-cpu.c,
all need a good cleanup when it comes to included header files.
Signed-off-by: Claudio Fontana
Acked-by: Richard Henderson
---
target/arm/cpu.c| 7 ++-
target/arm/cpu32.c | 14 --
target/arm/cpu64.c
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