From: Sean Christopherson
On real hardware, on systems that supports SGX Launch Control, those
MSRs are initialized to digest of Intel's signing key; on systems that
don't support SGX Launch Control, those MSRs are not available but
hardware always uses digest of Intel's signing key in EINIT.
From: Sean Christopherson
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc_piix.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index
This QMP query command can be used by some userspaces to retrieve
the SGX information when SGX is enabled on Intel platform.
Signed-off-by: Yang Zhong
---
monitor/qmp-cmds.c | 6 ++
qapi/misc.json | 42 ++
tests/qtest/qmp-cmd-test.c |
From: Sean Christopherson
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc_q35.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index
From: Sean Christopherson
The ACPI Device entry for SGX EPC is essentially a hack whose primary
purpose is to provide software with a way to autoprobe SGX support,
e.g. to allow software to implement SGX support as a driver. Details
on the individual EPC sections are not enumerated through ACPI
Since there is no fill_device_info() callback support, and when we
execute "info memory-devices" command in the monitor, the segfault
will be found.
This patch will add this callback support and "info memory-devices"
will show sgx epc memory exposed to guest. The result as below:
qemu) info
From: Sean Christopherson
KVM_CAP_SGX_ATTRIBUTE is a proposed capability for Intel SGX that can be
used by userspace to enable privileged attributes, e.g. access to the
PROVISIONKEY.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
linux-headers/linux/kvm.h | 1 +
1 file
Daniel P. Berrangé writes:
> On Thu, Apr 29, 2021 at 11:59:41AM +0200, Markus Armbruster wrote:
>> Myself, but I only documented it; it's actually Kevin Wolf:
>>
>> ``blockdev-open-tray``, ``blockdev-close-tray`` argument ``device``
>> (since 2.8.0)
>>
>>
Add the sgx_memory_backend_reset() interface to handle EPC backend
reset when VM is reset. This reset function will destroy previous
backend memory region and re-mmap the EPC section for guest.
Signed-off-by: Yang Zhong
---
backends/hostmem-epc.c | 16
include/hw/i386/pc.h |
On Thu, Apr 29, 2021 at 04:13:26PM +0200, Laurent Vivier wrote:
As for "hw/elf_ops: clear uninitialized segment space" we need to
clear the uninitialized space when the ELF is set in ROM.
Signed-off-by: Laurent Vivier
Reviewed-by: Stefano Garzarella
From: Bin Meng
Update the 'sifive_u' machine documentation to mention the '-dtb'
option that can be used to pass a custom DTB to QEMU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
docs/system/riscv/sifive_u.rst | 47 +-
1
From: Bin Meng
The OpenSBI BIOS image names are used by many RISC-V machines.
Let's define macros for them.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/riscv/boot.h | 5 +
hw/riscv/sifive_u.c | 6 ++
hw/riscv/spike.c| 6
From: Sean Christopherson
Request SGX an SGX Launch Control to be enabled in FEATURE_CONTROL
when the features are exposed to the guest. Our design is the SGX
Launch Control bit will be unconditionally set in FEATURE_CONTROL,
which is unlike host bios.
Signed-off-by: Sean Christopherson
From: Sean Christopherson
CPUID leaf 12_0_EBX is an Intel-defined feature bits leaf enumerating
the platform's SGX extended capabilities. Currently there is a single
capabilitiy:
- EXINFO: record information about #PFs and #GPs in the enclave's SSA
Signed-off-by: Sean Christopherson
From: Sean Christopherson
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX
EPC above 4g ends. Use the helpers to adjust the device memory range
if SGX EPC exists above 4g.
For multiple virtual EPC sections, we just put them together physically
contiguous for the
From: Sean Christopherson
Expose SGX to the guest if and only if KVM is enabled and supports
virtualization of SGX. While the majority of ENCLS can be emulated to
some degree, because SGX uses a hardware-based root of trust, the
attestation aspects of SGX cannot be emulated in software, i.e.
From: Sean Christopherson
If the guest want to fully use SGX, the guest needs to be able to
access provisioning key. Add a new KVM_CAP_SGX_ATTRIBUTE to KVM to
support provisioning key to KVM guests.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/cpu.c |
The command can be used to show the SGX information in the monitor
when SGX is enabled on intel platform.
Signed-off-by: Yang Zhong
---
hmp-commands-info.hx | 15 +++
include/monitor/hmp.h | 1 +
monitor/hmp-cmds.c| 6 ++
3 files changed, 22 insertions(+)
diff --git
Add the sgx_get_info() interface for hmp and QMP usage, which
will get the SGX info from this API.
Signed-off-by: Yang Zhong
---
hw/i386/sgx-epc.c | 22 ++
include/hw/i386/pc.h | 1 +
include/hw/i386/sgx-epc.h | 1 +
monitor/hmp-cmds.c| 20
From: Sean Christopherson
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
docs/intel-sgx.txt | 173 +
1 file changed, 173 insertions(+)
create mode 100644 docs/intel-sgx.txt
diff --git a/docs/intel-sgx.txt b/docs/intel-sgx.txt
new
On Fri, Apr 30, 2021 at 08:41:25AM +0200, Andrew Jones wrote:
> On Fri, Apr 30, 2021 at 01:09:00PM +0800, wangyanan (Y) wrote:
> > But I think the requirement for ARM "if even one parameter other than cpus
> > or maxcpus
> > is provided then all parameters must be provided" will be better. This
Hi Gerd,
> > res->remapsz = QEMU_ALIGN_UP(res->remapsz,
> > qemu_real_host_page_size);
> >
> > res->remapped = mmap(NULL, res->remapsz, PROT_READ, @@ -152,7
> > +155,9 @@ void virtio_gpu_init_udmabuf(struct virtio_gpu_simple_resource
> > *res)
> > pdata = res->remapped;
> >
shakti_c machine documentation was missed in the riscv target doc.
Signed-off-by: Bin Meng
---
docs/system/target-riscv.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index 8d5946fbbb..4b3c78382c 100644
---
From: Bin Meng
Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
adds the official DT bindings for CLINT, which uses "sifive,clint0"
as the compatible string. "riscv,clint0" is now legacy and has to
be kept for backward compatibility of legacy systems.
Signed-off-by:
From: Sean Christopherson
SGX EPC is enumerated through CPUID, i.e. EPC "devices" need to be
realized prior to realizing the vCPUs themselves, which occurs long
before generic devices are parsed and realized. Because of this,
do not allow 'sgx-epc' devices to be instantiated after vCPUS have
From: Sean Christopherson
Add a new RAMBlock flag to denote "protected" memory, i.e. memory that
looks and acts like RAM but is inaccessible via normal mechanisms,
including DMA. Use the flag to skip protected memory regions when
mapping RAM for DMA in VFIO.
Signed-off-by: Sean Christopherson
Since Sean Christopherson has left Intel and i am responsible for Qemu SGX
upstream work. His @intel.com address will be bouncing and his new email(
sea...@google.com) is also in CC lists.
This series is Qemu SGX virtualization implementation rebased on latest
Qemu release.
You can find Qemu
From: Sean Christopherson
EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
SGX (Software Guard Extensions). The SDM desribes EPC as:
The Enclave Page Cache (EPC) is the secure storage used to store
enclave pages when they are a part of an executing enclave. For an
From: Sean Christopherson
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
From: Sean Christopherson
SGX adds multiple flags to FEATURE_CONTROL to enable SGX and Flexible
Launch Control.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/kvm/kvm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/kvm/kvm.c
From: Sean Christopherson
SGX capabilities are enumerated through CPUID_0x12.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 63253bf606..41050960c5 100644
From: Sean Christopherson
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating
the platform's SGX capabilities that may be utilized by an enclave, e.g.
whether or not an enclave can gain access to the provision key.
Currently there are six capabilities:
- INIT: set when the
If the VM is reset, we need make sure sgx virt epc in clean status.
Once the VM is reset, and sgx epc virt device will be reseted by
reset callback registered by qemu_register_reset(). Since this epc
virt device depend on backend, this reset will call backend reset
interface to re-mmap epc to
On Fri, Apr 30, 2021 at 01:09:00PM +0800, wangyanan (Y) wrote:
> Hi Drew,
>
> On 2021/4/29 19:02, Andrew Jones wrote:
> > On Thu, Apr 29, 2021 at 04:56:06PM +0800, wangyanan (Y) wrote:
> > > On 2021/4/29 15:16, Andrew Jones wrote:
> > > > On Thu, Apr 29, 2021 at 10:14:37AM +0800, wangyanan (Y)
Add new CONFIG_SGX for sgx support in the Qemu, and the Kconfig
default enable sgx in the i386 platform.
Signed-off-by: Yang Zhong
---
backends/meson.build | 2 +-
default-configs/devices/i386-softmmu.mak | 1 +
hw/i386/Kconfig | 5 +
From: Bin Meng
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array
helper"),
we can use the new helper to set the compatible strings for the
SiFive test device node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2:
- use "static const char *
From: Bin Meng
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array
helper"),
we can use the new helper to set the clock name for the ethernet
controller node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2:
- use "static const char * const"
Philippe Mathieu-Daudé writes:
> On 4/29/21 3:22 PM, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé writes:
> Now than we can probe if the TCG accelerator is available
> at runtime with a QMP command, do it once at the beginning
> and only register the tests we can run.
> We
From: Sean Christopherson
Note that SGX EPC is currently guaranteed to reside in a single
contiguous chunk of memory regardless of the number of EPC sections.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc.c | 4
1 file changed, 4 insertions(+)
diff --git
From: Sean Christopherson
CPUID leaf 12_0_EAX is an Intel-defined feature bits leaf enumerating
the CPU's SGX capabilities, e.g. supported SGX instruction sets.
Currently there are four enumerated capabilities:
- SGX1 instruction set, i.e. "base" SGX
- SGX2 instruction set for dynamic EPC
Add the new 'memory-backend-epc' user creatable QOM object in
the ObjectOptions to support SGX, or the sgx backend object
cannot bootup.
Signed-off-by: Yang Zhong
---
qapi/qom.json | 2 ++
1 file changed, 2 insertions(+)
diff --git a/qapi/qom.json b/qapi/qom.json
index cd0e76d564..fd6fbee597
From: Sean Christopherson
Add CPUID defines for SGX and SGX Launch Control (LC), as well as
defines for their associated FEATURE_CONTROL MSR bits. Define the
Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist
when SGX LC is present (in CPUID), and are writable when SGX LC is
From: Sean Christopherson
The SGX sub-leafs are enumerated at CPUID 0x12. Indices 0 and 1 are
always present when SGX is supported, and enumerate SGX features and
capabilities. Indices >=2 are directly correlated with the platform's
EPC sections. Because the number of EPC sections is dynamic
The libvirt can use qmp_query_sgx_capabilities() to get the host
sgx capabilitis.
Signed-off-by: Yang Zhong
---
hw/i386/sgx-epc.c | 66 ++
include/hw/i386/pc.h | 1 +
monitor/qmp-cmds.c | 5 +++
qapi/misc.json | 19
The Qemu should enable bit mask macro like Linux did in the
kernel, the GENMASK(h, l) and GENMASK_ULL(h, l) will set the
bit to 1 from l to h bit in the 32 bit or 64 bit long type.
Signed-off-by: Yang Zhong
---
include/qemu/bitops.h | 7 +++
1 file changed, 7 insertions(+)
diff --git
Philippe Mathieu-Daudé writes:
> On 4/29/21 3:46 PM, Gerd Hoffmann wrote:
>
>> Hmm. Not so easy I suspect. While most sound cards map to a single
>> device there are exceptions. pcspk is build-in and hda is two devices.
>
> What do you mean by "pcspk is build-in"?
>
> Do you mean "the 'pcspk'
On Thu, Apr 29, 2021 at 05:05:35PM +0200, Philippe Mathieu-Daudé wrote:
> On 4/29/21 3:46 PM, Gerd Hoffmann wrote:
>
> > Hmm. Not so easy I suspect. While most sound cards map to a single
> > device there are exceptions. pcspk is build-in and hda is two devices.
>
> What do you mean by "pcspk
From: Bin Meng
At present the Microchip Icicle Kit machine only supports using
'-bios' to load the HSS, and does not support '-kernel' for direct
kernel booting just like other RISC-V machines do. One has to use
U-Boot which is chain-loaded by HSS, to load a kernel for testing.
This is not so
From: Bin Meng
The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the
compatible string in the upstream Linux kernel. "riscv,plic0" is
now legacy and has to be kept for backward compatibility of legacy
systems.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20210419202257.161730-31-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/translate-a64.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
Currently the gpex PCI controller implements no special behaviour for
guest accesses to areas of the PIO and MMIO where it has not mapped
any PCI devices, which means that for Arm you end up with a CPU
exception due to a data abort.
Most host OSes expect "like an x86 PC" behaviour, where bad
On Fri, Apr 30, 2021 at 04:59:36PM +0800, wangyanan (Y) wrote:
>
> On 2021/4/30 14:41, Andrew Jones wrote:
> > On Fri, Apr 30, 2021 at 01:09:00PM +0800, wangyanan (Y) wrote:
> > > Hi Drew,
> > >
> > > On 2021/4/29 19:02, Andrew Jones wrote:
> > > > On Thu, Apr 29, 2021 at 04:56:06PM +0800,
From: Vladimir Sementsov-Ogievskiy
Passing parent aio context is redundant, as child_class and parent
opaque pointer are enough to retrieve it. Drop the argument and use new
bdrv_child_get_parent_aio_context() interface.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Alberto Garcia
From: Vladimir Sementsov-Ogievskiy
These functions are called only from bdrv_reopen_multiple() in block.c.
No reason to publish them.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Alberto Garcia
Reviewed-by: Kevin Wolf
Message-Id: <20210428151804.439460-8-vsement...@virtuozzo.com>
From: Vladimir Sementsov-Ogievskiy
Refactor calling driver callbacks to a separate transaction action to
be used later.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Message-Id: <20210428151804.439460-15-vsement...@virtuozzo.com>
Signed-off-by: Kevin Wolf
---
block.c |
From: Vladimir Sementsov-Ogievskiy
Using bdrv_replace_node() for removing filter is not good enough: it
keeps child reference of the filter, which may conflict with original
top node during permission update.
Instead let's create new interface, which will do all graph
modifications first and
From: Vladimir Sementsov-Ogievskiy
Split no-perm part of bdrv_attach_child as separate transaction action.
It will be used in later commits.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Message-Id: <20210428151804.439460-20-vsement...@virtuozzo.com>
Signed-off-by: Kevin
From: Vladimir Sementsov-Ogievskiy
Move bdrv_reopen_multiple to new paradigm of permission update:
first update graph relations, then do refresh the permissions.
We have to modify reopen process in file-posix driver: with new scheme
we don't have prepared permissions in raw_reopen_prepare(), so
From: Vladimir Sementsov-Ogievskiy
Now, bdrv_node_check_perm() is called only with fresh cumulative
permissions, so its actually "refresh_perm".
Move permission calculation to the function. Also, drop unreachable
error message and rewrite the remaining one to be more generic (as now
we don't
From: Vladimir Sementsov-Ogievskiy
Split part of bdrv_replace_node_common() to be used separately.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Message-Id: <20210428151804.439460-21-vsement...@virtuozzo.com>
Signed-off-by: Kevin Wolf
---
block.c | 50
From: Vladimir Sementsov-Ogievskiy
To be used in the further commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Message-Id: <20210428151804.439460-27-vsement...@virtuozzo.com>
Signed-off-by: Kevin Wolf
---
block.c | 46 ++
From: Vladimir Sementsov-Ogievskiy
bdrv_check_perm_common() has only one caller, so no more sense in
"common".
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Message-Id: <20210428151804.439460-33-vsement...@virtuozzo.com>
Signed-off-by: Kevin Wolf
---
block.c | 32
virtio_add_queue() aborts when queue_size > VIRTQUEUE_MAX_SIZE, so
vhost_user_blk_device_realize() should check this before calling it.
Simple reproducer:
qemu-system-x86_64 \
-chardev null,id=foo \
-device vhost-user-blk-pci,queue-size=4096,chardev=foo
Fixes:
Currently we have one virtio-gpu device. Problem with this approach is
that if you compile a full-featured qemu you'll get a virtio-gpu device
which depends on opengl and virgl, so these dependencies must be
installed and the libraries will be loaded into memory even if you don't
use virgl. Also
Signed-off-by: Gerd Hoffmann
---
include/hw/virtio/virtio-gpu.h | 1 +
hw/display/virtio-gpu-gl.c | 17 +
hw/display/virtio-gpu.c| 19 +--
3 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/include/hw/virtio/virtio-gpu.h
Drops last virgl/opengl dependency from virtio-gpu-device.
Signed-off-by: Gerd Hoffmann
---
hw/display/virtio-gpu.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c
index 2c0065277ffd..34cf35127a3d 100644
---
Move two virglrenderer state variables to struct VirtIOGPUGL.
Signed-off-by: Gerd Hoffmann
---
include/hw/virtio/virtio-gpu.h | 5 +++--
hw/display/virtio-gpu-gl.c | 15 +--
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/include/hw/virtio/virtio-gpu.h
From: John Snow
Signed-off-by: John Snow
Message-Id: <20210421182032.3521476-18-js...@redhat.com>
Reviewed-by: Markus Armbruster
Signed-off-by: Markus Armbruster
---
scripts/qapi/expr.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/qapi/expr.py
From: John Snow
This is a small rewrite to address some minor style nits.
Don't compare against the empty list to check for the empty condition, and
move the normalization forward to unify the check on the now-normalized
structure.
With the check unified, the local nested function isn't needed
Just a skeleton for starters, following patches will add more code.
Signed-off-by: Gerd Hoffmann
---
include/hw/virtio/virtio-gpu.h | 7 ++
hw/display/virtio-gpu-gl.c | 41 ++
util/module.c | 1 +
hw/display/meson.build | 2 +-
From: John Snow
mypy isn't fond of allowing you to check for bool membership in a
collection of str elements. Guard this lookup for precisely when we were
given a name.
Signed-off-by: John Snow
Reviewed-by: Eduardo Habkost
Reviewed-by: Cleber Rosa
Message-Id:
Signed-off-by: Gerd Hoffmann
---
include/hw/virtio/virtio-gpu.h | 2 ++
hw/display/virtio-gpu-gl.c | 11 +++
hw/display/virtio-gpu.c| 9 +
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h
From: John Snow
Signed-off-by: John Snow
Message-Id: <20210421182032.3521476-13-js...@redhat.com>
Reviewed-by: Markus Armbruster
Signed-off-by: Markus Armbruster
---
scripts/qapi/expr.py | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/scripts/qapi/expr.py
On 14.04.21 19:03, Emanuele Giuseppe Esposito wrote:
Add -gdb flag and GDB_QEMU environmental variable
to python tests to attach a gdbserver to each qemu instance.
if -gdb is not provided but $GDB_QEMU is set, ignore the
environmental variable.
Signed-off-by: Emanuele Giuseppe Esposito
---
Hi,
> [Kasireddy, Vivek] Right, we don't. I was also going to slightly change the
> names of some
> of the new functions in v3 to keep them consistent with the rest of the code.
> Do you have
> any additional feedback for the other patches that I can include in v3?
Looks fine to me
From: John Snow
This is a minor adjustment that lets parameters @required and
@optional take tuple arguments, in particular (). Later patches will
make use of that.
(Iterable would also have worked, but Iterable also includes things like
generator expressions which are consumed upon iteration,
From: Richard Henderson
> From: Luis Fernando Fujita Pires
>
> Allow '64' to be specified for the instruction width command line params and
> use
> the appropriate extract and deposit functions in that case.
>
> This will be used to implement the new 64-bit Power ISA 3.1 instructions.
>
>
From: John Snow
mypy does not know the types of values stored in Dicts that masquerade
as objects. Help the type checker out by constraining the type.
Signed-off-by: John Snow
Message-Id: <20210421182032.3521476-5-js...@redhat.com>
Reviewed-by: Markus Armbruster
Signed-off-by: Markus
From: John Snow
It is -- maybe -- possibly -- three nanoseconds faster.
Signed-off-by: John Snow
Reviewed-by: Eduardo Habkost
Reviewed-by: Cleber Rosa
Message-Id: <20210421182032.3521476-17-js...@redhat.com>
Reviewed-by: Markus Armbruster
Signed-off-by: Markus Armbruster
---
From: John Snow
The function can just use the argument from the scope above. Otherwise,
we get shadowed argument errors because the parameter name clashes with
the name of a variable already in-scope.
Signed-off-by: John Snow
Reviewed-by: Eduardo Habkost
Reviewed-by: Cleber Rosa
Message-Id:
cmd： ~/qemu-5.1.0/arm-linux-user/qemu-arm ~/test2
QEMU version: qemu-arm version 5.1.0
Sorry that I didn't test it on the latest version of QEMU.
** Attachment added: "test2"
https://bugs.launchpad.net/qemu/+bug/1926759/+attachment/5493873/+files/test2
--
You received this bug notification
From: John Snow
No functional change.
Note: QAPISourceError's info parameter is Optional[] because schema.py
treats the info property of its various classes as Optional to
accommodate built-in types, which have no source. See prior commit
'qapi/error: assert QAPISourceInfo is not None'.
Hey,
On Fri, Apr 30, 2021, at 7:58 AM, Markus Armbruster wrote:
> > I did not add a Since: here because I wasn't sure how that is handled.
> > Should I add something or is that taken care of at the time of release
> > somehow?
>
> You should add (since 6.1) at the end, like this
>
> #
Please provide a test case binary and your QEMU command line.
--
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https://bugs.launchpad.net/bugs/1926759
Title:
WFI instruction results in unhandled CPU exception
Status in QEMU:
New
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20210419202257.161730-29-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/translate-a64.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff
From: Vladimir Sementsov-Ogievskiy
Add the test that shows that concept of ignore_children is incomplete.
Actually, when we want to update something, ignoring permission of some
existing BdrvChild, we should ignore also the propagated effect of this
child to the other children. But that's not
From: Vladimir Sementsov-Ogievskiy
Split out non-recursive parts, and refactor as block graph transaction
action.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Message-Id: <20210428151804.439460-11-vsement...@virtuozzo.com>
Signed-off-by: Kevin Wolf
---
block.c | 79
From: Vladimir Sementsov-Ogievskiy
Each of them has only one caller. Open-coding simplifies further
pemission-update system changes.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Alberto Garcia
Reviewed-by: Kevin Wolf
Message-Id: <20210428151804.439460-13-vsement...@virtuozzo.com>
From: Vladimir Sementsov-Ogievskiy
bdrv_append is not very good for inserting filters: it does extra
permission update as part of bdrv_set_backing_hd(). During this update
filter may conflict with other parents of top_bs.
Instead, let's first do all graph modifications and after it update
From: Vladimir Sementsov-Ogievskiy
Add simple transaction API to use in further update of block graph
operations.
Supposed usage is:
- "prepare" is main function of the action and it should make the main
effect of the action to be visible for the following actions, keeping
possibility of
From: Vladimir Sementsov-Ogievskiy
bdrv_replace_child() has only one caller, the second argument is
unused. Inline it now. This triggers deletion of some more unused
interfaces.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Message-Id:
From: Vladimir Sementsov-Ogievskiy
We are going to drop recursive bdrv_child_* functions, so stop use them
in bdrv_child_try_set_perm() as a first step.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Message-Id: <20210428151804.439460-12-vsement...@virtuozzo.com>
For a successful conversion of an image, we must make sure that its
content doesn't change during the conversion.
A special case of this is using the same image file both as the source
and as the destination. If both input and output format are raw, the
operation would just be useless work, with
From: Vladimir Sementsov-Ogievskiy
Old interfaces dropped, nobody directly calls
bdrv_child_set_perm_abort() and bdrv_child_set_perm_commit(), so we can
use personal state structure for the action and stop exploiting
BdrvChild structure. Also, drop "_safe" suffix which is redundant now.
"Gustavo Noronha Silva" writes:
> Hey Markus,
>
> On Fri, Apr 30, 2021, at 4:20 AM, Markus Armbruster wrote:
>> Please indent like this
>>
>># @full-grab: Capture all key presses, including system combos. This
>># requires accessibility permissions, since it performs
>>#
From: Vladimir Sementsov-Ogievskiy
During reopen we may add backing bs from other aio context, which may
lead to changing original context of top bs.
We are going to move graph modification to prepare stage. So, it will
be possible that bdrv_flush() in bdrv_reopen_prepare called on bs in
On 21.04.21 09:58, Vladimir Sementsov-Ogievskiy wrote:
If mirror is READY than cancel operation is not discarding the whole
result of the operation, but instead it's a documented way get a
point-in-time snapshot of source disk.
So, we should not cancel any requests if mirror is READ and
On 14.04.21 19:03, Emanuele Giuseppe Esposito wrote:
Add a new _qmp_timer field to the QEMUMachine class.
The default timer is 15 sec, as per the default in the
qmp accept() function.
Signed-off-by: Emanuele Giuseppe Esposito
---
python/qemu/machine.py | 3 ++-
1 file changed, 2
On Fri, Apr 30, 2021 at 12:17:06PM +0200, Philippe Mathieu-Daudé wrote:
> Refactor qemu_xkeymap_mapping_table() to have a single exit point,
> so we can easily free the memory allocated by XGetAtomName(),
>
> This fixes when running a binary configured with --enable-sanitizers:
>
> Direct leak
From: John Snow
The linter yaps after 0825f62c842. Fix this trivial issue to restore the
linter baseline.
(Yes, ideally -- and soon -- the linter will be part of CI so we don't
clutter up the log with fixups. For now, though, the baseline is useful
for testing intermediate commits as types are
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