On 2021/7/29 4:16, Andrew Jones wrote:
On Wed, Jul 28, 2021 at 11:48:38AM +0800, Yanan Wang wrote:
To pave the way for the functional improvement in later patches,
make some refactor/cleanup for the smp parsers, including using
local maxcpus instead of ms->smp.max_cpus in the calculation,
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We have lacked expressive support for memory sizes larger
> than 64-bits for a while. Fixing that requires adjustment
> to several points where we used this for array indexing,
> and two places that develop -Wswitch warnings after the change.
>
>
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: qemu-s3...@nongnu.org
> Signed-off-by: Richard Henderson
> ---
> target/s390x/tcg/mem_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
From: Matheus Ferst
In commit 8f0a4b6a9b, we started to require L=0 for ppc32 to match what
The Programming Environments Manual say:
"For 32-bit implementations, the L field must be cleared, otherwise
the instruction form is invalid."
The stricter behavior, however, broke AROS boot on
From: Fabiano Rosas
PowerPC has two KVM types (HV, PR) that translate into three kernel
modules:
kvm.ko - common kvm code
kvm_hv.ko - kvm running with MSR_HV=1 or MSR_HV|PR=0 in a nested guest.
kvm_pr.ko - kvm running in usermode MSR_PR=1.
Since the two KVM types can both be running at the
Hi,
Qemu-system-ppc built from current master can no longer run Fedora 12 ppc
as guest. (This the only ppc distro I tested.) Host is Fedora 34. Please
see screen shot attached.
Booting from both an installation DVD and from an installed system fail.
To reproduce:
compile qemu-system-ppc from
* Thomas Huth (th...@redhat.com) wrote:
> On 28/07/2021 23.41, Peter Xu wrote:
> > Even if seems to exist for all archs on linux, however
> > including
> > it with __linux__ defined seems to be not working yet as it'll try to
> > include
> > asm/kvm.h and that can be missing for archs that do
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: Mark Cave-Ayland
> Signed-off-by: Richard Henderson
> ---
> linux-user/sparc/cpu_loop.c | 11 +++
> target/sparc/cpu.c | 2 +-
> target/sparc/ldst_helper.c | 2 --
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
>
Le 27/07/2021 à 22:41, Peter Maydell a écrit :
> docs/barrier.txt has a couple of TODO notes about things to be
> implemented in this device; move them into a comment in the
> source code.
>
> Signed-off-by: Peter Maydell
> ---
> docs/barrier.txt | 4
> ui/input-barrier.c | 5 +
> 2
Le 27/07/2021 à 22:41, Peter Maydell a écrit :
> Most of docs/barrier.txt is describing the protocol implemented
> by the input-barrier device. Move this into the interop
> section of the manual, and rstify it.
>
> Signed-off-by: Peter Maydell
> ---
> docs/barrier.txt | 318
On 29.07.21 12:02, Vladimir Sementsov-Ogievskiy wrote:
28.07.2021 10:00, Max Reitz wrote:
On 27.07.21 18:47, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
That's an alternative to (part of) Max's
"[PATCH for-6.1? v2 0/7] mirror: Handle errors after READY cancel"
and shows' my idea of handling
A cut-and-paste error meant we handled signed VADDV like
unsigned VADDV; fix the type used.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/mve_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/mve_helper.c
Implement the MVE fp scalar comparisons VCMP and VPT.
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 18 +++
target/arm/mve.decode | 61 +
target/arm/mve_helper.c| 62 ++
Implement the MVE VPNOT insn, which inverts the bits in VPR.P0
(subject to both predication and to beatwise execution).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 1 +
target/arm/mve.decode | 1 +
target/arm/mve_helper.c| 17
Implement more simple 2-operand floating point MVE insns.
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 15 +++
target/arm/mve.decode | 6 ++
target/arm/mve_helper.c| 24
target/arm/translate-mve.c | 5 +
4 files changed,
On Thu, 29 Jul 2021, Ani Sinha wrote:
>
>
> On Wed, 28 Jul 2021, Michael S. Tsirkin wrote:
>
> > On Mon, Jul 26, 2021 at 10:27:43PM +0530, Ani Sinha wrote:
> > > All existing code using acpi_get_i386_pci_host() checks for a non-null
> > > return value from this function call. Instead of
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We shouldn't be ignoring SIGBUS for user-only.
> Move our existing TCGCPUOps hook out from CONFIG_SOFTMMU.
>
> Signed-off-by: Richard Henderson
> ---
> include/hw/core/tcg-cpu-ops.h | 14 +++---
> 1 file changed, 7 insertions(+), 7
From: BALATON Zoltan
Add the differential clock input feature bit to the generated SPD
data. Most guests don't seem to care but pegasos2 firmware version 1.2
checks for this bit and stops with unsupported module type error if
it's not present. Since this feature is likely present on real memory
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The previous placement in tcg/tcg.h was not logical.
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/cpu_ldst.h | 87 +++
> include/tcg/tcg.h | 87 ---
>
On Wed, Jul 28, 2021 at 06:08:26PM +, John Johnson wrote:
>
>
> > On Jul 27, 2021, at 9:34 AM, Stefan Hajnoczi wrote:
> >
> > On Sun, Jul 18, 2021 at 11:27:42PM -0700, Elena Ufimtseva wrote:
> >> From: John G Johnson
> >>
> >> Add user.c and user.h files for vfio-user with the basic
> >>
Hi Peter!
The following changes since commit 69ea12b19a15ae006521cd5cc0f627f27f738746:
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-07-27' into
staging (2021-07-28 13:32:12 +0100)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git
Hi,
> > So we need more work to make this actually work right.
>
> Yes. I want have all of tcg in the tcg accel module, not only parts of
> it, but that needs some more refactoring. I'll go start looking at this
> once I managed to wade through my vacation backlog.
So, changed the
On Wed, Jul 28 2021, Yanan Wang wrote:
> In the sanity-check of smp_cpus and max_cpus against mc in function
> machine_set_smp(), we are now using ms->smp.max_cpus for the check
> but using current_machine->smp.max_cpus in the error message.
> Tweak this by uniformly using the local ms.
>
>
Raised exceptions don't return, so mark the helper with
noreturn.
Fixes: 032c76bc6f9 ("nios2: Add architecture emulation support")
Signed-off-by: Philippe Mathieu-Daudé
---
v2: use TCG_CALL_NO_WG instead of noreturn (rth)
Probably too late for 6.1, sorry I simply forgot to resend this patch
Hi,
> And another comment: I think we should have some progress on ARM with
> the kvm/tcg split and with the KConfig of boards, before we continue
> here.
Why? This can easily be tacked in parallel. We can flip the switch
for modular tcg per target in meson.build.
take care,
Gerd
For vector loads, predicated elements are zeroed, instead of
retaining their previous values (as happens for most data
processing operations). This means we need to distinguish
"beat not executed due to ECI" (don't touch destination
element) from "beat executed but predicated out" (zero
Implement the MVE incrementing/decrementing dup insns VIDUP, VDDUP,
VIWDUP and VDWDUP. These fill the elements of a vector with
successively incrementing values, starting at the offset specified in
a general purpose register. The final value of the offset is written
back to this register. The
We got an edge case wrong in the 48-bit SQRSHRL implementation: if
the shift is to the right, although it always makes the result
smaller than the input value it might not be within the 48-bit range
the result is supposed to be if the input had some bits in [63..48]
set and the shift didn't bring
Implement the MVE VADD (floating-point) insn. Handling of this is
similar to the 2-operand integer insns, except that we must take care
to only update the floating point exception status if the least
significant bit of the predicate mask for each element is active.
Signed-off-by: Peter Maydell
In commit a777d6033447a we added an assertion to parts_silence_nan() that
prohibits calling float*_silence_nan() when in default-NaN mode.
This ties together a property of the output ("do we generate a default
NaN when the result is a NaN?") with an operation on an input ("silence
this input
On 2021/7/29 4:22, Andrew Jones wrote:
On Wed, Jul 28, 2021 at 11:48:40AM +0800, Yanan Wang wrote:
Currently we directly calculate the omitted cpus based on the given
incomplete collection of parameters. This makes some cmdlines like:
-smp maxcpus=16
-smp sockets=2,maxcpus=16
-smp
From: BALATON Zoltan
The -append option is currently not compatible with -bios (as we don't
yet emulate nvram so we can only put it in the environment with VOF).
Therefore a warning is printed if -append is used with -bios but
because the default value of kernel_cmdline seems to be an empty
Hi, Peter.
> This adds a64fx to the list of CPUs we support in the 'virt' board, but it
> hasn't
> changed the valid_cpus[] array in hw/arm/virt.c, so trying to actually use
> -cpu
> a64fx with -machine virt will fail.
I'm sorry, but just to be sure, let me check.
Is it correct to understand
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The helper_*_mmu functions were the only thing available
> when this code was written. This could have been adjusted
> when we added cpu_*_mmuidx_ra, but now we can most easily
> use the newest set of interfaces.
>
> Cc: qemu-...@nongnu.org
>
On 28/07/21 13:37, Lara Lazier wrote:
+uint32_t int_ctl = x86_ldl_phys(cs,
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
+if (virtual_gif_enabled(env, int_ctl) && likely(env->hflags &
HF_GUEST_MASK)) {
+x86_stl_phys(cs, env->vm_vmcb +
On 7/29/21 5:39 AM, Jiaxun Yang wrote:
> ELF kernel allows us debugging much easier with DWARF symbols.
You can load the symbols using the 'loader' device:
docs/system/generic-loader.rst.
> Signed-off-by: Jiaxun Yang
> ---
> hw/mips/boston.c | 38 ++
> 1
The thing is I still think this extra operation during sync() can be ignored by
simply clear dirty log during bitmap init, then.. why not? :)
I guess clearing the dirty log (especially in KVM) might be more expensive.
If we send one ioctl per cb that'll be expensive for sure. I think it'll
These two jobs are currently failing very often - the linker seems to
get killed due to out-of-memory problems. Since apparently nobody has
currently an idea how to fix that nicely, let's mark the jobs as manual
for the time being until someone comes up with a proper fix.
Message-Id:
From: Philippe Mathieu-Daudé
We introduced the QEMU_CI_AVOCADO_TESTING variable in commit f56bf4caf
("gitlab: Run Avocado tests manually (except mainstream CI)"), but
forgot to document it properly. Do it now.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel
28.07.2021 10:00, Max Reitz wrote:
On 27.07.21 18:47, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
That's an alternative to (part of) Max's
"[PATCH for-6.1? v2 0/7] mirror: Handle errors after READY cancel"
and shows' my idea of handling soft-cancelling READY mirror case
directly in
On 23.07.2021 12:59, Denis Plotnikov wrote:
ping!
On 19.07.2021 17:21, Denis Plotnikov wrote:
On vhost-user-blk migration, qemu normally sends a number of commands
to enable logging if VHOST_USER_PROTOCOL_F_LOG_SHMFD is negotiated.
Qemu sends VHOST_USER_SET_FEATURES to enable buffers logging
Implement the MVE integer vector comparison instructions. These are
"VCMP (vector)" encodings T1, T2 and T3, and "VPT (vector)" encodings
T1, T2 and T3.
These insns compare corresponding elements in each vector, and update
the VPR.P0 predicate bits with the results of the comparison. VPT
also
In some situations we need a mask telling us which parts of the
vector correspond to beats that are not being executed because of
ECI, separately from the combined "which bytes are predicated away"
mask. Factor this mask calculation out of mve_element_mask() into
its own function.
Signed-off-by:
Factor out the "generate code to update VPR.MASK01/MASK23" part of
trans_VPST(); we are going to want to reuse it for the VPT insns.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-mve.c | 31 +--
1 file changed, 17
Implement the MVE integer min/max across vector insns
VMAXV, VMINV, VMAXAV and VMINAV, which find the maximum
from the vector elements and a general purpose register,
and store the maximum back into the general purpose
register.
These insns overlap with VRMLALDAVH (they use what would
be
Implement the MVE VCMUL and VCMLA insns.
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 18
target/arm/mve.decode | 35
target/arm/mve_helper.c| 86 ++
target/arm/translate-mve.c | 8
4 files changed,
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The printf should have been qemu_log_mask, the parameters
> themselves no longer compile, and because this is placed
> before unwinding the PC is actively wrong.
>
> We get better (and correct) logging on the other side of
> raising the exception, in
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We will shortly use the MemOpIdx directly, but in the meantime
> re-compute the trace meminfo.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/atomic_template.h | 48 +--
> accel/tcg/atomic_common.c.inc | 30
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: qemu-...@nongnu.org
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-a64.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We should not have been using the helper_ret_* set of
> functions, as they are supposed to be private to tcg.
> Nor should we have been using the plain cpu_*_data set
> of functions, as they do not handle unwinding properly.
>
> Cc: Philippe
On 16/07/21 13:58, Vitaly Kuznetsov wrote:
QEMU coding style requires braces around bodies of ifs.
Reported-by: Peter Maydell
Signed-off-by: Vitaly Kuznetsov
---
target/i386/kvm/kvm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/i386/kvm/kvm.c
On 7/29/21 5:39 AM, Jiaxun Yang wrote:
> Use memmap array to unfiy address of memory map.
> That would allow us reuse address information for FDT generation.
>
> Signed-off-by: Jiaxun Yang
> ---
> hw/mips/boston.c | 95
> 1 file changed, 71
On Wed, 28 Jul 2021 10:19:51 -0500
Eric DeVolder wrote:
> On 7/27/21 7:55 AM, Igor Mammedov wrote:
> > PS:
> > If I haven't said it already, use checkpatch script before posting patches.
> >
>
> I do run checkpatch. On occasion I allow a warning about a line too long. And
> there is the
Hello everybody,
please, can somebody accept the fix for master?
It should be ideally applied even to stable
branches.
Or should I send request through some other form
then on the list?
Thanks,
Pavel
On Monday 26 of July 2021 18:24:58 Pavel Pisa wrote:
> Problem reported by openEuler fuzz-sig
Implement the MVE narrowing move insns VMOVN, VQMOVN and VQMOVUN.
These take a double-width input, narrow it (possibly saturating) and
store the result to either the top or bottom half of the output
element.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
We were not paying attention to the ECI state when advancing the VPT
state. Architecturally, VPT state advance happens for every beat
(see the pseudocode VPTAdvance()), so on every beat the 4 bits of
VPR.P0 corresponding to the current beat are inverted if required,
and at the end of beats 1 and
The MVEGenDualAccOpFn is a bit misnamed, since it is used for
the "long dual accumulate" operations that use a 64-bit
accumulator. Rename it to MVEGenLongDualAccOpFn so we can
use the former name for the 32-bit accumulator insns.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
Implement the MVE VCTP insn, which sets the VPR.P0 predicate bits so
as to predicate any element at index Rn or greater is predicated. As
with VPNOT, this insn itself is predicable and subject to beatwise
execution.
The calculation of the mask is the same as is used to determine
ltpmask in
Implement the MVE VMAXNMA and VMINNMA insns; these are 2-operand, but
the destination register must be the same as one of the source
registers.
We defer the decode of the size in bit 28 to the individual insn
patterns rather than doing it in the format, because otherwise we
would have a single
Implement the MVE VFMA and VFMS insns.
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 6 ++
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c| 36
target/arm/translate-mve.c | 2 ++
4 files changed, 47 insertions(+)
diff
From: Alexey Kardashevskiy
Coverity reported issues which are caused by mixing of signed return codes
from DTC and unsigned return codes of the client interface.
This introduces PROM_ERROR and makes distinction between the error types.
This fixes NEGATIVE_RETURNS, OVERRUN issues reported by
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The helper_*_mmu functions were the only thing available
> when this code was written. This could have been adjusted
> when we added cpu_*_mmuidx_ra, but now we can most easily
> use the newest set of interfaces.
>
> Cc: qemu-s3...@nongnu.org
>
On 28/07/21 13:37, Lara Lazier wrote:
+if (virtual_gif_enabled(env, int_ctl) && likely(env->hflags &
HF_GUEST_MASK)) {
+x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
+int_ctl | V_GIF_MASK);
+} else {
I would put the
On 7/28/21 4:03 PM, Guenter Roeck wrote:
> On 7/28/21 6:25 AM, Ard Biesheuvel wrote:
>> On Wed, 28 Jul 2021 at 15:11, Michael S. Tsirkin wrote:
>>>
>>> On Tue, Jul 27, 2021 at 12:36:03PM +0200, Igor Mammedov wrote:
>>> As others noted the original commit was kind of vague:
>>>
>>> 1. it said
Le 27/07/2021 à 22:41, Peter Maydell a écrit :
> The remaining text in docs/barrier.txt is user-facing description
> of what the device is and how to use it. Move this into the
> system manual and rstify it.
>
> Signed-off-by: Peter Maydell
> ---
> docs/barrier.txt| 48
Hello,
On Thu, 29 Jul 2021, Howard Spoelstra wrote:
Hi,
Qemu-system-ppc built from current master can no longer run Fedora 12 ppc
as guest. (This the only ppc distro I tested.) Host is Fedora 34. Please
see screen shot attached.
Booting from both an installation DVD and from an installed
Implement the MVE VMLA insn, which multiplies a vector by a scalar
and accumulates into another vector.
Signed-off-by: Peter Maydell
---
Changes v1->v2: don't decode U bit
---
target/arm/helper-mve.h| 4
target/arm/mve.decode | 1 +
target/arm/mve_helper.c| 5 +
Implement the MVE integer vector comparison instructions that compare
each element against a scalar from a general purpose register. These
are "VCMP (vector)" encodings T4, T5 and T6 and "VPT (vector)"
encodings T4, T5 and T6.
We have to move the decodetree pattern for VPST, because it
overlaps
Implement the MVE gather-loads and scatter-stores which
form the address by adding a base value from a scalar
register to an offset in each element of a vector.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
v2: UNDEF the UNPREDICTABLE Qd==Qm case for loads
---
Implement the MVE VPSEL insn, which sets each byte of the destination
vector Qd to the byte from either Qn or Qm depending on the value of
the corresponding bit in VPR.P0.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 2 ++
target/arm/mve.decode
Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These
calculate the maximum or minimum of floating point elements across a
vector, starting with a value in a general purpose register and
returning the result there.
The pseudocode silences a possible SNaN in the accumulating result
On 28/07/21 12:17, Lara Lazier wrote:
v1->v2: Fixed Mask
The APM2 states that The processor takes a virtual INTR interrupt
if V_IRQ and V_INTR_PRIO indicate that there is a virtual interrupt pending
whose priority is greater than the value in V_TPR.
Signed-off-by: Lara Lazier
---
On 29.07.21 02:46, Richard Henderson wrote:
Cc: qemu-s3...@nongnu.org
Signed-off-by: Richard Henderson
---
target/s390x/cpu.c | 2 +-
target/s390x/tcg/excp_helper.c | 28 +++-
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: Max Filippov
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/cpu.c| 2 +-
> target/xtensa/helper.c | 30 +++---
> 2 files changed, 16 insertions(+), 16 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé
Jobs depending on another should not use the 'when: always'
condition, because if a dependency failed we should not keep
running jobs depending on it. The correct condition is
'when: on_success'.
Fixes: 71920809cea ("gitlab-ci.yml: Add jobs to build EDK2 firmware
If maintainers are currently pushing to a branch called "staging"
in their repository, they are ending up with some stuck jobs - unless
they have a s390x CI runner machine available. That's ugly, we should
make sure that the related jobs are really only started if such a
runner is available. So
The iotests 197 and 215 are occasionally failing in the gitlab-CI now.
According to the log, the failure is "./common.rc: Killed" which might
be an indication that the process has been killed due to out-of-memory
reasons. Both tests are doing a big read with 2G that likely causes
this issue. It
On Thu, Jul 29, 2021 at 11:10:29AM +0200, Fabian Ebner wrote:
Linux SCSI can throw spurious -EAGAIN in some corner cases in its
completion path, which will end up being the result in the completed
io_uring request.
Resubmitting such requests should allow block jobs to complete, even
if such
Cc'ing QEMU fuzz team.
On 7/29/21 11:19 AM, Pavel Pisa wrote:
> Hello everybody,
>
> please, can somebody accept the fix for master?
> It should be ideally applied even to stable
> branches.
>
> Or should I send request through some other form
> then on the list?
I suppose the patch fell
On 7/29/21 12:29 PM, Gerd Hoffmann wrote:
> Hi,
>
>> And another comment: I think we should have some progress on ARM with
>> the kvm/tcg split and with the KConfig of boards, before we continue
>> here.
>
> Why? This can easily be tacked in parallel. We can flip the switch
> for modular tcg
Include the MVE VPR register value in the CPU dumps produced by
arm_cpu_dump_state() if we are printing FPU information. This
makes it easier to interpret debug logs when predication is
active.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 3 +++
1 file
Implement the MVE 1-operand saturating operations VQABS and VQNEG.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 8
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c| 37 +
Implement the MVE instructions which perform shifts by a scalar.
These are VSHL T2, VRSHL T2, VQSHL T1 and VQRSHL T2. They take the
shift amount in a general purpose register and shift every element in
the vector by that amount.
Mostly we can reuse the helper functions for shift-by-immediate; we
Implement the MVE VMLAS insn, which multiplies a vector by a vector
and adds a scalar.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
changes: don't decode U bit as it does not affect output values
---
target/arm/helper-mve.h| 4
target/arm/mve.decode | 3 +++
Implement the MVE saturating doubling multiply accumulate insns
VQDMLAH, VQRDMLAH, VQDMLASH and VQRDMLASH. These perform a multiply,
double, add the accumulator shifted by the element size, possibly
round, saturate to twice the element size, then take the high half of
the result. The *MLAH insns
On 28/07/2021 20.26, Philippe Mathieu-Daudé wrote:
On 7/28/21 7:38 PM, Thomas Huth wrote:
If maintainers are currently pushing to a branch called "staging"
in their repository, they are ending up with some stuck jobs - unless
they have a s390x CI runner machine available. That's ugly, we should
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: qemu-...@nongnu.org
> Signed-off-by: Richard Henderson
> ---
> target/ppc/translate.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The function is trivial for user-only, but still must be present.
>
> Cc: Taylor Simpson
> Signed-off-by: Richard Henderson
> ---
> target/hexagon/cpu.h | 9 +
> 1 file changed, 9 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 29.07.21 02:46, Richard Henderson wrote:
Cc: qemu-s3...@nongnu.org
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index
On 05/05/21 17:38, Stefan Hajnoczi wrote:
On Wed, May 05, 2021 at 07:13:13PM +0400, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
../subprojects/libvhost-user/libvhost-user.c:1070:12: error: format ‘%lx’
expects argument of type ‘long unsigned int’, but argument 3 has type
From: Philippe Mathieu-Daudé
Jobs depending on another should not use the 'when: always'
condition, because if a dependency failed we should not keep
running jobs depending on it. The correct condition is
'when: on_success'.
Fixes: c6fc0fc1a71 ("gitlab-ci.yml: Add jobs to build OpenSBI firmware
From: Philippe Mathieu-Daudé
Jobs depending on another should not use the 'when: always'
condition, because if a dependency failed we should not keep
running jobs depending on it. The correct condition is
'when: on_success'.
Fixes: f56bf4caf71 ("gitlab: Run Avocado tests manually (except
From: Peter Xu
Even if seems to exist for all archs on linux, however including
it with __linux__ defined seems to be not working yet as it'll try to include
asm/kvm.h and that can be missing for archs that do not support kvm.
To fix this (instead of any attempt to fix linux headers..), we can
From: Richard Zak
Haiku does not support compiling with -fpie. See the discussion here
for details:
https://discuss.haiku-os.org/t/qemu-on-haiku-sdl-issue/10961/6?u=rjzak
Signed-off-by: Richard Zak
Message-Id:
[thuth: Tweaked title and patch description]
Signed-off-by: Thomas Huth
---
On Wed, Jul 28 2021, Yanan Wang wrote:
> In the real SMP hardware topology world, it's much more likely that
> we have high cores-per-socket counts and few sockets totally. While
> the current preference of sockets over cores in smp parsing results
> in a virtual cpu topology with low
Linux SCSI can throw spurious -EAGAIN in some corner cases in its
completion path, which will end up being the result in the completed
io_uring request.
Resubmitting such requests should allow block jobs to complete, even
if such spurious errors are encountered.
Co-authored-by: Stefan Hajnoczi
On Thu, 29 Jul 2021 at 08:31, ishii.shuuic...@fujitsu.com
wrote:
>
> Hi, Peter.
>
> > This adds a64fx to the list of CPUs we support in the 'virt' board, but it
> > hasn't
> > changed the valid_cpus[] array in hw/arm/virt.c, so trying to actually use
> > -cpu
> > a64fx with -machine virt will
Implement the MVE VMULL (polynomial) insn. Unlike Neon, this comes
in two flavours: 8x8->16 and a 16x16->32. Also unlike Neon, the
inputs are in either the low or the high half of each double-width
element.
The assembler for this insn indicates the size with "P8" or "P16",
encoded into bit 28
In mve_element_mask(), we calculate a mask for tail predication which
should have a number of 1 bits based on the value of LR. However,
our MAKE_64BIT_MASK() macro has undefined behaviour when passed a
zero length. Special case this to give the all-zeroes mask we
require.
Signed-off-by: Peter
In do_sqrshl48_d() and do_uqrshl48_d() we got some of the edge
cases wrong and failed to saturate correctly:
(1) In do_sqrshl48_d() we used the same code that do_shrshl_bhs()
does to obtain the saturated most-negative and most-positive 48-bit
signed values for the large-shift-left case. This
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