Move the following instructions to decodetree:
dtstdc: DFP Test Data Class
dtstdcq: DFP Test Data Class Quad
dtstdg: DFP Test Data Group
dtstdgq: DFP Test Data Group Quad
Signed-off-by: Luis Pires
---
target/ppc/dfp_helper.c | 8 +++
target/ppc/helper.h | 8
On Tue, 24 Aug 2021 at 15:27, Markus Armbruster wrote:
>
> Peter Maydell writes:
>
> > On Tue, 24 Aug 2021 at 13:05, Markus Armbruster wrote:
> >> When you know that all callers handle errors like _fatal does, use
> >> of _fatal doesn't produce wrong behavior. It's still kind of
> >> wrong,
On Mon, Aug 16, 2021 at 09:42:38AM -0700, Elena Ufimtseva wrote:
> @@ -62,5 +65,10 @@ typedef struct VFIOProxy {
>
> VFIOProxy *vfio_user_connect_dev(SocketAddress *addr, Error **errp);
> void vfio_user_disconnect(VFIOProxy *proxy);
> +void vfio_user_set_reqhandler(VFIODevice *vbasdev,
Am 17.08.2021 um 20:48 hat Peter Maydell geschrieben:
> On Tue, 17 Aug 2021 at 17:27, Dr. David Alan Gilbert
> wrote:
> >
> > * Gabriel Southern (gsout...@qti.qualcomm.com) wrote:
> > > Hi,
> > >
> > > Are there plans to support using -loadvm with -snapshot?
> > >
> > > I saw some past discussion
pylint proposes using `[]` instead of `list()` and `{}` instead of
`dict()`, because it is faster. That seems simple enough, so heed its
advice.
Signed-off-by: Hanna Reitz
---
tests/qemu-iotests/iotests.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Hi,
I’ve updated my pylint to 2.10.2 and was greeted with some new warnings.
Some are fixed by John’s “Run iotest linters during Python CI” series
(https://lists.nongnu.org/archive/html/qemu-block/2021-07/msg00611.html),
but some are not (namely unspecified-encoding, use-list-literal, and
As of recently, pylint complains when `open()` calls are missing an
`encoding=` specified. Everything we have should be UTF-8 (and in fact,
everything should be UTF-8, period (exceptions apply)), so use that.
Signed-off-by: Hanna Reitz
---
tests/qemu-iotests/297| 2 +-
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
You should mention in the commit message that this fixes two bugs:
* SIGSEGV not distinguishing MAPERR from ACCERR
* SIGTRAP on breakpoint not
On 8/22/21 5:55 AM, Richard Henderson wrote:
> From: Peter Maydell
>
> Use the new force_sig_fault() function instead of setting up
> a target_siginfo_t and calling queue_signal().
>
> Signed-off-by: Peter Maydell
> Message-Id: <20210813131809.28655-8-peter.mayd...@linaro.org>
> Signed-off-by:
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions
(Perf event PM_INST_CMPL) by counting the amount of instructions
translated
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter.
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu.h| 3 +++
The initial PMU support were made under the assumption that the counters
would be set before running the PMU and read after either freezing the
PMU manually or via a performance monitor alert.
Turns out that some EBB powerpc kernel tests set the counters after
unfreezing the counters. Setting a
On Dienstag, 24. August 2021 16:45:12 CEST Markus Armbruster wrote:
> Christian Schoenebeck writes:
> > On Dienstag, 24. August 2021 10:22:52 CEST Markus Armbruster wrote:
> [...]
>
> >> Please use GPLv2+ unless you have a compelling reason not to.
> >>
> >> [...]
> >
> > Is that a
On 8/22/21 5:55 AM, Richard Henderson wrote:
> From: Peter Maydell
>
> The target_siginfo_t we populate in force_sig() will eventually
> get copied onto the target's stack. Zero it out so that any extra
> padding in the sifields union is consistently zero when the guest
> sees it.
>
>
From: Gustavo Romero
Similar to the previous patch, user write on some PowerPC
PMU regs, in this case, MMCR0, is limited. Create a new
function to handle that.
CC: Gustavo Romero
Signed-off-by: Gustavo Romero
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu_init.c | 2 +-
This patch adds the barebones of the PMU logic by enabling cycle
counting, done via the performance monitor counter 6. The overall logic
goes as follows:
- a helper is added to control the PMU state on each MMCR0 write. This
allows for the PMU to start/stop as the frozen counter bit (MMCR0_FC)
is
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
Where this is changing behaviour to fix bugs you should mention
it in the commit message:
* address field for breakpoint trap
* si_code for
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/mips/cpu_loop.c | 45 --
> 1 file changed, 14
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
Hi
On Tue, Aug 24, 2021 at 7:27 PM Peter Xu wrote:
> Both dump-guest-memory and live migration caches vm state at the beginning.
> Either of them entering the other one will cause race on the vm state, and
> even
> more severe on that (please refer to the crash report in the bug link).
>
>
Peter Maydell writes:
> On Tue, 24 Aug 2021 at 15:27, Markus Armbruster wrote:
>>
>> Peter Maydell writes:
>>
>> > On Tue, 24 Aug 2021 at 13:05, Markus Armbruster wrote:
>> >> When you know that all callers handle errors like _fatal does, use
>> >> of _fatal doesn't produce wrong behavior.
Both dump-guest-memory and live migration have vm state cached internally.
Allowing them to happen together means the vm state can be messed up. Simply
block live migration for dump-guest-memory.
One trivial thing to mention is we should still allow dump-guest-memory even if
-only-migratable is
Both dump-guest-memory and live migration caches vm state at the beginning.
Either of them entering the other one will cause race on the vm state, and even
more severe on that (please refer to the crash report in the bug link).
Let's block live migration in dump-guest-memory, and that'll also
On Dienstag, 24. August 2021 17:24:50 CEST Christian Schoenebeck wrote:
> On Dienstag, 24. August 2021 16:45:12 CEST Markus Armbruster wrote:
> > Christian Schoenebeck writes:
> > > On Dienstag, 24. August 2021 10:22:52 CEST Markus Armbruster wrote:
> > [...]
> >
> > >> Please use GPLv2+ unless
On Mon, Aug 16, 2021 at 09:42:39AM -0700, Elena Ufimtseva wrote:
> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
> index 7005d9f891..eae33e746f 100644
> --- a/hw/vfio/pci.c
> +++ b/hw/vfio/pci.c
> @@ -3397,6 +3397,12 @@ static void vfio_user_pci_realize(PCIDevice *pdev,
> Error **errp)
>
On Mon, Aug 16, 2021 at 09:42:40AM -0700, Elena Ufimtseva wrote:
> +int vfio_user_get_info(VFIODevice *vbasedev)
> +{
> +VFIOUserDeviceInfo msg;
> +
> +memset(, 0, sizeof(msg));
> +vfio_user_request_msg(, VFIO_USER_DEVICE_GET_INFO, sizeof(msg),
> 0);
> +msg.argsz = sizeof(struct
On 24.08.21 00:05, Michael S. Tsirkin wrote:
On Mon, Aug 23, 2021 at 03:18:51PM -0400, Peter Xu wrote:
On Mon, Aug 23, 2021 at 02:49:12PM -0400, Eduardo Habkost wrote:
On Wed, Aug 18, 2021 at 03:43:18PM -0400, Peter Xu wrote:
QEMU creates -device objects in order as specified by the user's
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> These si_codes were changed in 535906c684fca, for linux 4.17.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/syscall_defs.h | 1 +
> linux-user/alpha/cpu_loop.c | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+
emulation and following PowerISA v3.1.
PowerISA v3.1 defines two PMU registers groups, A and B:
- group A contains all performance monitor counters (PMCs), MMCR0, MMCR2
and MMCRA;
- group B contains MMCR1, MMCR3, SIER,
On Thu, Aug 12, 2021 at 3:04 PM Daniel P. Berrangé wrote:
>
> This splits the CI docs into one file talking about job setup and usage
> and another file describing provisioning of custom runners.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> docs/devel/ci-jobs.rst| 40 ++
>
Up until this moment we were assuming that the counter negative
enabled bits, PMC1CE and PMCjCE, would never be changed when the
PMU is already started.
Turns out that there is no such restriction in the PowerISA v3.1,
and software can enable/disable overflow conditions of the counters
at any
The current logic is only considering event-based exceptions triggered
by the performance monitor. This is true now, but we might want to add
support for external event-based exceptions in the future.
Let's make it a bit easier to do so by adding the bit logic that would
happen in case we were
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> These si_codes have been properly set by the kernel since the beginning.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On 20.07.21 19:33, John Snow wrote:
GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-package-iotest
CI: https://gitlab.com/jsnow/qemu/-/pipelines/340144191
I’ll take the liberty of applying patches 1 and 2 to my block-next
branch, because, well, they fix some of the 297 errors I’m
[ Cc: qemu-block ]
Am 11.08.2021 um 13:36 hat Christopher Pereira geschrieben:
> Hi,
>
> I'm reading a directory with 5.000.000 files (2,4 GB) inside a guest using
> "find | grep -c".
>
> On the host I saw high write IO (40 MB/s !) during over 1 hour using
> virt-top.
>
> I later repeated the
On Tue, Aug 24, 2021 at 10:52:24AM +0800, Jason Wang wrote:
> It looks to me this doesn't solve the issue of using virtio-mmio with vhost?
No IOMMU supported for any of the MMIO devices, right? Or am I wrong? Thanks,
--
Peter Xu
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
24.08.2021 18:51, Hanna Reitz wrote:
On 24.08.21 10:38, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
v8:
06: add Hanna's r-b
07: keep is_fleecing detection in _new() function
08,17,18: add Hanna's r-b
19: wording, s/6.1/6.2/, add Markus's a-b
25: new
29: add John's r-b
34: new
Patches without
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> This si_code was changed in 75abf64287cab, for linux 4.17.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/syscall_defs.h | 1 +
> linux-user/hppa/cpu_loop.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Fix a typo for ESR_EC_DIVZERO, which is integral not floating-point.
> Fix the if ladder for decoding floating-point exceptions.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/microblaze/cpu_loop.c | 20 +++-
>
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/openrisc/cpu_loop.c | 37 +-
> 1 file changed, 10
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/sh4/cpu_loop.c | 14 --
> 1 file changed, 4 insertions(+), 10 deletions(-)
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/s390x/cpu_loop.c | 16 +---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/xtensa/cpu_loop.c | 34 --
> 1 file changed, 12
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Most linux-user targets so far do not distinguish between SEGV_MAPERR
> and SEGV_ACCERR. This function will be used to fix that.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/signal-common.h | 1 +
> linux-user/signal.c
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> This si_code was changed in 4cc13e4f6d441, for linux 4.17.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new function instead of setting up a target_siginfo_t
> and calling queue_signal. Note that we were incorrectly using
> QEMU_SI_KILL instead of QEMU_SI_FAULT for raising SIGSEGV.
>
> Signed-off-by: Richard Henderson
> ---
>
This patch starts the counter negative EBB support by enabling PMC1
counter negative overflow when PMC1 is counting cycles.
A counter negative overflow happens when a performance monitor counter
reaches the value 0x8000. When that happens, if counter negative
condition events are enabled in
Enabling counter negative overflow for the PMCs that are counting
instructions is simpler than when counting cycles. Instruction
counting is done via helper_insns_inc(), which is called every
time a TB ends.
Firing a performance monitor alert due to a counter negative overflow
in this case is a
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> Signed-off-by: Richard Henderson
Commit message should mention behaviour changes.
Otherwise
Reviewed-by: Peter Maydell
thanks
-- PMM
On 8/22/21 5:55 AM, Richard Henderson wrote:
> Rename to do_tr_or_bp, as per the kernel function.
> Add a 'trap' argument, akin to the kernel's si_code, but clearer.
> The return value is always 0, so change the return value to void.
> Use force_sig and force_sig_fault.
>
> Signed-off-by: Richard
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Use the new functions instead of setting up a target_siginfo_t
> and calling queue_signal.
>
> The user-only version of ppc_cpu_tlb_fill does not distinguish
> between the various hw codes. Drop all of that and just use
> the new
On Tue, Aug 24, 2021 at 7:27 PM Peter Xu wrote:
> An internal version that removes -only-migratable implications. It can be
> used
> for temporary migration blockers like dump-guest-memory.
>
> Signed-off-by: Peter Xu
>
Reviewed-by: Marc-André Lureau
---
> include/migration/blocker.h | 16
An internal version that removes -only-migratable implications. It can be used
for temporary migration blockers like dump-guest-memory.
Signed-off-by: Peter Xu
---
include/migration/blocker.h | 16
migration/migration.c | 21 +
2 files changed, 29
On 24.08.21 10:38, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
v8:
06: add Hanna's r-b
07: keep is_fleecing detection in _new() function
08,17,18: add Hanna's r-b
19: wording, s/6.1/6.2/, add Markus's a-b
25: new
29: add John's r-b
34: new
Patches without r-b: 07, 25, 34
Thanks! I’ve
Am 24.08.2021 um 17:25 hat Peter Maydell geschrieben:
> On Tue, 24 Aug 2021 at 16:21, Kevin Wolf wrote:
> >
> > Am 17.08.2021 um 20:48 hat Peter Maydell geschrieben:
> > > On Tue, 17 Aug 2021 at 17:27, Dr. David Alan Gilbert
> > > wrote:
> > > >
> > > > * Gabriel Southern
We're missing two counter freeze bits that are used to further control
how the PMCs behaves: MMCR0_FC14 and MMCR0_FC56. These bits can frozen
PMCs separately: MMCR0_FC14 freezes PMCs 1 to 4 and MMCR0_FC56 freezes
PMCs 5 and 6.
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu.h|
This patch enable all PMCs but PMC5 to count cycles. To do that we
need to implement MMCR1 bits where the event are stored, retrieve
them, see if the PMC was configured with a PM_CYC event, and
calculate cycles if that's the case.
PowerISA v3.1 defines the following conditions to count cycles:
-
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The EBB
On Sun, 22 Aug 2021 at 04:55, Richard Henderson
wrote:
>
> Reduce the number of ifdefs within cpu_loop().
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, Aug 24, 2021 at 4:02 AM Richard Henderson
wrote:
>
> We distinguish write-only by passing ret_value as NULL.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/csr.c | 23 +++
> 1 file changed, 15 insertions(+), 8 deletions(-)
>
Reviewed-by: Bin Meng
On 8/24/21 12:26 AM, Alexander Bulekov wrote:
> On 210823 1650, Peter Xu wrote:
>> On Mon, Aug 23, 2021 at 08:10:50PM +0100, Peter Maydell wrote:
>>> On Mon, 23 Aug 2021 at 17:42, Philippe Mathieu-Daudé
>>> wrote:
This series aim to kill a recent class of bug, the infamous
"DMA
. Add "smmuv3_sidmap" to set non PCI/PCIe devices SID value
. Pass non PCI/PCIe devices SID value to SMMU v3 model creation
. Store SMMU v3 device in virtual machine then non PCI/PCIe can get its
memory region later
Signed-off-by: Li, Chunming
---
hw/arm/virt.c | 18
Replace "smmuv3_flush_config" with "g_hash_table_foreach_remove" based on
devices SID.
"smmu_iommu_mr" function can't get MR according to SID for non PCI/PCIe devices.
Signed-off-by: Li, Chunming
---
hw/arm/smmuv3.c | 35 ++-
Hi all!
v8:
06: add Hanna's r-b
07: keep is_fleecing detection in _new() function
08,17,18: add Hanna's r-b
19: wording, s/6.1/6.2/, add Markus's a-b
25: new
29: add John's r-b
34: new
Patches without r-b: 07, 25, 34
Vladimir Sementsov-Ogievskiy (34):
block: introduce bdrv_replace_child_bs()
Finally, copy-before-write gets own .bdrv_open and .bdrv_close
handlers, block_init() call and becomes available through bdrv_open().
To achieve this:
- cbw_init gets unused flags argument and becomes cbw_open
- block_copy_state_free() call moved to new cbw_close()
- in bdrv_cbw_append:
-
On 24/08/2021 11.16, Peter Maydell wrote:
On Tue, 24 Aug 2021 at 08:27, Thomas Huth wrote:
The versions that we specify for macOS are way too old already. Let's
rephrase this without specific version numbers, pointing the users
to the latest version instead.
Signed-off-by: Thomas Huth
---
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 19 ---
include/hw/misc/mos6522.h | 3 +++
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 8991f4..5b1657ac0d 100644
--- a/hw/misc/mos6522.c
+++
The LBA28 capacity (at offsets 60/61 of identification) is supposed to
express the maximum size supported by LBA28 commands. If the device is
larger than this, we have to cap it to 2^28-1.
At least NetBSD happens to be using this value to determine whether to use
LBA28 or LBA48 for its commands,
On Tue, 24 Aug 2021, Ani Sinha wrote:
>
>
> On Tue, 24 Aug 2021, Igor Mammedov wrote:
>
> > On Mon, 23 Aug 2021 19:06:47 -0400
> > "Michael S. Tsirkin" wrote:
> >
> > > On Sat, Aug 21, 2021 at 08:35:35PM +0530, Ani Sinha wrote:
> > > > Bsel property of the pci bus indicates whether the bus
Gerd Hoffmann 于2021年8月24日周二 下午8:02写道：
>
> Hi,
>
> > I was vaguely tossing an idea around in the back of my mind
> > about whether you could have a flag on devices that marked
> > them as "this device is currently involved in IO", such that
> > you could then just fail the last DMA (or
From: Andrew Jones
Support device tree CPU topology descriptions.
In accordance with the Devicetree Specification, the Linux Doc
"arm/cpus.yaml" requires that cpus and cpu nodes in the DT are
present. And we have already met the requirement by generating
/cpus/cpu@* nodes for members within
qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it
also adds all missing subnodes from the given path. We'll use it
in a coming patch where we will add cpu-map to the device tree.
And we also tweak an error message of qemu_fdt_add_subnode().
Cc: David Gibson
Cc: Alistair Francis
On Mon, Aug 23, 2021 at 06:41:57PM +0200, Philippe Mathieu-Daudé wrote:
> Check bus permission in flatview_access_allowed() before
> running any bus transaction.
>
> There is not change for the default case (MEMTXPERM_UNSPECIFIED).
>
> The MEMTXPERM_UNRESTRICTED case works as an allow list.
On 8/24/21 3:15 PM, Stefan Hajnoczi wrote:
> On Mon, Aug 23, 2021 at 06:41:57PM +0200, Philippe Mathieu-Daudé wrote:
>> Check bus permission in flatview_access_allowed() before
>> running any bus transaction.
>>
>> There is not change for the default case (MEMTXPERM_UNSPECIFIED).
>>
>> The
Should have done this much sooner given the amount of reviewing I'm
already doing in this area.
Signed-off-by: Darren Kenny
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6b3697962c1b..5bef084ca173 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
Simplify qemu_vfio_dma_[un]map() handlers by replacing a pair of
qemu_mutex_lock/qemu_mutex_unlock calls by the WITH_QEMU_LOCK_GUARD
macro.
Signed-off-by: Philippe Mathieu-Daudé
---
util/vfio-helpers.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git
qemu_vfio_add_mapping() returns a pointer to an indexed entry
in pre-allocated QEMUVFIOState::mappings[], thus can not be NULL.
Remove the pointless check.
Signed-off-by: Philippe Mathieu-Daudé
---
util/vfio-helpers.c | 4
1 file changed, 4 deletions(-)
diff --git a/util/vfio-helpers.c
In preparation for changing the divu128/divs128 implementations
to allow for quotients larger than 64 bits, move the div-by-zero
and overflow checks to the callers.
Signed-off-by: Luis Pires
---
include/hw/clock.h| 5 +++--
include/qemu/host-utils.h | 36
This will be used to implement PowerPC's dcffixqq.
Signed-off-by: Luis Pires
---
include/libdecnumber/decNumber.h | 2 ++
libdecnumber/decNumber.c | 36
2 files changed, 38 insertions(+)
diff --git a/include/libdecnumber/decNumber.h
Signed-off-by: Luis Pires
---
tests/unit/meson.build | 1 +
tests/unit/test-div128.c | 185 +++
2 files changed, 186 insertions(+)
create mode 100644 tests/unit/test-div128.c
diff --git a/tests/unit/meson.build b/tests/unit/meson.build
index
Christian Schoenebeck writes:
> On Dienstag, 24. August 2021 10:22:52 CEST Markus Armbruster wrote:
[...]
>> Please use GPLv2+ unless you have a compelling reason not to.
>>
>> [...]
>
> Is that a requirement?
>
> It is just my personal license preference. AFAICS there are numerous sources
>
Move the following instructions to decodetree:
ddedpd: DFP Decode DPD To BCD
ddedpdq: DFP Decode DPD To BCD Quad
denbcd: DFP Encode BCD To DPD
denbcdq: DFP Encode BCD To DPD Quad
dscli: DFP Shift Significand Left Immediate
dscliq: DFP Shift Significand Left Immediate Quad
dscri: DFP Shift
On 8/24/21 1:06 PM, Ani Sinha wrote:
> On Tue, 24 Aug 2021, Ani Sinha wrote:
>> On Tue, 24 Aug 2021, Igor Mammedov wrote:
>>> On Mon, 23 Aug 2021 19:06:47 -0400
>>> "Michael S. Tsirkin" wrote:
>>>
On Sat, Aug 21, 2021 at 08:35:35PM +0530, Ani Sinha wrote:
> Bsel property of the pci bus
On Tue, 24 Aug 2021 at 13:05, Markus Armbruster wrote:
> When you know that all callers handle errors like _fatal does, use
> of _fatal doesn't produce wrong behavior. It's still kind of
> wrong, because relying on such a non-local argument without a genuine
> need is.
Not using error_fatal
This new version is based on patch series [1] which introduces some
fix and improvement for smp parsing.
Description:
Once the view of an accurate virtual cpu topology is provided to guest,
with a well-designed vCPU pinning to the pCPU we may get a huge benefit,
e.g., the scheduling performance
Dear QEMU & KVM community,
QEMU will apply for the Outreachy December-March round. This
internship program offers paid, full-time, remote work internships for
contributing to open source. QEMU can act as an umbrella organization
for KVM kernel projects.
If you are interested in applying for an
nvme_create_queue_pair() does not return a boolean value (indicating
eventual error) but a pointer, and is inconsistent in how it fills the
error handler. To fulfill callers expectations, always set an error
message on failure.
Reported-by: Auger Eric
Signed-off-by: Philippe Mathieu-Daudé
---
Fix when building with -Wshorten-64-to-32:
warning: implicit conversion loses integer precision: 'unsigned long' to
'int' [-Wshorten-64-to-32]
Signed-off-by: Philippe Mathieu-Daudé
---
block/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/trace-events
Currently qemu_vfio_dma_map() displays errors on stderr.
When using management interface, this information is simply
lost. Pass qemu_vfio_dma_map() an Error** handle so it can
propagate the error to callers.
Reviewed-by: Fam Zheng
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Philippe
Christian Schoenebeck writes:
> On Sonntag, 22. August 2021 15:16:46 CEST Christian Schoenebeck wrote:
>> Implements deep auto free of arrays while retaining common C-style
>> squared bracket access.
>>
>> Signed-off-by: Christian Schoenebeck
>> ---
>> include/qemu/qarray.h | 150
We expect the first qemu_vfio_dma_map() to fail (indicating
DMA mappings exhaustion, see commit 15a730e7a3a). Do not
report the first failure as error, since we are going to
flush the mappings and retry.
This removes spurious error message displayed on the monitor:
(qemu) c
(qemu) qemu-kvm:
This series moves all existing DFP instructions to decodetree and
implements the 2 new instructions (dcffixqq and dctfixqq) from
Power ISA 3.1.
In order to implement dcffixqq, divu128/divs128 were modified to
support 128-bit quotients (previously, they were limited to 64-bit
quotients), along
The previous code didn't detect overflows if the high 64-bit
of the dividend were equal to the 64-bit divisor. In that case,
64 bits wouldn't be enough to hold the quotient.
Signed-off-by: Luis Pires
---
util/host-utils.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Move the following instructions to decodetree:
dqua: DFP Quantize
dquaq: DFP Quantize Quad
drrnd: DFP Reround
drrndq: DFP Reround Quad
Signed-off-by: Luis Pires
---
target/ppc/dfp_helper.c | 8 ++---
target/ppc/helper.h | 8 ++---
target/ppc/insn32.decode
This is a patch series that I started last year. The aim was to try to
get a monotonic clocksource for Linux/m68k guests. That aim hasn't been
achieved yet (for q800 machines) but I'm submitting the patch series as
an RFC because,
- It does improve 6522 emulation fidelity.
- It allows
This code appears to be unnecessary.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 22 +-
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 1c57332b40..a478c1ca43 100644
--- a/hw/misc/mos6522.c
+++
On Tue, Aug 24, 2021 at 11:19 AM Peter Maydell wrote:
> On Tue, 24 Aug 2021 at 09:22, Philippe Mathieu-Daudé wrote:
> > On 8/23/21 9:46 PM, Gautam Bhat wrote:
> > > On Sun, Aug 22, 2021 at 10:18 PM Peter Maydell
> > > wrote:
> > >> On Sun, 22 Aug 2021 at 15:37, Gautam Bhat wrote:
> > >>>
> >
With the thread pool disabled, we add the requests in the queue to a
GList, processing by iterating over there afterwards.
For adding them, we're using "g_list_prepend()", which is more
efficient but causes the requests to be processed in reverse order,
breaking the read-ahead and request-merging
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