Vasilev Oleg writes:
> Hi everyone,
>
> I've recently been tasked with improving QEMU performance and would like
> to discuss several possible optimizations which we could implement and
> later upstream.
Excellent - it's always good to see others that want to improve our
emulation performance
We may have gotten a measurement update interval from the underlying host
via vfio -- Use it to set the interval via which we update the function
measurement block.
Fixes: 28dc86a072 ("s390x/pci: use a PCI Group structure")
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-inst.c | 5 +++--
1
A collection of small fixes for s390x PCI (not urgent). The first 3 are
fixes related to always using the host-provided CLP value when provided
vs a hard-coded value. The last patch adds logic for QEMU to report a
proper DTSM clp response rather than just 0s (guest
From: Hyman Huang(黄勇)
Introduce the third method GLOBAL_DIRTY_LIMIT of dirty
tracking for calculate dirtyrate periodly for dirty restraint.
Implement thread for calculate dirtyrate periodly, which will
be used for dirty restraint.
Add dirtylimit.h to introduce the util function for dirty
limit
From: Hyman Huang(黄勇)
Impose dirty restraint on vCPU by kicking it and sleep
as the auto-converge does during migration, but just
kick the specified vCPU instead, not all vCPUs of vm.
Start a thread to track the dirtylimit status and adjust
the throttle pencentage dynamically depend on current
On 12/2/21 11:42, Cédric Le Goater wrote:
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in the chip. In case of user
created devices, a
On 12/2/21 11:42, Cédric Le Goater wrote:
This requires a link to the chip to add the regions under the XSCOM
address space. This change will help us providing support for user
created PHB3 devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
On 12/2/21 11:42, Cédric Le Goater wrote:
Each PEC devices of the POWER9 chip has a predefined number of stacks,
s/devices/device ?
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove
On Thu, 2 Dec 2021 12:11:38 -0500
Matthew Rosato wrote:
> >
> > What happens if we migrate a VM from old to new QEMU? Won't the guest be
> > able to observe the change?
> >
>
> Yes, technically -- But # itself is not really all that important, it
> is provided from CLP Q PCI FN to be
On 11/19/21 05:47, Chao Peng wrote:
This RFC series try to implement the fd-based KVM guest private memory
proposal described at [1] and an improved 'New Proposal' described at [2].
I generally like this. Thanks!
On 12/2/2021 5:54 PM, Vladimir Sementsov-Ogievskiy wrote:
02.12.2021 11:53, Daniel P. Berrangé wrote:
On Thu, Dec 02, 2021 at 01:14:47PM +0800, Rao, Lei wrote:
Sorry, resending with correct indentation and quoting.
On 12/1/2021 10:27 PM, Vladimir Sementsov-Ogievskiy wrote:
01.12.2021
On 11/19/21 05:47, Chao Peng wrote:
From: "Kirill A. Shutemov"
The new seal type provides semantics required for KVM guest private
memory support. A file descriptor with the seal set is going to be used
as source of guest memory in confidential computing environments such as
Intel TDX and AMD
在 2021/12/3 0:02, Markus Armbruster 写道:
huang...@chinatelecom.cn writes:
From: Hyman Huang(黄勇)
Implement dirtyrate calculation periodically basing on
dirty-ring and throttle vCPU until it reachs the quota
dirty page rate given by user.
Introduce qmp commands
From: Hyman Huang(黄勇)
Impose dirty restraint on vCPU by kicking it and sleep
as the auto-converge does during migration, but just
kick the specified vCPU instead, not all vCPUs of vm.
Start a thread to track the dirtylimit status and adjust
the throttle pencentage dynamically depend on current
From: Hyman Huang(黄勇)
Implement dirtyrate calculation periodically basing on
dirty-ring and throttle vCPU until it reachs the quota
dirty page rate given by user.
Introduce qmp commands "vcpu-dirty-limit", "query-vcpu-dirty-limit"
to enable, disable, query dirty page limit for virtual CPU.
From: Hyman Huang(黄勇)
v9:
- rebase on master
- fix the meson directory change, keep it untouched.
v8:
- rebase on master
- polish the error message and remove the "unlikely" compilation syntax
according to the advice given by Markus.
- keep the dirty tracking enabled during "dirtylimit-calc"
The 1.15.0 version of SeaBIOS has now been released. For more
information on the release, please see:
http://seabios.org/Releases
New in this release:
* Improved support for USB devices with multiple interfaces.
* Support for USB XHCI devices using direct MMIO access (instead of PCI).
* NVMe
On 12/2/21 6:06 PM, Halil Pasic wrote:
On Thu, 2 Dec 2021 12:11:38 -0500
Matthew Rosato wrote:
What happens if we migrate a VM from old to new QEMU? Won't the guest be
able to observe the change?
Yes, technically -- But # itself is not really all that important, it
is provided from
From: Hyman Huang(黄勇)
Introduce the third method GLOBAL_DIRTY_LIMIT of dirty
tracking for calculate dirtyrate periodly for dirty restraint.
Implement thread for calculate dirtyrate periodly, which will
be used for dirty restraint.
Add dirtylimit.h to introduce the util function for dirty
limit
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Add target/riscv/kvm.c to place kvm_arch_* function needed by
> kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
Looks good to me.
On Thu, Dec 2, 2021 at 4:47 AM Vasilev Oleg wrote:
> The mentioned paper[4] also describes other possible improvements.
> Some of those are already implemented (such as victim TLB and dynamic
> size for TLB), but others are not (e.g. TLB lookup uninlining and
> set-associative TLB layer). Do you
On Thu, Dec 02, 2021 at 02:44:42PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 17:19, Stefan Hajnoczi wrote:
> >
> > Compiler optimizations can cache TLS values across coroutine yield
> > points, resulting in stale values from the previous thread when a
> > coroutine is re-entered by a
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. In addition, add kvm_riscv.h to place riscv specific
> interface.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
On Thu, Dec 02, 2021 at 11:49:25AM +0800, Jason Wang wrote:
> On Thu, Dec 2, 2021 at 4:55 AM David Woodhouse wrote:
> >
> > From: David Woodhouse
> >
> > By setting none of the SAGAW bits we can indicate to a guest that DMA
> > translation isn't supported. Tested by booting Windows 10, as well
Hello Daniel,
On Tue, Nov 23, 2021 at 6:45 AM Daniel P. Berrangé wrote:
>
> On Mon, Nov 22, 2021 at 08:18:09PM -0300, Leonardo Bras Soares Passos wrote:
> > Hello Daniel,
> > Thanks for the feedback!
> >
> > On Fri, Nov 12, 2021 at 7:13 AM Daniel P. Berrangé
> > wrote:
> > >
> > > On Fri, Nov
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
> ---
> target/riscv/kvm.c | 141 -
> 1
The default block size is same as to the THP size, which is either
retrieved from "/sys/kernel/mm/transparent_hugepage/hpage_pmd_size"
or hardcoded to 2MB. There are flaws in both mechanisms and this
intends to fix them up.
* When "/sys/kernel/mm/transparent_hugepage/hpage_pmd_size" is
used
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Add asm-riscv/kvm.h for RISC-V KVM, and update linux/kvm.h
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> linux-headers/asm-riscv/kvm.h | 128
Hello Daniel,
On Tue, Nov 23, 2021 at 6:56 AM Daniel P. Berrangé wrote:
>
> On Tue, Nov 23, 2021 at 01:46:44AM -0300, Leonardo Bras Soares Passos wrote:
> > Hello Daniel,
> >
> > On Fri, Nov 12, 2021 at 7:54 AM Daniel P. Berrangé
> > wrote:
> > [...]
> > > > @@ -561,12 +577,15 @@ static
On 12/2/21 9:21 PM, Emilio Cota wrote:
On Thu, Dec 2, 2021 at 4:47 AM Vasilev Oleg wrote:
The mentioned paper[4] also describes other possible improvements.
Some of those are already implemented (such as victim TLB and dynamic
size for TLB), but others are not (e.g. TLB lookup uninlining and
On 12/1/21 8:03 PM, David Hildenbrand wrote:
* It has been passing the tests with various combinations like 64KB
and 4KB page sizes on host and guest, different memory device
backends like normal, transparent huge page and HugeTLB, plus
migration.
Perfect. A note
This series supports virtio-mem-pci device, by simply following the
implementation on x86. The exception is the block size is 512MB on
ARM64 instead of 128MB on x86, compatible with the memory section
size in linux guest.
The work was done by David Hildenbrand and then Jonathan Cameron. I'm
This supports virtio-mem-pci device on "virt" platform, by simply
following the implementation on x86.
* This implements the hotplug handlers to support virtio-mem-pci
device hot-add, while the hot-remove isn't supported as we have
on x86.
* The block size is 512MB on ARM64
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
> ---
> target/riscv/kvm.c | 150 -
>
On Thu, Dec 02, 2021 at 11:53:25AM +0800, Jason Wang wrote:
> On Thu, Dec 2, 2021 at 4:58 AM David Woodhouse wrote:
> >
> > From: David Woodhouse
> >
> > We should probably check if we were meant to be exposing IR, before
> > letting the guest turn the IRE bit on.
>
> This looks correct, but
On Thu, Dec 02, 2021 at 01:14:47PM +0800, Rao, Lei wrote:
> Sorry, resending with correct indentation and quoting.
>
> On 12/1/2021 10:27 PM, Vladimir Sementsov-Ogievskiy wrote:
> > 01.12.2021 12:48, Rao, Lei wrote:
> > >
> > >
> > > -Original Message-
> > > From: Daniel P. Berrangé
>
On 01/12/2021 19.45, Collin Walling wrote:
Polite ping. I may have missed if this patch was picked already. Thanks!
I've already queued it to my s390x-next branch:
https://gitlab.com/thuth/qemu/-/commits/s390x-next/
It just came in very late for 6.2, and it didn't seem too critical to me,
On 7/23/2021 1:53 AM, Connor Kuehl wrote:
On 7/7/21 7:54 PM, isaku.yamah...@gmail.com wrote:
From: Xiaoyao Li
Reuse -cpu,tsc-frequency= to get user wanted tsc frequency and pass it
to KVM_TDX_INIT_VM.
Besides, sanity check the tsc frequency to be in the legal range and
legal granularity
02.12.2021 11:53, Daniel P. Berrangé wrote:
On Thu, Dec 02, 2021 at 01:14:47PM +0800, Rao, Lei wrote:
Sorry, resending with correct indentation and quoting.
On 12/1/2021 10:27 PM, Vladimir Sementsov-Ogievskiy wrote:
01.12.2021 12:48, Rao, Lei wrote:
-Original Message-
From: Daniel
On Thu, Dec 02, 2021 at 02:50:34AM +0800, 罗勇刚(Yonggang Luo) wrote:
> On Wed, Nov 24, 2021 at 7:06 PM Gerd Hoffmann wrote:
> >
> > qemu -display egl-headless
>
> Thanks a lot, I tried this, and it's forced me to provide rendernode
> option like this:
> ```
> -display
I fat-fingered Edgar's e-mail address. Sorry for the inconvenience.
在2021年11月30日十一月 下午9:52，Philippe Mathieu-Daudé写道：
> On 11/30/21 22:17, Jiaxun Yang wrote:
>> bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
>> while sd is illegal on 32 bit CPUs.
>>
>> Replace sd with sw on 32bit CPUs.
>>
>> Fixes: 3ebbf86 ("hw/mips: Add a bootloader helper")
>>
* Juan Quintela (quint...@redhat.com) wrote:
> This patch adds counters and similar. Logic will be added on the
> following patch.
>
> Signed-off-by: Juan Quintela
> ---
> migration/multifd.h| 13 -
> migration/multifd.c| 22 +++---
> migration/trace-events
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> This patch adds counters and similar. Logic will be added on the
>> following patch.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> migration/multifd.h| 13 -
>> migration/multifd.c| 22
On Mon, 1 Feb 2021 16:59:31 -0800
Ben Widawsky wrote:
> This cleanup will make it easier to add support for CXL to the mix.
>
> Signed-off-by: Ben Widawsky
Hi Ben / all (particularly PCI experts!)
So... I was looking at the large impact this has on needing to update
ACPI tables for the tests
On Mon, Nov 29, 2021 at 02:05:08PM +, Daniel P. Berrangé wrote:
> Currently QEMU defaults to a resolution of 1024x768 when exposing EDID
> info to the guest OS. The EDID default info is important as this will
> influence what resolution many guest OS will configure the screen with
> on boot.
On Mon, 29 Nov 2021 at 14:13, Daniel P. Berrangé wrote:
> This patch thus suggests a modest change to 1280x800 (WXGA).
Does this change need to be versioned so as to not change
behaviour for older machine types ?
thanks
-- PMM
On Thu, Dec 02, 2021 at 11:00:53AM +, Peter Maydell wrote:
> On Mon, 29 Nov 2021 at 14:13, Daniel P. Berrangé wrote:
> > This patch thus suggests a modest change to 1280x800 (WXGA).
>
> Does this change need to be versioned so as to not change
> behaviour for older machine types ?
I don't
Philippe Mathieu-Daudé writes:
> On 11/29/21 13:58, Alex Bennée wrote:
>>
>> Juro Bystricky writes:
>>
>>> Fix compiler warnings. The warnings can result in a broken build.
>>> This patch fixes warnings such as:
>>
>> Queued to for-6.2/more-misc-fixes, thanks.
>
> I wondered if this single
Hi,
> The virtio-gpu change I'm not so sure about - it feeds into the
> EDID code, but not sure if it has other consequences that matter
> from a guest ABI pov.
virtio-gpu has two ways to query the display resolution (one predating
edid support), the change will affect both. The effect will
On 11/29/21 13:58, Alex Bennée wrote:
>
> Juro Bystricky writes:
>
>> Fix compiler warnings. The warnings can result in a broken build.
>> This patch fixes warnings such as:
>
> Queued to for-6.2/more-misc-fixes, thanks.
I wondered if this single patch would justify delaying the 6.2
release
Leonardo Bras Soares Passos wrote:
> On Tue, Nov 16, 2021 at 1:08 PM Juan Quintela wrote:
>>
>> I would prefer to check for QIO_CHANNEL_FEATUR_WRITE_ZEROCPY there, but
>> I can't see a way of doing that without a qio.
>
> Yeah, I think I should leave the feature testing in here, and move the
>
On Wed, Dec 01, 2021 at 12:55:08PM +0100, Stefano Garzarella wrote:
> On Tue, Nov 30, 2021 at 11:20:57AM +, Stefan Hajnoczi wrote:
> > @@ -657,10 +704,7 @@ bool aio_poll(AioContext *ctx, bool blocking)
> > }
> >
> > progress |= aio_bh_poll(ctx);
> > -
> > -if (ret > 0) {
> > -
On Wed, Dec 01, 2021 at 07:24:33PM +0100, Florian Weimer wrote:
> * Stefan Hajnoczi:
>
> > +#elif defined(__x86_64__)
> > +#define QEMU_CO_TLS_ADDR(ret, var) \
> > +asm volatile("rdfsbase %0\n\t" \
> > + "lea
On Thu, Dec 02, 2021 at 01:09:23PM +, Stefan Hajnoczi wrote:
On Wed, Dec 01, 2021 at 12:55:08PM +0100, Stefano Garzarella wrote:
On Tue, Nov 30, 2021 at 11:20:57AM +, Stefan Hajnoczi wrote:
> @@ -657,10 +704,7 @@ bool aio_poll(AioContext *ctx, bool blocking)
> }
>
> progress |=
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 2 +-
hw/ppc/pnv.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/pnv.h
It is never used.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index bd768dcc28ad..988b305398b2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1764,7 +1764,6 @@ static Property pnv_chip_properties[] = {
POWER9 processor comes with 3 PHB4 PECs (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9
This requires a link to the chip to add the regions under the XSCOM
address space. This change will help us providing support for user
created PHB3 devices.
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb3.h | 3 +++
hw/pci-host/pnv_phb3.c | 1 +
Hello,
On the POWER8 processor, powernv8 machine, PHB3 devices can simply be
created with :
-device pnv-phb3,chip-id=0,index=1
with a maximum of 3 PHB3s per chip, each PHB3 adding a new PCIe bus.
On the POWER9 processor, powernv9 machine, the logic is different. The
the chip comes with 3
Next changes will make use of it.
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/include/hw/pci-host/pnv_phb4.h
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB3 device is parented to its chip by reparenting
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in the chip. In case of user
created devices, a lookup on 'chip-id' is required to assign the
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