Excerpts from Cédric Le Goater's message of December 22, 2021 4:48 pm:
> Adding Nicholas.
These look fine by me. The whole series looks like a really nice
cleanup actually.
Thanks,
Nick
>
> On 12/20/21 19:18, Fabiano Rosas wrote:
>> None of the interrupt setup code touches 'vector', so we can
On 12/25/21 02:23, Richard Henderson wrote:
> On 12/24/21 3:45 PM, Philippe Mathieu-Daudé wrote:
>> Similarly to commit e63ed64c6d1 ("tests/qtest/virtio-net-failover:
>> Use g_file_open_tmp() to create temporary file"), avoid calling
>> g_test_rand_int() before g_test_init(): use
Trying to boot VM with TPM 2.0 CRB in passthrough mode without this change
I got "Requested buffer size of 3968 is smaller than host TPM's fixed
buffer size of 4096".
Looks like it can not be less than backend buffer size nor less than
CRB_CTRL_CMD_SIZE.
Signed-off-by: Yuri Konotopov
---
Hi staffs at qemu, I'm a newcomer to qemu project. I'm currently trying to
understand this great masterpiece, and in order to achieve this task.
Source code level debugging is mandatory and necessary for me. Which IDE on
Linux would you recommend to import the latest QEMU project? Could you
From: "BALATON Zoltan" bala...@eik.bme.hu
To: "Fabiano Rosas" faro...@linux.ibm.com
Cc: qemu-devel@nongnu.org, qemu-...@nongnu.org, c...@kaod.org,
danielhb...@gmail.com, ma...@locati.it
Date: Mon, 13 Dec 2021 20:51:15 +0100 (CET)
Subject: Re: [PATCH] target/ppc: Fix e6500 boot
On Mon, 13 Dec
Commit 812b31d3f91 refactor missed to update this path.
Fixes: 812b31d3f91 ("configs: rename default-configs to configs and reorganise")
Signed-off-by: Philippe Mathieu-Daudé
---
tests/tcg/Makefile.target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 12/24/21 04:55, Richard Henderson wrote:
> We need to read the floating-point flags before printf may do
> other floating-point operations which may affect the flags.
>
> Hexagon reference files regenerated by Taylor Simpson.
>
> Signed-off-by: Taylor Simpson
> Signed-off-by: Richard
On Sat, 25 Dec 2021, ma...@locati.it wrote:
I have tried to launch a freshly compiled qemu from git master on a NXP
T2080RDB devkit that has a e6500 CPU in combination with a freshly
compiled kernel 5.16-rc6
I have Debian SID ppc64 up and running using such a kernel, and when I
launch qemu to
Generated on Loongson-3A4000 (Loongson-3 V0.4 FPU V0.1).
Signed-off-by: Philippe Mathieu-Daudé
---
tests/tcg/mips64el/float_convs.ref | 748
tests/tcg/mips64el/float_madds.ref | 768 +
2 files changed, 1516 insertions(+)
create mode
On 12/24/21 7:13 PM, liweiwei wrote:
In RV64 case, this should be nan-boxing value( upper bits are all ones). However, zfinx
will not check nan-boxing of source, the upper 32 bits have no effect on the final result.
So I think both zero-extended or sign-extended are OK.
There is no nanboxing
+Marc-André
On 12/25/21 13:38, Yuri Konotopov wrote:
> Trying to boot VM with TPM 2.0 CRB in passthrough mode without this change
> I got "Requested buffer size of 3968 is smaller than host TPM's fixed
> buffer size of 4096".
> Looks like it can not be less than backend buffer size nor less than
Unfortunately this fails:
$ make run-tcg-tests-mips64el-linux-user
...
Files float_convs.out and tests/tcg/mips64el/float_convs.ref differ
--- float_convs.out 2021-12-26 01:03:48.585973637 +0100
+++ tests/tcg/mips64el/float_convs.ref 2021-12-26 00:29:35.804465340 +0100
@@ -1,40
The test doesn't pass, so I presume there is a bug in our model...
Based-on: <20211224035541.2159966-1-richard.hender...@linaro.org>
https://lore.kernel.org/qemu-devel/20211224035541.2159966-1-richard.hender...@linaro.org/
Philippe Mathieu-Daudé (2):
tests/tcg/mips64el: Add float reference
Sorry. In the old spec(version 0.41), nanboxing is not totally disabled,
but "NaN-boxing is limited to |XLEN| bits, not |FLEN| bits". Taking
misa.mxl into acount, if misa.mxl is RV32, and maximum is RV64, this
should be sign-extended. Is there any other new update for nanboxing to
the spec?
On 12/25/21 5:42 PM, liweiwei wrote:
Sorry. In the old spec(version 0.41), nanboxing is not totally disabled, but "NaN-boxing
is limited to |XLEN| bits, not |FLEN| bits". Taking misa.mxl into acount, if misa.mxl is
RV32, and maximum is RV64, this should be sign-extended. Is there any other new
On Thu, Dec 23, 2021 at 10:49:46AM +0100, Philippe Mathieu-Daudé wrote:
> What are your thoughts on Daniel idea to where (IIUC) cores can are
> external processes wired via vhost-user. One problem is not all
> operating systems supported provide this possibility.
There is no fundamental
OK. It have been changed to sign-extended in the "processing of Narrower
Values" section of the new spec(version 1.0.0.rc) . I'll fix this and
update other nan-boxing processing in current implementation.
在 2021/12/26 上午9:42, liweiwei 写道:
Sorry. In the old spec(version 0.41), nanboxing is
在2021年12月26日十二月 上午12:19，Philippe Mathieu-Daudé写道：
> Unfortunately this fails:
>
> $ make run-tcg-tests-mips64el-linux-user
> ...
> Files float_convs.out and tests/tcg/mips64el/float_convs.ref differ
> --- float_convs.out 2021-12-26 01:03:48.585973637 +0100
> +++
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