[PATCH v2 2/3] spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall

The behaviour of the Address Translation Mode on Interrupt resource is not consistently supported by all CPU versions or all KVM versions: KVM-HV does not support mode 2, and does not support mode 3 on POWER7 or early POWER9 processesors. KVM PR only supports mode 0. TCG supports all modes (0, 2,

[PATCH] tcg: Add 'signed' bit to typecodes

Commit 7319d83a (tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode) converted the tcg type system to a 3-bit field from two separate 1-bit fields. This subtly lost the 'signed' information from the types as it uses the dh_alias macro to reduce the types down to basic machine types. However,

Re: [PATCH v3 1/3] s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x

On 15.02.22 21:26, David Miller wrote: > resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 > implements: > AND WITH COMPLEMENT (NCRK, NCGRK) > NAND (NNRK, NNGRK) > NOT EXCLUSIVE OR (NXRK, NXGRK) > NOR (NORK, NOGRK) > OR WITH COMPLEMENT(OCRK,

Re: [PULL 00/40] riscv-to-apply queue

On Wed, Feb 16, 2022 at 11:59 AM Alistair Francis wrote: > > On Tue, Feb 15, 2022 at 9:39 PM Peter Maydell > wrote: > > > > On Sat, 12 Feb 2022 at 00:07, Alistair Francis > > wrote: > > > > > > From: Alistair Francis > > > > > > The following changes since commit > > >

Re: [PATCH v1 1/4] hyperv: SControl is optional to enable SynIc

On 04/02/2022 11:07, Jon Doron wrote: > SynIc can be enabled regardless of the SControl mechanisim which can > register a GSI for a given SintRoute. > > This behaviour can achived by setting enabling SIMP and then the guest > will poll on the message slot. > > Once there is another message

[PATCH 7/8] target/i386: Enable Arch LBR migration states in vmstate

The Arch LBR record MSRs and control MSRs will be migrated to destination guest if the vcpus were running with Arch LBR active. Signed-off-by: Yang Weijiang --- target/i386/machine.c | 38 ++ 1 file changed, 38 insertions(+) diff --git

Re: [PATCH] arm: Remove swift-bmc machine

On 2/16/22 09:03, Joel Stanley wrote: It was scheduled for removal in 7.0. Signed-off-by: Joel Stanley Could you please send a v2 with an update of docs/about/deprecated.rst ? With that, Reviewed-by: Cédric Le Goater Thanks, C. --- docs/system/arm/aspeed.rst | 1 - hw/arm/aspeed.c

[PATCH 0/6] aspeed extensions

Hi, Here is a set of extensions for the Aspeed machines, the most important ones being the removal of a deprecated machine and a simple model for the Secure Boot Controller, both from Joel. Thanks, C. Cédric Le Goater (2): aspeed/smc: Add an address mask on segment registers aspeed/sdmc:

Re: [PATCH v3 3/3] s390x/tcg/tests: Tests for Miscellaneous-Instruction-Extensions Facility 3

Am 16.02.22 um 10:17 schrieb David Hildenbrand: On 15.02.22 21:27, David Miller wrote: tests/tcg/s390x/mie3-compl.c: [N]*K instructions tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction tests/tcg/s390x/mie3-sel.c: SELECT instruction Signed-off-by: David Miller ---

Re: [PATCH RFCv2 2/4] i386/pc: relocate 4g start to 1T where applicable

On Tue, Feb 15, 2022 at 07:37:40PM +, Joao Martins wrote: > On 2/15/22 09:53, Gerd Hoffmann wrote: > > What is missing: > > > > * Some way for the firmware to get a phys-bits value it can actually > >use. One possible way would be to have a paravirtual bit somewhere > >telling

Re: [PATCH 1/2] spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall

If we do, we should probably change the default value for this cap based on cpu model in default_caps_with_cpu(). We allegedly still support POWER7 KVM in Linux. I've never tested it and I don't know how much it's used at all. Probably should keep it working here if possible. I'll look into

Re: [PATCH 0/9] ppc: nested KVM HV for spapr virtual hypervisor

Excerpts from Fabiano Rosas's message of February 16, 2022 5:20 am: > Daniel Henrique Barboza writes: > >> On 2/15/22 15:33, Cédric Le Goater wrote: >>> On 2/15/22 04:16, Nicholas Piggin wrote: Here is the rollup of patches in much better shape since the RFC. I include the 2 first ones

Re: [PATCH 1/4] block: bdrv_merge_dirty_bitmap: add return value

I forget that I already sent it in other series: [PATCH v3 02/19] block/dirty-bitmap: bdrv_merge_dirty_bitmap(): add return value "[PATCH v3 02/19] block/dirty-bitmap: bdrv_merge_dirty_bitmap(): add return value" is a bit better as it adds a comment. And has Hanna's r-b 15.02.2022 20:53,

Re: [PATCH] arm: Remove swift-bmc machine

On Wed, Feb 16, 2022 at 08:08:46AM +, Joel Stanley wrote: > On Wed, 16 Feb 2022 at 08:07, Cédric Le Goater wrote: > > > > On 2/16/22 09:03, Joel Stanley wrote: > > > It was scheduled for removal in 7.0. > > > > > > Signed-off-by: Joel Stanley > > > > Could you please send a v2 with an update

Re: [PATCH v3 3/3] s390x/tcg/tests: Tests for Miscellaneous-Instruction-Extensions Facility 3

On 16.02.22 10:28, Christian Borntraeger wrote: > > > Am 16.02.22 um 10:17 schrieb David Hildenbrand: >> On 15.02.22 21:27, David Miller wrote: >>> tests/tcg/s390x/mie3-compl.c: [N]*K instructions >>> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction >>> tests/tcg/s390x/mie3-sel.c: SELECT

Re: [PATCH v6 00/11] 9p: Add support for darwin

On Montag, 14. Februar 2022 21:33:37 CET Will Cohen wrote: > Hello all, > > I'm seeing on the updated release schedule that we're now looking at March > 8 for soft feature freeze ( > https://wiki.qemu.org/Planning/7.0#Release_Schedule). Is there anything > additional that should be prepared for

[PATCH v12 4/5] target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions

PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB exceptions that had to be postponed because the thread wasn't in problem state at the time the event-based branch was supposed to occur. ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB exception and External

[PATCH v12 3/5] target/ppc: finalize pre-EBB PMU logic

There are still PMU exclusive bits to handle in fire_PMC_interrupt() before implementing the EBB support. Let's finalize it now to avoid dealing with PMU and EBB logic at the same time in the next patches. fire_PMC_interrupt() will fire an Performance Monitor alert depending on MMCR0_PMAE. If we

[PATCH v12 2/5] target/ppc: make power8-pmu.c CONFIG_TCG only

This is an exclusive TCG helper. Gating it with CONFIG_TCG and changing meson.build accordingly will prevent problems --disable-tcg and --disable-linux-user later on. Suggested-by: Fabiano Rosas Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu_init.c | 5 ++--- target/ppc/machine.c

[PATCH v12 5/5] target/ppc: trigger PERFM EBBs from power8-pmu.c

This patch adds the EBB exception support that are triggered by Performance Monitor alerts. This happens when a Performance Monitor alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set. fire_PMC_interrupt() will execute a new ebb_perfm_excp() helper that will check for MMCR0_EBE, BESCR_PME

Re: [PULL v2 07/35] target/riscv: access cfg structure through DisasContext

Alistair, This PULL seems not to include the fixup (which you had intended to squash into it) for the regression introduced (i.e. the condition being inverted): https://patchwork.kernel.org/project/qemu-devel/patch/20220203153946.2676353-1-philipp.toms...@vrull.eu/ Without that change this

[PATCH v2 0/9] ppc: nested KVM HV for spapr virtual hypervisor

This should account for AFAIKS all comments, except maybe some about naming. Changes since v1: - Per-CPU spapr nested state moved to SpaprCpuState from PowerPCCPU. - address_space_map ops are used, small rearrangement to make any given access region store-only or load-only. - Some style,

[PATCH v2 3/4] hyperv: Add support to process syndbg commands

SynDbg commands can come from two different flows: 1. Hypercalls, in this mode the data being sent is fully encapsulated network packets. 2. SynDbg specific MSRs, in this mode only the data that needs to be transfered is passed. Signed-off-by: Jon Doron --- docs/hyperv.txt |

[PATCH v2 8/9] target/ppc: Introduce a vhyp framework for nested HV support

Introduce virtual hypervisor methods that can support a "Nested KVM HV" implementation using the bare metal 2-level radix MMU, and using HV exceptions to return from H_ENTER_NESTED (rather than cause interrupts). HV exceptions can now be raised in the TCG spapr machine when running a nested KVM

Re: [PATCH v1 3/4] hyperv: Add support to process syndbg commands

On 16/02/2022, Emanuele Giuseppe Esposito wrote: On 04/02/2022 11:07, Jon Doron wrote: SynDbg commands can come from two different flows: 1. Hypercalls, in this mode the data being sent is fully encapsulated network packets. 2. SynDbg specific MSRs, in this mode only the data that needs to

[PATCH v2 7/9] target/ppc: Add powerpc_reset_excp_state helper

This moves the logic to reset the QEMU exception state into its own function. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 41 1 file changed, 21 insertions(+), 20 deletions(-) diff --git

Re: [PULL 0/5] 9p queue 2022-02-10

On Wed, 16 Feb 2022 11:30:12 +0100 Christian Schoenebeck wrote: > On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote: > > On Mon, 14 Feb 2022 17:43:51 +0300 > > > > Vitaly Chikunov wrote: > > > Why g_new0 and not just g_malloc0? This is smallest code change, which > > > seems

[PATCH v2 23/27] target/ppc: Rename spr_tcg.h to spr_common.h

Initial intent for the spr_tcg header was to expose the spr_read|write callbacks that are only used by TCG code. However, although these routines are TCG-specific, the KVM code needs access to env->sprs which creation is currently coupled to the callback registration. We are probably not going to

[PATCH v2 14/27] target/ppc: cpu_init: Deduplicate 7xx SPR registration

Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 68 +++ 1 file changed, 11 insertions(+), 57 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 131c2da4c2..ea4ed19bde 100644 ---

[PATCH v2 17/27] target/ppc: cpu_init: Move 604e SPR registration into a function

This is done to improve init_proc readability and to make subsequent patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 43 --- 1 file changed, 24 insertions(+), 19 deletions(-)

[PATCH v2 06/27] target/ppc: cpu_init: Move 405 SPRs into register_405_sprs

Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 1eef006a04..330b765ba9 100644 --- a/target/ppc/cpu_init.c +++

Re: [PATCH v2 4/8] configure: Disable out-of-line atomic operations on Aarch64

On 2022/02/17 0:08, Philippe Mathieu-Daudé wrote: On 16/2/22 11:19, Richard Henderson wrote: On 2/16/22 04:01, Philippe Mathieu-Daudé via wrote: GCC 10.1 introduced the -moutline-atomics option on Aarch64. This options is enabled by default, and triggers a link failure:    Undefined symbols

Re: [PATCH 1/4] python/utils: add enboxify() text decoration utility

On 16.02.22 17:16, John Snow wrote: On Tue, Feb 15, 2022, 6:57 PM Philippe Mathieu-Daudé wrote: On 16/2/22 00:53, John Snow wrote: > On Tue, Feb 15, 2022 at 5:55 PM Eric Blake wrote: >> >> On Tue, Feb 15, 2022 at 05:08:50PM -0500, John Snow wrote: >>

Re: [PATCH 2/6] ast2600: Add Secure Boot Controller model

On 16/2/22 10:21, Cédric Le Goater wrote: From: Joel Stanley Just a stub that indicates the system has booted in secure boot mode. Used for testing the driver: https://lore.kernel.org/all/20211019080608.283324-1-j...@jms.id.au/ Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater

Re: [PATCH 3/6] aspeed: rainier: Add i2c LED devices

On 16/2/22 10:21, Cédric Le Goater wrote: From: Joel Stanley This helps quieten booting the current Rainier kernel. Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater --- hw/arm/aspeed.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/aspeed.c

Re: [PULL v2 00/35] riscv-to-apply queue

-15 > 19:30:33 +) > > are available in the Git repository at: > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220216 > > for you to fetch changes up to 7035b8420fa52e8c94cf4317c0f88c1b73ced28d: > > docs/system: riscv: Upda

Re: [PULL 0/5] 9p queue 2022-02-10

Christian, On Wed, Feb 16, 2022 at 11:30:12AM +0100, Christian Schoenebeck wrote: > On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote: > > On Mon, 14 Feb 2022 17:43:51 +0300 > > > > Vitaly Chikunov wrote: > > > Why g_new0 and not just g_malloc0? This is smallest code change, which > >

Re: [PATCH 1/4] python/utils: add enboxify() text decoration utility

On Tue, Feb 15, 2022, 6:57 PM Philippe Mathieu-Daudé wrote: > On 16/2/22 00:53, John Snow wrote: > > On Tue, Feb 15, 2022 at 5:55 PM Eric Blake wrote: > >> > >> On Tue, Feb 15, 2022 at 05:08:50PM -0500, John Snow wrote: > >> print(enboxify(msg, width=72, name="commit message")) > >>> ┏━

[PATCH v2 01/27] target/ppc: cpu_init: Remove not implemented comments

The /* XXX : not implemented */ comments all over cpu_init are confusing and ambiguous. Do they mean not implemented by QEMU, not implemented in a specific access mode? Not implemented by the CPU? Do they apply to just the register right after or to a whole block? Do they mean we have an action

[PATCH v2 07/27] target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs

Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 41 ++--- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 330b765ba9..29f25e093f 100644 ---

[PATCH v2 04/27] target/ppc: cpu_init: Move Timebase registration into the common function

Now that the 601 was removed, all of our CPUs have a timebase, so that can be moved into the common function. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 98 --- 1 file changed, 18 insertions(+), 80 deletions(-)

[PATCH v2 03/27] target/ppc: cpu_init: Group registration of generic SPRs

The top level init_proc calls register_generic_sprs but also registers some other SPRs outside of that function. Let's group everything into a single place. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 58 --- 1 file

Re: [PATCH 0/6] ui/dbus: Share one listener for a console

On 2022/02/17 1:51, Marc-André Lureau wrote: Hi Akihiko, (I suppose you meant to reply-all, feel free to add back qemu-devel) My bad, restored Ccs. On Tue, Feb 15, 2022 at 5:56 PM Akihiko Odaki > wrote: On Tue, Feb 15, 2022 at 10:32 PM Marc-André

Re: [PATCH] MAINTAINERS: Adding myself as a reviewer of some components

On Mon, 31 Jan 2022 at 12:20, Ani Sinha wrote: > > Added myself as a reviewer of vmgenid, unimplemented device and empty slot. > > Signed-off-by: Ani Sinha > --- > MAINTAINERS | 3 +++ > 1 file changed, 3 insertions(+) > Applied to target-arm.next, thanks. -- PMM

Re: [PATCH v2 0/5] Misc OHCI clean ups

On Tue, 8 Feb 2022, BALATON Zoltan wrote: On Tue, 25 Jan 2022, BALATON Zoltan wrote: v2 - Fixed checkpatch errors Hello, Ping? Ping^2 https://patchew.org/QEMU/cover.1643117600.git.bala...@eik.bme.hu/ Regards, BALATON Zoltan I have these patches from last October when we've looked at

Re: [PATCH v2] nbd/server: Allow MULTI_CONN for shared writable exports

On Wed, Feb 16, 2022 at 12:13 PM Richard W.M. Jones wrote: > On Tue, Feb 15, 2022 at 05:24:14PM -0600, Eric Blake wrote: > > Oh. The QMP command (which is immediately visible through > > nbd-server-add/block-storage-add to qemu and qemu-storage-daemon) > > gains "multi-conn":"on", but you may be

[PATCH v4 0/2] riscv: Add support for Zicbo[m,z,p] instructions

The RISC-V base cache management operation ISA extension has been ratified [1]. This patchset adds support for the defined instructions. As the exception behavior of these instructions depend on the PMP configuration, the first patch introduces a new API to probe the access of an address range

[PATCH v2 15/27] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function

This is just to have 755-specific registers contained into a function, intead of leaving them open-coded in init_proc_755. It makes init_proc easier to read and keeps later patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson ---

[PATCH v2 22/27] target/ppc: cpu_init: Remove register_usprg3_sprs

This function registers just one SPR and has only two callers, so open code it. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu_init.c

[PATCH v2 13/27] target/ppc: cpu_init: Deduplicate 745/755 SPR registration

The 745 and 755 can share the HID registration, so move it all into register_755_sprs, which applies for both CPUs. Also rename that function to register_745_sprs, since the 745 is the earliest of the two. This will help with separating 755-specific registers in a subsequent patch.

[PATCH v2 19/27] target/ppc: cpu_init: Reuse init_proc_604 for the 604e

Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 12 +--- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 975257c19b..638e16c583 100644 --- a/target/ppc/cpu_init.c +++

[PATCH v2 21/27] target/ppc: cpu_init: Rename register_ne_601_sprs

The important part of this function is that it applies to non-embedded CPUs, not that it also applies to the 601. We removed support for the 601 anyway, so rename this function. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 41

[PATCH v2 24/27] target/ppc: cpu_init: Expose some SPR registration helpers

The following patches will move CPU-specific code into separate files, so expose the most used SPR registration functions: register_sdr1_sprs | 22 callers register_low_BATs | 20 callers register_non_embedded_sprs | 19 callers register_high_BATs | 10 callers

Re: [PATCH 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header

David Gibson writes: > On Tue, Feb 15, 2022 at 06:41:47PM -0300, Fabiano Rosas wrote: >> These will need to be accessed from other files once we move the CPUs >> code to separate files. >> >> Signed-off-by: Fabiano Rosas >> --- >> target/ppc/cpu.h | 57

Re: [PATCH 22/27] target/ppc: cpu_init: Rename register_ne_601_sprs

David Gibson writes: > On Tue, Feb 15, 2022 at 06:41:43PM -0300, Fabiano Rosas wrote: >> The important part of this function is that it applies to non-embedded >> CPUs, not that it also applies to the 601. We removed support for the >> 601 anyway, so rename this function. >> >> Signed-off-by:

Re: [PATCH v2] nbd/server: Allow MULTI_CONN for shared writable exports

Eric Blake writes: > According to the NBD spec, a server advertising > NBD_FLAG_CAN_MULTI_CONN promises that multiple client connections will > not see any cache inconsistencies: when properly separated by a single > flush, actions performed by one client will be visible to another > client,

Re: [PULL 00/30] Misc mostly build system patches for 2022-02-15

On 2/16/22 10:56, Peter Maydell wrote: Hi; this fails to build on OpenBSD (on the tests/vm/ setup). Meson thinks it's found OpenGL: OpenGL support (epoxy) : YES 1.5.4 but either it's wrong or else it's not putting the right include directory onto the path, because the compiler fails

Re: [PATCH v3 3/3] s390x/tcg/tests: Tests for Miscellaneous-Instruction-Extensions Facility 3

David Hildenbrand writes: > On 15.02.22 21:27, David Miller wrote: >> tests/tcg/s390x/mie3-compl.c: [N]*K instructions >> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction >> tests/tcg/s390x/mie3-sel.c: SELECT instruction >> >> Signed-off-by: David Miller >> --- >>

Re: [PATCH v2 4/8] configure: Disable out-of-line atomic operations on Aarch64

On 16/2/22 11:19, Richard Henderson wrote: On 2/16/22 04:01, Philippe Mathieu-Daudé via wrote: GCC 10.1 introduced the -moutline-atomics option on Aarch64. This options is enabled by default, and triggers a link failure:    Undefined symbols for architecture arm64:

Re: Undelivered Mail Returned to Sender

On 16/2/22 14:54, Joseph Fitzgerald (KM1P) wrote: Thank you for this trouble report. We recommend that Philippe subscribe to the qemu mailing list via a "real" mailing address rather than his f4...@amsat.org mail alias/forwarding address. Sigh, OK :( There is some combination of the Free

[PATCH v4 1/2] accel/tcg: Add probe_access_range_flags interface

The existing probe_access* functions do not allow to specify the access size and a non-faulting behavior at the same time. This is resolved by adding a generalization of probe_access_flags() that takes an additional size parameter. The semantics is basically the same as probe_access_flags(), but

[PATCH v2 27/27] target/ppc: Move common SPR functions out of cpu_init

Let's leave cpu_init with just generic CPU initialization and QOM-related functions. The rest of the SPR registration functions will be moved in the following patches along with the code that uses them. These are only the commonly used ones. Signed-off-by: Fabiano Rosas Reviewed-by: David

[PATCH v2 25/27] target/ppc: cpu_init: Move SPR registration macros to a header

Put the SPR registration macros in a header that is accessible outside of cpu_init.c. The following patches will move CPU-specific code to separate files and will need to access it. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 65

[PATCH v2 20/27] target/ppc: cpu_init: Reuse init_proc_745 for the 755

The init_proc_755 function is identical to the 745 one except for the 755-specific registers. I think it is worth it to make them share code. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 18 +- 1 file changed, 1 insertion(+), 17

Re: [PATCH] tests/vm: Update haiku test vm to R1/Beta3

rantup.com/haiku-os/boxes/r1beta2-x86_64/versions/20200702/providers/libvirt.box; -csum = "41c38b316e0cbdbc66b5dbaf3612b866700a4f35807cb1eb266a5bf83e9e68d5" +link = "https://app.vagrantup.com/haiku-os/boxes/r1beta3-x86_64/versions/2

Re: [PATCH v2 4/8] configure: Disable out-of-line atomic operations on Aarch64

On 16/2/22 17:42, Akihiko Odaki wrote: On 2022/02/17 0:08, Philippe Mathieu-Daudé wrote: On 16/2/22 11:19, Richard Henderson wrote: On 2/16/22 04:01, Philippe Mathieu-Daudé via wrote: GCC 10.1 introduced the -moutline-atomics option on Aarch64. This options is enabled by default, and triggers

[PATCH v2] tests/qemu-iotests: Rework the checks and spots using GNU sed

Instead of failing the iotests if GNU sed is not available (or skipping them completely in the check-block.sh script), it would be better to simply skip the bash-based tests that rely on GNU sed, so that the other tests could still be run. Thus we now explicitely use "gsed" (either as direct

Re: [PULL 00/30] Misc mostly build system patches for 2022-02-15

On Wed, 16 Feb 2022 at 14:03, Paolo Bonzini wrote: > > On 2/16/22 10:56, Peter Maydell wrote: > > Hi; this fails to build on OpenBSD (on the tests/vm/ setup). > > > > Meson thinks it's found OpenGL: > > OpenGL support (epoxy) : YES 1.5.4 > > > > but either it's wrong or else it's not

Re: [PATCH 1/6] arm: Remove swift-bmc machine

On 16/2/22 10:21, Cédric Le Goater wrote: From: Joel Stanley It was scheduled for removal in 7.0. Signed-off-by: Joel Stanley Message-Id: <20220216080947.65955-1-j...@jms.id.au> Signed-off-by: Cédric Le Goater --- docs/about/deprecated.rst | 7 - docs/system/arm/aspeed.rst | 1 -

Re: [PATCH v4 00/15] hw/nvme: SR-IOV with Virtualization Enhancements

On Fri, Feb 11, 2022 at 08:26:10AM +0100, Klaus Jensen wrote: > On Jan 26 18:11, Lukasz Maniak wrote: > > Changes since v3: > > - Addressed comments to review on pcie: Add support for Single Root I/O > > Virtualization (SR/IOV) > > - Fixed issues reported by checkpatch.pl > > > > Knut Omang

Re: [PATCH 28/31] vdpa: Expose VHOST_F_LOG_ALL on SVQ

On Tue, Feb 8, 2022 at 9:25 AM Jason Wang wrote: > > > 在 2022/2/1 下午7:45, Eugenio Perez Martin 写道: > > On Sun, Jan 30, 2022 at 7:50 AM Jason Wang wrote: > >> > >> 在 2022/1/22 上午4:27, Eugenio Pérez 写道: > >>> SVQ is able to log the dirty bits by itself, so let's use it to not > >>> block

Re: QEMU's Haiku CI image

On 16/2/22 17:32, Thomas Huth wrote: On 16/02/2022 16.52, Alexander von Gluck IV wrote: February 16, 2022 6:31 AM, "Thomas Huth" wrote: while researching the different "sed" options on our supported build platform today, I started "make vm-build-haiku.x86_64" in my QEMU build directory for

Re: [PATCH v15 7/7] softmmu/dirtylimit: Implement dirty page rate limit

huang...@chinatelecom.cn writes: > From: Hyman Huang(黄勇) > > Implement dirtyrate calculation periodically basing on > dirty-ring and throttle virtual CPU until it reachs the quota > dirty page rate given by user. > > Introduce qmp commands "set-vcpu-dirty-limit", > "cancel-vcpu-dirty-limit",

Re: [PATCH v3] Check and report for incomplete 'global' option format

Rohit Kumar writes: > Qemu might crash when provided incomplete '-global' option. > For example: > qemu-system-x86_64 -global driver=isa-fdc > qemu-system-x86_64: ../../devel/qemu/qapi/string-input-visitor.c:394: > string_input_visitor_new: Assertion `str' failed. > Aborted

Re: [PATCH] tests/qemu-iotests: Rework the checks and spots using GNU sed

On Wed, Feb 16, 2022 at 12:39:06PM +0100, Thomas Huth wrote: > > > -$SED -re 's/[0-9]{4}-[0-9]{2}-[0-9]{2} > > > [0-9]{2}:[0-9]{2}:[0-9]{2}/-mm-dd hh:mm:ss/' > > > +gsed -re 's/[0-9]{4}-[0-9]{2}-[0-9]{2} > > > [0-9]{2}:[0-9]{2}:[0-9]{2}/-mm-dd hh:mm:ss/' > > > > GNU sed

Re: [PULL 0/5] 9p queue 2022-02-10

On Mittwoch, 16. Februar 2022 17:09:56 CET Vitaly Chikunov wrote: > Christian, > > On Wed, Feb 16, 2022 at 11:30:12AM +0100, Christian Schoenebeck wrote: > > On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote: > > > On Mon, 14 Feb 2022 17:43:51 +0300 > > > > > > Vitaly Chikunov wrote: >

[PATCH v2 11/27] target/ppc: cpu_init: Deduplicate 603 SPR registration

Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 28 +--- 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 711834a4c1..cae4ab69fe 100644 --- a/target/ppc/cpu_init.c +++

[PATCH v2 09/27] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx

We're considering these two to be from different CPU families, so duplicate some code to keep them separate. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 107 +++--- 1 file changed, 91 insertions(+), 16 deletions(-)

[PATCH v2 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header

These will need to be accessed from other files once we move the CPUs code to separate files. The check_pow_hid0 and check_pow_hid0_74xx are too specific to be moved to a header so I'll deal with them later when splitting this code between the multiple CPU families. Signed-off-by: Fabiano Rosas

[PATCH v2 12/27] target/ppc: cpu_init: Deduplicate 604 SPR registration

Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 17 +++-- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index cae4ab69fe..c54f10cb48 100644 --- a/target/ppc/cpu_init.c +++

[PATCH v2 18/27] target/ppc: cpu_init: Reuse init_proc_603 for the e300

init_proc_603 is defined after init_proc_e300, so I had to move some code around to make it work. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 104 +++--- 1 file changed, 46 insertions(+), 58 deletions(-) diff --git

Re: [PATCH v2 9/9] spapr: implement nested-hv capability for the virtual hypervisor

Excerpts from Nicholas Piggin's message of February 16, 2022 9:38 pm: > Excerpts from Cédric Le Goater's message of February 16, 2022 8:52 pm: >> On 2/16/22 11:25, Nicholas Piggin wrote: >>> This implements the Nested KVM HV hcall API for spapr under TCG. >>> >>> The L2 is switched in when the

Re: [PATCH v3 3/3] s390x/tcg/tests: Tests for Miscellaneous-Instruction-Extensions Facility 3

On 16.02.22 15:19, Alex Bennée wrote: > > David Hildenbrand writes: > >> On 15.02.22 21:27, David Miller wrote: >>> tests/tcg/s390x/mie3-compl.c: [N]*K instructions >>> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction >>> tests/tcg/s390x/mie3-sel.c: SELECT instruction >>> >>> Signed-off-by:

Re: [PATCH v2] tests/qemu-iotests: Rework the checks and spots using GNU sed

On 16/2/22 13:54, Thomas Huth wrote: Instead of failing the iotests if GNU sed is not available (or skipping them completely in the check-block.sh script), it would be better to simply skip the bash-based tests that rely on GNU sed, so that the other tests could still be run. Thus we now

Re: [PATCH 01/20] migration: Dump sub-cmd name in loadvm_process_command tp

* Peter Xu (pet...@redhat.com) wrote: > It'll be easier to read the name rather than index of sub-cmd when debugging. > > Signed-off-by: Peter Xu Reviewed-by: Dr. David Alan Gilbert > --- > migration/savevm.c | 3 ++- > migration/trace-events | 2 +- > 2 files changed, 3 insertions(+), 2

Re: QEMU's Haiku CI image

February 16, 2022 6:31 AM, "Thomas Huth" wrote: > > while researching the different "sed" options on our supported build platform > today, I started > "make vm-build-haiku.x86_64" in my QEMU build directory for the first time > since many months again. > And I had to discover that this is

[PATCH v2 00/27] target/ppc: SPR registration cleanups

The goal of this series is to do some untangling of SPR registration code in cpu_init.c and prepare for moving the CPU initialization into separate files for each CPU family. After this series we'll have only cpu-specific SPR code in cpu_init.c, i.e. code that can be split and moved as a unit

[PATCH v2 08/27] target/ppc: cpu_init: Decouple G2 SPR registration from 755

We're considering these two to be in different CPU families (6xx and 7xx), so keep their SPR registration separate. The code was copied into register_G2_sprs and the common function was renamed to apply only to the 755. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson ---

[PATCH v2 10/27] target/ppc: cpu_init: Deduplicate 440 SPR registration

Move some of the 440 registers that are being repeated in the 440* CPUs to register_440_sprs. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 100 +++--- 1 file changed, 26 insertions(+), 74 deletions(-) diff --git

[PATCH v2 16/27] target/ppc: cpu_init: Move e300 SPR registration into a function

This is done to improve init_proc readability and to make subsequent patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson --- target/ppc/cpu_init.c | 64 +++ 1 file changed, 35 insertions(+), 29 deletions(-)

Re: [PATCH v2] nbd/server: Allow MULTI_CONN for shared writable exports

On Wed, Feb 16, 2022 at 10:08 AM Vladimir Sementsov-Ogievskiy wrote: > > 16.02.2022 02:24, Eric Blake wrote: > > On Tue, Feb 15, 2022 at 09:23:36PM +0200, Nir Soffer wrote: > >> On Tue, Feb 15, 2022 at 7:22 PM Eric Blake wrote: > >> > >>> According to the NBD spec, a server advertising > >>>

Re: [PATCH RFCv2 2/4] i386/pc: relocate 4g start to 1T where applicable

Hi, > What I overlooked was the emphasis you had on desktops (qemu default bigger > than > host-advertised), where I am thinking mostly in servers. Yep, on servers you have the reverse problem that phys-bits=40 might be too small for very large guests. > > To make things even worse: The

QEMU's Haiku CI image

Hi, while researching the different "sed" options on our supported build platform today, I started "make vm-build-haiku.x86_64" in my QEMU build directory for the first time since many months again. And I had to discover that this is completely out of date. The image does not contain any

Re: [PULL 0/5] 9p queue 2022-02-10

On 16/2/22 11:30, Christian Schoenebeck wrote: On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote: On Mon, 14 Feb 2022 17:43:51 +0300 Vitaly Chikunov wrote: Why g_new0 and not just g_malloc0? This is smallest code change, which seems appropriate for a bug fix. I prefer g_new0() for

[PATCH] tests/vm: Update haiku test vm to R1/Beta3

702/providers/libvirt.box; -csum = "41c38b316e0cbdbc66b5dbaf3612b866700a4f35807cb1eb266a5bf83e9e68d5" +link = "https://app.vagrantup.com/haiku-os/boxes/r1beta3-x86_64/versions/20220216/providers/libvirt.box; +csum = "e67d4aacbcc687013d5cc91990ddd86cc5d70a5d28432ae2

[PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

The RISC-V base cache management operation ISA extension has been ratified. This patch adds support for the defined instructions. The cmo.prefetch instructions are nops for QEMU (no emulation of the memory hierarchy, no illegal instructions, no permission faults, no traps), therefore there's only

[PATCH 1/1] numa: check mem or memdev in numa configuration

If there is no mem or memdev in numa configuration, it always reports the error as the following: total memory for NUMA nodes (0x0) should equal RAM size (0x1) This error is confusing and the reason is that total memory of numa nodes is always 0 if there is no mem or memdev in numa

Re: [PATCH v3] target/riscv: Enable Zicbo[m,z,p] instructions

On Fri, Feb 11, 2022 at 3:41 AM Weiwei Li wrote: > > 在 2022/2/11 上午12:34, Christoph Muellner 写道: > > The RISC-V base cache management operation ISA extension has been > > ratified [1]. This patch adds support for the defined instructions. > > > > The cmo.prefetch instructions are nops for QEMU

Re: [PATCH] tests/tcg/s390x: Build tests with debian11

David Hildenbrand writes: > We need a newer compiler to build upcoming tests that test for z15 > features with -march=z15. So let's do it similar to arm64 and powerpc, > using an environment based on debian11 to build tests only. > > Cc: Thomas Huth > Cc: Cornelia Huck > Cc: Richard

Re: [PATCH 02/20] migration: Finer grained tracepoints for POSTCOPY_LISTEN

* Peter Xu (pet...@redhat.com) wrote: > The enablement of postcopy listening has a few steps, add a few tracepoints to > be there ready for some basic measurements for them. > > Signed-off-by: Peter Xu Reviewed-by: Dr. David Alan Gilbert > --- > migration/savevm.c | 9 - >

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