[PATCH v16 0/7] support dirty restraint on vCPU

From: Hyman Huang(黄勇) v16 - rebase on master - drop the unused typedef syntax in [PATCH v15 6/7] - add the Reviewed-by and Acked-by tags by the way v15 - rebase on master - drop the 'init_time_ms' parameter in function vcpu_calculate_dirtyrate - drop the 'setup' field in dirtylimit_state and

[PATCH v16 7/7] softmmu/dirtylimit: Implement dirty page rate limit

From: Hyman Huang(黄勇) Implement dirtyrate calculation periodically basing on dirty-ring and throttle virtual CPU until it reachs the quota dirty page rate given by user. Introduce qmp commands "set-vcpu-dirty-limit", "cancel-vcpu-dirty-limit", "query-vcpu-dirty-limit" to enable, disable, query

[PATCH v3 2/7] malta: Move PCI interrupt handling from gt64xxx_pci to piix4

Handling PCI interrupts in piix4 increases cohesion and reduces differences between piix4 and piix3. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 55 ++ hw/mips/gt64xxx_pci.c | 60 -- hw/mips/malta.c

Re: [PATCH v3 3/7] hw/isa/piix4: Resolve redundant i8259[] attribute

On 16/2/22 23:45, Bernhard Beschow wrote: This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to PIIX4State to make the code movement more obvious. However, i8259[] seems redundant to *isa, so remove it.

Re: [PATCH v2 23/27] target/ppc: Rename spr_tcg.h to spr_common.h

On Wed, Feb 16, 2022 at 01:24:22PM -0300, Fabiano Rosas wrote: > Initial intent for the spr_tcg header was to expose the spr_read|write > callbacks that are only used by TCG code. However, although these > routines are TCG-specific, the KVM code needs access to env->sprs > which creation is

Re: [PATCH v2 3/3] target/ppc/kvm: Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support

On Wed, Feb 16, 2022 at 04:39:03PM +1000, Nicholas Piggin wrote: > Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support for KVM > guests. Keep the fallback heuristic for KVM hosts that pre-date this > CAP. > > This is only proposed the KVM CAP has not yet been allocated. I will > ask to

Re: [PATCH] hw/arm/virt: Fix CPU's default NUMA node ID

On 1/26/22 5:14 PM, Igor Mammedov wrote: On Wed, 26 Jan 2022 13:24:10 +0800 Gavin Shan wrote: The default CPU-to-NUMA association is given by mc->get_default_cpu_node_id() when it isn't provided explicitly. However, the CPU topology isn't fully considered in the default association and it

Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

在 2022/2/16 下午11:48, Christoph Muellner 写道: diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 39ffb883fc..04500fe352 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -764,6 +764,10 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Counters", RISCVCPU,

[PATCH] tcg: Remove dh_alias indirection for dh_typecode

The dh_alias redirect is intended to handle TCG types as distinguished from C types. TCG does not distinguish signed int from unsigned int, because they are the same size. However, we need to retain this distinction for dh_typecode, lest we fail to extend abi types properly for the host call

[PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants

This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably didn't want to use piix4-specific constants. Now that the interrupt handing resides in piix4, its constants can be used. Signed-off-by: Bernhard Beschow ---

Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

On Thu, Feb 17, 2022 at 3:15 AM Weiwei Li wrote: > > 在 2022/2/16 下午11:48, Christoph Muellner 写道: > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 39ffb883fc..04500fe352 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -764,6 +764,10 @@ static Property

[PATCH v3 3/7] hw/isa/piix4: Resolve redundant i8259[] attribute

This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to PIIX4State to make the code movement more obvious. However, i8259[] seems redundant to *isa, so remove it. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c |

Re: [PATCH v3 7/7] hw/mips/gt64xxx_pci: Resolve gt64120_register()

On 16/2/22 23:45, Bernhard Beschow wrote: Now that gt64120_register() lost its pic parameter, there is an opportunity to remove it. gt64120_register() is old style by wrapping qdev API, and the new style is to use qdev directly. So take the opportunity and modernize the code. Suggested-by:

Re: Adding a handshake to qemu-guest-agent

On Wed, Feb 16, 2022 at 10:12:36AM +0100, Markus Armbruster wrote: > Michael Roth writes: > > > On Mon, Feb 14, 2022 at 03:14:37PM +0100, Markus Armbruster wrote: > >> Cc: the qemu-ga maintainer > >> > >> John Snow writes: > >> > >> > [Moving our discussion upstream, because it stopped being

Re: [PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants

On 16/2/22 23:45, Bernhard Beschow wrote: This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably didn't want to use piix4-specific constants. Now that the interrupt handing resides in piix4, its constants can be

Re: [PATCH 22/27] target/ppc: cpu_init: Rename register_ne_601_sprs

On Wed, Feb 16, 2022 at 10:19:40AM -0300, Fabiano Rosas wrote: > David Gibson writes: > > > On Tue, Feb 15, 2022 at 06:41:43PM -0300, Fabiano Rosas wrote: > >> The important part of this function is that it applies to non-embedded > >> CPUs, not that it also applies to the 601. We removed

[PATCH v16 1/7] accel/kvm/kvm-all: Refactor per-vcpu dirty ring reaping

From: Hyman Huang(黄勇) Add a non-required argument 'CPUState' to kvm_dirty_ring_reap so that it can cover single vcpu dirty-ring-reaping scenario. Signed-off-by: Hyman Huang(黄勇) Reviewed-by: Peter Xu --- accel/kvm/kvm-all.c | 23 +-- 1 file changed, 13 insertions(+), 10

[PATCH v16 2/7] cpus: Introduce cpu_list_generation_id

From: Hyman Huang(黄勇) Introduce cpu_list_generation_id to track cpu list generation so that cpu hotplug/unplug can be detected during measurement of dirty page rate. cpu_list_generation_id could be used to detect changes of cpu list, which is prepared for dirty page rate measurement.

Re: [PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants

On Wed, Feb 16, 2022 at 11:45:18PM +0100, Bernhard Beschow wrote: > This is a follow-up on patch "malta: Move PCI interrupt handling from > gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably > didn't want to use piix4-specific constants. Now that the interrupt > handing resides

Re: [PATCH v3 4/7] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq()

On Wed, Feb 16, 2022 at 11:45:16PM +0100, Bernhard Beschow wrote: > Passing PIIX4State rather than just the qemu_irq allows for resolving > the global piix4_dev variable. > > Signed-off-by: Bernhard Beschow > Reviewed-by: Peter Maydell > Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael

Re: [PATCH 2/2] Allow VIRTIO_F_IN_ORDER to be negotiated for vdpa devices

On Tue, Feb 15, 2022 at 12:52:31PM +0530, Gautam Dawar wrote: > This patch adds the ability to negotiate VIRTIO_F_IN_ORDER bit > for vhost-vdpa backend when the underlying device supports this > feature. > This would aid in reaping performance benefits with HW devices > that implement this

Re: [PATCH 3/3] x86: Switch to q35 as the default machine type

On 16/02/2022 18.57, Dr. David Alan Gilbert wrote: * Daniel P. Berrangé (berra...@redhat.com) wrote: On Wed, Feb 16, 2022 at 05:40:44PM +, Dr. David Alan Gilbert wrote: * Thomas Huth (th...@redhat.com) wrote: On 16/02/2022 12.01, Dr. David Alan Gilbert wrote: * Gerd Hoffmann

[PATCH v2 3/8] x86: Grant AMX permission for guest

Kernel allocates 4K xstate buffer by default. For XSAVE features which require large state component (e.g. AMX), Linux kernel dynamically expands the xstate buffer only after the process has acquired the necessary permissions. Those are called dynamically- enabled XSAVE features (or dynamic

[PATCH v2 0/8] AMX support in Qemu

Intel introduces Advanced Matrix Extensions (AMX) [1] feature that consists of configurable two-dimensional "TILE" registers and new accelerator instructions that operate on them. TMUL (Tile matrix MULtiply) is the first accelerator instruction set to use the new registers. Since AMX KVM patches

Re: [PATCH v3 0/7] malta: Fix PCI IRQ levels to be preserved during migration, cleanup

On Wed, Feb 16, 2022 at 11:45:12PM +0100, Bernhard Beschow wrote: > Tested with [1]: > > qemu-system-mipsel -M malta -kernel vmlinux-3.2.0-4-4kc-malta -hda \ > debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=tty0" > > It was possible to log in as root and `poweroff` the

Re: Call for GSoC and Outreachy project ideas for summer 2022

On Fri, Jan 28, 2022 at 6:04 PM Stefan Hajnoczi wrote: > > Dear QEMU, KVM, and rust-vmm communities, > QEMU will apply for Google Summer of Code 2022 > (https://summerofcode.withgoogle.com/) and has been accepted into > Outreachy May-August 2022 (https://www.outreachy.org/). You can now > submit

[PATCH v6 05/19] remote/machine: add vfio-user property

Add vfio-user to x-remote machine. It is a boolean, which indicates if the machine supports vfio-user protocol. The machine configures the bus differently vfio-user and multiprocess protocols, so this property informs it on how to configure the bus. This property should be short lived. Once

[PATCH v6 15/19] vfio-user: handle device interrupts

Forward remote device's interrupts to the guest Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman --- include/hw/pci/pci.h | 6 ++ include/hw/remote/vfio-user-obj.h | 6 ++ hw/pci/msi.c | 13 +++- hw/pci/msix.c

[PATCH v2 7/8] x86: Support XFD and AMX xsave data migration

From: Zeng Guang XFD(eXtended Feature Disable) allows to enable a feature on xsave state while preventing specific user threads from using the feature. Support save and restore XFD MSRs if CPUID.D.1.EAX[4] enumerate to be valid. Likewise migrate the MSRs and related xsave state necessarily.

[PATCH v2 6/8] x86: add support for KVM_CAP_XSAVE2 and AMX state migration

From: Jing Liu When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave area would be larger than 4KB. KVM_GET_XSAVE2 and KVM_SET_XSAVE under KVM_CAP_XSAVE2 works with a xsave buffer larger than 4KB. Always use the new ioctls under KVM_CAP_XSAVE2 when KVM supports it. Signed-off-by:

Re: [PATCH 1/2] linux headers: update against Linux 5.17-rc4

On Tue, Feb 15, 2022 at 3:23 PM Gautam Dawar wrote: > > This update is done to bring in the definition of VIRTIO_F_IN_ORDER > from Linux kernel's include/uapi/linux/virtio_config.h. > A patch was recently published to add VIRTIO_F_IN_ORDER's definition > in the Linux kernel on top of version

Re: QEMU's Haiku CI image

On 16/02/2022 20.21, Daniel P. Berrangé wrote: [...] The main issue is that for non-Linux, we don't have full automation for building the VM templates. We need someone to prepare the image by getting it able to run and expose SSH, whereupon we can provision the build-deps. That's easy: In QEMU

[PATCH v6 09/19] vfio-user: find and init PCI device

Find the PCI device with specified id. Initialize the device context with the QEMU PCI device Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Reviewed-by: Stefan Hajnoczi --- hw/remote/vfio-user-obj.c | 59 +++

[PATCH v2 4/8] x86: Add XFD faulting bit for state components

From: Jing Liu Intel introduces XFD faulting mechanism for extended XSAVE features to dynamically enable the features in runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set as 1, it indicates support for XFD faulting of this state component. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong

[PATCH v2 1/8] x86: Fix the 64-byte boundary enumeration for extended state

From: Jing Liu The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1] indicate whether the extended state component locates on the next 64-byte boundary following the preceding state component when the compacted format of an XSAVE area is used. Right now, they are all zero because no

[PATCH v2 8/8] linux-header: Sync the linux headers

This patch will be dropped once Qemu sync linux 5.17 header. Making all linux-headers changes here are only for maintainers to easily remove those changes once those patches are queued. Signed-off-by: Yang Zhong --- linux-headers/asm-x86/kvm.h | 17 + linux-headers/linux/kvm.h

Re: [PATCH v5 01/18] configure, meson: override C compiler for cmake

> On Jan 20, 2022, at 8:27 AM, Paolo Bonzini wrote: > > On 1/19/22 22:41, Jagannathan Raman wrote: >> The compiler path that cmake gets from meson is corrupted. It results in >> the following error: >> | -- The C compiler identification is unknown >> | CMake Error at CMakeLists.txt:35

Re: [PATCH v3 5/7] hw/isa/piix4: Resolve global instance variable

On Wed, Feb 16, 2022 at 11:45:17PM +0100, Bernhard Beschow wrote: > Now that piix4_set_irq's opaque parameter references own PIIX4State, > piix4_dev becomes redundant. > > Signed-off-by: Bernhard Beschow > Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S. Tsirkin > --- >

Re: [PATCH v3 3/7] hw/isa/piix4: Resolve redundant i8259[] attribute

On Wed, Feb 16, 2022 at 11:45:15PM +0100, Bernhard Beschow wrote: > This is a follow-up on patch "malta: Move PCI interrupt handling from > gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to > PIIX4State to make the code movement more obvious. However, i8259[] > seems redundant to

Re: [PATCH v8 3/3] qapi/monitor: allow VNC display id in set/expire_password

Am 09.02.22 um 15:07 schrieb Markus Armbruster: > Fabian Ebner writes: > >> From: Stefan Reiter >> >> It is possible to specify more than one VNC server on the command line, >> either with an explicit ID or the auto-generated ones à la "default", >> "vnc2", "vnc3", ... >> >> It is not possible

[PATCH v6 01/19] configure, meson: override C compiler for cmake

The compiler path that cmake gets from meson is corrupted. It results in the following error: | -- The C compiler identification is unknown | CMake Error at CMakeLists.txt:35 (project): | The CMAKE_C_COMPILER: | /opt/rh/devtoolset-9/root/bin/cc;-m64;-mcx16 | is not a full path to an existing

[PATCH v6 11/19] vfio-user: handle PCI config space accesses

Define and register handlers for PCI config space accesses Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Reviewed-by: Stefan Hajnoczi --- hw/remote/vfio-user-obj.c | 45 +++ hw/remote/trace-events| 2 ++

Re: [PATCH 28/31] vdpa: Expose VHOST_F_LOG_ALL on SVQ

On Wed, Feb 16, 2022 at 11:54 PM Eugenio Perez Martin wrote: > > On Tue, Feb 8, 2022 at 9:25 AM Jason Wang wrote: > > > > > > 在 2022/2/1 下午7:45, Eugenio Perez Martin 写道: > > > On Sun, Jan 30, 2022 at 7:50 AM Jason Wang wrote: > > >> > > >> 在 2022/1/22 上午4:27, Eugenio Pérez 写道: > > >>> SVQ is

[PATCH v2 2/8] x86: Add AMX XTILECFG and XTILEDATA components

From: Jing Liu The AMX TILECFG register and the TMMx tile data registers are saved/restored via XSAVE, respectively in state component 17 (64 bytes) and state component 18 (8192 bytes). Add AMX feature bits to x86_ext_save_areas array to set up AMX components. Add structs that define the layout

[PATCH v2 5/8] x86: Add AMX CPUIDs enumeration

From: Jing Liu Add AMX primary feature bits XFD and AMX_TILE to enumerate the CPU's AMX capability. Meanwhile, add AMX TILE and TMUL CPUID leaf and subleaves which exist when AMX TILE is present to provide the maximum capability of TILE and TMUL. Signed-off-by: Jing Liu Signed-off-by: Yang

Re: [PATCH v2 3/8] x86: Grant AMX permission for guest

On Wed, Feb 16, 2022 at 10:04:29PM -0800, Yang Zhong wrote: > Kernel allocates 4K xstate buffer by default. For XSAVE features > which require large state component (e.g. AMX), Linux kernel > dynamically expands the xstate buffer only after the process has > acquired the necessary permissions.

Re: [PATCH 2/2] Allow VIRTIO_F_IN_ORDER to be negotiated for vdpa devices

On Tue, Feb 15, 2022 at 3:23 PM Gautam Dawar wrote: > > This patch adds the ability to negotiate VIRTIO_F_IN_ORDER bit > for vhost-vdpa backend when the underlying device supports this > feature. > This would aid in reaping performance benefits with HW devices > that implement this feature. At

Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

在 2022/2/17 上午11:59, Christoph Müllner 写道: On Thu, Feb 17, 2022 at 3:15 AM Weiwei Li > wrote: 在 2022/2/16 下午11:48, Christoph Muellner 写道: > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 39ffb883fc..04500fe352 100644 > ---

[PATCH v6 00/19] vfio-user server in QEMU

Hi, This is v6 of the server side changes to enable vfio-user in QEMU. Thank you very much for your feedback for the last revision which helped to streamline the overall design. We've made the following changes to this revision: [PATCH v6 03/19] qdev: unplug blocker for devices - removed test

[PATCH v6 04/19] remote/machine: add HotplugHandler for remote machine

Allow hotplugging of PCI(e) devices to remote machine Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman --- hw/remote/machine.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/remote/machine.c b/hw/remote/machine.c index

[PATCH 17/20] migration: Postcopy preemption preparation on channel creation

Create a new socket for postcopy to be prepared to send postcopy requested pages via this specific channel, so as to not get blocked by precopy pages. A new thread is also created on dest qemu to receive data from this new channel based on the ram_load_postcopy() routine. The

[PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback

From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang

[PULL v2 34/35] target/riscv: add support for svpbmt extension

From: Weiwei Li - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel

[PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension

From: Philipp Tomsich This adds the decoder and translation for the XVentanaCondOps custom extension (vendor-defined by Ventana Micro Systems), which is documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf This

[PATCH 16/20] migration: Add postcopy-preempt capability

Firstly, postcopy already preempts precopy due to the fact that we do unqueue_page() first before looking into dirty bits. However that's not enough, e.g., when there're host huge page enabled, when sending a precopy huge page, a postcopy request needs to wait until the whole huge page that is

[PULL v2 17/35] target/riscv: Add AIA cpu feature

From: Anup Patel We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by:

[PATCH] arm: Remove swift-bmc machine

It was scheduled for removal in 7.0. Signed-off-by: Joel Stanley --- docs/system/arm/aspeed.rst | 1 - hw/arm/aspeed.c| 53 -- 2 files changed, 54 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index

[PATCH v2 3/3] target/ppc/kvm: Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support

Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support for KVM guests. Keep the fallback heuristic for KVM hosts that pre-date this CAP. This is only proposed the KVM CAP has not yet been allocated. I will ask to merge the new KVM cap when there are no objections on the QEMU side.

[PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs

From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang

[PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps

From: Philipp Tomsich The XVentanaCondOps extension is supported by VRULL on behalf of the Ventana Micro. Add myself as a point-of-contact. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id:

Re: [PATCH v2] nbd/server: Allow MULTI_CONN for shared writable exports

16.02.2022 02:24, Eric Blake wrote: On Tue, Feb 15, 2022 at 09:23:36PM +0200, Nir Soffer wrote: On Tue, Feb 15, 2022 at 7:22 PM Eric Blake wrote: According to the NBD spec, a server advertising NBD_FLAG_CAN_MULTI_CONN promises that multiple client connections will not see any cache

[PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts

From: Anup Patel The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish

Re: [PATCH v15 0/7] support dirty restraint on vCPU

On Wed, Feb 16, 2022 at 12:13:31PM +0800, huang...@chinatelecom.cn wrote: > From: Hyman Huang(黄勇) > > v15 > - rebase on master > - drop the 'init_time_ms' parameter in function vcpu_calculate_dirtyrate > - drop the 'setup' field in dirtylimit_state and call dirtylimit_process > directly,

Re: [PATCH] arm: Remove swift-bmc machine

On Wed, 16 Feb 2022 at 08:07, Cédric Le Goater wrote: > > On 2/16/22 09:03, Joel Stanley wrote: > > It was scheduled for removal in 7.0. > > > > Signed-off-by: Joel Stanley > > Could you please send a v2 with an update of docs/about/deprecated.rst ? Sure. Do we remove the machine from the list

[PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART

From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by:

[PULL v2 16/35] target/riscv: Allow setting CPU feature from machine/device emulation

From: Anup Patel The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example,

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