On 2022/01/03 20:45, Carwyn Ellis wrote:
The menu bar is only accessible when the Cocoa UI is windowed. In order
to allow the menu bar to be accessible in fullscreen mode, this change
makes the menu visible when the mouse is ungrabbed.
When the mouse is grabbed the menu is hidden again.
On Sun, 2 Jan 2022 at 17:42, Carwyn Ellis wrote:
>
> When switching between guest and host on a Mac using command-tab the
> command key is sent to the guest which can trigger functionality in the
> guest OS. Specifying left-command-key=off disables forwarding this key
> to the guest. Defaults to
Reviewed-by: Akihiko Odaki
On 2022/01/03 2:41, Carwyn Ellis wrote:
This resolves an issue where using command-tab to switch between QEMU
and other windows on the host can leave the mouse pointer visible.
By releasing the mouse when the user switches away, the user must left
click on the QEMU
On Thu, 17 Feb 2022 at 12:01, Daniel P. Berrangé wrote:
>
> The following changes since commit ad38520bdeb2b1e0b487db317f29119e94c1c88d:
>
> Merge remote-tracking branch
> 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2022-02-15
> 19:30:33 +)
>
> are available in the Git
The latest version of the SBI specification includes a Performance Monitoring
Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode
From: Atish Patra
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h |
The latest version of the SBI specification includes a Performance Monitoring
Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode
From: Atish Patra
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as
From: Atish Patra
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair
Hi all,
How does one pass Objective-C compilation flags (e.g., a sysroot
specification) when configuring/building? `configure` exposes
`--extra-cflags` and `--extra-cxxflags` for C/C++ compilation, but
there isn't an equivalent for Objective-C.
In my particular case, I'd like to specify a
This is a preparation before implementing another PCI IDE controller
that relies on these functions, so these can be shared between both
implementations.
Signed-off-by: Liav Albani
---
hw/ide/bmdma.c | 84 ++
hw/ide/meson.build | 2 +-
On 220128 1547, Stefan Hajnoczi wrote:
> Dear QEMU, KVM, and rust-vmm communities,
> QEMU will apply for Google Summer of Code 2022
> (https://summerofcode.withgoogle.com/) and has been accepted into
> Outreachy May-August 2022 (https://www.outreachy.org/). You can now
> submit internship project
Hi Joshua,
On 18/2/22 22:58, Joshua Seaton wrote:
Hi all,
How does one pass Objective-C compilation flags (e.g., a sysroot
specification) when configuring/building? `configure` exposes
`--extra-cflags` and `--extra-cxxflags` for C/C++ compilation, but
there isn't an equivalent for Objective-C.
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension.
From: Atish Patra
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret
The sscofpmf extension was ratified as a part of priv spec v1.12.
Mark the csr_ops accordingly.
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 90 ++
1 file changed, 60 insertions(+), 30 deletions(-)
diff --git a/target/riscv/csr.c
On 2/19/22 02:04, Peter Maydell wrote:
Hi; is anybody else seeing 'make check-acceptance' fail on some of
the s390 tests?
(009/183) tests/avocado/boot_linux.py:BootLinuxS390X.test_s390_ccw_virtio_tcg:
INTERRUPTED: Test interrupted by SIGTERM\nRunner error occurred:
Timeout reached\nOriginal
From: Atish Patra
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
On Fri, 18 Feb 2022, Liav Albani wrote:
This type of IDE controller has support for relocating the IO ports and
doesn't use IRQ 14 and 15 but one allocated PCI IRQ for the controller.
There's no x86 chipset in QEMU that will try to attach this device by
default. It is considered a legacy-free
Reviewed-by: Akihiko Odaki
On 2022/01/03 2:41, Carwyn Ellis wrote:
When switching between guest and host on a Mac using command-tab the
command key is sent to the guest which can trigger functionality in the
guest OS. Specifying left-command-key=off disables forwarding this key
to the guest.
On 18/2/22 19:55, Peter Maydell wrote:
On Sun, 2 Jan 2022 at 17:42, Carwyn Ellis wrote:
When switching between guest and host on a Mac using command-tab the
command key is sent to the guest which can trigger functionality in the
guest OS. Specifying left-command-key=off disables forwarding
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Signed-off-by: Atish Patra
Commit 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s")
changed phb4_pec code to create the default PHB4 objects in
pnv_pec_default_phb_realize(). In this process the stacks[] PEC array was
removed and each PHB4 object is tied together with its PEC via the
phb->pec pointer.
This
This is version 2 of this patch, this time a patch series, after following
the suggestions from BALATON Zoltan. I implemented this device because I have an
old machine from 2009 which has the ICH7 south bridge in it, so when I tried to
run Linux on it, it booted just fine (as you might expect),
On Fri, Feb 18, 2022 at 01:37:51PM +, Peter Maydell wrote:
> On Thu, 3 Feb 2022 at 14:01, Edgar E. Iglesias
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > Add a model of the Xilinx ZynqMP CRF. At the moment this
> > is mostly a stub model.
> >
> > Reviewed-by: Philippe Mathieu-Daudé
>
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.
Reviewed-by: Bin Meng
From: Atish Patra
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Reviewed-by: Bin Meng
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
This type of IDE controller has support for relocating the IO ports and
doesn't use IRQ 14 and 15 but one allocated PCI IRQ for the controller.
There's no x86 chipset in QEMU that will try to attach this device by
default. It is considered a legacy-free device in the aspect of PCI bus
resource
On Fri, 18 Feb 2022, Liav Albani wrote:
This is a preparation before implementing another PCI IDE controller
that relies on these functions, so these can be shared between both
implementations.
Signed-off-by: Liav Albani
---
hw/ide/bmdma.c | 84
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented
From: Atish Patra
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
target/riscv/cpu_helper.c | 26
This will allow us to attach machine state attributes like
the device tree fdt.
Signed-off-by: Stafford Horne
Reviewed-by: Philippe Mathieu-Daudé
---
hw/openrisc/openrisc_sim.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git
Changes since v2:
- Fix description to say devicetree "generation" not "support"
- Fix up various indentation issues.
- Use HWADDR_PRIx string formatting.
- Split device tree population out to device init.
- Do not load device tree or initrd if we have no kernel.
- Added patches to split
On 2/19/22 02:50, BALATON Zoltan wrote:
+/*
+ * QEMU IDE Emulation: PCI ICH6/ICH7 IDE support.
This is a small thing, but if these two are the same maybe keeping
this comment but using the ich7 name everywhere else would make it
less likely to get it confused with ich9. I mean ich6 and
Now that we no longer have a limit of 2 CPUs due to fixing the
IRQ routing issues we can increase the max. Here we increase
the limit to 4, we could go higher, but currently OMPIC has a
limit of 4, so we align with that.
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 8 +---
A guest could craft a specific stream of instructions that will have QEMU
write 0xF9 to inappropriate locations in memory. Add additional asserts
to check for this. Generate a #UD if there are more than 14 prefix bytes.
Found by Julian Stecklina
Signed-off-by: Cameron Esfahani
Signed-off-by:
The initrd passed via the command line is loaded into memory. It's
location and size is then added to the device tree so the kernel knows
where to find it.
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
---
hw/openrisc/openrisc_sim.c | 31 +++
1 file
Currently the OpenRISC SMP configuration only supports 2 cores due to
the UART IRQ routing being limited to 2 cores. As was done in commit
1eeffbeb11 ("hw/openrisc/openrisc_sim: Use IRQ splitter when connecting
IRQ to multiple CPUs") we can use a splitter to wire more than 2 CPUs.
This patch
Move magic numbers to variables and enums. These will be reused for
upcoming fdt initialization.
Signed-off-by: Stafford Horne
Reviewed-by: Philippe Mathieu-Daudé
---
hw/openrisc/openrisc_sim.c | 42 ++
1 file changed, 34 insertions(+), 8 deletions(-)
diff
On 2/19/22 02:12, BALATON Zoltan wrote:
On Fri, 18 Feb 2022, Liav Albani wrote:
This is a preparation before implementing another PCI IDE controller
that relies on these functions, so these can be shared between both
implementations.
Signed-off-by: Liav Albani
---
hw/ide/bmdma.c |
Using the device tree means that qemu can now directly tell
the kernel what hardware is configured rather than use having
to maintain and update a separate device tree file.
This patch adds automatic device tree generation support for the
OpenRISC simulator. A device tree is built up based on
On Wed, 2021-12-22 at 11:05 -0800, Steve Sistare wrote:
> Allocate anonymous memory using memfd_create if the memfd-alloc
> machine
> option is set.
>
> Signed-off-by: Steve Sistare
> ---
> hw/core/machine.c | 19 +++
> include/hw/boards.h | 1 +
> qemu-options.hx | 6
From: Joel Stanley
When time permits, we should introduce defines for the HW strapping
registers to cleanly decode the values.
SCU500 = 0x00422016
Disable ARM JTAG trusted world debug: 0x1
Disable ARM JTAG debug: 0x1
VGA Memory Size: 0x1 [16MB]
Cortex M3: 0x1 [Disabled]
Boot device:
On Thu, Feb 17, 2022 at 06:44:49PM +0100, Lukasz Maniak wrote:
> Changes since v4:
> - Added hello world example for SR-IOV to the docs
> - Moved AER initialization from nvme_init_ctrl to nvme_init_state
> - Fixed division by zero issue in calculation of vqfrt and vifrt
> capabilities
BTW you
On Fri, Feb 18, 2022 at 2:38 PM Alistair Francis
wrote:
>
> From: Wilfred Mallawa
>
> This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
> base addresses. Also adds these as unimplemented devices.
>
> The address references can be found [1].
>
> [1]
>
On 2/17/22 11:31, Joel Stanley wrote:
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Thanks,
C.
--
v2: also remove from docs/about/deprecated.rst
v3: remove strap define, add note to removed-features.rst
---
docs/about/deprecated.rst
From: Joel Stanley
Just a stub that indicates the system has booted in secure boot mode.
Used for testing the driver:
https://lore.kernel.org/all/20211019080608.283324-1-j...@jms.id.au/
Signed-off-by: Joel Stanley
[ clg: - Fixed typo
- Adjusted Copyright dates ]
Signed-off-by: Cédric
Only a limited set of bits are used for decoding the Start and End
addresses of the mapping window of a flash device.
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/aspeed_smc.h | 1 +
hw/ssi/aspeed_smc.c | 11 +++
2 files changed, 12 insertions(+)
diff --git
On Thu, Feb 17, 2022 at 06:44:49PM +0100, Lukasz Maniak wrote:
> Changes since v4:
> - Added hello world example for SR-IOV to the docs
> - Moved AER initialization from nvme_init_ctrl to nvme_init_state
> - Fixed division by zero issue in calculation of vqfrt and vifrt
> capabilities
So do
On Feb 18 03:26, Michael S. Tsirkin wrote:
> On Thu, Feb 17, 2022 at 06:44:49PM +0100, Lukasz Maniak wrote:
> > Changes since v4:
> > - Added hello world example for SR-IOV to the docs
> > - Moved AER initialization from nvme_init_ctrl to nvme_init_state
> > - Fixed division by zero issue in
This is useful to analyze changes in the U-Boot RAM driver when SDRAM
training is performed.
Signed-off-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 2 ++
hw/misc/trace-events | 4
2 files changed, 6 insertions(+)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index
On Thu, Feb 17, 2022 at 06:44:52PM +0100, Lukasz Maniak wrote:
> From: Łukasz Gieryk
>
> Convenience function for retrieving the PCIDevice object of the N-th VF.
>
> Signed-off-by: Łukasz Gieryk
> Reviewed-by: Knut Omang
Reviewed-by: Michael S. Tsirkin
> ---
> hw/pci/pcie_sriov.c
From: Joel Stanley
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Message-Id: <20220217103141.385345-1-j...@jms.id.au>
Signed-off-by: Cédric Le Goater
---
docs/about/deprecated.rst | 7
docs/about/removed-features.rst | 5 +++
On Thu, Feb 17, 2022 at 06:44:50PM +0100, Lukasz Maniak wrote:
> From: Knut Omang
>
> This patch provides the building blocks for creating an SR/IOV
> PCIe Extended Capability header and register/unregister
> SR/IOV Virtual Functions.
>
> Signed-off-by: Knut Omang
Reviewed-by: Michael S.
Hi,
Here is a set of extensions for the Aspeed machines, the most
important ones being the removal of a deprecated machine and a simple
model for the Secure Boot Controller, both from Joel.
Thanks,
C.
Changes in v2:
- new create_pca9552() helper (Philippe)
- fixed typos
- fixed removal of
From: Joel Stanley
This helps quieten booting the current Rainier kernel.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed.c
This unifies the way we create the pca9552 devices on the different boards.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 49 +++--
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git
On Thu, Feb 17, 2022 at 06:44:51PM +0100, Lukasz Maniak wrote:
> From: Knut Omang
>
> Add a small intro + minimal documentation for how to
> implement SR/IOV support for an emulated device.
>
> Signed-off-by: Knut Omang
Reviewed-by: Michael S. Tsirkin
> ---
> docs/pcie_sriov.txt | 115
On Thu, Feb 17, 2022 at 06:44:53PM +0100, Lukasz Maniak wrote:
> From: Łukasz Gieryk
>
> Signed-off-by: Łukasz Gieryk
Reviewed-by: Michael S. Tsirkin
> ---
> include/hw/pci/pci_regs.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/hw/pci/pci_regs.h
On Wed, 2021-12-22 at 11:05 -0800, Steve Sistare wrote:
> Save accepted socket fds before cpr-save, and look for them after
> cpr-load.
> in the environment after cpr-load. Reject cpr-exec if a socket
> enables
> the TLS or websocket option. Allow a monitor socket by closing it on
> exec.
>
>
If there is no memdev in numa configuration, it always reports
the error as the following:
total memory for NUMA nodes (0x0) should equal RAM size (0x1)
This error is confusing, and the total memory is the memory of
NUMA nodes with memdev specified actually. The memory size of a node
Goto label is incorrect so msi cleanup would not occur if there is
an error in the ssvid initialization.
Signed-off-by: Jonathan Cameron
---
Noticed whilst working on equivalent CXL upstream switch port.
hw/pci-bridge/xio3130_upstream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Shivaprasad G Bhat
The patch adds support for the SCM flush hcall for the nvdimm devices.
To be available for exploitation by guest through the next patch. The
hcall is applicable only for new SPAPR specific device class which is
also introduced in this patch.
The hcall expects the
From: Fabiano Rosas
Make sure that every register_*_sprs function only has calls to
spr_register* to register individual SPRs. Do not allow nesting. This
makes the code easier to follow and a look at init_proc_* should
suffice to know what SPRs a CPU has.
Signed-off-by: Fabiano Rosas
From: Fabiano Rosas
The G2LE CPU initialization code is the same as the G2. Use the latter
for both.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-3-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu_init.c | 42
From: Fabiano Rosas
Now that the 601 was removed, all of our CPUs have a timebase, so that
can be moved into the common function.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-5-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
From: Fabiano Rosas
We're considering these two to be in different CPU families (6xx and
7xx), so keep their SPR registration separate.
The code was copied into register_G2_sprs and the common function was
renamed to apply only to the 755.
Signed-off-by: Fabiano Rosas
Reviewed-by: David
From: Nicholas Piggin
Introduce virtual hypervisor methods that can support a "Nested KVM HV"
implementation using the bare metal 2-level radix MMU, and using HV
exceptions to return from H_ENTER_NESTED (rather than cause interrupts).
HV exceptions can now be raised in the TCG spapr machine
From: Nicholas Piggin
This implements the Nested KVM HV hcall API for spapr under TCG.
The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is switched back in returned from the hcall when a HV exception
is sent to the vhyp. Register state is copied in and out according to
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-12-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu_init.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git
On Tue, 8 Feb 2022 at 20:08, Peter Maydell wrote:
>
> The osdep.h header is included by every C file we compile, so it helps
> build times to keep it small. (As the comment at the top of the file
> notes, in an ideal world this header would contain only things that
> everybody needs and things
From: Shivaprasad G Bhat
A new subclass inheriting NVDIMMDevice is going to be introduced in
subsequent patches. The new subclass uses the realize and unrealize
callbacks. Add them on NVDIMMClass to appropriately call them as part
of plug-unplug.
Signed-off-by: Shivaprasad G Bhat
Acked-by:
-20220218
for you to fetch changes up to 65e0446c86ee70d2125c1f1d1e36e6c2dfb08642:
target/ppc: Move common SPR functions out of cpu_init (2022-02-18 08:34:15
+0100)
ppc-7.0 queue
* target/ppc: SPR registration cleanups (Fabiano
From: Nicholas Piggin
In prepartion for implementing a full partition table option for
vhyp, update the get_pate method to take an lpid and return a
success/fail indicator.
The spapr implementation currently just asserts lpid is always 0
and always return success.
Reviewed-by: Cédric Le Goater
From: Fabiano Rosas
init_proc_603 is defined after init_proc_e300, so I had to move some
code around to make it work.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-19-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-15-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu_init.c | 68 +++
1 file changed, 11 insertions(+), 57
From: Nicholas Piggin
The radix on vhyp MMU uses a single-level radix table walk, with the
partition scope mapping provided by the flat QEMU machine memory.
A subsequent change will use the two-level radix walk on vhyp in some
situations, so provide a helper which can abstract that logic.
From: Fabiano Rosas
The top level init_proc calls register_generic_sprs but also registers
some other SPRs outside of that function. Let's group everything into
a single place.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-4-faro...@linux.ibm.com>
From: Fabiano Rosas
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-18-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
From: Nicholas Piggin
This moves the logic to reset the QEMU exception state into its own
function.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-8-npig...@gmail.com>
Signed-off-by: Cédric Le Goater
---
From: Fabiano Rosas
Let's leave cpu_init with just generic CPU initialization and
QOM-related functions.
The rest of the SPR registration functions will be moved in the
following patches along with the code that uses them. These are only
the commonly used ones.
Signed-off-by: Fabiano Rosas
From: Fabiano Rosas
Initial intent for the spr_tcg header was to expose the spr_read|write
callbacks that are only used by TCG code. However, although these
routines are TCG-specific, the KVM code needs access to env->sprs
which creation is currently coupled to the callback registration.
We are
On Tue, Feb 15, 2022 at 12:52:31PM +0530, Gautam Dawar wrote:
> This patch adds the ability to negotiate VIRTIO_F_IN_ORDER bit
> for vhost-vdpa backend when the underlying device supports this
> feature.
> This would aid in reaping performance benefits with HW devices
> that implement this
From: Fabiano Rosas
This is just to have 755-specific registers contained into a function,
intead of leaving them open-coded in init_proc_755. It makes init_proc
easier to read and keeps later patches that touch this code a bit
cleaner.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
From: Fabiano Rosas
The init_proc_755 function is identical to the 745 one except for the
755-specific registers. I think it is worth it to make them share
code.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-21-faro...@linux.ibm.com>
Signed-off-by:
I've noticed that the meson incremental build doesn't seem to
cleanly handle a config file going away, as ppc64abi32-linux-user
has recently. The build fails with:
../../meson.build:1941:2: ERROR: Failed to load
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/configs/targets/ppc64abi32-linux-user.mak:
On 18/02/2022 12.59, Peter Maydell wrote:
I've noticed that the meson incremental build doesn't seem to
cleanly handle a config file going away, as ppc64abi32-linux-user
has recently. The build fails with:
../../meson.build:1941:2: ERROR: Failed to load
Wrong goto label, so msi cleanup would not occur if there is
an error in the ssvid initialization.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/xio3130_downstream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-bridge/xio3130_downstream.c
On Thu, Feb 17, 2022 at 8:32 AM Michael S. Tsirkin wrote:
>
> On Tue, Feb 15, 2022 at 12:52:31PM +0530, Gautam Dawar wrote:
> > This patch adds the ability to negotiate VIRTIO_F_IN_ORDER bit
> > for vhost-vdpa backend when the underlying device supports this
> > feature.
> > This would aid in
From: Fabiano Rosas
Put the SPR registration macros in a header that is accessible outside
of cpu_init.c. The following patches will move CPU-specific code to
separate files and will need to access it.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id:
From: Fabiano Rosas
The following patches will move CPU-specific code into separate files,
so expose the most used SPR registration functions:
register_sdr1_sprs | 22 callers
register_low_BATs | 20 callers
register_non_embedded_sprs | 19 callers
register_high_BATs | 10
From: Fabiano Rosas
These will need to be accessed from other files once we move the CPUs
code to separate files.
The check_pow_hid0 and check_pow_hid0_74xx are too specific to be
moved to a header so I'll deal with them later when splitting this
code between the multiple CPU families.
On Fri, Feb 18, 2022 at 09:51:12AM +0100, Klaus Jensen wrote:
> On Feb 18 03:26, Michael S. Tsirkin wrote:
> > On Thu, Feb 17, 2022 at 06:44:49PM +0100, Lukasz Maniak wrote:
> > > Changes since v4:
> > > - Added hello world example for SR-IOV to the docs
> > > - Moved AER initialization from
On Fri, 18 Feb 2022 10:23:02 +
Jonathan Cameron via wrote:
> Goto label is incorrect so msi cleanup would not occur if there is
> an error in the ssvid initialization.
>
> Signed-off-by: Jonathan Cameron
+Cc: linux...@huawei.com Turns out you get a weird result if you miss
a space in
From: Fabiano Rosas
This function registers just one SPR and has only two callers, so open
code it.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-23-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu_init.c | 21
From: Fabiano Rosas
The /* XXX : not implemented */ comments all over cpu_init are
confusing and ambiguous.
Do they mean not implemented by QEMU, not implemented in a specific
access mode? Not implemented by the CPU? Do they apply to just the
register right after or to a whole block? Do they
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-13-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu_init.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-20-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu_init.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220216162426.1885923-7-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu_init.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git
Peter,
On 2/18/22 09:18, Cédric Le Goater wrote:
Hi,
Here is a set of extensions for the Aspeed machines, the most
important ones being the removal of a deprecated machine and a simple
model for the Secure Boot Controller, both from Joel.
I have a PR ready to be sent if there are no further
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