On 16/02/2022 15.54, Alex Bennée wrote:
David Hildenbrand writes:
We need a newer compiler to build upcoming tests that test for z15
features with -march=z15. So let's do it similar to arm64 and powerpc,
using an environment based on debian11 to build tests only.
Cc: Thomas Huth
Cc:
On 28.02.22 09:45, Thomas Huth wrote:
> On 16/02/2022 15.54, Alex Bennée wrote:
>>
>> David Hildenbrand writes:
>>
>>> We need a newer compiler to build upcoming tests that test for z15
>>> features with -march=z15. So let's do it similar to arm64 and powerpc,
>>> using an environment based on
ping
https://patchew.org/QEMU/20220120084634.131450-1-luo...@unicloud.com/
发件人: 罗飞
发送时间: 2022年1月20日 16:46
收件人: qemu-devel
抄送: Paolo Bonzini; Marcelo Tosatti; k...@vger.kernel.org; 罗飞
主题: [PATCH] i386: Set MCG_STATUS_RIPV bit for mce SRAR error
In the
Add a new field 'cpu0-id' to the response of query-sev-capabilities QMP
command. The value of the field is the base64-encoded unique ID of CPU0
(socket 0), which can be used to retrieve the signed CEK of the CPU from
AMD's Key Distribution Service (KDS).
Signed-off-by: Dov Murik
---
v3:
-
On Thu, Feb 24, 2022 at 6:51 PM Igor Mammedov wrote:
>
> On Thu, 24 Feb 2022 18:14:35 +0530
> Ani Sinha wrote:
>
> > On Thu, Feb 24, 2022 at 2:33 PM Igor Mammedov wrote:
> > >
> > > On Wed, 23 Feb 2022 17:30:34 +0530
> > > Ani Sinha wrote:
> > >
> > > > On Wed, Feb 23, 2022 at 2:34 PM Igor
On Mon, 28 Feb 2022 at 09:13, Daniel P. Berrangé wrote:
> We only support the current major release, and thue previous major
> release for 2 years overlap. If we consider 11.x releases as major,
> then 11.3 went out of scope from QEMU's POV in Aug 2020, and thus
> we don't need to care about this
Split block_copy_reset() out of block_copy_reset_unallocated() to be
used separately later.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Hanna Reitz
---
include/block/block-copy.h | 1 +
block/block-copy.c | 21 +
2 files changed, 14 insertions(+), 8
On Sonntag, 27. Februar 2022 23:35:22 CET Will Cohen wrote:
> From: Keno Fischer
>
> To allow VirtFS on darwin, we need to check that pthread_fchdir_np is
> available, which has only been available since macOS 10.12.
>
> Additionally, virtfs_proxy_helper is disabled on Darwin. This patch
>
commit
f862ddbb1a4 (hw/i386: Remove the deprecated pc-1.x machine types)
removed the last user of broken APIC ID compat knob,
but compat_apic_id_mode itself was forgotten.
Clean it up and simplify x86_cpu_apic_id_from_index()
Signed-off-by: Igor Mammedov
---
include/hw/i386/x86.h | 2 --
On Mon, Feb 28, 2022 at 07:16:56AM -0500, Michael S. Tsirkin wrote:
> On Fri, Feb 25, 2022 at 02:35:36PM +, Daniel P. Berrangé wrote:
> > On Fri, Feb 25, 2022 at 09:10:44AM -0500, Michael S. Tsirkin wrote:
> > > QOM reference counting is not designed with an infinite amount of
> > > references
QEMU's default screen resolution recently changed to 1280x800, so the
resolution in the screen shot header changed of course, too.
Fixes: de72c4b7cd ("edid: set default resolution to 1280x800 (WXGA)")
Reported-by: Peter Maydell
Message-Id: <20220221101933.307525-1-th...@redhat.com>
Reviewed-by:
Cleber Rosa writes:
> Since Avocado 94.0[1], the "avocado.utils.network" dropped a lot of
> previously deprecated API names, having the new names into a finer
> grained structure.
>
> This simply uses the new API names for the network port utility
> module.
>
> [1] -
>
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_bits.h | 9 ++
target/riscv/csr.c | 64 +
We generally target glibc 2.12 in the Julia ecosystem, since CentOS 6 is
still quite common in the HPC community.
Best,
Simeon
On 2/28/22 09:38, Daniel P. Berrangé wrote:
> On Mon, Feb 28, 2022 at 02:15:11PM +, Peter Maydell wrote:
>> On Mon, 28 Feb 2022 at 14:12, Simeon Schaub wrote:
>>>
On Mon, 28 Feb 2022 at 14:38, Daniel P. Berrangé wrote:
>
> On Mon, Feb 28, 2022 at 02:15:11PM +, Peter Maydell wrote:
> > On Mon, 28 Feb 2022 at 14:12, Simeon Schaub wrote:
> > >
> > > >From e77de12cc33846a3de71d1858e497fbf4cdbff96 Mon Sep 17 00:00:00 2001
> > > From: Simeon David Schaub
>
Daniel P. Berrangé writes:
> $SUBJECT =~ s/lci-tool/lcitool/
>
> On Fri, Feb 25, 2022 at 05:20:07PM +, Alex Bennée wrote:
>> Using lci-tool update debian-arm64-cross to a Debian 11 based system.
>
> Likewise
>
>> As a result we can drop debian-arm64-test-cross just for building
>> tests.
The PQ_disable configuration bit disables the check done on the PQ
state bits when processing new MSI interrupts. When bit 9 is enabled,
the PHB forwards any MSI trigger to the XIVE interrupt controller
without checking the PQ state bits. The XIVE IC knows from the trigger
message that the PQ bits
Reviewed-by: David Gibson
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 10 ++
include/hw/ppc/pnv_homer.h | 3 ++
include/hw/ppc/pnv_xscom.h | 3 ++
hw/ppc/pnv.c | 20
hw/ppc/pnv_homer.c | 64 ++
5
Our OCC model is very mininal and POWER10 can simply reuse the OCC
model we introduced for POWER9.
Reviewed-by: David Gibson
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 1 +
include/hw/ppc/pnv_occ.h | 2 ++
include/hw/ppc/pnv_xscom.h | 3 +++
hw/ppc/pnv.c
>From b6ec17a85a8fb2431545f9c5093dbce9a090b522 Mon Sep 17 00:00:00 2001
From: Simeon David Schaub
Date: Mon, 28 Feb 2022 10:51:04 -0500
Subject: [PATCH] allow disabling tests
Adds an option to avoid running tests as part of the build process. I
ran `make update-buildoptions` to update the meson
Ah, yes, sorry, I didn't check whether the tests were actually run. I
can rename this to something more like `build-tests` if you think that's
more informative.
Best,
Simeon
On 2/28/22 11:16, Peter Maydell wrote:
> On Mon, 28 Feb 2022 at 16:10, Simeon Schaub wrote:
>>
>> From
On Mon, Feb 28, 2022 at 04:16:43PM +, Alex Bennée wrote:
>
> Stefan Hajnoczi writes:
>
> > [[PGP Signed Part:Undecided]]
> > On Fri, Feb 25, 2022 at 05:32:43PM +, Alex Bennée wrote:
> >>
> >> [Apologies to CC list for repost due to fat fingering the mailing list
> >> address]
> >>
>
On Mon, 28 Feb 2022 at 13:28, Marc-André Lureau
wrote:
>
> Hi
>
> On Mon, Feb 28, 2022 at 5:24 PM Peter Maydell
> wrote:
> >
> > On Mon, 28 Feb 2022 at 12:19, wrote:
> > >
> > > From: Marc-André Lureau
> > >
> > > testfile.c: In function 'main':
> > > testfile.c:5:11: error: incorrect number
On Mon, 28 Feb 2022 at 14:07, ~ubzeme wrote:
>
> I recently bought a Mac with M1 Pro chip, and use QEMU to setup a Linux
> virtual machine. QEMU crashed when I started a VM with HVF accelerator
> enabled and with the device, bochs-display, added.
>
> After digging into the source code, I found
From: Yan-Jie Wang
Follow the QEMU coding style. Use hwaddr for guest physical address.
Signed-off-by: Yan-Jie Wang
---
accel/hvf/hvf-mem.c | 2 +-
include/sysemu/hvf_int.h | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/accel/hvf/hvf-mem.c
From: Yan-Jie Wang
Follow the QEMU coding style. Structured type names are in CamelCase.
Signed-off-by: Yan-Jie Wang
---
accel/hvf/hvf-mem.c | 14 +++---
include/sysemu/hvf_int.h | 8
target/i386/hvf/hvf.c| 4 ++--
3 files changed, 13 insertions(+), 13 deletions(-)
From: Yan-Jie Wang
Currently, there are only 32 memory slots in the fixed size array.
It is not scalable. Instead of using fixed size array, use GTree
(from glib library) and dynamically-allocated structures to store
memory slots.
Signed-off-by: Yan-Jie Wang
---
accel/hvf/hvf-mem.c | 63
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn32.decode | 5
target/riscv/insn_trans/trans_rvk.c.inc | 37 +
2 files changed,
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu.h | 13 +
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..9e8bbce6f1
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvk.c.inc | 63
PHB4 and PHB5 are very similar. Use the PHB4 models with some minor
adjustements in a subclass for P10.
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 12
include/hw/ppc/pnv.h | 3 ++
include/hw/ppc/pnv_xscom.h | 6
hw/pci-host/pnv_phb4.c
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive2.h | 1 +
hw/intc/pnv_xive2.c| 5 +
hw/intc/xive2.c| 3 ++-
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index
On Mon, Feb 28, 2022 at 10:59:24AM -0500, Simeon Schaub wrote:
> From b6ec17a85a8fb2431545f9c5093dbce9a090b522 Mon Sep 17 00:00:00 2001
> From: Simeon David Schaub
> Date: Mon, 28 Feb 2022 10:51:04 -0500
> Subject: [PATCH] allow disabling tests
>
> Adds an option to avoid running tests as part
On Mon, 28 Feb 2022 at 16:46, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Fri, 25 Feb 2022 at 17:36, Alex Bennée wrote:
> >>
> >> We will need an update shortly for some new images.
> >>
> >> Signed-off-by: Alex Bennée
> >> Message-Id:
On 2/28/22 12:52, Cédric Le Goater wrote:
PHB4 and PHB5 are very similar. Use the PHB4 models with some minor
adjustements in a subclass for P10.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
include/hw/pci-host/pnv_phb4.h | 12
On Sonntag, 27. Februar 2022 23:35:20 CET Will Cohen wrote:
> From: Keno Fischer
>
> Darwin does not support mknodat. However, to avoid race conditions
> with later setting the permissions, we must avoid using mknod on
> the full path instead. We could try to fchdir, but that would cause
>
On 28/02/2022 14.20, Christian Schoenebeck wrote:
On Sonntag, 27. Februar 2022 23:35:20 CET Will Cohen wrote:
From: Keno Fischer
Darwin does not support mknodat. However, to avoid race conditions
with later setting the permissions, we must avoid using mknod on
the full path instead. We could
From: David Miller
tests/tcg/s390x/mie3-compl.c: [N]*K instructions
tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
tests/tcg/s390x/mie3-sel.c: SELECT instruction
Signed-off-by: David Miller
Message-Id: <20220223223117.0-4-dmiller...@gmail.com>
[thuth: Squash mnemonic -> .insn patch, white
On Mon, Feb 28, 2022 at 8:11 AM Christian Schoenebeck <
qemu_...@crudebyte.com> wrote:
> On Sonntag, 27. Februar 2022 23:35:22 CET Will Cohen wrote:
> > From: Keno Fischer
> >
> > To allow VirtFS on darwin, we need to check that pthread_fchdir_np is
> > available, which has only been available
Hi!
The following changes since commit fa435db8ce1dff3b15e3f59a12f55f7b3a347b08:
Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request'
into staging (2022-02-24 12:48:14 +)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git
On Mon, 28 Feb 2022 08:37:10 -0500
Will Cohen wrote:
> On Mon, Feb 28, 2022 at 8:20 AM Christian Schoenebeck <
> qemu_...@crudebyte.com> wrote:
>
> > On Sonntag, 27. Februar 2022 23:35:20 CET Will Cohen wrote:
> > > From: Keno Fischer
> > >
> > > Darwin does not support mknodat. However, to
From: Yan-Jie Wang
* Remove mac_slot and use hvf_slot only. The function of the two structures
are similar.
* Refactor function hvf_set_phys_mem():
- Remove unnecessary checks because any modified memory sections
will be removed first (region_del called first) before being added.
>From e77de12cc33846a3de71d1858e497fbf4cdbff96 Mon Sep 17 00:00:00 2001
From: Simeon David Schaub
Date: Sun, 27 Feb 2022 22:59:19 -0500
Subject: [PATCH] explicitly link libqemuutil against rt
Qemu uses `clock_gettime` which is already part of more recent versions
of glibc, but on older versions
On Mon, Feb 28, 2022 at 02:15:11PM +, Peter Maydell wrote:
> On Mon, 28 Feb 2022 at 14:12, Simeon Schaub wrote:
> >
> > >From e77de12cc33846a3de71d1858e497fbf4cdbff96 Mon Sep 17 00:00:00 2001
> > From: Simeon David Schaub
> > Date: Sun, 27 Feb 2022 22:59:19 -0500
> > Subject: [PATCH]
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn32.decode | 5
target/riscv/insn_trans/trans_rvk.c.inc | 32 +
2 files changed,
Ok, I understand.
On 2/28/22 10:17, Peter Maydell wrote:
> On Mon, 28 Feb 2022 at 15:13, Simeon Schaub wrote:
>>
>> We generally target glibc 2.12 in the Julia ecosystem, since CentOS 6 is
>> still quite common in the HPC community.
>
> Unfortunately you're on your own there then -- CentOS 6 is
POWER10 adds support for StoreEOI operation and 64K ESB pages on PSIHB
to be consistent with the other interrupt sources of the system.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 6 ++
hw/ppc/pnv_psi.c | 30 --
2
On Mon, 28 Feb 2022 at 16:10, Simeon Schaub wrote:
>
> From b6ec17a85a8fb2431545f9c5093dbce9a090b522 Mon Sep 17 00:00:00 2001
> From: Simeon David Schaub
> Date: Mon, 28 Feb 2022 10:51:04 -0500
> Subject: [PATCH] allow disabling tests
>
> Adds an option to avoid running tests as part of the
Alex Bennée writes:
> Richard Henderson writes:
>
>> On 2/25/22 07:20, Alex Bennée wrote:
>>> +++ b/tests/tcg/i386/Makefile.target
>>> @@ -71,3 +71,9 @@ TESTS=$(MULTIARCH_TESTS) $(I386_TESTS)
>>> # On i386 and x86_64 Linux only supports 4k pages (large pages
>>> are a different hack)
>>>
On 28/2/22 06:22, Kshitij Suri wrote:
Libpng is only detected if VNC is enabled currently. This patch adds a
generalised png option in the meson build which is aimed to replace use of
CONFIG_VNC_PNG with CONFIG_PNG.
Signed-off-by: Kshitij Suri
---
meson.build| 10 +-
On 28/02/2022 14.16, Igor Mammedov wrote:
commit
f862ddbb1a4 (hw/i386: Remove the deprecated pc-1.x machine types)
removed the last user of broken APIC ID compat knob,
but compat_apic_id_mode itself was forgotten.
Clean it up and simplify x86_cpu_apic_id_from_index()
Signed-off-by: Igor
On Montag, 28. Februar 2022 14:36:30 CET Thomas Huth wrote:
> On 28/02/2022 14.20, Christian Schoenebeck wrote:
> > On Sonntag, 27. Februar 2022 23:35:20 CET Will Cohen wrote:
> >> From: Keno Fischer
> >>
> >> Darwin does not support mknodat. However, to avoid race conditions
> >> with later
From: Yan-Jie Wang
This fixes the mobile version of the website.
Resolves: https://gitlab.com/qemu-project/qemu-web/-/issues/5
Signed-off-by: Yan-Jie Wang
---
assets/css/style-desktop.css | 9 -
assets/css/style.css | 1 +
2 files changed, 1 insertion(+), 9 deletions(-)
diff
On Mon, 28 Feb 2022 at 14:12, Simeon Schaub wrote:
>
> >From e77de12cc33846a3de71d1858e497fbf4cdbff96 Mon Sep 17 00:00:00 2001
> From: Simeon David Schaub
> Date: Sun, 27 Feb 2022 22:59:19 -0500
> Subject: [PATCH] explicitly link libqemuutil against rt
>
> Qemu uses `clock_gettime` which is
On Fri, Feb 25, 2022 at 05:32:43PM +, Alex Bennée wrote:
>
> [Apologies to CC list for repost due to fat fingering the mailing list
> address]
>
> Hi Michael,
>
> I was updating my vhost-user-rpmb implementation when I realised it
> wasn't handling config space access properly. However
On Wed, Feb 16, 2022 at 11:53:52AM +0100, Hanna Reitz wrote:
> Hi,
>
> v1 with detailed reasoning:
> https://lists.nongnu.org/archive/html/qemu-block/2022-02/msg00508.html
>
> This series makes bdrv_refresh_limits() non-recursive so that it is
> sufficient for callers to ensure that the node on
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 105
target/riscv/helper.h | 6 ++
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 28
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 6 +++
On Mon, 28 Feb 2022 at 15:13, Simeon Schaub wrote:
>
> We generally target glibc 2.12 in the Julia ecosystem, since CentOS 6 is
> still quite common in the HPC community.
Unfortunately you're on your own there then -- CentOS 6 is
well out of QEMU upstream's supported-build-platforms list,
and we
and use a pnv_chip_power10_quad_realize() helper to avoid code
duplication with P9. This still needs some refinements on the XSCOM
registers handling in PnvQuad.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 3 +++
hw/ppc/pnv.c | 50
The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE2 structures, and a set of new features
which are described below.
The thread interrupt management area (TIMA) is a set of pages mapped
in the Hypervisor and in the guest OS address space giving access to
the interrupt thread context registers for interrupt management, ACK,
EOI, CPPR, etc.
XIVE2 changes slightly the TIMA layout with extra bits for the new
On Mon, 28 Feb 2022 at 16:22, Simeon Schaub wrote:
>
> Ah, yes, sorry, I didn't check whether the tests were actually run. I
> can rename this to something more like `build-tests` if you think that's
> more informative.
What problem are you trying to solve here ? It shouldn't
matter whether we
Stefan Hajnoczi writes:
> [[PGP Signed Part:Undecided]]
> On Fri, Feb 25, 2022 at 05:32:43PM +, Alex Bennée wrote:
>>
>> [Apologies to CC list for repost due to fat fingering the mailing list
>> address]
>>
>>
>> (aside: this continues my QOM confusion about when things should be in a
On Mon, 28 Feb 2022 at 12:19, wrote:
>
> From: Marc-André Lureau
>
> testfile.c: In function 'main':
> testfile.c:5:11: error: incorrect number of arguments to function
> '__atomic_load'
> 5 | y = __atomic_load(, 0);
> | ^
> testfile.c:6:7: error: argument
On 28/2/22 14:16, Igor Mammedov wrote:
commit
f862ddbb1a4 (hw/i386: Remove the deprecated pc-1.x machine types)
removed the last user of broken APIC ID compat knob,
but compat_apic_id_mode itself was forgotten.
Clean it up and simplify x86_cpu_apic_id_from_index()
Signed-off-by: Igor
On 2/26/22 10:49, Cédric Le Goater wrote:
On 2/18/22 21:28, Daniel Henrique Barboza wrote:
Commit 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s")
changed phb4_pec code to create the default PHB4 objects in
pnv_pec_default_phb_realize(). In this process the stacks[] PEC array was
From: Yan-Jie Wang
We follow how KVM accel does in its memory listener (kvm-all.c) and add
a lock for the memory related functions.
Signed-off-by: Yan-Jie Wang
---
accel/hvf/hvf-mem.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/accel/hvf/hvf-mem.c
From: Yan-Jie Wang
Signed-off-by: Yan-Jie Wang
---
accel/hvf/hvf-accel-ops.c | 220 +
accel/hvf/hvf-mem.c | 252 ++
accel/hvf/meson.build | 1 +
include/sysemu/hvf_int.h | 2 +
4 files changed, 256
I recently bought a Mac with M1 Pro chip, and use QEMU to setup a Linux
virtual machine. QEMU crashed when I started a VM with HVF accelerator
enabled and with the device, bochs-display, added.
After digging into the source code, I found that dirty-tracking in HVF
did not work properly, which
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 170 ++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
On Montag, 28. Februar 2022 15:06:07 CET Peter Maydell wrote:
> On Mon, 28 Feb 2022 at 13:58, Christian Schoenebeck
>
> wrote:
> > On Montag, 28. Februar 2022 14:36:30 CET Thomas Huth wrote:
> > > For lines less than 90 characters, it's just a warning, and I think it's
> > > ok
> > > in such
The XIVE2 interrupt controller of the POWER10 processor as the same
logic as on POWER9 but its SW interface has been largely reworked. The
interrupt controller has a new register interface, different BARs,
extra VSDs. These will be described when we add the device model for
the baremetal machine.
The trigger message coming from a HW source contains a special bit
informing the XIVE interrupt controller that the PQ bits have been
checked at the source or not. Depending on the value, the IC can
perform the check and the state transition locally using its own PQ
state bits.
The following
Hi,
The skiboot merged in QEMU already has POWER10 support. This series
adds a minimum set of models (XIVE2, PHB5) to boot a baremetal POWER10
machine using the OpenPOWER firmware images.
The major change is the support for the interrupt controller of the
POWER10 processor. XIVE2 is very much
Add GEN1 config even if we don't use it yet in the core framework.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive2.h | 8
hw/intc/pnv_xive2.c| 13 +
hw/intc/xive2.c| 7 +++
3 files changed, 28 insertions(+)
From: David Miller
TCG implements everything we need to run basic z15 OS+software
Signed-off-by: David Miller
Message-Id: <20220223223117.0-3-dmiller...@gmail.com>
Reviewed-by: David Hildenbrand
Signed-off-by: Thomas Huth
---
hw/s390x/s390-virtio-ccw.c | 3 +++
From: Nico Boehr
We previously loaded into in1, but in1 is not filled during
disassembly and hence always zero. This leads to an assertion failure:
qemu-system-s390x: /home/nrb/qemu/include/tcg/tcg.h:654: temp_idx:
Assertion `n >= 0 && n < tcg_ctx->nb_temps' failed.`
Instead, use
Hi
On Mon, Feb 28, 2022 at 5:24 PM Peter Maydell wrote:
>
> On Mon, 28 Feb 2022 at 12:19, wrote:
> >
> > From: Marc-André Lureau
> >
> > testfile.c: In function 'main':
> > testfile.c:5:11: error: incorrect number of arguments to function
> > '__atomic_load'
> > 5 | y =
On Mon, 28 Feb 2022 at 13:58, Christian Schoenebeck
wrote:
>
> On Montag, 28. Februar 2022 14:36:30 CET Thomas Huth wrote:
> > For lines less than 90 characters, it's just a warning, and I think it's ok
> > in such cases to keep it longer than 80 characters, if the result of
> > breaking it up
+/* These tests match the CPU_FTR_P9_RADIX_PREFETCH_BUG flag in Linux */
+if (((pcc->pvr & 0xff00) == CPU_POWERPC_POWER9_DD1) ||
+((pcc->pvr & 0xff00) == CPU_POWERPC_POWER9_DD20) ||
+((pcc->pvr & 0xff00) == CPU_POWERPC_POWER9_DD21)) {
+return 0;
+}
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
2 files changed, 4
This patchset implements RISC-V scalar crypto extension v1.0.0 version
instructions.
Partial instructions are reused from B-extension.
Specification:
https://github.com/riscv/riscv-crypto
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v7
To test rvk
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9e8bbce6f1..11a35fb5d6 100644
--- a/target/riscv/cpu.c
+++
e820 reserved entries were used before the dynamic entries with fw config files
were intoduced into qemu with the following change:
7d67110f2d9a6("pc: add etc/e820 fw_cfg file")
Identical support was introduced into seabios as well with the following commit:
ce39bd4031820 ("Add support for
When the Address-Based Interrupt Trigger mode is activated, the PHB
maps the interrupt source number into the interrupt command address.
The PHB directly triggers the IC ESB page of the interrupt number and
not the notify page of the IC anymore.
Reviewed-by: Daniel Henrique Barboza
These bits control the availability of interrupt features : StoreEOI,
PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE
exploitation mode. These bits can be set at early boot time of the
system to activate/deactivate a feature for testing purposes. The
default value should be '1'.
The XIVE interrupt controller on P10 can automatically save and
restore the state of the interrupt registers under the internal NVP
structure representing the VCPU. This saves a costly store/load in
guest entries and exits.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Only the CAM line updates done by the hypervisor are specific to
POWER10. Instead of duplicating the TM ops table, we handle these
commands locally under the PowerNV XIVE2 model.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive2.h | 8
> On Feb 21, 2022, at 10:27 AM, Stefan Hajnoczi wrote:
>
> On Thu, Feb 17, 2022 at 02:48:50AM -0500, Jagannathan Raman wrote:
>> Add blocker to prevent hot-unplug of devices
>>
>> Signed-off-by: Elena Ufimtseva
>> Signed-off-by: John G Johnson
>> Signed-off-by: Jagannathan Raman
>> ---
>>
Peter Maydell writes:
> On Fri, 25 Feb 2022 at 17:36, Alex Bennée wrote:
>>
>> We will need an update shortly for some new images.
>>
>> Signed-off-by: Alex Bennée
>> Message-Id: <20220211160309.335014-4-alex.ben...@linaro.org>
>> ---
>> tests/docker/dockerfiles/opensuse-leap.docker | 3 +--
On Sat, 26 Feb 2022 at 02:03, Stafford Horne wrote:
>
> The following changes since commit 4aa2e497a98bafe962e72997f67a369e4b52d9c1:
>
> Merge remote-tracking branch
> 'remotes/berrange-gitlab/tags/misc-next-pull-request' into staging
> (2022-02-23 09:25:05 +)
>
> are available in the Git
On 28/2/22 04:27, Zhenzhong Duan wrote:
While there is already a local variable opts in main function scope,
no need to define another one with same name in smaller scope.
No functional changes.
Signed-off-by: Zhenzhong Duan
---
softmmu/vl.c | 4 +---
1 file changed, 1 insertion(+), 3
From: David Miller
implements:
AND WITH COMPLEMENT (NCRK, NCGRK)
NAND (NNRK, NNGRK)
NOT EXCLUSIVE OR (NXRK, NXGRK)
NOR (NORK, NOGRK)
OR WITH COMPLEMENT(OCRK, OCGRK)
SELECT(SELR, SELGR)
SELECT HIGH (SELFHR)
MOVE RIGHT TO LEFT
On Mon, Feb 28, 2022 at 8:20 AM Christian Schoenebeck <
qemu_...@crudebyte.com> wrote:
> On Sonntag, 27. Februar 2022 23:35:20 CET Will Cohen wrote:
> > From: Keno Fischer
> >
> > Darwin does not support mknodat. However, to avoid race conditions
> > with later setting the permissions, we must
QEMU will soon drop the support for Ubuntu 18.04, so let's update
the Travis jobs that were still using this version to 20.04 instead.
While we're at it, also remove an obsolete comment about Ubuntu
Xenial being the default for our Travis jobs.
Reviewed-by: Richard Henderson
Message-Id:
Richard Henderson writes:
> On 2/25/22 07:20, Alex Bennée wrote:
>> +++ b/tests/tcg/i386/Makefile.target
>> @@ -71,3 +71,9 @@ TESTS=$(MULTIARCH_TESTS) $(I386_TESTS)
>> # On i386 and x86_64 Linux only supports 4k pages (large pages
>> are a different hack)
>>
From: Yan-Jie Wang
Dirty-tracking in HVF is not properly implemented.
On Intel Macs, Ubuntu ISO boot menu does not show properly.
On Apple Silicon, using bochs-display may cause the guest crashes because
the guest may uses load/store instructions on framebuffer which causes
vmexits and the
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/bitmanip_helper.c | 53 ++
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
crypto/meson.build | 1 +
crypto/sm4.c | 49
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