`cpu_pc` at this point does not necessary point to the current
instruction (i.e., the wait instruction being translated), so it's
incorrect to calculate the new value of `cpu_pc` based on this. It must
be updated with `ctx->base.pc_next`, which contains the correct address
of the next instruction.
Generation with widl needs to be triggered explicitly and requires
library and include directories containing referenced *.idl and *.tlb
as parameters.
Signed-off-by: Helge Konetzka
---
For tested Msys2 build all referenced resources reside in //include.
Msys2 provides its flavours in
Use tcg_constant_{i32,i64,ptr} as appropriate throughout, which
means we get to remove lots of tcg_temp_free_*. Drop variables
in many cases, passing the constant directly to another function.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 302
This function is incorrect in that it does not properly consider
CPTR_EL2.FPEN. We've already got another mechanism for raising
an FPU access trap: ARM_CP_FPU, so use that instead.
Remove CP_ACCESS_TRAP_FP_EL{2,3}, which becomes unused.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h
The operation we're performing with the movcond
is either min/max depending on cond -- simplify.
Use tcg_constant_i64 while we're at it.
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 050d80f6f9..6f0ebdc88e 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -332,16
Give this enum a name and use in ARMCPRegInfo,
add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h | 6 +++---
target/arm/helper.c | 6 --
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpregs.h
Hi Nicolin,
On 4/15/22 10:37 AM, Nicolin Chen wrote:
> Hi,
>
> Thanks for the work!
>
> On Thu, Apr 14, 2022 at 03:46:52AM -0700, Yi Liu wrote:
>
>> - More tests
> I did a quick test on my ARM64 platform, using "iommu=smmuv3"
> string. The behaviors are different between using default and
>
I've CCed all the people from previous threads.
> [...]
> +static bool applesmc_read_osk(uint8_t *osk)
> +{
> +#if defined(__APPLE__) && defined(__MACH__)
> +struct AppleSMCParams {
> +uint32_t key;
> +uint8_t __pad0[16];
> +uint8_t result;
> +uint8_t
On 4/16/22 23:02, Tomoaki Kawada wrote:
`cpu_pc` at this point does not necessary point to the current
instruction (i.e., the wait instruction being translated), so it's
incorrect to calculate the new value of `cpu_pc` based on this. It must
be updated with `ctx->base.pc_next`, which contains
With this, we don't need movcond to determine
which stack pointer is current.
Signed-off-by: Richard Henderson
---
target/rx/cpu.h | 1 +
target/rx/translate.c | 42 +++---
2 files changed, 24 insertions(+), 19 deletions(-)
diff --git
We properly perform this swap in helper_set_psw for MVTC,
but we missed doing so for the CLRPSW/SETPSW of the U bit.
Reported-by: Tomoaki Kawada
Signed-off-by: Richard Henderson
---
target/rx/translate.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
For aa32, the function has a parameter to use the new el.
For aa64, that never happens.
Use tcg_constant_i32 while we're at it.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 21 +---
target/arm/translate.c | 40 +++---
2
Bool is a more appropriate type for this value.
Move the member down in the struct to keep the
bool type members together and remove a hole.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 2 +-
target/arm/translate-a64.c | 2 +-
2 files changed, 2 insertions(+), 2
Instead of computing
tmp1 = shift & 0xff;
dest = (tmp1 > 0x1f ? 0 : value) << (tmp1 & 0x1f)
use
tmpd = value << (shift & 0x1f);
dest = shift & 0xe ? 0 : tmpd;
which has a flatter dependency tree.
Use tcg_constant_i32 while we're at it.
Signed-off-by: Richard Henderson
---
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE. The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.
Reviewed-by: Peter Maydell
Signed-off-by: Richard
Similar to tcg_const_ptr, defer to tcg_constant_{i32,i64}.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 73869fd9d0..cd6eaae410 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@
Currently we assume all fields are 32-bit.
Prepare for fields of a single byte, using sizeof.
Signed-off-by: Richard Henderson
---
target/arm/translate-a32.h | 13 +
target/arm/translate.c | 21 -
2 files changed, 25 insertions(+), 9 deletions(-)
diff --git
Supercedes: 20220412003326.588530-1-richard.hender...@linaro.org
("target/arm: 8 new features, A76 and N1")
Changes for v3:
* More field updates for H.a. This is not nearly complete, but what
I've encountered so far as I've begun implementing SME.
* Use bool instead of uint32_t for
The length of the previous insn may be computed from
the difference of start and end addresses.
Use tcg_constant_i32 while we're at it.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git
Common code for reset_btype and set_btype.
Use tcg_constant_i32.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
Instead of defining ARM_CP_FLAG_MASK to remove flags,
define ARM_CP_SPECIAL_MASK to isolate special cases.
Sort the specials to the low bits. Use an enum.
Make ARM_CP_CONST a special case, and ARM_CP_NOP an alias.
Split the large comment block so as to document each
value separately.
Move ARMCPRegInfo and all related declarations to a new
internal header, out of the public cpu.h.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h| 413 +
target/arm/cpu.h | 368 -
hw/arm/pxa2xx.c
Use tcg_constant_{i32,i64} as appropriate throughout.
Signed-off-by: Richard Henderson
---
target/arm/translate-vfp.c | 76 --
1 file changed, 23 insertions(+), 53 deletions(-)
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index
Hi Helge,
In general, the patch looks good but I want to make sure
that we will not break other compilation environments.
What version of MSYS2 do you use?
In my case, I can compile GA without this patch.
Best Regards,
Konstantin Kostiuk.
On Sun, Apr 17, 2022 at 5:50 PM Helge Konetzka
On 4/15/22 20:20, Tomoaki Kawada wrote:
The control register field PSW.U determines which stack pointer register
(ISP or USP) is mapped as R0. In QEMU, this is implemented by having a
value copied between ISP or USP and R0 whenever PSW.U is updated or
access to ISP/USP is made by an mvtc/mvic
On 4/16/22 21:59, Tomoaki Kawada wrote:
This patch fixes the implementation of the wait instruction to
implicitly update PSW.I as required by the ISA specification.
Signed-off-by: Tomoaki Kawada
---
target/rx/op_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On Donnerstag, 14. April 2022 19:25:04 CEST Shi, Guohuai wrote:
> > -Original Message-
> > From: Christian Schoenebeck
> > Sent: 2022年4月14日 19:24
> > To: qemu-devel@nongnu.org; Shi, Guohuai
> > Cc: Bin Meng ; Greg Kurz
> > Subject: Re: [RFC PATCH 0/4] 9pfs: Add 9pfs support for Windows
Hi Konstantin,
sorry not being clear about QEMU versions.
On building the RCs of QEMU 7.0.0:
qemu-ga.exe is produced
qga-vss.dll is produced
qga-vss.tlb is not created
In RCs of QEMU 7.0.0 qga-vss.tlb is no part of the tarball anymore.
The git history of qga/vss-win32/meson.build suggests
Update SCR_EL3 fields per ARM DDI0487 H.a.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 12
1 file changed, 12 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9a29a4a215..f843c62c83 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1544,6
Bool is a more appropriate type for this value.
Adjust the assignments to use true/false.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 2 +-
target/arm/cpu.c| 2 +-
target/arm/helper-a64.c | 4 ++--
target/arm/helper.c | 2 +-
target/arm/hvf/hvf.c| 2 +-
5
Bool is a more appropriate type for this value.
Adjust the assignments to use true/false.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 +-
linux-user/arm/cpu_loop.c | 2 +-
target/arm/cpu.c | 2 +-
target/arm/m_helper.c | 6 +++---
4 files changed, 6
Update isar fields per ARM DDI0487 H.a.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Add ID_AA64DFR0.HPMN0
---
target/arm/cpu.h | 24
1 file changed, 24 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 23879de5fa..9a29a4a215
Use tcg_constant_{i32,i64} as appropriate throughout.
Signed-off-by: Richard Henderson
---
target/arm/translate-m-nocp.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
index d9e144e8eb..27363a7b4e
Remove a possible source of error by removing REGINFO_SENTINEL
and using ARRAY_SIZE (convinently hidden inside a macro) to
find the end of the set of regs being registered or modified.
The space saved by not having the extra array element reduces
the executable's .data.rel.ro section by about 9k.
Use tcg_constant_{i32,i64,ptr} as appropriate throughout, which
means we get to remove lots of tcg_temp_free_*. Drop variables
in many cases, passing the constant directly to another function.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 250
Use tcg_gen_umin_i32 instead of tcg_gen_movcond_i32.
Use tcg_constant_i32 while we're at it.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Update SCTLR_ELx fields per ARM DDI0487 H.a.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f843c62c83..9ae9c935a2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1232,6
Cast the uint32_t key into a gpointer directly, which
allows us to avoid allocating storage for each key.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 4 ++--
target/arm/gdbstub.c | 2 +-
target/arm/helper.c | 45
3 files changed,
These particular data structures are not modified at runtime.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d6c34c7826..94b41c7e88 100644
---
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 55 ++---
1 file changed, 17 insertions(+), 38
Use tcg_constant_{i32,i64} as appropriate throughout.
Signed-off-by: Richard Henderson
---
target/arm/translate-neon.c | 21 +++--
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index
Have one check in move_to_cr instead of one in each
function that calls move_to_cr.
Signed-off-by: Richard Henderson
---
target/rx/translate.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index
This is a follow up to Kawada-san's patch for the problem
of a missed update to the stack pointer in CLRPSW/SETPSW.
This fixes the problem without movcond by tracking the
current state of PSW.U within the TB.
r~
Richard Henderson (4):
target/rx: Put tb_flags into DisasContext
target/rx:
Copy tb->flags into ctx->tb_flags; we'll want to modify
this value throughout the tb in future.
Signed-off-by: Richard Henderson
---
target/rx/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index
Bool is a more appropriate type for this value.
Move the member down in the struct to keep the
bool type members together and remove a hole.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 2 +-
target/arm/translate-a64.c | 2 +-
target/arm/translate.c | 2 +-
3 files
The new_key is always non-zero during redirection,
so remove the if. Update opc0 et al from the new key.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 35 +++
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/target/arm/helper.c
Use tcg_constant_{i32,i64} as appropriate throughout.
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 198 +
1 file changed, 68 insertions(+), 130 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index
Enable the n1 for virt and sbsa board use.
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 66
4 files changed, 69 insertions(+)
diff
Per the recommendations in qapi/error.h, return false on failure.
Use the return value in the monitor, the only place we aren't
already passing error_fatal or error_abort.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/log.h | 2 +-
monitor/misc.c | 3 +--
This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
2
This is redundant with the logging done in cpu_common_reset.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/nios2/cpu.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index
Do not reference qemu_logfile directly;
use the predicate provided by qemu/log.h.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
os-posix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/os-posix.c b/os-posix.c
index
Use the qemu_fdt_setprop_reg64() to replace the code
that sets the property manually.
Signed-off-by: Ben Dooks
---
hw/riscv/sifive_u.c | 41 +++--
1 file changed, 11 insertions(+), 30 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index
On 4/15/22 02:40, Xiaojuan Yang wrote:
+++ b/configs/devices/loongarch64-softmmu/default.mak
@@ -0,0 +1,3 @@
+# Default configuration for loongarch64-softmmu
+
+CONFIG_LOONGARCH_VIRT=y
Again, you can't add this file until you're ready to build.
We do get farther that patch 30, ending in
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Rely on EL3-no-EL2 squashing during registration.
---
target/arm/helper.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git
Use a single memory allocation for name and reginfo.
Perform the override check early; use assert not printf+abort.
Use a switch statement to validate state.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c| 16 +
target/arm/helper.c | 154
Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.
This will shortly be used from cpu_tcg.c also.
Signed-off-by: Richard Henderson
---
v2: New patch.
---
target/arm/internals.h | 6
Create a typedef as well, and use it in ARMCPRegInfo.
This won't be perfect for debugging, but it'll nicely
display the most common cases.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h | 44 +++-
target/arm/helper.c | 5 ++---
2 files changed,
This extension concerns cache speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
This extension concerns branch speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.
Signed-off-by: Richard Henderson
---
v2: Honor EAE for reporting VSERR to aa32.
---
target/arm/cpu.h | 2 ++
target/arm/internals.h | 8
target/arm/syndrome.h
Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 96
We have already looked up and locked the filepointer.
Use fprintf instead of qemu_log directly for output
in and around tcg_dump_ops.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 109 ++
1 file changed, 52
Most of the changes here reduce the amount of locking involved
in logging, due to repeated qemu_log calls, each of which takes
and releases the rcu_read_lock.
This makes more use of qemu_log_lock/unlock around code blocks,
which both keeps the output together in the face of threads and
also plays
The only user of this feature, tcg_dump_ops, has been
converted to use fprintf directly.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/log-for-trace.h | 2 +-
util/log.c | 13 ++---
2 files changed, 3 insertions(+), 12 deletions(-)
diff
Now that all uses have been updated, consider a missing
test of the result of qemu_log_trylock a bug and Werror.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/log.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/qemu/log.h
Rename to emphasize this is the file-scope global variable.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
util/log.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/util/log.c b/util/log.c
index
Perform all logfile setup in one step.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
linux-user/main.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index d263b2a669..0297ae8321 100644
---
Rename to emphasize this is the file-scope global variable.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
util/log.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/util/log.c b/util/log.c
index
When the CPU-to-NUMA association isn't provided by user, the default NUMA
node ID for the specific CPU is returned from virt_get_default_cpu_node_id().
Unfortunately, the default NUMA node ID breaks socket boundary and leads to
the broken CPU topology warning message in Linux guest. This series
This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
CPU with its NUMA node.
*
Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
is handled in define_one_arm_cp_reg_with_opaque.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h | 7 ---
target/arm/helper.c | 3 ++-
2 files changed,
Check for and defer any pending virtual SError.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Retain m-profile check; improve comments.
---
target/arm/helper.h| 1 +
target/arm/a32.decode | 16 --
target/arm/t32.decode | 18
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo,
and the local vpidr_regs definition, and rely on the
squasing to ARM_CP_CONST while registering.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 158
1 file changed, 13 insertions(+),
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm/cpu_tcg.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/docs/system/arm/emulation.rst
Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 2 +
target/arm/cpu64.c | 50 +-
target/arm/cpu_tcg.c | 114
Enable the a76 for virt and sbsa board use.
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 66
4 files changed, 69 insertions(+)
diff
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/log.h | 28 +++-
util/log.c | 23 +++
2 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/include/qemu/log.h
This buffering was introduced during the Paleozoic: 9fa3e853531.
There has never been an explanation as to why we may not allow
glibc to allocate the file buffer itself. We certainly have
many other uses of mmap and malloc during user-only startup,
so presumably whatever the issue was, it has
We have extra stuff to log at the same time.
Hoist the qemu_log_trylock/unlock to the caller and use fprintf.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
bsd-user/main.c | 35 ++-
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git
All uses flush output immediately before or after qemu_log_unlock.
Instead of a separate call, move the flush into qemu_log_unlock.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/log.h| 2 --
accel/tcg/translate-all.c |
Use qemu_log_lock/unlock instead of the raw rcu_read.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tests/unit/test-logging.c | 33 +++--
1 file changed, 15 insertions(+), 18 deletions(-)
diff --git a/tests/unit/test-logging.c
Add a helper to set a property from a set of strings
to reduce the following code:
static const char * const clint_compat[2] = {
"sifive,clint0", "riscv,clint0"
};
qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
(char **)_compat, ARRAY_SIZE(clint_compat));
Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify
the code.
Signed-off-by; Ben Dooks
---
hw/riscv/sifive_u.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 1fe364cbb0..b00086d86e 100644
---
Add a macro qemu_fdt_setprop_reg64() to set the given
node's reg property directly from the memory map entry
to avoid open coding of the following:
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_DEV_OTP].base,
0x0, memmap[SIFIVE_U_DEV_OTP].size);
I've been doing a bit of looking at riscv and dt creation, and
was thinking the following two helper functions would be useful
so implemented qemu_fdt_setprop_reg64() and qemu_fdt_setprop_strings()
and then applied them to the hw/riscv/sifive_u.c machine.
I thought I should get a review in before
On 4/15/22 02:40, Xiaojuan Yang wrote:
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 75 +
hw/intc/meson.build
On 4/15/22 02:40, Xiaojuan Yang wrote:
+memory_region_init(>mmio[cpu], OBJECT(s),
+ "loongarch_extioi", EXTIOI_SIZE);
+
+memory_region_init_io(>mmio_nodetype[cpu], OBJECT(s),
+ _nodetype_ops, s,
+
More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
squash to ARM_CP_CONST.
This will simplify cpreg registration for conditional arm features.
Signed-off-by:
Add the aa64 predicate for detecting RAS support from id registers.
We already have the aa32 version from the M-profile work.
Add the 'any' predicate for testing both aa64 and aa32.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
1 file
This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU. Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.
Reviewed-by: Peter Maydell
Signed-off-by:
We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 4
1 file changed, 4 insertions(+)
diff
This code appears to be trying to make sure there is a logfile.
But that's already true -- the logfile will either be set by -D,
or will be stderr. In either case, not appropriate here.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/hexagon/translate.c | 6 --
1 file
This function is no longer used.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/log.h | 15 ---
1 file changed, 15 deletions(-)
diff --git a/include/qemu/log.h b/include/qemu/log.h
index d090faf22a..2d9455dc85 100644
--- a/include/qemu/log.h
+++
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.
This reworks build_pptt() to avoid by reusing the existing one in
ms->possible_cpus. Currently, the only user of
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.
This takes account of SMP configuration when the CPU topology
is populated. The
Rearrange the values of the enumerators of CPAccessResult
so that we may directly extract the target el. For the two
special cases in access_check_cp_reg, use CPAccessResult.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h| 26
target/arm/op_helper.c | 56
Add only the system registers required to implement zero error
records. This means we need to save state for ERRSELR, but all
values are out of range, so none of the indexed error record
registers need be implemented.
Add the EL2 registers required for injecting virtual SError.
Signed-off-by:
There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.
Signed-off-by: Richard Henderson
---
v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy
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