Hi, Jason,
Mostly good to me, just a few nitpicks below.
On Mon, Mar 21, 2022 at 01:54:27PM +0800, Jason Wang wrote:
> We introduce VTDBus structure as an intermediate step for searching
> the address space. This works well with SID based matching/lookup. But
> when we want to support SID plus
On Fri, Apr 22, 2022 at 8:48 AM Alistair Francis
wrote:
> On Thu, Apr 21, 2022 at 12:17 PM Bin Meng wrote:
> >
> > On Wed, Apr 20, 2022 at 5:57 PM wrote:
> > >
> > > From: Frank Chang
> > >
> > > Allow user to set core's marchid, mvendorid, mipid CSRs through
> > > -cpu command line option.
>
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Create a platform bus to allow dynamic devices to be connected. This is
> based on the ARM implementation.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Edgar E. Iglesias
> ---
>
Now that dino_init() is completely decoupled from dino.c it can be moved to
machine.c with the rest of the board configuration.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/dino.c | 14 --
hw/hppa/hppa_sys.h | 2 --
hw/hppa/machine.c | 12
3 files changed, 12
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 3 ++-
hw/hppa/lasi.c | 4 ++--
hw/hppa/machine.c | 3 ++-
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h
index 0929dedded..3832b787d1 100644
--- a/hw/hppa/hppa_sys.h
+++
This is in preparation for using more qdev APIs during the configuration of the
HPPA generic machine.
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/dino.c | 8 +++-
hw/hppa/hppa_sys.h | 3 ++-
hw/hppa/machine.c | 6 --
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git
Signed-off-by: Mark Cave-Ayland
---
hw/hppa/hppa_sys.h | 3 ---
hw/hppa/lasi.h | 4
hw/hppa/machine.c | 2 ++
hw/hppa/pci.c | 3 +++
4 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h
index f7a127be19..9964d4a7a7 100644
---
Replace tcg_const_* for numeric literals with tcg_constant_*.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index
On 4/21/22 14:39, Max Filippov wrote:
Exception number, exception cause and debug cause codes are small
numbers, use tcg_contant_* for them.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
Reviewed-by: Richard
On 4/21/22 14:39, Max Filippov wrote:
dtlb is a boolean flag, use tcg_constant_* for it.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson
r~
On Wed, Mar 30, 2022 at 04:36:36PM +0800, Jason Wang wrote:
> > If not, do we want to apply this version scheme only when it
> > reaches the production quality or also in the experimental phase?
>
> Yes. E.g if we think scalable mode is mature, we can enable 3.0.
Sorry to come back to the
From: Weiwei Li
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share
the same helper
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20220325085902.29500-2-liwei...@iscas.ac.cn>
Signed-off-by: Alistair
On Thu, Apr 21, 2022 at 3:58 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
> tried to avoid adding *NULL* bootargs to device tree, but unfortunately
> the changes were entirely useless, due to MachineState::kernel_cmdline
> can't
From: Bin Meng
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-2-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
From: Jim Shu
This commit implements reset function of all ACLINT devices.
ACLINT device reset will clear MTIME and MSIP register to 0.
Depend on RISC-V ACLINT spec v1.0-rc4:
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
On Mon, Apr 18, 2022 at 5:13 AM Ben Dooks wrote:
>
> Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify
> the code.
>
> Signed-off-by; Ben Dooks
; should be replaced to :
Not sure how you did that, but you can do with "git commit -s" and git
will take care of the SoB tag.
> ---
>
+Richard
On Wed, Apr 20, 2022 at 4:16 PM Bin Meng wrote:
>
> On Tue, Apr 12, 2022 at 9:11 AM Bin Meng wrote:
> >
> > On Thu, Mar 24, 2022 at 9:48 PM Bin Meng wrote:
> > >
> > > From: Bin Meng
> > >
> > > Sync uboot_image.h from upstream U-Boot v2022.01 release [1].
> > >
> > > [1]
This add two addition test cases for accumulative mode under sg enabled.
The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
The padding length depends on algorithm, i.e. SHA512 (1024 bit),
SHA256 (512 bit).
The result was calculated by command line sha512sum/sha256sum
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Add support for plugging in devices, this was tested with the TPM
> device.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Edgar E. Iglesias
> ---
> hw/riscv/virt.c | 35
From: Frank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
Jag Raman writes:
>> On Apr 21, 2022, at 10:55 AM, Markus Armbruster wrote:
>>
>> Jagannathan Raman writes:
>>
>>> Add blocker to prevent hot-unplug of devices
>>
>> Why do you need this? I'm not doubting you do, I just want to read your
>> reasons here :)
>
> Hi Markus, :)
>
> The
On 2022/04/22 0:07, Christian Schoenebeck wrote:
mknod() on macOS does not support creating sockets, so divert to
call sequence socket(), bind() and chmod() respectively if S_IFSOCK
was passed with mode argument.
Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/
On Fri, Apr 22, 2022 at 10:53 AM Bin Meng wrote:
>
> On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer
> wrote:
> >
> > Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> > case, walk_pte will erroneously merge them.
> >
> > Enforce the split up, by tracking the virtual base
Jag Raman writes:
>> On Apr 21, 2022, at 10:59 AM, Markus Armbruster wrote:
>>
>> Jagannathan Raman writes:
>>
>>> Setup a handler to run vfio-user context. The context is driven by
>>> messages to the file descriptor associated with it - get the fd for
>>> the context and hook up the
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Imply the TPM sysbus devices. This allows users to add TPM devices to
> the RISC-V virt board.
>
> This was tested by first creating an emulated TPM device:
>
> swtpm socket --tpm2 -t -d --tpmstate
Support HACE28: Hash HMAC Key Buffer Base Address Register.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_hace.c | 7 +++
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/misc/aspeed_hace.c
This patch series implements ast2600 hace engine with accumulative mode
and unit test against to it.
Verified with following models
- AST2600 with OpenBmc VERSION_ID=2.12.0-dev-660-g4c7b3e692-dirty
- check hash verification in uboot and check whether qemu crashed
during openbmc web gui
On Tue, Mar 8, 2022 at 10:28 PM Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 10:15:49PM +0530, Ani Sinha wrote:
> >
> > Change log:
> > v2: rebased the patchset. Laine's response is appended at the end.
> >
> > I am re-introducing the patchset for which got
> > reverted here few months
On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer
wrote:
>
> Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> case, walk_pte will erroneously merge them.
>
> Enforce the split up, by tracking the virtual base address.
>
> Let's say we have the mapping:
> 0x8120 -> 0x89623000
On 4/21/22 11:40, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
The following changes since commit 28298069afff3eb696e4995e63b2579b27adf378:
Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into
staging (2022-04-21 09:27:54 -0700)
are available in
The aspeed ast2600 accumulative mode is described in datasheet
ast2600v10.pdf section 25.6.4:
1. Allocating and initiating accumulative hash digest write buffer
with initial state.
* Since QEMU crypto/hash api doesn't provide the API to set initial
state of hash library, and the
Coverity issues several UNINIT warnings against amd_iommu.c [1]. This
patch fixes them by clearing evt before encoding. On top of it, this
patch changes the event log size to 16 bytes per IOMMU specification,
and fixes the event log entry format in amdvi_encode_event().
[1] CID
I think the part adding POWERPC_EXCP_SEMIHOST should be proposed in
a separate patch.
Ok, I can move it to a separate patch. That would be all changes in
target/ppc/cpu.h and target/ppc/excp_helper.c, right?
yes.
Thanks,
C.
On 4/21/22 04:04, Nicholas Piggin wrote:
Excerpts from Leandro Lupori's message of April 21, 2022 4:09 am:
On 4/18/22 17:22, Cédric Le Goater wrote:
On 4/18/22 21:10, Leandro Lupori wrote:
Add semihosting support for PPC64. This implementation is
based on the standard for ARM semihosting
/pull-riscv-to-apply-20220421
for you to fetch changes up to e63e7b6cca93242a4d037610caba5626c980b990:
hw/riscv: boot: Support 64bit fdt address. (2022-04-21 16:29:57 +1000)
First RISC-V PR for QEMU 7.1
* Add support for Ibex SPI
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-Id: <20220317061817.3856850-2-alistair.fran...@opensource.wdc.com>
---
target/riscv/cpu.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff
From: Weiwei Li
The spec for vmvr.v says: 'the instructions operate as if EEW=SEW,
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte for vstart != 0 should take sew into account
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Message-Id:
From: Weiwei Li
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share
the same helper
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20220325085902.29500-2-liwei...@iscas.ac.cn>
Signed-off-by: Alistair
From: Dylan Jhong
The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram
address within 3GB,
but not all platforms have dram_base within 3GB.
This patch adds an exception for dram base not within 3GB,
which will place fdt at dram_end align 16MB.
riscv_setup_rom_reset_vec()
From: Ralf Ramsauer
The -bios option is silently ignored if used in combination with -enable-kvm.
The reason is that the machine starts in S-Mode, and the bios typically runs in
M-Mode.
Better exit in that case to not confuse the user.
Signed-off-by: Ralf Ramsauer
Reviewed-by: Alistair
On Tue, 19 Apr 2022 13:41:15 +0200
Christian Schoenebeck wrote:
> The 'rdev' field in 9p reponse 'Rgetattr' is of type dev_t,
> which is actually a system dependant type and therefore both the
> size and encoding of dev_t differ between macOS and Linux.
>
> So far we have sent 'rdev' to guest
There are cases that malicious virtual machine can cause CPU stuck (due
to event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event window means no event (NMI, SMI and
IRQ) can be delivered. It leads the CPU to be unavailable to host or
other VMs.
By default quirk_mode_page_apple should be enabled for all scsi-hd devices
connected to the q800 machine to enable MacOS to detect and use them.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index
From: Bin Meng
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-7-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
include/hw/core/tcg-cpu-ops.h | 1 +
1
One of the mechanisms MacOS uses to identify drives compatible with MacOS is to
send a custom MODE SELECT command for page 0x30 to the drive. The response to
this is a hard-coded manufacturer string which must match in order for the
drive to be usable within MacOS.
Add an implementation of the
This linux-header update is only a reference to include some definitions
related to notify VM exit.
Signed-off-by: Chenyi Qiang
---
linux-headers/asm-x86/kvm.h | 4 +++-
linux-headers/linux/kvm.h | 10 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git
On Thu, Mar 17, 2022 at 8:25 AM Tomasz Jeznach wrote:
>
> The patch introduces baseline implementation of a draft proposal
> of RISC-V IOMMU specification as discussed in the RISC-V Forum [1] [2].
>
> The implementation follows a draft version of the specification published
> at [3] including all
On 4/21/22 05:07, Alexey Kardashevskiy wrote:
On 14/04/2022 22:41, Cédric Le Goater wrote:
After re-reading what I just wrote, I am leaning towards disabling use of
KVM_CAP_IRQFD_RESAMPLE as it seems last worked on POWER8 and never since :)
Did I miss something in the picture (hey
From: Atish Patra
Add the definition for ratified privileged specification version v1.12
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220303185440.512391-3-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
1 file changed, 1
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible
From: Bin Meng
This adds initial support for the Sdtrig extension via the Trigger
Module, as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2
From: Bin Meng
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-2-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
From: Atish Patra
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.
This commit enforces the privilege version for csrs introduced in
v1.12 or after.
From: Bin Meng
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-4-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 4
The Apple HD SC Setup program uses a SCSI INQUIRY command to check that any SCSI
hard disks detected match a whitelist of vendors and products before allowing
the "Initialise" button to prepare an empty disk.
Add known-good default vendor and product information using the existing
compat_prop
From: Tsukasa OI
Some bits in RISC-V `misa' CSR should not be reflected in the ISA
string. For instance, `S' and `U' (represents existence of supervisor
and user mode, respectively) in `misa' CSR must not be copied since
neither `S' nor `U' are valid single-letter extensions.
This commit also
Here are the next set of patches from my ongoing work to allow the q800
machine to boot MacOS related to SCSI devices.
The first patch implements a dummy FORMAT UNIT command which is used by
the Apple HD SC Setup program when preparing an empty disk to install
MacOS.
Patches 2 adds a new quirks
From: Atish Patra
The Linux kernel parses the ISA extensions from "riscv,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.
Generate the
From: Frank Chang
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory
Since the MacOS SCSI implementation is quite old (and Apple added some firmware
customisations to their drives for m68k Macs) there is need to add a mechanism
to correctly handle Apple-specific quirks.
Add a new quirks bitmap to SCSIDiskState that can be used to enable these
features as required.
Notify VM exit is introduced to mitigate the potential DOS attach from
malicious VM. This series is the userspace part to enable this feature
through a new KVM capability KVM_CAP_X86_NOTIFY_VMEXIT. The detailed
info can be seen in Patch 3.
The corresponding KVM patches are avaiable at:
Hello Steven,
+static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
+ bool acc_mode)
{
struct iovec iov[ASPEED_HACE_MAX_SG];
g_autofree uint8_t *digest_buf;
size_t digest_len = 0;
+int niov = 0;
int i;
+
Dov Murik writes:
> Commit 811b4ec7f8eb ("qapi, target/i386/sev: Add cpu0-id to
> query-sev-capabilities") wrongly stated that the new field is available
> since version 7.0.
>
> Fix the QAPI documentation to state that the cpu0-id field is included
> since 7.1.
>
> Signed-off-by: Dov Murik
>
+ Philippe's another email address as the redhat one is unreachable
On Thu, Apr 21, 2022 at 1:56 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
> tried to avoid adding *NULL* bootargs to device tree, but unfortunately
> the
From: Atish Patra
Currently, the privileged specification version are defined in
a complex manner for no benefit.
Simplify it by changing it to a simple enum based on.
Suggested-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id:
From: Atish Patra
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and
From: Atish Patra
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id:
Hello,
On 3/18/22 14:28, Cédric Le Goater wrote:
Hello Philippe,
I am restarting the discussion we started in :
http://patchwork.ozlabs.org/project/qemu-devel/list/?series=250563
This series adds an extension for a new eMMC device using the
framework you put in place. It's not perfect but
The MacOS CDROM driver uses a SCSI INQUIRY command to check that any SCSI CDROMs
detected match a whitelist of vendors and products before adding them to the
list of available devices.
Add known-good default vendor and product information using the existing
compat_prop mechanism so the user
From: Alistair Francis
The RISC-V specification states that:
"Supervisor-level external interrupts are made pending based on the
logical-OR of the software-writable SEIP bit and the signal from the
external interrupt controller."
We currently only allow either the interrupt controller or
From: Atish Patra
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time
From: Richard Henderson
The riscv_raise_exception function stores its argument into
exception_index and then exits to the main loop. When we
have already set exception_index, we can just exit directly.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id:
From: Nicolas Pitre
There is an overflow with the current code where a pmpaddr value of
0x1fff is decoded as sa=0 and ea=0 whereas it should be sa=0 and
ea=0x.
Fix that by simplifying the computation. There is in fact no need for
ctz64() nor special case for -1 to achieve proper
When initialising a drive ready to install MacOS, Apple HD SC Setup first
attempts
to format the drive. Add a simple FORMAT UNIT command which simply returns
success
to allow the format to succeed.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/scsi-disk.c | 4
hw/scsi/trace-events | 1 +
From: Jim Shu
This commit implements reset function of all ACLINT devices.
ACLINT device reset will clear MTIME and MSIP register to 0.
Depend on RISC-V ACLINT spec v1.0-rc4:
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
From: Bin Meng
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-3-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
On Thu, Mar 17, 2022 at 8:23 AM Tomasz Jeznach wrote:
>
> This is the series of patches to introduce RISC-V IOMMU emulation in QEMU.
>
> The Rivos IOMMU device implementation is based on a draft proposal of a
> RISC-V I/O Management Unit (IOMMU) [1] as published on 2022/03/10, shared and
>
On 4/21/22 03:17, Bin Meng wrote:
From: Bin Meng
Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug
Event" and chapter 8.4.5 "Instruction Complete Debug Event":
"A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT]
are set ... Branch taken debug events are
From: Wilfred Mallawa
Adds the SPI_HOST device model for ibex. The device specification is as per
[1]. The model has been tested on opentitan with spi_host unit tests
written for TockOS.
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair
From: Wilfred Mallawa
Connect spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220303045426.511588-2-alistair.fran...@opensource.wdc.com>
Signed-off-by: Alistair Francis
---
From: Niklas Cassel
The device tree property "mmu-type" is currently exported as either
"riscv,sv32" or "riscv,sv48".
However, the riscv cpu device tree binding [1] has a specific value
"riscv,none" for a HART without a MMU.
Set the device tree property "mmu-type" to "riscv,none" when the CPU
From: Bin Meng
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-5-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/machine.c | 32
1 file
From: Weiwei Li
for some cases, scale is always equal or less than 0, since lmul is not larger
than 3
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20220325085902.29500-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair
From: Bin Meng
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-6-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
For the direct triple faults, i.e. hardware detected and KVM morphed
to VM-Exit, KVM will never lose them. But for triple faults sythesized
by KVM, e.g. the RSM path, if KVM exits to userspace before the request
is serviced, userspace could migrate the VM and lose the triple fault.
A new flag
On Wed, Apr 20, 2022 at 21:16:15, Klaus Jensen wrote:
> Discussed this with the TP authors and, no, reftag should not be
> re-computed for PRACT 0, regardless of the PI type.
Ok, should i resend patch with only adding nvme_dif_mangle_mdata in
the read part?
On Mon, 11 Apr 2022 at 17:58, Hao Wu wrote:
>
> Currently, the PWRON STRAP values in NPCM7XX boards are magic
> numbers. Similar to the aspeed ones in hw/arm/aspeed.c, we
> define bit fields constants for them and use these fields instead
> of the magic numbers in the current implementation. The
Current implementation have problem in the read part of copy command.
Because there is no metadata mangling before nvme_dif_check invocation,
reftag error could be thrown for blocks of namespace that have not been
previously written to.
Signed-off-by: Dmitry Tikhov
---
v2:
* remove
On Tue, 5 Apr 2022 at 23:38, Hao Wu wrote:
>
> This allows different FIUs to have different flash sizes, useful
> in NPCM8XX which has multiple different sized FIU modules.
>
> Signed-off-by: Hao Wu
> Reviewed-by: Patrick Venture
> ---
> hw/arm/npcm7xx.c | 6 ++
>
On Donnerstag, 21. April 2022 12:48:35 CEST Greg Kurz wrote:
> On Tue, 19 Apr 2022 13:41:59 +0200
>
> Christian Schoenebeck wrote:
> > Linux and macOS only share some errno definitions with equal macro
> > name and value. In fact most mappings for errno are completely
> > different on the two
On Tue, 5 Apr 2022 at 23:38, Hao Wu wrote:
>
> The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
> PHY. This implementation contains all the default registers and
> the soft reset feature that are required to load the Linux kernel
> driver. Further features have not been
From: "Edgar E. Iglesias"
Add a model of the Xilinx Versal CRL.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Frederic Konrad
Reviewed-by: Francisco Iglesias
Message-id: 20220406174303.2022038-4-edgar.igles...@xilinx.com
Signed-off-by: Peter Maydell
---
include/hw/misc/xlnx-versal-crl.h |
9c125d17e9402c232c46610802e5931b3639d77b:
Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging
(2022-04-20 16:43:11 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220421
for you to fetch changes up
From: "Edgar E. Iglesias"
Connect the 4 TTC timers on the ZynqMP.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Reviewed-by: Francisco Iglesias
Message-id: 20220331222017.2914409-3-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
The Exynos4210 SoC device currently uses a custom device
"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
line. We have a standard TYPE_OR_IRQ device for this now, so use
that instead.
(This is a migration compatibility break, but that is OK for this
machine type.)
From: "Edgar E. Iglesias"
Create an APU CPU Cluster. This is in preparation to add the RPU.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
Message-id: 20220406174303.2022038-2-edgar.igles...@xilinx.com
Signed-off-by: Peter Maydell
---
include/hw/arm/xlnx-versal.h | 2 ++
The exynos4210 SoC mostly creates its child devices as if it were
board code. This includes the a9mpcore object. Switch that to a
new-style "embedded in the state struct" creation, because in the
next commit we're going to want to refer to the object again further
down in the
The only time we use the ext_gic_irq[] array in the Exynos4210Irq
struct is during realize of the SoC -- we initialize it with the
input IRQs of the external GIC device, and then connect those to
outputs of other devices further on in realize (including in the
exynos4210_init_board_irqs()
The only time we use the int_gic_irq[] array in the Exynos4210Irq
struct is in the exynos4210_realize() function: we initialize it with
the GPIO inputs of the a9mpcore device, and then a bit later on we
connect those to the outputs of the internal combiner. Now that the
a9mpcore object is easily
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