From: Łukasz Gieryk
With four new properties:
- sriov_v{i,q}_flexible,
- sriov_max_v{i,q}_per_vf,
one can configure the number of available flexible resources, as well as
the limits. The primary and secondary controller capability structures
are initialized accordingly.
Since the number of
From: Łukasz Gieryk
An NVMe device with SR-IOV capability calculates the BAR size
differently for PF and VF, so it makes sense to extract the common code
to a separate function.
Signed-off-by: Łukasz Gieryk
Reviewed-by: Klaus Jensen
Acked-by: Michael S. Tsirkin
---
hw/nvme/ctrl.c | 45
From: Łukasz Gieryk
This patch updates the initialization place for the AER queue, so it’s
initialized once, at controller initialization, and not every time
controller is enabled.
While the original version works for a non-SR-IOV device, as it’s hard
to interact with the controller if it’s not
From: Łukasz Gieryk
The n->reg_size parameter unnecessarily splits the BAR0 size calculation
in two phases; removed to simplify the code.
With all the calculations done in one place, it seems the pow2ceil,
applied originally to reg_size, is unnecessary. The rounding should
happen as the last
Introduce handling for Secondary Controller List (Identify command with
CNS value of 15h).
Secondary controller ids are unique in the subsystem, hence they are
reserved by it upon initialization of the primary controller to the
number of sriov_max_vfs.
ID reservation requires the addition of an
From: Łukasz Gieryk
This patch implements the Function Level Reset, a feature currently not
implemented for the Nvme device, while listed as a mandatory ("shall")
in the 1.4 spec.
The implementation reuses FLR-related building blocks defined for the
pci-bridge module, and follows the same
From: Łukasz Gieryk
PCI device capable of SR-IOV support is a new, still-experimental
feature with only a single working example of the Nvme device.
This patch in an attempt to fix a double-free problem when a
SR-IOV-capable Nvme device is hot-unplugged in the following scenario:
Qemu CLI:
On Mon, May 9, 2022 at 10:13 PM Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> CMD19 (SEND_TUNING_BLOCK) and CMD23 (SET_BLOCK_COUNT) were
> added in the Physical SD spec v3.01. When earlier spec version
nits: it should be spec v3.00, despite the fact that in QEMU we have
Implementation of Primary Controller Capabilities data
structure (Identify command with CNS value of 14h).
Currently, the command returns only ID of a primary controller.
Handling of remaining fields are added in subsequent patches
implementing virtualization enhancements.
Signed-off-by: Lukasz
From: Łukasz Gieryk
The NVMe device defines two properties: max_ioqpairs, msix_qsize. Having
them as constants is problematic for SR-IOV support.
SR-IOV introduces virtual resources (queues, interrupts) that can be
assigned to PF and its dependent VFs. Each device, following a reset,
should
Hi, Alex
On 2022/4/27 上午12:35, Alex Williamson wrote:
On Tue, 26 Apr 2022 12:43:35 +
Shameerali Kolothum Thodi wrote:
-Original Message-
From: Eric Auger [mailto:eric.au...@redhat.com]
Sent: 26 April 2022 12:45
To: Shameerali Kolothum Thodi ; Yi
Liu ; alex.william...@redhat.com;
This patch implements initial support for Single Root I/O Virtualization
on an NVMe device.
Essentially, it allows to define the maximum number of virtual functions
supported by the NVMe controller via sriov_max_vfs parameter.
Passing a non-zero value to sriov_max_vfs triggers reporting of
From: Łukasz Gieryk
With the new command one can:
- assign flexible resources (queues, interrupts) to primary and
secondary controllers,
- toggle the online/offline state of given controller.
Signed-off-by: Łukasz Gieryk
Acked-by: Michael S. Tsirkin
Reviewed-by: Klaus Jensen
---
Changes since v7:
- Fixed description of hw/acpi: Make the PCI hot-plug aware of SR-IOV
- Added description to docs: Add documentation for SR-IOV and
Virtualization Enhancements
- Added Reviewed-by and Acked-by tags
- Rebased on master
Lukasz Maniak (4):
hw/nvme: Add support for SR-IOV
On 5/5/22 18:17, Bernhard Beschow wrote:
Commit 250263033c5343012b2cd6f01210ffb5b908a159 'isa: introduce wrapper
isa_connect_gpio_out' introduced it in 2016. Since then, its only user
remained mc146818rtc. Remove this one-off solution.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c
> On 14 February, 2022, at 19:55, Philippe Mathieu-Daudé via
> wrote:
>
> From: Cameron Esfahani
>
> Pass through RDPID and RDTSCP support in CPUID if host supports it.
> Correctly detect if CPU_BASED_TSC_OFFSET and CPU_BASED2_RDTSCP would
> be supported in primary and secondary
On 5/5/22 11:50, Peter Maydell wrote:
We have about 30 instances of the typo/variant spelling 'writeable',
and over 500 of the more common 'writable'. Standardize on the
latter.
Change produced with:
sed -i -e 's/\([Ww][Rr][Ii][Tt]\)[Ee]\([Aa][Bb][Ll][Ee]\)/\1\2/g' $(git grep
-il
Daniel P. Berrangé writes:
On Mon, Apr 25, 2022 at 01:53:28PM +0100, Alex Bennée wrote:
Stefan Hajnoczi writes:
[[PGP Signed Part:Undecided]]
Hi,
QEMU needs to enroll in GitLab for Open Source before July 1st to
receive 50,000 CI/CD pipeline minutes and GitLab Ultimate features:
* Peter Xu (pet...@redhat.com) wrote:
> On Fri, May 06, 2022 at 10:57:54PM -0300, Leonardo Bras wrote:
> > diff --git a/io/channel-socket.c b/io/channel-socket.c
> > index 05c425abb8..f03a068f25 100644
> > --- a/io/channel-socket.c
> > +++ b/io/channel-socket.c
> > @@ -25,9 +25,18 @@
> > #include
From: Philippe Mathieu-Daudé
CMD19 (SEND_TUNING_BLOCK) and CMD23 (SET_BLOCK_COUNT) were
added in the Physical SD spec v3.01. When earlier spec version
is requested, we should return ILLEGAL.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 4 ++--
1 file changed, 2 insertions(+), 2
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> This significantly expands the migration test suite to cover testing
> with TLS over TCP and UNIX sockets, with both PSK (pre shared keys)
> and x509 credentials, and for both single and multifd scenarios.
>
> It identified one bug in handling
Eric Auger writes:
> Up to now the virt-machine node contains a virtio-mmio node.
> However no driver produces any PCI interface node. Hence, PCI
> tests cannot be run with aarch64 binary.
>
> Add a GPEX driver node that produces a pci interface node. This latter
> then can be consumed by all
* Eric Blake (ebl...@redhat.com) wrote:
> On Tue, Apr 26, 2022 at 05:00:42PM +0100, Daniel P. Berrangé wrote:
> > This validates that we correctly handle migration success and failure
> > scenarios when using TLS with pre shared keys.
> >
> > Signed-off-by: Daniel P. Berrangé
> > ---
> >
On 5/9/22 13:53, Daniel P. Berrangé wrote:
Apart from this, I also identified the following functions that
can be called both in coroutine context and outside:
snip
- qio_channel_readv_full_all_eof
- qio_channel_writev_full_all
I'm trying to understand what criteria makes those two
>
> On 14 February, 2022, at 19:55, Philippe Mathieu-Daudé via
> wrote:
>
> From: Cameron Esfahani
>
> Pass through RDPID and RDTSCP support in CPUID if host supports it.
> Correctly detect if CPU_BASED_TSC_OFFSET and CPU_BASED2_RDTSCP would
> be supported in primary and secondary
On 9/5/22 15:18, Thomas Huth wrote:
On 09/05/2022 14.20, Philippe Mathieu-Daudé wrote:
On 12/4/22 18:58, Thomas Huth wrote:
Many of the disassemblers in the disas folder are based on old
versions from the GNU tools (libopcode, GDB, ...) that were still
licensed under the GPL v2. The GNU tools
On 09/05/2022 14.20, Philippe Mathieu-Daudé wrote:
On 12/4/22 18:58, Thomas Huth wrote:
Many of the disassemblers in the disas folder are based on old
versions from the GNU tools (libopcode, GDB, ...) that were still
licensed under the GPL v2. The GNU tools switched to GPL v3 at one
point in
virtio_scsi_handle_cmd_vq() is only called from hw/scsi/virtio-scsi.c
now and its return value is no longer used. Remove the function
prototype from virtio-scsi.h and drop the return value.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Paolo Bonzini
Message-id:
On 5/9/22 12:36, Daniel P. Berrangé wrote:
On Mon, May 09, 2022 at 12:19:07PM +0200, Paolo Bonzini wrote:
The ``loaded=on`` option in the command line or QMP ``object-add`` either had
no effect (if ``loaded`` was the last option) or caused options to be
effectively ignored as if they were not
On 5/9/22 2:31 PM, Philippe Mathieu-Daudé wrote:
> On 3/5/22 11:40, Claudio Fontana wrote:
>> On 3/7/22 12:17 AM, Philippe Mathieu-Daudé wrote:
>>> From: Philippe Mathieu-Daudé
>>>
>>> Few patches to be able to build QEMU on macOS 12 (Monterey).
>>>
>>> Missing review:
>>>
virtio_scsi_handle_ctrl_vq() is only called from hw/scsi/virtio-scsi.c
now and its return value is no longer used. Remove the function
prototype from virtio-scsi.h and drop the return value.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Paolo Bonzini
Message-id:
On 14/4/22 13:46, Thomas Huth wrote:
Allow the same set of tests for all MIPS targets, so that "mipsel"
now gets some additional test coverage, too. While we're at it,
simplify the definitions for qtests_mips64 and qtests_mips64el.
Signed-off-by: Thomas Huth
---
tests/qtest/endianness-test.c
On 4/5/22 13:03, Stefan Pejic wrote:
From: Dragan Mladjenovic
There are currently two problems related to the emulation of the
instruction BPOSGE32C.
The nanoMips instruction BPOSGE32C belongs to DSP R3 instructions
(actually, as of now, it is the only instruction of DSP R3). The
presence of
On 09/05/2022 14.41, Daniel P. Berrangé wrote:
When running 'make check' we only get a summary of progress on the
console. Fortunately meson/ninja have saved the raw test output to a
logfile. Exposing this log will make it easier to debug failures that
happen in CI.
Signed-off-by: Daniel P.
On 27/4/22 12:01, Stefan Hajnoczi wrote:
Commit 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend
Program conventions for vhost-user-scsi") introduced fd-passing support
as part of implementing the vhost-user backend program conventions.
When fd passing is used the UNIX domain
On 26/4/22 12:36, Laurent Vivier wrote:
Le 12/04/2022 à 13:38, Thomas Huth a écrit :
The last change to this file has been done in 2012, so it
seems like this is not really used anymore, and the content
is likely very out of date now.
Signed-off-by: Thomas Huth
---
target/mips/TODO | 51
On 3/5/22 11:40, Claudio Fontana wrote:
On 3/7/22 12:17 AM, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Few patches to be able to build QEMU on macOS 12 (Monterey).
Missing review:
0006-hvf-Fix-OOB-write-in-RDTSCP-instruction-decode.patch
On 5/5/22 18:18, Bernhard Beschow wrote:
etsec_create() wraps qdev API which is outdated. It is also unused,
so remove it.
Signed-off-by: Bernhard Beschow
---
hw/net/fsl_etsec/etsec.c | 23 ---
hw/net/fsl_etsec/etsec.h | 7 ---
2 files changed, 30 deletions(-)
Hello everyone,
The FI bit in FPSCR is said to be a non-sticky bit on Power ISA.
One could think this means that, if an instruction is said to modify
the FPSCR register, the bit FI should be cleared. This is what QEMU
does today.
This is not, however, what the real hardware appears to do. It
The virtio-scsi event virtqueue is not emptied by its handler function.
This is typical for rx virtqueues where the device uses buffers when
some event occurs (e.g. a packet is received, an error condition
happens, etc).
Polling non-empty virtqueues wastes CPU cycles. We are not waiting for
new
On 5/5/22 18:17, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
hw/i386/pc.c | 4 ++--
include/hw/i386/pc.h | 3 ---
2 files changed, 2 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 4/5/22 13:04, Stefan Pejic wrote:
Switch statements for the code segments that handle nanoMips
instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS
do not have proper default case, resulting in not generating
reserved instruction exception for certain illegal opcodes.
Fix this by
On 09/05/2022 14.41, Daniel P. Berrangé wrote:
When running I/O tests using TAP output mode, we get a single TAP test
with a sub-test reported for each I/O test that is run. The output looks
something like this:
1..123
ok qcow2 011
ok qcow2 012
ok qcow2 013
ok qcow2 217
...
If
On 12/4/22 18:58, Thomas Huth wrote:
Many of the disassemblers in the disas folder are based on old
versions from the GNU tools (libopcode, GDB, ...) that were still
licensed under the GPL v2. The GNU tools switched to GPL v3 at one
point in time, so QEMU is stuck with the old versions, i.e.
From: Nicolas Saenz Julienne
'event-loop-base' provides basic property handling for all 'AioContext'
based event loops. So let's define a new 'MainLoopClass' that inherits
from it. This will permit tweaking the main loop's properties through
qapi as well as through the command line using the
On Mon, 9 May 2022 at 13:44, Philippe Mathieu-Daudé wrote:
>
> On 9/5/22 11:41, Peter Maydell wrote:
> > Accidentally (but harmlessly)
>
> This makes crash clang tools such clang-format, I'll amend that
> to the description.
That sounds like a bug in clang-format :-)
-- PMM
There is no longer a need to expose the request and related APIs in
virtio-scsi.h since there are no callers outside virtio-scsi.c.
Note the block comment in VirtIOSCSIReq has been adjusted to meet the
coding style.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Paolo Bonzini
Message-id:
The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into
staging (2022-05-08 17:03:26 -0500)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/block-pull-request
Commit f34e8d8b8d48d73f36a67b6d5e492ef9784b5012 ("virtio-scsi: prepare
virtio_scsi_handle_cmd for dataplane") prepared the virtio-scsi cmd
virtqueue handler function to be used in both the dataplane and
non-datpalane code paths.
It failed to convert the ctrl and event virtqueue handler functions,
On 5/5/22 18:17, Bernhard Beschow wrote:
The tables contain spcifically crafted constants for algorithms, so make
them immutable.
Signed-off-by: Bernhard Beschow
---
hw/audio/cs4231a.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/5/22 11:41, Peter Maydell wrote:
On Mon, 9 May 2022 at 09:53, Philippe Mathieu-Daudé
wrote:
From: Philippe Mathieu-Daudé
"qom/object.h" doesn't need to include itself.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h | 1 -
1 file changed, 1 deletion(-)
diff --git
This patch fixes another not-so-clear situation in Power ISA
regarding the inexact bits in FPSCR. The ISA states that:
"""
When Overflow Exception is disabled (OE=0) and an
Overflow Exception occurs, the following actions are
taken:
...
2. Inexact Exception is set
XX <- 1
...
FI is set to 1
...
virtio_scsi_handle_event_vq() is only called from hw/scsi/virtio-scsi.c
now and its return value is no longer used. Remove the function
prototype from virtio-scsi.h and drop the return value.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Paolo Bonzini
Message-id:
From: Nicolas Saenz Julienne
Introduce the 'event-loop-base' abstract class, it'll hold the
properties common to all event loops and provide the necessary hooks for
their creation and maintenance. Then have iothread inherit from it.
EventLoopBaseClass is defined as user creatable and provides a
Currently with the TAP harness we see essentially no useful information
about the I/O tests execution. To pick a random job:
https://gitlab.com/qemu-project/qemu/-/jobs/2429330423
All that we get is this:
184/204 qemu:block / qemu-iotests qcow2 OK 309.10s 116 subtests passed
The full
From: Nicolas Saenz Julienne
The thread pool regulates itself: when idle, it kills threads until
empty, when in demand, it creates new threads until full. This behaviour
doesn't play well with latency sensitive workloads where the price of
creating a new thread is too high. For example, when
It looks like a race condition in the test case. The failed test case
(tests/unit/test-aio.c:test_timer_schedule()) assumes the process will
be scheduled in a timely manner. A timer is scheduled for 750 ms and
the test waits for 1 second before running the event loop. At that
point a callback
The FI bit in FPSCR is said to be a non-sticky bit on Power ISA.
One could think this means that, if an instruction is said to modify
the FPSCR register, the bit FI should be cleared. This is what QEMU
does today.
However, the following inconsistency was found when comparing results
from the
When running 'make check' we only get a summary of progress on the
console. Fortunately meson/ninja have saved the raw test output to a
logfile. Exposing this log will make it easier to debug failures that
happen in CI.
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/buildtest-template.yml |
On 5/9/22 19:12, Klaus Jensen wrote:
On May 7 15:26, zhenwei pi wrote:
Hi,
In this series, firstly introduce smart related bits of aen cfg, then
support this in oaes.
Linux guest does not support this currently, I also send a series to
enable smart AEN:
When running I/O tests using TAP output mode, we get a single TAP test
with a sub-test reported for each I/O test that is run. The output looks
something like this:
1..123
ok qcow2 011
ok qcow2 012
ok qcow2 013
ok qcow2 217
...
If everything runs or fails normally this is fine, but
From: Gavin Shan
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.
This reworks build_pptt() to avoid by reusing the existing IDs in
ms->possible_cpus. Currently,
On 5/5/22 18:17, Bernhard Beschow wrote:
TYPE_I8042 is exported, so reuse it for consistency.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc.c | 4 ++--
hw/sparc64/sun4u.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
From: Gavin Shan
In aarch64_numa_cpu(), the CPU and NUMA association is something
like below. Two threads in the same core/cluster/socket are
associated with two individual NUMA nodes, which is unreal as
Igor Mammedov mentioned. We don't expect the association to break
NUMA-to-socket boundary,
From: Gavin Shan
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.
This takes account of SMP configuration when the CPU topology
From: Gavin Shan
The CPU topology isn't enabled on arm/virt machine yet, but we're
going to do it in next patch. After the CPU topology is enabled by
next patch, "thread-id=1" becomes invalid because the CPU core is
preferred on arm/virt machine. It means these two CPUs have 0/1
as their core
From: Gavin Shan
This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
CPU with its NUMA node.
*
From: Leif Lindholm
The sbsa-ref machine is continuously evolving. Some of the changes we
want to make in the near future, to align with real components (e.g.
the GIC-700), will break compatibility for existing firmware.
Introduce two new properties to the DT generated on machine generation:
-
From: Richard Henderson
This extension concerns cache speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-22-richard.hender...@linaro.org
Signed-off-by: Peter
On Mon, May 09, 2022 at 09:12:49AM +0200, Igor Mammedov wrote:
> On Wed, 4 May 2022 08:16:39 -0500
> Suravee Suthikulpanit wrote:
>
> > This is the maximum number of vCPU supported by
> > the AMD x2APIC virtualization.
> >
> > Signed-off-by: Suravee Suthikulpanit
> > ---
> > hw/i386/pc_q35.c
From: Richard Henderson
Enable the a76 for virt and sbsa board use.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-24-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
From: Richard Henderson
There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Richard Henderson
This extension concerns not merging memory access, which TCG does
not implement. Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Richard Henderson
This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-19-richard.hender...@linaro.org
Signed-off-by: Peter
From: Gavin Shan
When CPU-to-NUMA association isn't explicitly provided by users,
the default one is given by mc->get_default_cpu_node_id(). However,
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings on booting Linux guest.
For
From: Richard Henderson
Enable the n1 for virt and sbsa board use.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-25-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c| 1 +
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-18-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c| 1 +
target/arm/cpu_tcg.c | 1 +
From: Richard Henderson
Check for and defer any pending virtual SError.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 1 +
target/arm/a32.decode
From: Richard Henderson
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-16-richard.hender...@linaro.org
Signed-off-by: Peter
From: Richard Henderson
Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
On Mon, May 9, 2022 at 2:54 PM Alistair Francis wrote:
>
> On Thu, May 5, 2022 at 12:36 PM Anup Patel wrote:
> >
> > On Thu, May 5, 2022 at 3:21 PM Alistair Francis
> > wrote:
> > >
> > > On Fri, Apr 29, 2022 at 1:38 PM Anup Patel
> > > wrote:
> > > >
> > > > Currently, QEMU does not set
From: Richard Henderson
Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-9-richard.hender...@linaro.org
Signed-off-by: Peter
From: Richard Henderson
Add only the system registers required to implement zero error
records. This means that all values for ERRSELR are out of range,
which means that it and all of the indexed error record registers
need not be implemented.
Add the EL2 registers required for injecting
From: Richard Henderson
This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU. Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.
Reviewed-by: Peter
From: Richard Henderson
This extension concerns branch speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-20-richard.hender...@linaro.org
Signed-off-by: Peter
From: Richard Henderson
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE. The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.
Reviewed-by: Peter Maydell
From: Richard Henderson
We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Richard Henderson
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Richard Henderson
Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
From: Richard Henderson
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
while registering for v8.
This is a behavior change for v7 cpus with Security Extensions and
without Virtualization Extensions, in that
From: Richard Henderson
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.c | 22
From: Richard Henderson
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220506180242.216785-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 15 +++
1 file
From: Richard Henderson
More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
either discard, squash to res0, const, or keep unchanged.
Per rule RJFFP, mark the 4
-20220508' of https://github.com/mcayland/qemu into
staging (2022-05-08 17:03:26 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220509
for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
hw/acpi/aml
From: Richard Henderson
Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.
This will shortly be used from cpu_tcg.c also.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
From: Leif Lindholm
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innovation Center (quicinc), so update
my email address to reflect this.
Signed-off-by: Leif Lindholm
On Mon, May 09, 2022 at 12:29:53PM +0200, Paolo Bonzini wrote:
> This is the initial result of reviving Marc-André's series at
> https://patchew.org/QEMU/20170704220346.29244-1-marcandre.lur...@redhat.com/.
> A lot of the patches are similar to the ones that Marc-André wrote,
> but due to the
On Mon, 2 May 2022, BALATON Zoltan wrote:
On Sat, 23 Apr 2022, BALATON Zoltan wrote:
During trying to implement via-ac97 I did some small clean ups to ac97
which is in this series. The via-ac97 is not working yet so that's not
included but these unrelated clean ups could be merged now.
v3:
Igor,
On 5/9/2022 2:12 PM, Igor Mammedov wrote:
On Wed, 4 May 2022 08:16:39 -0500
Suravee Suthikulpanit wrote:
This is the maximum number of vCPU supported by
the AMD x2APIC virtualization.
Signed-off-by: Suravee Suthikulpanit
---
hw/i386/pc_q35.c | 2 +-
1 file changed, 1 insertion(+),
101 - 200 of 276 matches
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