://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging (2022-06-10 18:15:34 -0700)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/mips-20220611
for you to fetch changes up to 6e0c18598814bffb67204a90890fb7b34cad288a:
docs/devel: Fix link to developer mailing
ailable in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/mips-20220611
>
> for you to fetch changes up to 37da3bcf01ccd19336fd8f43bedcd0841d71bb6a:
>
> docs/devel: Fix link to developer mail
From: Bernhard Beschow
Fixes compilation due to false positives with -Werror:
In file included from /usr/include/glib-2.0/glib.h:114,
from qemu/src/include/glib-compat.h:32,
from qemu/src/include/qemu/osdep.h:144,
from
On 2022/06/12 1:34, Volker Rümelin wrote:
Am 10.06.22 um 22:16 schrieb Richard Henderson:
On 6/10/22 02:20, Gerd Hoffmann wrote:
The following changes since commit
9cc1bf1ebca550f8d90f967ccd2b6d2e00e81387:
Merge tag 'pull-xen-20220609' of
On 6/11/22 06:55, Warner Losh wrote:
The following changes since commit 2663c41cfa2c3be34c62de97902a375b81027efd:
Merge tag 'pull-target-arm-20220610' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-06-10
13:16:48 -0700)
are available in the Git repository at:
On 6/9/22 11:26 AM, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> The D-Bus connection starts processing messages before QEMU has the time
> to set the object manager server. This is causing dbus-display-test to
> fail randomly with:
>
>
in the Git repository at:
https://github.com/philmd/qemu.git tags/mips-20220611
for you to fetch changes up to 37da3bcf01ccd19336fd8f43bedcd0841d71bb6a:
docs/devel: Fix link to developer mailing lists (2022-06-11 11:44:50 +0200
On Sat, Jun 11, 2022 at 5:27 PM Bernhard Beschow wrote:
> On Fri, Jun 10, 2022 at 4:04 PM Philippe Mathieu-Daudé
> wrote:
>> On 5/6/22 17:19, Bernhard Beschow wrote:
>> > Fixes compilation due to false positives with -Werror:
>> >
>> >In file included from /usr/include/glib-2.0/glib.h:114,
This small patch is the result of some recent malware research I did
in a QEMU VM. The malware used multiple ways of querying info from
the VM disk and I needed a clean way to change those values from the
hypervisor.
I believe this functionality could be useful to more people from multiple
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which is always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the
CSR ops.")
Signed-off-by: Anup Patel
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v6 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required
On Fri, Jun 10, 2022 at 5:43 PM Mark Cave-Ayland
wrote:
>
> On 10/06/2022 16:35, Philippe Mathieu-Daudé wrote:
>
> > On 7/6/22 17:54, Mark Cave-Ayland wrote:
> >> On 22/05/2022 19:17, Mark Cave-Ayland wrote:
> >>
> >>> This series came about when looking at improving the LASI PS2 device for
> >>>
On 6/6/22 12:56, Mark Cave-Ayland wrote:
On 30/05/2022 12:27, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
This series moves the outstanding logic from piix4_pm_init() into
the relevant instance init() and realize() functions, changes the
IRQs to use qdev gpios, and then
On 3/6/22 20:50, Bernhard Beschow wrote:
Bernhard Beschow (11):
hw/southbridge/piix: Aggregate all PIIX southbridge type names
hw/isa/piix4: Use object_initialize_child() for embedded struct
hw/isa/piix4: Move pci_map_irq_fn' near pci_set_irq_fn
hw/isa/piix4: QOM'ify PCI device
/qemu.git tags/mips-20220611
for you to fetch changes up to 37da3bcf01ccd19336fd8f43bedcd0841d71bb6a:
docs/devel: Fix link to developer mailing lists (2022-06-11 11:44:50 +0200)
MIPS patches queue
- Various TCG fixes (Marcin
From: Marcin Nowakowski
bit 31 (M) of WatchHiN register is a read-only register indicating
whether the next WatchHi register is present. It must not be reset
during user writes to the register.
Signed-off-by: Marcin Nowakowski
Reviewed-by: David Daney
Signed-off-by: Philippe Mathieu-Daudé
From: Ni Hui
Fix the SAT_S and SAT_U trans helper confusion.
Fixes: 4701d23aef ("target/mips: Convert MSA BIT instruction format to
decodetree")
Signed-off-by: Ni Hui
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Dragan Mladjenovic
There are currently two problems related to the emulation of the
instruction BPOSGE32C.
The nanoMIPS instruction BPOSGE32C belongs to DSP R3 instructions
(actually, as of now, it is the only instruction of DSP R3). The
presence of DSP R3 instructions in QEMU is
From: Ni Hui
This patch fix the issue that helper_msa_st_b() write high 64bit
data to where the low 64bit resides, leaving high 64bit undefined.
Fixes: 68ad9260e0 ("target/mips: Use 8-byte memory ops for msa load/store")
Signed-off-by: Ni Hui
Reviewed-by: Richard Henderson
Reviewed-by:
From: Dragan Mladjenovic
The field rs in the instruction EXTRV_S.H rt, ac, rs is specified in
nanoMIPS documentation as opcode[20..16]. It is, however, erroneously
considered as opcode[25..21] in the current QEMU implementation. In
function gen_pool32axf_2_nanomips_insn(), the variable v0_t
From: Ni Hui
Only for msa COPY_U/COPY_S with wd zero, we treat it as NOP.
Move this special rule into COPY_U and COPY_S trans function.
Fixes: 97fe675519 ("target/mips: Convert MSA COPY_S and INSERT opcodes to
decodetree")
Signed-off-by: Ni Hui
Reviewed-by: Philippe Mathieu-Daudé
From: Mark Cave-Ayland
This logic can be included as part of piix4_pm_realize() and does not need to
be handled externally.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ani Sinha
Message-Id: <20220528091934.15520-2-mark.cave-ayl...@ilande.co.uk>
From: Stefan Pejic
Switch statements for the code segments that handle nanoMIPS
instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS
do not have proper default case, resulting in not generating
reserved instruction exception for certain illegal opcodes.
Fix this by adding default
From: Mark Cave-Ayland
This is in preparation for conversion to a qdev property.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ani Sinha
Message-Id: <20220528091934.15520-3-mark.cave-ayl...@ilande.co.uk>
[PMD: Change simm_enabled from int to bool, suggested
From: Mark Cave-Ayland
This allows the QOM types in hw/acpi/piix4.c to be used elsewhere by simply
including
hw/acpi/piix4.h.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-5-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Bernhard Beschow
From: Mark Cave-Ayland
This exposes the PIIX4_PM device to the caller to allow any qdev gpios to be
mapped outside of piix4_pm_init().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-6-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Bernhard
From: Mark Cave-Ayland
This allows the smm_enabled value to be set using a standard qdev property
instead
of being referenced directly in piix4_pm_init().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ani Sinha
Message-Id:
From: Mark Cave-Ayland
When QOMifying a device it is typical to use _init() as the suffix for an
instance_init function, however this name is already in use by the legacy
piix4_pm_init() wrapper function. Eventually the wrapper function will be
removed, but for now rename it to piix4_pm_initfn()
From: Bernhard Beschow
TYPE_PIIX3_PCI_DEVICE resides there as already, so add the remaining
ones, too.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220603185045.143789-2-shen...@gmail.com>
Signed-off-by: Philippe
From: Bernhard Beschow
During the previous changesets piix4_create() became a trivial
wrapper around more generic functions. Modernize the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Message-Id:
From: Mark Cave-Ayland
Now that all external logic has been removed from piix4_pm_initfn() the PIIX4_PM
device can be instantiated directly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-12-mark.cave-ayl...@ilande.co.uk>
Reviewed-by:
From: Mark Cave-Ayland
Now that all external logic has been removed from piix4_pm_initfn() the PIIX4_PM
device can be instantiated directly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-11-mark.cave-ayl...@ilande.co.uk>
Reviewed-by:
From: Bernhard Beschow
TYPE_I8042 is exported, so reuse it for consistency.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Acked-by: Mark Cave-Ayland
Message-Id: <20220520180109.8224-2-shen...@gmail.com>
Signed-off-by: Philippe
From: Bernhard Beschow
Reported-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Message-Id: <20220603185045.143789-3-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c | 2 +-
1 file changed, 1
From: Bernhard Beschow
Modernizes the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Message-Id: <20220603185045.143789-11-shen...@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc_piix.c | 3 ++-
From: Bernhard Beschow
The pci_map_irq_fn was implemented below type_init() which made it
inaccessible to QOM functions. So move it up.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220603185045.143789-4-shen...@gmail.com>
From: Bernhard Beschow
Just like the real hardware, create the PIIX4 ACPI controller as part of
the PIIX4 southbridge. This also mirrors how the IDE and USB functions
are already created.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Message-Id:
From: Bernhard Beschow
Ammends commit 9f73de8df0335c9387f4ee39e207a65a1615676f 'docs: rSTify
the "SubmitAPatch" wiki'.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Bernhard Beschow
Acked-by: Mark Cave-Ayland
Message-Id: <20220520180109.8224-11-shen...@gmail.com>
Signed-off-by: Philippe
From: Bernhard Beschow
The pci_map_irq_fn was implemented below type_init() which made it
inaccessible to QOM functions. So move it up.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220603185045.143789-9-shen...@gmail.com>
From: Bernhard Beschow
Since commit 3b004a16540aa41f2aa6a1ceb0bf306716766914 'hw/rtc/
mc146818rtc: QOM'ify IRQ number' mc146818rtc's IRQ number is
configurable. Fix microvm-dt to respect its value.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe
From: Bernhard Beschow
Exposing the io_base offset as a QOM property not only allows it to be
configurable but also to be displayed in HMP:
Before:
(qemu) info qtree
...
dev: mc146818rtc, id ""
gpio-out "" 1
base_year = 0 (0x0)
irq = 8 (0x8)
From: Bernhard Beschow
etsec_create() wraps qdev API which is outdated. It is also unused,
so remove it.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Acked-by: Mark Cave-Ayland
Message-Id: <20220520180109.8224-8-shen...@gmail.com>
From: Bernhard Beschow
The macro seems to be used only internally, so remove it.
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
Acked-by: Mark Cave-Ayland
Message-Id: <20220520180109.8224-4-shen...@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe
From: Bernhard Beschow
New code will be added where this is best practice. So update existing code
as well.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220529184006.10712-2-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
From: Bernhard Beschow
The tables contain spcifically crafted constants for algorithms, so make
them immutable.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Mark Cave-Ayland
Message-Id: <20220520180109.8224-3-shen...@gmail.com>
Signed-off-by: Philippe
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Michael S. Tsirkin
Acked-by: Mark Cave-Ayland
Message-Id: <20220520180109.8224-5-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 4 ++--
From: Bernhard Beschow
Commit 3a841ab53f165910224dc4bebabf1a8f1d04200c 'qapi: introduce
x-query-jit QMP command' basically moved the only function using
dump_drift_info() to cpu-exec.c. Therefore, dump_drift_info() doesn't
need to be exported any longer.
Signed-off-by: Bernhard Beschow
From: Bernhard Beschow
dump_opcount_info() is a one-line wrapper around tcg_dump_op_count()
which is also exported. So use the latter directly.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Mark Cave-Ayland
Message-Id:
The riscv_cpu_realize() sets priv spec version to v1.12 when it is
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
value of priv spec v1.10 is zero.
Due to above issue, the sifive_u machine will see priv spec v1.12
instead of priv spec v1.10.
To fix this issue, we set latest priv
From: Ni Hui
Actually look into dfe structure data so that df_extract_val() and
df_extract_df() can return immediate and datafield other than BYTE.
Fixes: 4701d23aef ("target/mips: Convert MSA BIT instruction format to
decodetree")
Signed-off-by: Ni Hui
Reviewed-by: Richard Henderson
From: Ni Hui
Fix the FTRUNC_S and FTRUNC_U trans helper problem.
Fixes: 5c5b64000c ("target/mips: Convert MSA 2RF instruction format to
decodetree")
Signed-off-by: nihui
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Ni Hui
Fix issue that condition of check_msa_enabled(ctx) is reversed
that causes segfault when msa elm_fn op encountered.
Fixes: 2f2745c81a ("target/mips: Convert MSA COPY_U opcode to decodetree")
Fixes: 97fe675519 ("target/mips: Convert MSA COPY_S and INSERT opcodes to
decodetree")
From: Dragan Mladjenovic
If both rs and rt are the same register, the nanoMIPS instruction
BNEC[32] rs, rt, address is equivalent to NOP (branch is not taken and
there is no delay slot). This commit provides such behavior. Without
this commit, this scenario results in an incorrect behavior.
From: Stefan Pejic
nanoMIPS ISA support in QEMU is actively used by MediaTek and is
planned to be maintained and potentially extended by MediaTek in
future.
Un-orphan nanoMIPS ISA support in QEMU by setting a maintainer from
MediaTek and remove deprecation notes from documentation as well.
From: Stefan Pejic
The field ac in nanoMIPS instruction MTHLIP rs, ac is specified in
nanoMIPS documentation as opcode[15..14] (2 bits). However, in the
current QEMU code, the corresponding argument passed to the helper
gen_helper_mthlip() has the value of opcode[15..11] (5 bits). Right
shift
From: Dragan Mladjenovic
nanoMIPS ISA does not support unaligned memory access. Adjust
DisasContext's default_tcg_memop_mask to reflect this.
Signed-off-by: Dragan Mladjenovic
Signed-off-by: Stefan Pejic
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Mark Cave-Ayland
Initialize the SMI IRQ in piix4_pm_init().
The smi_irq can now be wired up directly using a qdev gpio instead
of having to set the IRQ externally in piix4_pm_initfn().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Peter Maydell
The sysbus floppy controllers (devices sysbus-fdc and sun-fdtwo)
don't support DMA. The core floppy controller code expects this to
be indicated by setting FDCtrl::dma_chann to -1. This used to be
done in the device instance_init functions sysbus_fdc_initfn() and
From: Mark Cave-Ayland
This function is now unused and so can be completely removed.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220528091934.15520-13-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Bernhard Beschow
Signed-off-by: Philippe Mathieu-Daudé
From: Bernhard Beschow
PCI interrupt wiring and device creation were performed in create()
functions which are obsolete. Move these tasks into QOM functions to
modernize the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Message-Id:
From: Mark Cave-Ayland
Introduce piix4_pm_init() instance init function and use it to
initialise the separate qdev gpio for the SCI IRQ.
The sci_irq can now be wired up directly using a qdev gpio instead
of having to set the IRQ externally in piix4_pm_initfn().
Signed-off-by: Mark Cave-Ayland
From: Bernhard Beschow
Modernizes the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220603185045.143789-6-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c| 6 +-
From: Bernhard Beschow
PCI interrupt wiring was performed in create() functions which are
obsolete. Move these tasks into QOM functions to modernize the code.
In order to avoid duplicate checking for xen_enabled() the realize
methods are now split.
Signed-off-by: Bernhard Beschow
Reviewed-by:
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Acked-by: Michael S. Tsirkin
Acked-by: Mark Cave-Ayland
Message-Id: <20220520180109.8224-6-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 3 ---
1 file changed, 3 deletions(-)
diff --git
From: Bernhard Beschow
During the previous changesets piix3_create() became a trivial
wrapper around more generic functions. Modernize the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Message-Id:
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 3 +
target/riscv/cpu_helper.c | 214
On 6/10/22 17:35, Michael S. Tsirkin wrote:
On Fri, Jun 10, 2022 at 11:05:13AM -0700, Richard Henderson wrote:
Build failure:
../backends/cryptodev-builtin.c:187:27: error: result of comparison of
unsigned enum expression < 0 is always false
[-Werror,-Wtautological-unsigned-enum-zero-compare]
v9 - v10:
- Minor fix of coding style by v9.
v8 - v9:
- Fix compiling error reported by clang-13/14:
opt->hash_alg = cryptodev_builtin_get_rsa_hash_algo(); this leads
implicit convertion from 'int' to 'uint32'. 'if (opt->hash_alg < 0)'
is always false. Thanks to Philippe Mathieu-Daudé.
v7
There are two parts in this patch:
1, support akcipher service by cryptodev-builtin driver
2, virtio-crypto driver supports akcipher service
In principle, we should separate this into two patches, to avoid
compiling error, merge them into one.
Then virtio-crypto gets request from guest side, and
Peter Maydell writes:
> On Fri, 10 Jun 2022 at 16:40, Alex Bennée wrote:
>>
>> We generate the XML for each vCPU we create which for heavily threaded
>> linux-user runs can add up to a lot of memory. Unfortunately we can't
>> only do it once as we may have vCPUs with different capabilities in
We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.
Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to
On Fri, Jun 10, 2022 at 4:04 PM Philippe Mathieu-Daudé
wrote:
> On 5/6/22 17:19, Bernhard Beschow wrote:
> > Fixes compilation due to false positives with -Werror:
> >
> >In file included from /usr/include/glib-2.0/glib.h:114,
> > from qemu/src/include/glib-compat.h:32,
>
On 10/06/2022 08:17, Mark Cave-Ayland wrote:
On 09/06/2022 12:18, Peter Maydell wrote:
On Sun, 22 May 2022 at 19:20, Mark Cave-Ayland
wrote:
This enables the IRQ to be wired up using qdev_connect_gpio_out() in
lasips2_initfn().
Signed-off-by: Mark Cave-Ayland
---
hw/input/lasips2.c
On 6/10/22 08:05, Philippe Mathieu-Daudé wrote:
+static void report_fault(CPUMIPSState *env)
+{
+ int op = env->active_tc.gpr[25];
+ error_report("Fault during UHI operation %d", op);
+ abort();
This is a guest error, no need to debug QEMU internals...
Can we simply exit(1) instead?
On 6/10/22 20:10, gaosong wrote:
pc 0x12638 0x12638
badvaddr 0x12638 0x12638
...
So badvaddr is the PC,
Yes.
void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
if (rj > rk) {
env->badvaddr =
Am 10.06.22 um 22:16 schrieb Richard Henderson:
On 6/10/22 02:20, Gerd Hoffmann wrote:
The following changes since commit
9cc1bf1ebca550f8d90f967ccd2b6d2e00e81387:
Merge tag 'pull-xen-20220609' of
https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging
(2022-06-09 08:25:17
In xen_pt_config_reg_init(), there is an error in the merging of the
emulated data with the host value. With the current Qemu, instead of
merging the emulated bits with the host bits as defined by emu_mask,
the emulated bits are merged with the host bits as defined by the
inverse of emu_mask. In
The following changes since commit 2663c41cfa2c3be34c62de97902a375b81027efd:
Merge tag 'pull-target-arm-20220610' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-06-10
13:16:48 -0700)
are available in the Git repository at:
Implement write, writev, pwrite and pwritev and connect them to the
system call dispatch routine.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 84 +++
Implement the exit system call. Bring in bsd-proc.h to contain all the
process system call implementation and helper routines.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
Reviewed-by: Kyle Evans
---
bsd-user/bsd-proc.h | 42
Releases the references to the iovec created by lock_iovec.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/freebsd/os-syscall.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/bsd-user/freebsd/os-syscall.c b/bsd-user/freebsd/os-syscall.c
index
Add in the tracing and this system call not implemented boilerplate. Do
this by moving the guts of do_freebsd_syscall to freebsd_syscall. Put
the tracing in the wrapper function. Since freebsd_syscall is a
singleton static function, it will almost certainly be inlined. Fix
comments that referred
lock_iovec will lock an I/O vec and the memory to which it refers and
create a iovec in the host space that refers to it, with full error
unwinding. Add helper_iovec_unlock to unlock the partially locked iovec
in case there's an error. The code will be used in iovec_unlock when
that is committed.
Implement do_bsd_{read,pread,readv,preadv}. Connect them to the system
call table.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 79 +++
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