ImageInfo sometimes contains flat information, and sometimes it does
not. Split off a BlockNodeInfo struct, which only contains information
about a single node and has no link to the backing image.
We do this so we can extend BlockNodeInfo to a BlockGraphInfo struct,
which has links to all child
On 20/06/2022 12.54, Michael Tokarev wrote:
20.06.2022 13:31, Thomas Huth write:
On 30/04/2022 16.11, Michael Tokarev wrote:
Hello!
Previously, it was possible to build qemu tools (such as qemu-img, or
qemu-ga)
on an unsupported cpu/architecture. In a hackish way, by specifying
This patch implements several Octeon-specific instructions:
- BADDU
- DMUL
- EXTS/EXTS32
- CINS/CINS32
- POP/DPOP
- SEQ/SEQI
- SNE/SNEI
Signed-off-by: Pavel Dovgalyuk
--
v3 changes:
- Fixed length field for EXTS/CINS
(bug found by Richard Henderson)
v2 changes:
- Using existing tcg
On Mon, May 30, 2022 at 06:04:32PM +0300, Roman Kagan wrote:
> On Mon, May 30, 2022 at 01:28:17PM +0200, Markus Armbruster wrote:
> > Roman Kagan writes:
> >
> > > On Wed, May 25, 2022 at 12:54:47PM +0200, Markus Armbruster wrote:
> > >> Konstantin Khlebnikov writes:
> > >>
> > >> > This event
The handling of STSI is enhanced with the interception of the
function code 15 for storing CPU topology.
Using the objects built during the plugging of CPU, we build the
SYSIB 15_1_x structures.
With this patch the maximum MNEST level is 2, this is also
the only level allowed and only SYSIB
On Fri, 17 Jun 2022 at 15:02, Martin Liška wrote:
>
> Fixes the following Sphinx warning (treated as error) starting
> with 5.0 release:
>
> Warning, treated as error:
> Invalid configuration value found: 'language = None'. Update your
> configuration to a valid langauge code. Falling back to
Use the new semihosting_exit_request instead of a call to exit when
handling a semihosted exit syscall.
Signed-off-by: Luc Michel
---
target/xtensa/xtensa-semi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c
index
Daniel P. Berrangé wrote:
> The only callers of qemu_fopen_ops pass 'true' for the 'has_ioc'
> parameter, so hardcode this assumption in QEMUFile, by passing in
> the QIOChannel object as a non-opaque parameter.
>
> Reviewed-by: Dr. David Alan Gilbert
> Signed-off-by: Daniel P. Berrangé
On Mon, Jun 20, 2022 at 02:39:43AM -0300, Leonardo Bras wrote:
> Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial
> part of the flushing mechanism got missing: incrementing zero_copy_queued.
>
> Without that, the flushing interface becomes a no-op, and there is no
>
Daniel P. Berrangé wrote:
> Reviewed-by: Dr. David Alan Gilbert
> Signed-off-by: Daniel P. Berrangé
Reviewed-by: Juan Quintela
On Mon, Jun 20, 2022 at 02:39:45AM -0300, Leonardo Bras wrote:
> When originally implemented, zero_copy_send was designed as a Migration
> paramenter.
>
> But taking into account how is that supposed to work, and how
> the difference between a capability and a parameter, it only makes sense
>
On Mon, Jun 20, 2022 at 11:23:53AM +0200, Juan Quintela wrote:
> Once discussed this, what I asked in the past is that you are having too
> much dirty memory on zero_copy. When you have a Multiterabyte guest, in
> a single round you have a "potentially" dirty memory on each channel of:
>
>
Hi,
This series is a v2 to:
https://lists.nongnu.org/archive/html/qemu-block/2022-05/msg00042.html
Like v1, the purpose is to have qemu-img info print the extent-size-hint
for images on filesystems that support it. In contrast to v1, it does
so in a more complicated way.
v1 printed this
qemu-img info never uses ImageInfo's backing-image field, because it
opens the backing chain one by one with BDRV_O_NO_BACKING, and prints
all backing chain nodes' information consecutively. Use BlockNodeInfo
to make it clear that we only print information about a single node, and
that we are not
Currently, when querying a qcow2 image, qemu-img info reports something
like this:
image: test.qcow2
file format: qcow2
virtual size: 64 MiB (67108864 bytes)
disk size: 196 KiB
cluster_size: 65536
Format specific information:
compat: 1.1
compression type: zlib
lazy refcounts: false
On 20/06/2022 13:22, Markus Armbruster wrote:
Laurent Vivier writes:
On 15/06/2022 13:46, Markus Armbruster wrote:
Laurent Vivier writes:
On 13/05/2022 13:44, Markus Armbruster wrote:
Laurent Vivier writes:
Copied from socket netdev file and modified to use SocketAddress
to be able to
Laurent Vivier writes:
> As qemu_opts_parse_noisily() flattens the QAPI structures ("type" field
> of Netdev structure can collides with "type" field of SocketAddress),
> we introduce a way to bypass qemu_opts_parse_noisily() and use directly
> visit_type_Netdev() to parse the backend
Daniel P. Berrangé wrote:
> This is for code which needs a portable equivalent to a QIOChannelFile
> connected to /dev/null.
>
> Signed-off-by: Daniel P. Berrangé
Reviewed-by: Juan Quintela
Daniel P. Berrangé wrote:
> This removes one further custom impl of QEMUFile, in favour of a
> QIOChannel based impl.
>
> Reviewed-by: Eric Blake
> Signed-off-by: Daniel P. Berrangé
Reviewed-by: Juan Quintela
On 220609 0958, Alexander Bulekov wrote:
> Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA.
> This flag is set/checked prior to calling a device's MemoryRegion
> handlers, and set when device code initiates DMA. The purpose of this
> flag is to prevent two types of
On Mon, 20 Jun 2022 at 15:25, Luc Michel wrote:
> This series implements a clean way for semihosted exit syscalls to
> terminate QEMU with a given return code.
>
> Until now, exit syscalls implementations consisted in calling exit()
> with the wanted return code. The problem with this approach is
Use the new semihosting_exit_request instead of a call to exit when
handling a semihosted exit syscall.
Signed-off-by: Luc Michel
---
target/nios2/nios2-semi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c
index
On 6/20/22 03:50, Peter Maydell wrote:
On Mon, 23 May 2022 at 16:08, Richard Henderson
wrote:
On 5/23/22 02:53, Peter Maydell wrote:
I just put some proposed dates into the 7.1 schedule page:
https://wiki.qemu.org/Planning/7.1#Release_Schedule
* 2022-07-12 Softfreeze
* 2022-07-19
Daniel P. Berrangé wrote:
> The name 'ftell' gives the misleading impression that the QEMUFile
> objects are seekable. This is not the case, as in general we just
> have an opaque stream. The users of this method are only interested
> in the total bytes processed. This switches to a new name that
Daniel P. Berrangé wrote:
> The only user of the hooks is RDMA which provides a QIOChannel backed
> impl of QEMUFile. It can thus use the qemu_file_get_ioc() method.
>
> Reviewed-by: Dr. David Alan Gilbert
> Signed-off-by: Daniel P. Berrangé
Reviewed-by: Juan Quintela
On Mon, Jun 20, 2022 at 02:39:42AM -0300, Leonardo Bras wrote:
> During implementation of MSG_ZEROCOPY feature, a lot of #ifdefs were
> introduced, particularly at qio_channel_socket_writev().
>
> Rewrite some of those changes so it's easier to read.
>
> Also, introduce an assert to help detect
Daniel P. Berrangé wrote:
> This directly implements the get_buffer logic using QIOChannel APIs.
>
> Reviewed-by: Dr. David Alan Gilbert
> Signed-off-by: Daniel P. Berrangé
Reviewed-by: Juan Quintela
Some features such as running in EL3 or running M profile code are
incompatible with virtualization as QEMU implements it today. To prevent
users from picking invalid configurations on Hvf as well, let's run the
same checks there as well.
Resolves:
Add some (optional) information that the file driver can provide for
image files, namely the extent size hint.
Signed-off-by: Hanna Reitz
---
qapi/block-core.json | 26 --
block/file-posix.c | 30 ++
2 files changed, 54 insertions(+), 2
These tests read size information (sometimes disk size, sometimes
virtual size) from qemu-img info's output. Once qemu-img starts
printing info about child nodes, we are going to see multiple instances
of that per image, but these tests are only interested in the first one,
so use "head -n 1" to
On 6/20/22 09:08, Alexander Graf wrote:
-if (kvm_enabled()) {
+if (kvm_enabled() || hvf_enabled()) {
I think this should be !tcg_enabled(). No hw virtualization can use EL3 (or M-profile),
only full emulation from TCG. There is such a thing as ARM on Windows, so I can imagine
that
This will be used for raising various traps for SME.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/syndrome.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index c105f9e6ba..73df5e3793 100644
---
This will be used for controlling access to SME cpregs.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h| 5 +
target/arm/translate-a64.c | 18 ++
2 files changed, 23 insertions(+)
diff --git a/target/arm/cpregs.h
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 2 ++
target/arm/sme.decode | 2 ++
target/arm/sme_helper.c| 52 ++
target/arm/translate-sme.c | 29 +
4 files changed, 85 insertions(+)
diff --git
These SME instructions are nominally within the SVE decode space,
so we add them to sve.decode and translate-sve.c.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 1 +
target/arm/sve.decode | 5 -
target/arm/translate-a64.c | 15 +++
Fold the return value setting into the goto, so each
point of failure need not do both.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/linux-user/aarch64/signal.c
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 20
1 file changed, 20 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index f7eae357f4..8135960305 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -601,6 +601,18 @@ enum {
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_cpu.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h
index 97a477bd3e..f90359faf2 100644
--- a/linux-user/aarch64/target_cpu.h
+++
Move the checks out of the parsing loop and into the
restore function. This more closely mirrors the code
structure in the kernel, and is slightly clearer.
Reject rather than silently skip incorrect VL and SVE record sizes.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 51
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 19 +++
bsd-user/freebsd/os-syscall.c | 8
2 files changed, 27 insertions(+)
Reviewed-by: Richard Henderson
r~
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 27 +++
bsd-user/freebsd/os-syscall.c | 8
2 files changed, 35 insertions(+)
Reviewed-by: Richard Henderson
r~
Some features such as running in EL3 or running M profile code are
incompatible with virtualization as QEMU implements it today. To prevent
users from picking invalid configurations on other virt solutions like
Hvf, let's run the same checks there too.
Resolves:
We need to fetch the name of the current accelerator in flexible error
messages more going forward. Let's create a helper that gives it to us
without casting in the target code.
Signed-off-by: Alexander Graf
---
accel/accel-common.c | 8
include/qemu/accel.h | 1 +
softmmu/vl.c
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 46 +++
bsd-user/freebsd/os-syscall.c | 16
2 files changed, 62 insertions(+)
Reviewed-by: Richard Henderson
r~
On 3/22/22 02:50, Bin Meng wrote:
CPUClass::memory_rw_debug() holds a callback for GDB memory access.
If not provided, cpu_memory_rw_debug() is used by the GDB stub.
Drop avr_cpu_memory_rw_debug() which does nothing special.
Signed-off-by: Bin Meng
Queued to tcg-next, for lack of anything
Check if each page dir/table base address is properly aligned and
log a guest error if not, as real hardware behave incorrectly in
this case.
These checks are only performed when DEBUG_MMU is defined, to avoid
hurting the performance.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c
On Mon, Jun 20, 2022 at 1:13 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/20/22 10:42, Warner Losh wrote:
> > These implement both the old-pre INO64 mknod variations, as well as the
> > now current INO64 variant. To implement the old stuff, we use some
> > linker magic to
Retreieve the refresh rate of the display and reflect it with
dpy_set_ui_info() and update_displaychangelistener(), allowing the
guest and DisplayChangeListener to consume the information.
Signed-off-by: Akihiko Odaki
---
meson.build | 3 ++-
ui/cocoa.m | 12
2 files changed, 14
On Jun 20, 2022, at 12:16 AM, Markus Armbruster
mailto:arm...@redhat.com>> wrote:
Peter Delevoryas mailto:p...@fb.com>> writes:
This lets you set the manufacturer's ID for a slirp netdev, which can be
queried from the guest through the Get Version ID NC-SI command. For
example, by setting the
* Juan Quintela (quint...@redhat.com) wrote:
> Nobody has ever showed up to unregister individual pages, and another
> set of patches written by Daniel P. Berrangé
> just remove qemu_rdma_signal_unregister() function needed here.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 27 +++
bsd-user/freebsd/os-syscall.c | 8
2 files changed, 35 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index f11369655a0..0b4b89c8d5c 100644
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 32
bsd-user/freebsd/os-syscall.c | 12
2 files changed, 44 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index 152579ad541..f5375a39a2c
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 13 +
bsd-user/freebsd/os-syscall.c | 4
2 files changed, 17 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index 79eb5a73a9b..94e756ae550 100644
---
These are required to determine if various insns
are allowed to issue.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 4
target/arm/helper.c| 4
target/arm/translate-a64.c | 2 ++
4 files
These cpregs control the streaming vector length and whether the
full a64 instruction set is allowed while in streaming mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 8 ++--
target/arm/helper.c | 41 +
2
Rename from cpu_arm_{get,set}_sve_default_vec_len,
and take the pointer to default_vq from opaque.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git
These functions are not used outside cpu64.c,
so make them static.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 3 ---
target/arm/cpu64.c | 4 ++--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
Place this late in the resettable section of the structure,
to keep the most common element offsets from being > 64k.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8
target/arm/machine.c | 34 ++
2 files
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 2 ++
target/arm/sme.decode | 1 +
target/arm/sme_helper.c| 74 ++
target/arm/translate-sme.c | 2 ++
4 files changed, 79 insertions(+)
diff --git a/target/arm/helper-sme.h
Pull the three sve_vq_* values into a structure.
This will be reused for SME.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 29 ++---
target/arm/cpu64.c | 22 +++---
target/arm/helper.c | 2 +-
target/arm/kvm64.c
Mirror the properties for SVE. The main difference is
that any arbitrary set of powers of 2 may be supported,
and not the stricter constraints that apply to SVE.
Include a property to control FEAT_SME_FA64, as failing
to restrict the runtime to the proper subset of insns
could be a major point
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 2 ++
target/arm/translate-a64.h | 1 +
target/arm/sme.decode | 4
target/arm/sme_helper.c| 25 +
target/arm/translate-a64.c | 14 ++
target/arm/translate-sme.c | 13
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 20 +
target/arm/translate-sve.c | 57 ++
2 files changed, 77 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index bbdaac6ac7..bf561c270a 100644
---
In parse_user_sigframe, the kernel rejects duplicate sve records,
or records that are smaller than the header. We were silently
allowing these cases to pass, dropping the record.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 5 -
1 file changed, 4 insertions(+), 1
We cannot reuse the SVE functions for LD[1-4] and ST[1-4],
because those functions accept only a Zreg register number.
For SME, we want to pass a pointer into ZA storage.
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 82 +
target/arm/sme.decode | 9 +
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 5 +++
target/arm/sme.decode | 9 +
target/arm/sme_helper.c| 67 ++
target/arm/translate-sme.c | 33 +++
4 files changed, 114 insertions(+)
diff --git
These prctl set the Streaming SVE vector length, which may
be completely different from the Normal SVE vector length.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_prctl.h | 48 +++
linux-user/syscall.c | 16 +++
2 files changed,
On 6/20/22 10:42, Warner Losh wrote:
+static abi_long do_bsd_readlink(CPUArchState *env, abi_long arg1,
+abi_long arg2, abi_long arg3)
+{
+abi_long ret;
+void *p1, *p2;
+
+LOCK_PATH(p1, arg1);
+p2 = lock_user(VERIFY_WRITE, arg2, arg3, 0);
+if (p2 == NULL) {
+
Note that SME remains effectively disabled for user-only,
because we do not yet set CPACR_EL1.SMEN. This needs to
wait until the kernel ABI is implemented.
Signed-off-by: Richard Henderson
---
docs/system/arm/emulation.rst | 4
target/arm/cpu64.c| 11 +++
2 files
On 6/20/22 04:27, Mark Cave-Ayland wrote:
On 18/06/2022 12:01, Daniel Henrique Barboza wrote:
It is not advisable to execute an object_dynamic_cast() to poke into
bus->qbus.parent and follow it up with a C cast into the PnvPHB type we
think we got.
A better way is to access the PnvPHB
There's no reason to set CPACR_EL1.ZEN if SVE disabled.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 75295a14a3..5cb9f9f02c 100644
--- a/target/arm/cpu.c
+++
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 13 +
bsd-user/freebsd/os-syscall.c | 4
2 files changed, 17 insertions(+)
Reviewed-by: Richard Henderson
r~
On 6/20/22 10:42, Warner Losh wrote:
+/*
+ * XXX arg4 should be locked, but it isn't clear how to do that
+ * since it's it may be not be a NULL-terminated string.
it's it.
Unless you meant https://www.itsiticecream.com/ ;-)
Reviewed-by: Richard Henderson
r~
On 6/20/22 05:52, Peter Maydell wrote:
On Wed, 15 Jun 2022 at 17:43, Richard Henderson
wrote:
The bug is an uninitialized memory read, along the translate_fail
path, which results in garbage being read from iotlb_to_section,
which can lead to a crash in io_readx/io_writex.
The bug may be
On 6/20/22 01:04, Xiaojuan Yang wrote:
In order to start the latest community BIOS and kernel of LoongArch,
we have added the following patches.
This series add some functions for LoongArch, and fix some errors.
Add bios, kernel, fdt, smbios and acpi options support.
The kernel file:
*
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 19 +++
bsd-user/freebsd/os-syscall.c | 8
2 files changed, 27 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index f5375a39a2c..f11369655a0 100644
---
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 48 +++
bsd-user/freebsd/os-syscall.c | 16
2 files changed, 64 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 46 +++
bsd-user/freebsd/os-syscall.c | 16
2 files changed, 62 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 32
bsd-user/freebsd/os-syscall.c | 12
2 files changed, 44 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index 0b4b89c8d5c..79eb5a73a9b
This is CheckSMEAccess, which is the basis for a set of
related tests for various SME cpregs and instructions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 1 +
target/arm/helper.c| 52
This register is part of SME, but isn't closely related to the
rest of the extension.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 +
target/arm/helper.c | 32
2 files changed, 33 insertions(+)
diff --git
When Streaming SVE mode is enabled, the size is taken from
SMCR_ELx instead of ZCR_ELx. The format is shared, but the
set of vector lengths is not. Further, Streaming SVE does
not require any particular length to be supported.
Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM
to the
Rename from cpu_arm_{get,set}_sve_vq, and take the
ARMVQMap as the opaque parameter.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu64.c
We can reuse the SVE functions for implementing moves to/from
horizontal tile slices, but we need new ones for moves to/from
vertical tile slices.
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 11
target/arm/helper-sve.h| 2 +
target/arm/translate-a64.h | 9 +++
We can handle both exception entry and exception return by
hooking into aarch64_sve_change_el.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index
On 6/20/22 17:36, Joao Martins wrote:
> On 6/20/22 15:27, Igor Mammedov wrote:
>> On Fri, 17 Jun 2022 14:33:02 +0100
>> Joao Martins wrote:
>>> On 6/17/22 13:32, Igor Mammedov wrote:
On Fri, 17 Jun 2022 13:18:38 +0100
Joao Martins wrote:
> On 6/16/22 15:23, Igor Mammedov wrote:
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 2 ++
target/arm/sve.decode | 1 +
target/arm/sve_helper.c| 16
target/arm/translate-sve.c | 2 ++
4 files changed, 21 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
On 3/23/22 10:17, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Reorg TCG AccelOpsClass initialization to emphasis icount
mode share more code with single-threaded TCG.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops.c | 15 ---
1 file changed, 8
Currently QEMU ignores madvise(MADV_DONTNEED), which break apps that
rely on this for zeroing out memory [1]. Improve the situation by doing
a passthrough when the range in question is a host-page-aligned
anonymous mapping.
This is based on the patches from Simon Hausmann [2] and Chris Fallin
On 20/06/2022 17:21, Markus Armbruster wrote:
Laurent Vivier writes:
Copied from socket netdev file and modified to use SocketAddress
to be able to introduce new features like unix socket.
"udp" and "mcast" are squashed into dgram netdev, multicast is detected
according to the IP address
Changes for v3:
* Rebase on mainline (20 patches upstreamed; new conflicts resolved).
* Test bit 31 before disas_sme.
The first 21 patches, excepting 17, have been reviewed.
r~
Richard Henderson (51):
target/arm: Implement TPIDR2_EL0
target/arm: Add SMEEXC_EL to TB flags
target/arm:
This cpreg is used to access two new bits of PSTATE
that are not visible via any other mechanism.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 6 ++
target/arm/helper.c | 13 +
2 files changed, 19 insertions(+)
diff --git
Keep all of the error messages together. This does mean that
when setting many sve length properties we'll only generate
one error, but we only really need one.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 15 +++
1 file changed, 7
Implement the streaming mode identification register, and the
two streaming priority registers. For QEMU, they are all RES0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 33 +
1 file changed, 33 insertions(+)
diff --git
We need SVL separate from VL for RDSVL et al, as well as
ZA storage loads and stores, which do not require PSTATE.SM.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 12
target/arm/translate.h | 1 +
target/arm/helper.c| 8
These two instructions are aliases of MSR (immediate).
Use the two helpers to properly implement svcr_write.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 +
target/arm/helper-sme.h| 21 +
target/arm/helper.h| 1 +
Add a TCGv_ptr base argument, which will be cpu_env for SVE.
We will reuse this for SME save and restore array insns.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 3 +++
target/arm/translate-sve.c | 48 --
2 files changed, 39
Drop the aa32-only inline fallbacks,
and just use a couple of ifdefs.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 --
target/arm/internals.h | 3 +++
target/arm/cpu.c | 2 ++
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git
This new behaviour is in the ARM pseudocode function
AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
the trap would be delivered is in AArch64 mode.
Given that ARMv9 drops support for AArch32 outside EL0,
the trap EL detection ought
We can reuse the SVE functions for LDR and STR, passing in the
base of the ZA vector and a zero offset.
Signed-off-by: Richard Henderson
---
target/arm/sme.decode | 7 +++
target/arm/translate-sme.c | 23 +++
2 files changed, 30 insertions(+)
diff --git
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