On Sun, 3 Jul 2022 at 09:25, Richard Henderson
wrote:
>
> This is a major reorg to arm page table walking. While the result
> here is "merely" Hardware-assited Access Flag and Dirty Bit Setting
> (HAFDBS), the ultimate goal is the Realm Management Extension (RME).
> RME "recommends" that HAFDBS
We're about to start validating PAGE_EXEC, which means that we've
got to mark page zero executable. We had been special casing this
entirely within translate.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 34 +++---
1 file changed, 31 insertions(+), 3
The base qemu_ram_addr_from_host function is already in
softmmu/physmem.c; move the nofail version to be adjacent.
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 1 +
accel/tcg/cputlb.c| 12
softmmu/physmem.c | 12
3 files changed, 13
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 10 +-
accel/tcg/cputlb.c | 8
accel/tcg/plugin-gen.c | 4 ++--
accel/tcg/user-exec.c | 4 ++--
4 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/include/exec/exec-all.h
Reuse the result that we just used with tb_lookup.
Pass in host_pc while touching these lines, to be used shortly.
We must widen the scope of the mmap_lock, so that the page table
lookup that is finally used is covered by the lock.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h
On Thu, 2022-08-11 at 08:42 -0700, Richard Henderson wrote:
> On 8/11/22 02:28, Ilya Leoshkevich wrote:
> > How is qemu-user's get_page_addr_code() involved here?
> >
> > I tried to experiment with it, and while I agree that it looks
> > buggy,
> > it's called only from translation code paths. If
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
Let's flip the switch.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
On Thu, Aug 4, 2022 at 12:44 PM Marc-André Lureau
wrote:
> Hi
>
> Great work so far! This seems easier to hack than my attempt to use
> clang-tidy to write some qemu checks
> (https://github.com/elmarco/clang-tools-extra)
>
> The code seems quite generic, I wonder if such a tool in python wasn't
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
User creatable root ports are being parented by the 'peripheral' or the
'peripheral-anon' container. This happens because this is the regular
QOM schema for sysbus devices that are added via the command line.
Let's make this QOM hierarchy
Bool is more appropriate type for the alloc parameter.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index cf99b2b876..65a23f47d6 100644
---
This function is used only once, so merge it into
its only caller, tb_lookup. This requires moving
the support routine, tb_lookup_cmp, and its private
data structure, tb_desc, up in the file.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 3 -
accel/tcg/cpu-exec.c| 134
The current implementation is a no-op, simply returning addr.
This is incorrect, because we ought to be checking the page
permissions for execution.
Make get_page_addr_code inline for both implementations.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 85
On 8/12/22 09:31, Peter Maydell wrote:
Is it possible to rearrange this patchset so the easy
refactoring patches that do "use a struct to return
values from get_phys_addr and friends" are at the front
(ie before the stuff that touches core code) ?
That way they're easy to take into the tree
Cache the translation from guest to host address, so we may
use direct loads when we hit on the primary translation page.
Look up the second translation page only once, during translation.
This obviates another lookup of the second page within tb_gen_code
after translation.
Fixes a bug in that
Use the pc coming from db->pc_first rather than the TB.
Use the cached host_addr rather than re-computing for the
first page. We still need a separate lookup for the second
page because it won't be computed for DisasContextBase until
the translator actually performs a read from the page.
On 8/12/22 10:41, Peter Maydell wrote:
cpu64.c has ended up in a slightly odd order -- it starts with the
initfns for most of the models-real-hardware CPUs; after that comes a
bunch of support code for SVE, SME, pauth and LPA2 properties. Then
come the initfns for the 'host' and 'max' CPU
On Fri, Aug 12, 2022 at 10:30 PM Victor Toso wrote:
>
> Hi,
>
> On Fri, Aug 12, 2022 at 06:10:31PM -0700, Joelle van Dyne wrote:
> > When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
> > setting up the hello packet (just as with "-incoming". On the latest version
> > of
On Fri, Aug 12, 2022 at 7:32 PM Richard Henderson
wrote:
>
> On 8/12/22 17:50, Furquan Shaikh wrote:
> >> Why do you need such fine-grained control? What is the use-case?
> >
> > I ran into a problem when I was testing a project (with a microkernel
> > in M-mode and tasks in U-mode) that uses
Hi,
On Fri, Aug 12, 2022 at 06:10:31PM -0700, Joelle van Dyne wrote:
> When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
> setting up the hello packet (just as with "-incoming". On the latest version
> of libusbredir, usbredirparser_unserialize() will return error if the
Hi,
On Fri, Aug 12, 2022 at 10:33:54PM -0700, Joelle van Dyne wrote:
> On Fri, Aug 12, 2022 at 10:30 PM Victor Toso wrote:
> >
> > Hi,
> >
> > On Fri, Aug 12, 2022 at 06:10:31PM -0700, Joelle van Dyne wrote:
> > > When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
> > >
On Fri, Aug 12, 2022 at 10:50 PM Victor Toso wrote:
>
> Hi,
>
> On Fri, Aug 12, 2022 at 10:33:54PM -0700, Joelle van Dyne wrote:
> > On Fri, Aug 12, 2022 at 10:30 PM Victor Toso wrote:
> > >
> > > Hi,
> > >
> > > On Fri, Aug 12, 2022 at 06:10:31PM -0700, Joelle van Dyne wrote:
> > > > When
On 8/11/22 13:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different privilege levels - M, S, U, VS, VU. As per the
On Fri, Aug 12, 2022 at 4:00 PM Palmer Dabbelt wrote:
>
> On Fri, 12 Aug 2022 15:05:08 PDT (-0700), furq...@rivosinc.com wrote:
> > On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones
> > wrote:
> >>
> >> On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> >> > Unlike ARM, RISC-V does
On Fri, Aug 12, 2022 at 4:42 PM Richard Henderson
wrote:
>
> On 8/12/22 16:27, Richard Henderson wrote:
> > On 8/11/22 13:41, Furquan Shaikh wrote:
> >> Unlike ARM, RISC-V does not define a separate breakpoint type for
> >> semihosting. Instead, it is entirely ABI. Thus, we need an option
> >> to
On 8/12/22 16:57, Furquan Shaikh wrote:
I am not sure if I understood your comment correctly. Currently, qemu
has a check in `riscv_cpu_do_interrupt` to allow semihosting calls
only in S and M modes. This prevents semihosting calls from U mode.
This patch changes the default behavior of checking
On Fri, Aug 12, 2022 at 5:30 PM Richard Henderson
wrote:
>
> On 8/12/22 16:57, Furquan Shaikh wrote:
> > I am not sure if I understood your comment correctly. Currently, qemu
> > has a check in `riscv_cpu_do_interrupt` to allow semihosting calls
> > only in S and M modes. This prevents
Run state is also in RUN_STATE_PRELAUNCH while "-S" is used.
This reverts commit 12d182898a4866e4be418e2abac286b497cfa1b2.
Signed-off-by: Joelle van Dyne
---
hw/usb/redirect.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
index
On 8/12/22 17:50, Furquan Shaikh wrote:
Why do you need such fine-grained control? What is the use-case?
I ran into a problem when I was testing a project (with a microkernel
in M-mode and tasks in U-mode) that uses semihosting for debugging.
The semihosting worked fine for M-mode but not in
On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones wrote:
>
> On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> > Unlike ARM, RISC-V does not define a separate breakpoint type for
> > semihosting. Instead, it is entirely ABI. Thus, we need an option
> > to allow users to configure what
David,
On 8/8/22 00:23, David Gibson wrote:
On Fri, Aug 05, 2022 at 06:39:29AM -0300, Daniel Henrique Barboza wrote:
At this moment, arm_load_dtb() can free machine->fdt when
binfo->dtb_filename is NULL. If there's no 'dtb_filename', 'fdt' will be
retrieved by binfo->get_dtb(). If get_dtb()
When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
setting up the hello packet (just as with "-incoming". On the latest version
of libusbredir, usbredirparser_unserialize() will return error if the parser
is not "pristine."
Signed-off-by: Joelle van Dyne
---
Previously, there was a bug in usbredir which prevented "-loadvm" from working
because libusbredir's usbredirparser_unserialize() fails when a HELLO packet is
sent as part of the device's initalization.
The fix was to not send HELLO when in the RUN_STATE_PRELAUNCH state. However,
recently we
This allows us to differentiate between a fresh boot and a restore boot.
Signed-off-by: Joelle van Dyne
---
softmmu/runstate.c | 1 +
softmmu/vl.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/softmmu/runstate.c b/softmmu/runstate.c
index 1e68680b9d..fa3dd3a4ab 100644
---
ull-target-arm-20220812
for you to fetch changes up to 4311682ea8293f720730f260e8a7601117d79e65:
cutils: Add missing dyld(3) include on macOS (2022-08-12 11:33:52 +0100)
target-arm queue:
* Don't report Statistical Profiling
On Fri, 12 Aug 2022 15:05:08 PDT (-0700), furq...@rivosinc.com wrote:
On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones wrote:
On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely
On Fri, Aug 12, 2022 at 4:28 AM Peter Maydell wrote:
>
> On Thu, 11 Aug 2022 at 21:47, Furquan Shaikh wrote:
> >
> > Unlike ARM, RISC-V does not define a separate breakpoint type for
> > semihosting. Instead, it is entirely ABI. Thus, we need an option
> > to allow users to configure what the
On 8/8/22 00:26, David Gibson wrote:
On Fri, Aug 05, 2022 at 06:39:38AM -0300, Daniel Henrique Barboza wrote:
The pSeries machine never bothered with the common machine->fdt
attribute. We do all the FDT related work using spapr->fdt_blob.
We're going to introduce HMP commands to read and
On 8/12/22 16:27, Richard Henderson wrote:
On 8/11/22 13:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different
Function "update_rx_fifo()" should operate on the RX FIFO
registers, not the TX FIFO ones.
Signed-off-by: Anton Kochkov
Resolves: https://gitlab.com/qemu-projects/qemu/-/issues/1123
---
hw/net/can/xlnx-zynqmp-can.c | 32
1 file changed, 16 insertions(+), 16
Unlike ARM, RISC-V does not define a separate breakpoint type for
semihosting. Instead, it is entirely ABI. Thus, we need an option
to allow users to configure what the ebreak behavior should be for
different privilege levels - M, S, U, VS, VU. As per the RISC-V
privilege specification[1], ebreak
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