Re: [PATCH 01/42] hw/i386/pc: Create DMA controllers in south bridges

On 1/9/22 18:25, Bernhard Beschow wrote: Just like in the real hardware (and in PIIX4), create the DMA controllers in the south bridges. Signed-off-by: Bernhard Beschow --- hw/i386/pc.c | 3 --- hw/i386/pc_piix.c | 2 ++ hw/isa/Kconfig| 2 ++ hw/isa/lpc_ich9.c | 3 +++

Re: [PATCH 05/42] hw/isa/piix3: Create USB controller in host device

On 1/9/22 18:25, Bernhard Beschow wrote: The USB controller is an integral part of PIIX3 (function 2). So create it as part of the south bridge. Note that the USB function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init.

Re: [PATCH 31/51] tests/qtest: Support libqtest to build and run on Windows

Hi On Wed, Aug 24, 2022 at 2:46 PM Bin Meng wrote: > From: Bin Meng > > At present the libqtest codes were written to depend on several > POSIX APIs, including fork(), kill() and waitpid(). Unfortunately > these APIs are not available on Windows. > > This commit implements the corresponding

Re: [PATCH v2 00/10] qapi examples fixes, simplified version

Victor Toso writes: > Hi, > > This is the follow up from v1. I've dropped a few patches that need > further discussion. I plan to revisit those when submiting the generator > again at a later time. Reviewed-by: Markus Armbruster and queued. Thanks! [...]

Re: [PATCH 48/51] io/channel-watch: Drop a superfluous '#ifdef WIN32'

On Wed, Aug 24, 2022 at 2:37 PM Bin Meng wrote: > From: Bin Meng > > In the win32 version qio_channel_create_socket_watch() body there is > no need to do a '#ifdef WIN32'. > > Signed-off-by: Bin Meng > Reviewed-by: Marc-André Lureau > --- > > io/channel-watch.c | 2 -- > 1 file changed, 2

[PATCH 01/19] target/ppc: Remove extra space from s128 field in ppc_vsr_t

Very trivial rogue space removal. There are two spaces between Int128 and s128 in ppc_vsr_t struct, where it should be only one. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index

Re: [PATCH] io/command: implement portable spawn

Hi On Thu, Sep 1, 2022 at 5:00 PM Daniel P. Berrangé wrote: > > On Thu, Sep 01, 2022 at 03:15:53PM +0400, marcandre.lur...@redhat.com wrote: > > From: Marc-André Lureau > > > > Using GLib spawn API is both simpler and portable. > > > > Signed-off-by: Marc-André Lureau > > --- > >

[PATCH 10/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_FP

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index ceb70ed36e..8a20413a78 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2692,6 +2692,8 @@ void

[PATCH 19/19] target/ppc: Clear fpstatus flags on VSX_ROUND

Fix xsrdpic and other instructions not clearing the flags and saving incorrect values to FPSCR. Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index fd3a966371..be47d73b14 100644

Re: [PATCH 09/10] hw/arm/virt: Fix devicetree warnings about the SMMU node

On Wed, Aug 24, 2022 at 08:45:05PM +0100, Peter Maydell wrote: > On Wed, 24 Aug 2022 at 16:51, Jean-Philippe Brucker > wrote: > > > > dt-validate reports three issues in the SMMU device-tree node: > > > > smmuv3@905: $nodename:0: 'smmuv3@905' does not match > > '^iommu@[0-9a-f]*' > >

[PATCH v5 12/13] hw/isa/vt82c686: Embed RTCState in host device

Embed the rtc in the host device, analoguous to the other child devices and analoguous to PIIX4. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index

[PATCH v5 02/13] hw/isa/vt82c686: Resolve unneeded attribute

Now that also the super io device is realized in the common realize method, the isa_bus attribute can be turned into a temporary. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/isa/vt82c686.c

[PATCH v5 10/13] hw/isa/vt82c686: Instantiate AC97 and MC97 functions in host device

The AC97 function's wakeup status is wired to the PM function and both the AC97 and MC97 interrupt routing is determined by the ISA function. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 16 hw/mips/fuloong2e.c | 4 hw/ppc/pegasos2.c | 5 - 3 files

Re: [PATCH 47/51] tests/qtest: libqtest: Correct the timeout unit of blocking receive calls for win32

Hi On Wed, Aug 24, 2022 at 3:44 PM Bin Meng wrote: > From: Bin Meng > > Some qtest cases don't get response from the the QEMU executable > "the the" > under test in time on Windows. It turns out that the socket receive > call got timeout before it receive the complete response. > > The

Re: [PATCH 46/51] tests/qtest: libqtest: Replace the call to close a socket with closesocket()

On Wed, Aug 24, 2022 at 3:09 PM Bin Meng wrote: > From: Bin Meng > > close() is a *nix function. It works on any file descriptor, and > sockets in *nix are an example of a file descriptor. > > closesocket() is a Windows-specific function, which works only > specifically with sockets. Sockets on

Re: [PATCH 44/51] tests/qtest: microbit-test: Fix socket access for win32

On Wed, Aug 24, 2022 at 3:27 PM Bin Meng wrote: > From: Bin Meng > > Sockets on Windows do not use *nix-style file descriptors, so > write()/read()/close() do not work on Windows. > > Switch over to use send()/recv()/closesocket() which work with > sockets on all platforms. > > Signed-off-by:

Re: [PATCH v5 00/13] Instantiate VT82xx functions in host device

On Thu, Sep 1, 2022 at 1:41 PM Bernhard Beschow wrote: > v5: > * Add patch "Inline vt82c686b_southbridge_init() and remove it" (Zoltan) > * Use machine parameter when creating rtc-time alias (Zoltan) > > Testing done: Same as in v3. > > v4: > * Fix in comment: AC97 Modem -> MC97 Modem (Zoltan) >

[PATCH 16/19] target/ppc: Clear fpstatus flags for xscvqpdp

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 627166672c..51142bd7d5 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2842,6 +2842,8 @@ void

Re: [PATCH 05/10] hw/arm/virt: Fix devicetree warning about the timer node

On Wed, Aug 24, 2022 at 08:40:21PM +0100, Peter Maydell wrote: > On Wed, 24 Aug 2022 at 16:51, Jean-Philippe Brucker > wrote: > > > > The compatible property of the Arm timer should contain either > > "arm,armv7-timer" or "arm,armv8-timer", not both. > > > > timer: compatible: 'oneOf'

[PATCH v5 09/13] hw/isa/vt82c686: Instantiate PM function in host device

The PM controller has activity bits which monitor activity of other built-in devices in the host device. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 13 + hw/mips/fuloong2e.c | 2 +- hw/ppc/pegasos2.c | 3 +-- include/hw/isa/vt82c686.h | 2 -- 4

[PATCH v5 00/13] Instantiate VT82xx functions in host device

v5: * Add patch "Inline vt82c686b_southbridge_init() and remove it" (Zoltan) * Use machine parameter when creating rtc-time alias (Zoltan) Testing done: Same as in v3. v4: * Fix in comment: AC97 Modem -> MC97 Modem (Zoltan) * Introduce TYPE_VT82C686B_USB_UHCI define (Zoltan) * Introduce

[PATCH 04/19] target/ppc: Set result to QNaN for DENBCD when VXCVI occurs

According to the ISA, for instruction DENBCD: "If an invalid BCD digit or sign code is detected in the source operand, an invalid-operation exception (VXCVI) occurs." In the Invalid Operation Exception section, there is the situation: "When Invalid Operation Exception is disabled (VE=0) and

[PATCH 06/19] target/ppc: Set OV32 when OV is set

According to PowerISA: "OV32 is set whenever OV is implicitly set, and is set to the same value that OV is defined to be set to in 32-bit mode". This patch changes helper_update_ov_legacy to set/clear ov32 when applicable. Signed-off-by: Víctor Colombo --- target/ppc/int_helper.c | 4 ++-- 1

Re: [PATCH v1 03/16] qapi: fix example of query-spice command

Hi, > I agree listing more channels in the example wouldn't help users. > > But do we want to indicate that the example is abridged? Hard to do if the result should be valid qmp ... Maybe add a second channel to clearly show the command returns a list of channels? I'm also curious why you

Re: TCG IR extraction

Tom Clark writes: > Hello, > > Thanks so much for reading this and I appreciate any and all time you put > into this. > > I'm a dev working on a project that's using QEMU as its basis. I'm interested > in extracting the IR representation of > translation blocks, preferably at the instruction

[PATCH 2/3] iotests: Test qemu-img checksum

Add simple tests creating an image with all kinds of extents, different formats, different backing chain, different protocol, and different image options. Since all images have the same guest visible content they must have the same checksum. To help debugging in case of failures, the output

[PATCH 3/3] qemu-img: Speed up checksum

Add coroutine based loop inspired by `qemu-img convert` design. Changes compared to `qemu-img convert`: - State for the entire image is kept in ImgChecksumState - State for single worker coroutine is kept in ImgChecksumworker. - "Writes" are always in-order, ensured using a queue. - Calling

Re: [PATCH 03/10] hw/arm/virt: Fix devicetree warnings about the GIC node

On Wed, Aug 24, 2022 at 08:36:33PM +0100, Peter Maydell wrote: > On Wed, 24 Aug 2022 at 16:51, Jean-Philippe Brucker > wrote: > > > > Fix three dt-validate warnings about the GIC node due to invalid names > > and missing property: > > > > intc@800: $nodename:0: 'intc@800' does not match

[PATCH v5 08/13] hw/isa/vt82c686: Instantiate USB functions in host device

The USB functions can be enabled/disabled through the ISA function. Also its interrupt routing can be influenced there. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 12 hw/mips/fuloong2e.c | 3 --- hw/ppc/pegasos2.c | 4 3 files changed, 12 insertions(+), 7

[PATCH v5 01/13] hw/isa/vt82c686: Resolve chip-specific realize methods

The object creation now happens in chip-specific init methods which allows the realize methods to be consolidated into one method. Shifting the logic into the init methods has the addidional advantage that the parent object's init methods are called implicitly - like constructors in

Re: [PATCH] docs: clarify absence of set_features in vhost-user

Alyssa Ross writes: > The previous wording was (at least to me) ambiguous about whether a > backend should enable features immediately after they were set using > VHOST_USER_SET_PROTOCOL_FEATURES, or wait for support for protocol > features to be acknowledged if it hasn't been yet before

Re: [PATCH v3 06/10] hw/isa/vt82c686: Instantiate USB functions in host device

On Wed, Aug 31, 2022 at 6:02 PM BALATON Zoltan wrote: > On Wed, 31 Aug 2022, BB wrote: > > Am 31. August 2022 17:03:35 MESZ schrieb BALATON Zoltan < > bala...@eik.bme.hu>: > >> On Wed, 31 Aug 2022, BB wrote: > >>> Am 31. August 2022 15:23:37 MESZ schrieb BALATON Zoltan < > bala...@eik.bme.hu>: >

[PATCH 05/19] target/ppc: Zero second doubleword for VSX madd instructions

In 205eb5a89e we updated most VSX instructions to zero the second doubleword, as is requested by PowerISA since v3.1. However, VSX_MADD helper was left behind unchanged, while it is also affected and should be fixed as well. This patch applies the fix for MADD instructions. Signed-off-by: Víctor

[PATCH 11/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_INT_VECTOR

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 8a20413a78..c6dc14d653 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3024,6 +3024,8 @@

[PATCH 08/19] target/ppc: Clear fpstatus flags on VSX_CVT_INT_TO_FP_VECTOR

Fix xscvsdqp incorrectly not clearing the FI bit. Power ISA states that xscvsdqp should always set FPSCR.FI=0 Right now, QEMU sometimes is incorrectly setting the flag to 1. Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH 07/19] target/ppc: Zero second doubleword of VSR registers for FPR insns

FPR register are mapped to the first doubleword of the VSR registers. Since PowerISA v3.1, the second doubleword of the target register must be zeroed for FP instructions. This patch does it by writting 0 to the second dw everytime the first dw is being written using set_fpr. Signed-off-by:

[PATCH 15/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_FP_VECTOR

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 39f0ec7431..627166672c 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2756,6 +2756,8 @@ void

Re: [PATCH] osdep: Introduce qemu_get_fd() to wrap the common codes

On Mittwoch, 31. August 2022 10:25:27 CEST Guoyi Tu wrote: > On 8/18/22 20:58, Christian Schoenebeck wrote: > > On Donnerstag, 18. August 2022 14:06:04 CEST Guoyi Tu wrote: > >> Ping... > >> > >> Any comments are welcome > >> > >> On 8/12/22 19:01, Guoyi Tu wrote: > >>> socket_get_fd() have much

Re: [PATCH v2] target/sh4: Fix TB_FLAG_UNALIGN

On Thu, 01 Sep 2022 19:15:09 +0900, Richard Henderson wrote: > > The value previously chosen overlaps GUSA_MASK. > > Rename all DELAY_SLOT_* and GUSA_* defines to emphasize > that they are included in TB_FLAGs. Add aliases for the > FPSCR and SR bits that are included in TB_FLAGS, so that > we

Re: 回复：Any interest in a QEMU emulation BoF at KVM Forum?

"刘志伟" writes: > These topics are interesting. I have two questions. > > 1. Can we join it on online? If so, could you share the meeting link before > the meeting. > > 2. If it is only offline, could you share the meeting content to the > public? I've created an etherpad for the day (which

Re: [PATCH 0/2] expose host-phys-bits to guest

On 9/1/22 08:07, Xiaoyao Li wrote: > On 8/31/2022 8:50 PM, Gerd Hoffmann wrote: >> When the guest (firmware specifically) knows how big >> the address space actually is it can be used better. >> >> Some more background: >>https://bugzilla.redhat.com/show_bug.cgi?id=2084533 > > QEMU enables

[PATCH v5 07/13] hw/isa/vt82c686: Introduce TYPE_VT82C686B_USB_UHCI define

Suggested-by: BALATON Zoltan Signed-off-by: Bernhard Beschow --- hw/mips/fuloong2e.c| 4 ++-- hw/ppc/pegasos2.c | 4 ++-- hw/usb/vt82c686-uhci-pci.c | 4 ++-- include/hw/isa/vt82c686.h | 1 + 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/mips/fuloong2e.c

[PATCH v5 05/13] hw/isa/vt82c686: Introduce TYPE_VIA_IDE define

Establishes consistency with other (VIA) devices. Signed-off-by: Bernhard Beschow --- hw/ide/via.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/ppc/pegasos2.c | 2 +- include/hw/isa/vt82c686.h | 1 + 4 files changed, 4 insertions(+), 3 deletions(-) diff --git

[PATCH v5 06/13] hw/isa/vt82c686: Instantiate IDE function in host device

The IDE function is closely tied to the ISA function (e.g. the IDE interrupt routing happens there), so it makes sense that the IDE function is instantiated within the south bridge itself. Signed-off-by: Bernhard Beschow --- configs/devices/mips64el-softmmu/default.mak | 1 - hw/isa/Kconfig

[PATCH v5 04/13] hw/isa/vt82c686: Reuse errp

Rather than terminating abruptly, make use of the already present errp and propagate the error to the caller. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index

[PATCH v5 11/13] hw/mips/fuloong2e: Inline vt82c686b_southbridge_init() and remove it

The previous patches moved most of this function into the via-isa device model such that it has become fairly trivial. So inline it for simplicity. Suggested-by: BALATON Zoltan Signed-off-by: Bernhard Beschow --- hw/mips/fuloong2e.c | 28 ++-- 1 file changed, 10

[PATCH v5 13/13] hw/isa/vt82c686: Create rtc-time alias in boards instead

According to good QOM practice, an object should only deal with objects of its own sub tree. Having devices create an alias on the machine object doesn't respect this good practice. To resolve this, create the alias in the machine's code. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c

Re: [PATCH] io/command: implement portable spawn

On Thu, Sep 01, 2022 at 03:15:53PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Using GLib spawn API is both simpler and portable. > > Signed-off-by: Marc-André Lureau > --- > io/channel-command.c | 115 --- > 1 file changed,

[PATCH 00/19] Multiple ppc instructions fixes

This patch set fixes multiple instructions for PPC targets that were producing incorrect results, or setting the wrong bits in FPSCR. Patch 1 is just a style fix, trivial. Patches 8 through 19 add helper_reset_fpstatus() calls to instructions that have an issue where the exception flags are

[PATCH 03/19] target/ppc: Zero second doubleword in DFP instructions

Starting at PowerISA v3.1, the second doubleword of the registers used to store results in DFP instructions are supposed to be zeroed. >From the ISA, chapter 7.2.1.1 Floating-Point Registers: """ Chapter 4. Floating-Point Facility provides 32 64-bit FPRs. Chapter 5. Decimal Floating-Point also

[PATCH 02/19] target/ppc: Remove unused xer_* macros

The macros xer_ov, xer_ca, xer_ov32, and xer_ca32 are both unused and hiding the usage of env. Remove them. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 4 1 file changed, 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 985ff86f55..6481f48087 100644 ---

[PATCH 12/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_INT2

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c6dc14d653..6f9a1a755e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2981,12

[PATCH 17/19] target/ppc: Clear fpstatus flags for xscvdpsp[n]

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 51142bd7d5..5f7f52ab5b 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2719,6 +2719,8 @@ void

[PATCH 1/3] qemu-img: Add checksum command

The checksum command compute a checksum for disk image content using the blkhash library[1]. The blkhash library is not packaged yet, but it is available via copr[2]. Example run: $ ./qemu-img checksum -p fedora-35.qcow2 6e5c00c995056319d52395f8d91c7f84725ae3da69ffcba4de4c7d22cff713a5

Re: Any interest in a QEMU emulation BoF at KVM Forum?

I'm very interested too. Thanks for organizing this, Alex! In particular we're interested in the infrastructure work to enable having a single build of QEMU using several different TCG frontends, which is probably preliminary to heterogeneous vCPU emulation. In fact, I was going to send an RFC

[PATCH v5 03/13] hw/isa/vt82c686: Prefer pci_address_space() over get_system_memory()

Unlike get_system_memory(), pci_address_space() respects the memory tree available to the parent device. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 9d12e1cae4..5582c0b179

Re: [Qemu-devel] [RFC PATCH] Add qemu .clang-format

"Wang, Lei" writes: > On 9/1/2022 4:12 PM, Daniel P. Berrangé wrote: >> On Thu, Sep 01, 2022 at 09:08:33AM +0800, Wang, Lei wrote: >>> On 8/31/2022 6:39 PM, Daniel P. Berrangé wrote: On Wed, Aug 31, 2022 at 05:18:34PM +0800, Wang, Lei wrote: > > > On 8/31/2022 4:49 PM, Daniel

Re: [PATCH 51/51] docs/devel: testing: Document writing portable test cases

Hi On Wed, Aug 24, 2022 at 2:57 PM Bin Meng wrote: > From: Bin Meng > > Update the best practices of how to write portable test cases that > can be built and run successfully on both Linux and Windows hosts. > > Signed-off-by: Bin Meng > Reviewed-by: Marc-André Lureau > --- > >

[PATCH 14/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_FP_HP

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index eb16fb20a9..39f0ec7431 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2791,6 +2791,8 @@ void

Re: [PATCH v3 06/10] hw/isa/vt82c686: Instantiate USB functions in host device

On Thu, 1 Sep 2022, Bernhard Beschow wrote: On Wed, Aug 31, 2022 at 6:02 PM BALATON Zoltan wrote: On Wed, 31 Aug 2022, BB wrote: Am 31. August 2022 17:03:35 MESZ schrieb BALATON Zoltan < bala...@eik.bme.hu>: On Wed, 31 Aug 2022, BB wrote: Am 31. August 2022 15:23:37 MESZ schrieb BALATON

[PATCH 18/19] target/ppc: Clear fpstatus flags on VSX_CMP

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 5f7f52ab5b..fd3a966371 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2639,6 +2639,8 @@ uint32_t

Re: [PATCH 0/2] expose host-phys-bits to guest

Hi, > I think the problem is for all the named CPU model, that they don't have > phys_bits defined. Thus they all have "cpu->phys-bits == 0", which leads to > cpu->phys_bits = TCG_PHYS_ADDR_BITS (36 for 32-bits build and 40 for 64-bits > build) Exactly. And if you run on hardware with

Re: 回复：Any interest in a QEMU emulation BoF at KVM Forum?

"刘志伟" writes: > These topics are interesting. I have two questions. > > 1. Can we join it on online? If so, could you share the meeting link > before the meeting. I will try to find out. > > 2. If it is only offline, could you share the meeting content to the > public? I'll certainly try

Re: [PATCH 0/2] expose host-phys-bits to guest

On 9/1/2022 9:58 PM, Gerd Hoffmann wrote: Anyway, IMO, guest including guest firmware, should always consult from CPUID leaf 0x8008 for physical address length. It simply can't for the reason outlined above. Even if we fix qemu today that doesn't solve the problem for the firmware

Re: [PATCH 02/10] hw/arm/boot: Fix devicetree warning about the PSCI node

On Wed, Aug 24, 2022 at 08:33:54PM +0100, Peter Maydell wrote: > On Wed, 24 Aug 2022 at 16:51, Jean-Philippe Brucker > wrote: > > > > dt-validate warns that an implementation compatible with arm,psci-1.0 > > shouldn't have arm,psci in their compatible string. > > > > psci: compatible: 'oneOf'

Re: [PATCH v2 1/1] monitor/hmp: print trace as option in help for log command

Dongli Zhang writes: > Hi Markus, > > On 8/30/22 4:04 AM, Markus Armbruster wrote: >> Dongli Zhang writes: >> >>> The below is printed when printing help information in qemu-system-x86_64 >>> command line, and when CONFIG_TRACE_LOG is enabled: >>> >>> $ qemu-system-x86_64 -d help >>> ... ...

[PULL 02/20] linux-user/hppa: Allocate page zero as a commpage

We're about to start validating PAGE_EXEC, which means that we've got to mark page zero executable. We had been special casing this entirely within translate. Acked-by: Ilya Leoshkevich Tested-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- linux-user/elfload.c | 34

[PULL 03/20] linux-user/x86_64: Allocate vsyscall page as a commpage

We're about to start validating PAGE_EXEC, which means that we've got to mark the vsyscall page executable. We had been special casing this entirely within translate. Acked-by: Ilya Leoshkevich Tested-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- linux-user/elfload.c | 23

[PULL 11/20] accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.c

The base qemu_ram_addr_from_host function is already in softmmu/physmem.c; move the nofail version to be adjacent. Reviewed-by: Alistair Francis Acked-by: Ilya Leoshkevich Tested-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 1 + accel/tcg/cputlb.c

[PATCH v3 07/23] i386: check SSE table flags instead of hardcoding opcodes

Put more flags to work to avoid hardcoding lists of opcodes. The op7 case for SSE_OPF_CMP is included for homogeneity and because AVX needs it, but it is never used by SSE or MMX. Extracted from a patch by Paul Brook . Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 75

Re: [Qemu-devel] [RFC PATCH] Add qemu .clang-format

On 9/1/2022 4:12 PM, Daniel P. Berrangé wrote: > On Thu, Sep 01, 2022 at 09:08:33AM +0800, Wang, Lei wrote: >> On 8/31/2022 6:39 PM, Daniel P. Berrangé wrote: >>> On Wed, Aug 31, 2022 at 05:18:34PM +0800, Wang, Lei wrote: On 8/31/2022 4:49 PM, Daniel P. Berrangé wrote: > On Wed,

Re: [PATCH 04/51] semihosting/arm-compat-semi: Avoid using hardcoded /tmp

On 9/1/22 08:11, Bin Meng wrote: -len = asprintf(, "/tmp/qemu-%x%02x", getpid(), (int)arg1 & 0xff); +len = asprintf(, "%s/qemu-%x%02x", g_get_tmp_dir(), + getpid(), (int)arg1 & 0xff); This is most likely wrong. I am not familiar with semihosting, but I

Re: [PATCH v5 08/18] dump: Rename write_elf*_phdr_note to prepare_elf*_phdr_note

On Thu, 2022-08-11 at 12:11 +, Janosch Frank wrote: > The functions in question do not actually write to the file descriptor > they set up a buffer which is later written to the fd. > > Signed-off-by: Janosch Frank Reviewed-by: Janis Schoetterl-Glausch

Re: [PATCH v2 0/8] vhost-user-blk: dynamically resize config space based on features

ping

Re: [PATCH] qio: fix command spawn RDONLY/WRONLY

On Thu, Sep 01, 2022 at 02:47:17PM +0400, Marc-André Lureau wrote: > Hi > > On Thu, Sep 1, 2022 at 2:32 PM Daniel P. Berrangé > wrote: > > > On Thu, Sep 01, 2022 at 02:11:20PM +0400, marcandre.lur...@redhat.com > > wrote: > > > From: Marc-André Lureau > > > > > > The in/out handling is

Re: [PATCH v1 12/16] qapi: fix example of blockdev-add command

Victor Toso writes: > Hi, > > First of all, I'm happy that this patch got us into this > discussion. Me too! > On Wed, Aug 31, 2022 at 04:53:49PM +0200, Markus Armbruster wrote: >> Victor Toso writes: >> >> > Hi, >> > >> > On Wed, Aug 31, 2022 at 03:16:54PM +0200, Markus Armbruster wrote: >>

Re: [PATCH 11/42] hw/isa/piix3: Remove extra '; ' outside of functions

On 1/9/22 18:25, Bernhard Beschow wrote: Fixes the "extra-semi" clang-tidy check. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/isa/piix3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PULL v2 00/60] ppc queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH 25/42] hw/isa/piix4: Move pci_ide_create_devs() call to board code

On 1/9/22 18:25, Bernhard Beschow wrote: For the VIA south bridges there was a comment to have the call in board code. Move it there for PIIX4 as well for consistency. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 1 - hw/mips/malta.c | 10 ++ 2 files changed, 6

[RFC 3/4] tcg/plugins: Support for inter-plugin interactions

Expand tcg-plugin system to allow for plugins to export functions and callbacks that can be used by other plugins. Exported functions can be called at runtime by other loaded plugins. Loaded plugins can register functions with exported callbacks and have these functions run whenever the callback

Re: [PULL 00/20] tcg patch queue

clang builds are failing: clang -m64 -mcx16 -Ilibqemu-alpha-softmmu.fa.p -I. -I.. -Itarget/alpha -I../target/alpha -Iqapi -Itrace -Iui -Iui/shader -I/usr/include/pixman-1 -I/usr/include/capstone -I/usr/include/spice-server -I/usr/include/spice-1 -I/usr/include/cacard -I/usr/include/glib-2.0

[PATCH 3/4] hw/timer: ibex_timer.c: Update register addresses

Updates the register addresses to match the OpenTitan spec. These changes were made in this commit: https://github.com/lowRISC/opentitan/commit/a25e162b8f91bd0ca32258c83d1d480f93327204 Signed-off-by: Tyler Ng --- hw/timer/ibex_timer.c | 20 ++-- 1 file changed, 10

[PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

Fixes a bug in which the index of the interrupt priority is off by 1. For example, using an IRQ number of 3 with a priority of 1 is supposed to set plic->source_priority[2] = 1, but instead it sets plic->source_priority[3] = 1. When an interrupt is claimed to be serviced, it checks the index 2

Re: [PATCH v8 3/7] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls

On 9/1/22 23:57, Markus Armbruster wrote: > Sam Li writes: > >> Markus Armbruster 于2022年8月31日周三 16:35写道： >>> >>> Sam Li writes: >>> Markus Armbruster 于2022年8月30日周二 19:57写道： > > Sam Li writes: > >> By adding zone management operations in BlockDriver, storage controller

Re: [PATCH v1 15/40] i386/tdx: Add property sept-ve-disable for tdx-guest object

On Fri, Sep 02, 2022, Xiaoyao Li wrote: > On 8/26/2022 1:57 PM, Gerd Hoffmann wrote: > >Hi, > > > For TD guest kernel, it has its own reason to turn SEPT_VE on or off. > > > E.g., > > > linux TD guest requires SEPT_VE to be disabled to avoid #VE on syscall gap > > > [1]. > > > > Why is that

Re: [PATCH v1 15/40] i386/tdx: Add property sept-ve-disable for tdx-guest object

On Fri, Sep 02, 2022 at 02:52:25AM +, Sean Christopherson wrote: > On Fri, Sep 02, 2022, Xiaoyao Li wrote: > > On 8/26/2022 1:57 PM, Gerd Hoffmann wrote: > > >Hi, > > > > For TD guest kernel, it has its own reason to turn SEPT_VE on or off. > > > > E.g., > > > > linux TD guest requires

[PATCH] RISC-V: Add support for Ztso

Ztso, the RISC-V extension that provides the TSO memory model, was recently frozen. This provides support for Ztso on targets that are themselves TSO. Signed-off-by: Palmer Dabbelt --- My first thought was to just add the TCG barries to load/store and AMOs that as defined by Ztso, but after

Re: [PATCH v3 1/3] util/main-loop: Fix maximum number of wait objects for win32

On Wed, Aug 24, 2022 at 4:52 PM Bin Meng wrote: > > From: Bin Meng > > The maximum number of wait objects for win32 should be > MAXIMUM_WAIT_OBJECTS, not MAXIMUM_WAIT_OBJECTS + 1. > > Signed-off-by: Bin Meng > --- > > Changes in v3: > - move the check of adding the same HANDLE twice to a

Re: [PATCH 27/42] hw/isa/piix4: Allow board to provide PCI interrupt routes

On 1/9/22 18:25, Bernhard Beschow wrote: PIIX3 initializes the PIRQx route control registers to the default values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) April 1997 manual. PIIX4, however, initializes the routes according to the Malta™ User’s Manual, ch 6.6, which are IRQs

Re: [PATCH 42/42] hw/i386/acpi-build: Resolve PIIX ISA bridge rather than ACPI controller

On 1/9/22 18:26, Bernhard Beschow wrote: Resolving the PIIX ISA bridge rather than the PIIX ACPI controller mirrors the ICH9 code one line below. Signed-off-by: Bernhard Beschow --- hw/i386/acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c

[PATCH] Hexagon (target/hexagon) implement mutability mask for GPRs

Some registers are defined to have immutable bits, this commit will implement that behavior. Signed-off-by: Brian Cain --- target/hexagon/gen_masked.c | 44 target/hexagon/gen_masked.h | 26 target/hexagon/genptr.c | 33 -

[PATCH 0/4] Implement the OpenTitan watchdog

This patch series does three things: 1) Adds an implementation of the OpenTitan Always-On Timer's watchdog functionality 2) Fixes a bug encountered with the SiFive PLIC device during development 3) Updates the register addresses and adds support for writes to mtime for the Ibex timer (2) is

Re: [PATCH] scsi/lsi53c895a: really fix use-after-free in lsi_do_msgout (CVE-2022-0216)

Hi, On Wed, Jul 13, 2022 at 8:45 PM Paolo Bonzini wrote: > > From: Mauro Matteo Cascella > > Set current_req to NULL, not current_req->req, to prevent reusing a free'd > buffer in case of repeated SCSI cancel requests. Also apply the fix to > CLEAR QUEUE and BUS DEVICE RESET messages as well,

Re: [PATCH 14/42] hw/isa/piix3: Modernize reset handling

On 1/9/22 18:25, Bernhard Beschow wrote: Rather than registering the reset handler via a function which appends the handler to a global list, prefer to implement it as a virtual method - PIIX4 does the same already. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 8 +++- 1 file

Re: [PATCH 22/42] hw/mips/malta: Reuse dev variable

On 1/9/22 18:25, Bernhard Beschow wrote: While at it, move the assignments closer to where they are used. Signed-off-by: Bernhard Beschow --- hw/mips/malta.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 00/20] ppc4xx_sdram QOMify and clean ups

On Fri, 19 Aug 2022, BALATON Zoltan wrote: Hello, This is based on gitlab.com/danielhb/qemu/tree/ppc-7.2 Now that the queue is flushed it should apply on master so Ping Regards, BALATON Zoltan This is the end of the QOMify series started by Cédric. This series handles the SDRAM controller

Re: [RFC] hw/registerfields: add `FIELDx_1CLEAR()` macro

On 1/9/22 07:32, Richard Henderson wrote: On 9/1/22 02:02, Wilfred Mallawa wrote: From: Wilfred Mallawa Adds a helper macro that implements the `rw1c` behaviour. Ex:    uint32_t data = FIELD32_1CLEAR(val, REG, FIELD); if the specified `FIELD` is set (single/multi bit all fields) then the

Re: [PATCH 0/2] expose host-phys-bits to guest

On 9/2/2022 12:17 AM, Gerd Hoffmann wrote: On Thu, Sep 01, 2022 at 10:36:19PM +0800, Xiaoyao Li wrote: On 9/1/2022 9:58 PM, Gerd Hoffmann wrote: Anyway, IMO, guest including guest firmware, should always consult from CPUID leaf 0x8008 for physical address length. It simply can't for the

[PATCH] KVM: use store-release to mark dirty pages as harvested

The following scenario can happen if QEMU sets more RESET flags while the KVM_RESET_DIRTY_RINGS ioctl is ongoing on another host CPU: CPU0 CPU1 CPU2 --

Re: [PATCH v1 15/40] i386/tdx: Add property sept-ve-disable for tdx-guest object

On 8/26/2022 1:57 PM, Gerd Hoffmann wrote: Hi, For TD guest kernel, it has its own reason to turn SEPT_VE on or off. E.g., linux TD guest requires SEPT_VE to be disabled to avoid #VE on syscall gap [1]. Why is that a problem for a TD guest kernel? Installing exception handlers is done

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