From: Tobias Röhmel
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
---
target/arm/cpu_tcg.c | 42 ++
1 file changed, 42 insertions(+)
diff --git
From: Tobias Röhmel
Sorry for the "Reviewed-by" messup. I missed that on the explanation
page. Thanks again for the review :)
v6:
patch 5:
- I also changed HPRENR from ARM_CP_ALIAS to ARM_CP_NO_RAW.
Its state is also present in the HPRLAR registers,
but it doesn't make sense to access it
From: Tobias Röhmel
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel
Reviewed-by:
Philippe Mathieu-Daudé writes:
> +Thomas
>
> On 6/12/22 02:10, David Woodhouse wrote:
>> On Mon, 2022-12-05 at 23:11 +0100, Philippe Mathieu-Daudé wrote:
>>> On 5/12/22 18:31, David Woodhouse wrote:
From: Joao Martins
This means handling the new exit reason for Xen but still
On 6/12/22 10:40, David Woodhouse wrote:
On Tue, 2022-12-06 at 09:16 +0100, Philippe Mathieu-Daudé wrote:
+Thomas
On 6/12/22 02:10, David Woodhouse wrote:
On Mon, 2022-12-05 at 23:11 +0100, Philippe Mathieu-Daudé wrote:
On 5/12/22 18:31, David Woodhouse wrote:
+#ifdef CONFIG_XEN
On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
> The guest uses the STSI instruction to get information on the
> CPU topology.
>
> Let us implement the STSI instruction for the basis CPU topology
> level, level 2.
>
> Signed-off-by: Pierre Morel
> ---
> target/s390x/cpu.h |
On 12/6/22 10:31, Janis Schoetterl-Glausch wrote:
On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
We will need a Topology device to transfer the topology
during migration and to implement machine reset.
The device creation is fenced by s390_has_topology().
Signed-off-by: Pierre
Hi Jason,
On 11/29/22 09:10, Jason Wang wrote:
> Without caching mode, MAP notifier won't work correctly since guest
> won't send IOTLB update event when it establishes new mappings in the
> I/O page tables. Let's fail the IOMMU notifiers early instead of
> misbehaving silently.
>
>
On 12/6/22 14:35, Janis Schoetterl-Glausch wrote:
On Tue, 2022-12-06 at 11:32 +0100, Pierre Morel wrote:
On 12/6/22 10:31, Janis Schoetterl-Glausch wrote:
On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
We will need a Topology device to transfer the topology
during migration and to
From: Tianren Zhang
The pci option rom is a RAMBlock mapped from a rom file,
but in some cases of migration, the src and dest machine
may have rom files with different size, which causes the
migration to fail due to mismatch of RAMBlock size.
In those cases, we could make the migration more
On 5/17/21 13:11, Philippe Mathieu-Daudé wrote:
> Guard declarations within hwaddr.h against inclusion
> from user-mode emulation.
>
> To make it clearer this header is sysemu specific,
> move it to the sysemu/ directory.
Hi Philippe,
do we need include/exec/sysemu/... .h
as opposed to just
On Mon, 21 Mar 2022 at 11:59, Alex Bennée wrote:
>
> At a couple of hundred bytes per notifier allocating one for every
> potential queue is very wasteful as most devices only have a few
> queues. Instead of having this handled statically dynamically assign
> them and track in a GPtrArray.
>
>
On 6/12/22 15:38, Gerd Hoffmann wrote:
Hi,
So on x86 we can have 16-bit I/O accesses unaligned to 8-bit boundary?
Yes.
So I _think_ today we should be good with removing the x86 line:
-# ifdef TARGET_I386
-{ 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
On 11/29/22 18:42, Pierre Morel wrote:
The guest uses the STSI instruction to get information on the
CPU topology.
Let us implement the STSI instruction for the basis CPU topology
level, level 2.
Signed-off-by: Pierre Morel
---
target/s390x/cpu.h | 77 +++
On 12/6/22 01:44, Philippe Mathieu-Daudé wrote:
On 6/12/22 05:17, Richard Henderson wrote:
This is always true for sparc64, so this is dead since 3a5f6805c7ca.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 57 ++--
1 file changed, 22
On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
Hi,
I'm trying to understand the x86 architecture-specific code in
hw/display/vga.c:
const MemoryRegionPortio vbe_portio_list[] = {
{ 0, 1, 2, .read = vbe_ioport_read_index,
Hi, Shivam,
On Tue, Dec 06, 2022 at 11:18:52AM +0530, Shivam Kumar wrote:
[...]
> > Note
> > --
> > --
> >
> > We understand that there is a good scope of improvement in the current
> > implementation. Here is a list of things we are working on:
> > 1) Adding dirty quota as a
On 12/6/22 17:05, Peter Xu wrote:
> On Tue, Dec 06, 2022 at 02:16:32PM +0100, Eric Auger wrote:
>> Hi Peter,
>> On 12/6/22 00:28, Peter Xu wrote:
>>> On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
> It seems not super clear
On 6/12/22 15:32, Philippe Mathieu-Daudé wrote:
On 26/5/21 20:15, Richard Henderson wrote:
On 5/17/21 4:11 AM, Philippe Mathieu-Daudé wrote:
--- a/include/exec/hwaddr.h
+++ b/include/exec/sysemu/hwaddr.h
@@ -1,8 +1,9 @@
/* Define hwaddr if it exists. */
-#ifndef HWADDR_H
-#define HWADDR_H
On Mon, 17 May 2021 at 12:16, Philippe Mathieu-Daudé wrote:
>
> Guard declarations within hwaddr.h against inclusion
> from user-mode emulation.
They're all safe, though; none of them are target-dependent.
I wonder if we should move MemMapEntry somewhere else -- it's used
in less than 20 files
On 26/5/21 20:15, Richard Henderson wrote:
On 5/17/21 4:11 AM, Philippe Mathieu-Daudé wrote:
--- a/include/exec/hwaddr.h
+++ b/include/exec/sysemu/hwaddr.h
@@ -1,8 +1,9 @@
/* Define hwaddr if it exists. */
-#ifndef HWADDR_H
-#define HWADDR_H
+#ifndef EXEC_SYSEMU_HWADDR_H
+#define
Hi,
> So on x86 we can have 16-bit I/O accesses unaligned to 8-bit boundary?
Yes.
> So I _think_ today we should be good with removing the x86 line:
>
> -# ifdef TARGET_I386
> -{ 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data
> },
> -# endif
Nope. Breaks
Hi,
On Tue, Dec 6, 2022 at 12:01 PM Chao Peng wrote:
>
> On Mon, Dec 05, 2022 at 09:23:49AM +, Fuad Tabba wrote:
> > Hi Chao,
> >
> > On Fri, Dec 2, 2022 at 6:19 AM Chao Peng
> > wrote:
> > >
> > > Currently in mmu_notifier invalidate path, hva range is recorded and
> > > then checked
On Thu, Dec 01, 2022 at 10:51:48PM -0800, Richard Henderson wrote:
> Previously we hard-coded R2 and R3.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 4 ++--
> tcg/s390x/tcg-target-con-str.h | 8 +--
> tcg/s390x/tcg-target.c.inc | 43
On 12/6/22 09:28, Ilya Leoshkevich wrote:
+switch (TCG_TARGET_CALL_ARG_I64) {
+case TCG_CALL_ARG_EVEN:
On a s390x host with gcc-11.0.1-0.3.1.ibm.fc34.s390x I get:
FAILED: libqemu-aarch64-softmmu.fa.p/tcg_tcg.c.o
../tcg/tcg.c: In function ‘init_call_layout’:
On Tue, Dec 06, 2022 at 02:16:32PM +0100, Eric Auger wrote:
> Hi Peter,
> On 12/6/22 00:28, Peter Xu wrote:
> > On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
> >> On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
> >>> It seems not super clear on when iova_tree is used, and why. Add
Hi,
On Fri, Dec 2, 2022 at 6:18 AM Chao Peng wrote:
>
> In confidential computing usages, whether a page is private or shared is
> necessary information for KVM to perform operations like page fault
> handling, page zapping etc. There are other potential use cases for
> per-page memory
On 12/6/22 01:48, Philippe Mathieu-Daudé wrote:
On 6/12/22 05:17, Richard Henderson wrote:
Now that tcg can handle direct and indirect goto_tb simultaneously,
we can optimistically leave space for a direct branch and fall back
to loading the pointer from the TB for an indirect branch.
On Tue, 2022-12-06 at 09:49 -0600, Richard Henderson wrote:
> On 12/6/22 09:28, Ilya Leoshkevich wrote:
> > > + switch (TCG_TARGET_CALL_ARG_I64) {
> > > + case TCG_CALL_ARG_EVEN:
> >
> > On a s390x host with gcc-11.0.1-0.3.1.ibm.fc34.s390x I get:
> >
> > FAILED:
On 6/12/22 16:38, Claudio Fontana wrote:
On 12/6/22 15:53, Claudio Fontana wrote:
On 5/17/21 13:11, Philippe Mathieu-Daudé wrote:
Guard declarations within hwaddr.h against inclusion
from user-mode emulation.
To make it clearer this header is sysemu specific,
move it to the sysemu/ directory.
Hi,
On Fri, Dec 2, 2022 at 6:18 AM Chao Peng wrote:
>
> From: "Kirill A. Shutemov"
>
> Introduce 'memfd_restricted' system call with the ability to create
> memory areas that are restricted from userspace access through ordinary
> MMU operations (e.g. read/write/mmap). The memory content is
On Thu, Dec 01, 2022 at 09:39:53PM -0800, Richard Henderson wrote:
> Pre-compute the function call layout for each helper at startup.
> Drop TCG_CALL_DUMMY_ARG, as we no longer need to leave gaps
> in the op->args[] array. This allows several places to stop
> checking for NULL TCGTemp, to which
On 12/6/22 15:53, Claudio Fontana wrote:
> On 5/17/21 13:11, Philippe Mathieu-Daudé wrote:
>> Guard declarations within hwaddr.h against inclusion
>> from user-mode emulation.
>>
>> To make it clearer this header is sysemu specific,
>> move it to the sysemu/ directory.
>
> Hi Philippe,
>
> do we
Hi,
On Fri, Dec 2, 2022 at 6:19 AM Chao Peng wrote:
>
> This new KVM exit allows userspace to handle memory-related errors. It
> indicates an error happens in KVM at guest memory range [gpa, gpa+size).
> The flags includes additional information for userspace to handle the
> error. Currently bit
On Tue, Dec 06, 2022 at 02:06:54PM +0100, Eric Auger wrote:
> >>> + * current VTD address space, because all UNMAP (including iotlb or
> >>> + * dev-iotlb) events can be transparently delivered to !MAP iommu
> >>> + * notifiers.
> >> because all UNMAP notifications (iotlb or dev-iotlb)
On Tue, 6 Dec 2022 at 15:56, Philippe Mathieu-Daudé wrote:
>
> On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
> > I don't know that bit of qemu well enough to know whether the cpu part
> > of qemu should be splitting the unaligned accesses or not.
> All I/O accesses are gated thru
On 12/6/22 10:02, Peter Maydell wrote:
On Tue, 6 Dec 2022 at 15:56, Philippe Mathieu-Daudé wrote:
On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
I don't know that bit of qemu well enough to know whether the cpu part
of qemu should be splitting the unaligned accesses or not.
All I/O
JFYI I miss the ability to use Unix socket right now.. I'm trying to use
vagrant + vagrant-qemu + socket_vmnet on Macbook m1. It'd be MUCH easier
to connect QEMU to the socket_vmnet' Unix socket directly w/o any
wrappers..
--
You received this bug notification because you are a member of qemu-
在 2022/12/6 16:30, Philippe Mathieu-Daudé 写道:
On 6/12/22 09:18, Longpeng(Mike) via wrote:
From: Longpeng
This allows the vhost-vdpa device to batch the setup of all its MRs of
host notifiers.
This significantly reduces the device starting time, e.g. the time spend
on setup the host
On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
> During a subsystem reset the Topology-Change-Report is cleared
> by the machine.
> Let's ask KVM to clear the Modified Topology Change Report (MTCR)
> bit of the SCA in the case of a subsystem reset.
^ weird space
[...]
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.c | 28 +++-
target/arm/cpu.h | 6 +
target/arm/helper.c | 302 +++
target/arm/machine.c | 28
4 files changed, 360 insertions(+), 4 deletions(-)
diff --git
From: Tobias Röhmel
Add PMSAv8r translation.
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
---
target/arm/ptw.c | 126 ++-
1 file changed, 104 insertions(+), 22 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index
From: Tobias Röhmel
RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
---
target/arm/cpu.c| 6 +-
From: Tobias Röhmel
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
---
From: Tobias Röhmel
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2
On 12/6/22 10:50, Janis Schoetterl-Glausch wrote:
On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
During a subsystem reset the Topology-Change-Report is cleared
by the machine.
Let's ask KVM to clear the Modified Topology Change Report (MTCR)
bit of the SCA in the case of a
Hi,
I'm trying to understand the x86 architecture-specific code in
hw/display/vga.c:
const MemoryRegionPortio vbe_portio_list[] = {
{ 0, 1, 2, .read = vbe_ioport_read_index,
.write = vbe_ioport_write_index },
# ifdef TARGET_I386
{ 1, 1, 2, .read =
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
> Hi,
>
> I'm trying to understand the x86 architecture-specific code in
> hw/display/vga.c:
>
> const MemoryRegionPortio vbe_portio_list[] = {
> { 0, 1, 2, .read = vbe_ioport_read_index,
>.write =
Hi Chao,
On Tue, Dec 6, 2022 at 11:58 AM Chao Peng wrote:
>
> On Mon, Dec 05, 2022 at 09:03:11AM +, Fuad Tabba wrote:
> > Hi Chao,
> >
> > On Fri, Dec 2, 2022 at 6:18 AM Chao Peng
> > wrote:
> > >
> > > In memory encryption usage, guest memory may be encrypted with special
> > > key and
Hi Peter,
On 12/1/22 20:22, Peter Xu wrote:
> On Thu, Dec 01, 2022 at 07:17:41PM +0100, Eric Auger wrote:
>> Hi Peter
> Hi, Eric,
>
>> On 12/1/22 17:25, Peter Xu wrote:
>>> It seems not super clear on when iova_tree is used, and why. Add a rich
>>> comment above iova_tree to track why we needed
在 2022/12/6 17:07, Philippe Mathieu-Daudé 写道:
On 6/12/22 09:18, Longpeng(Mike) via wrote:
From: Longpeng
This allows the vhost device to batch the setup of all its host
notifiers.
This significantly reduces the device starting time, e.g. the time spend
on enabling notifiers reduce from
On 6/12/22 12:43, Tobias Roehmel wrote:
On 06.12.22 11:39, Philippe Mathieu-Daudé wrote:
On 6/12/22 11:24, tobias.roeh...@rwth-aachen.de wrote:
From: Tobias Röhmel
v6:
patch 5:
- I'm freeing the PRBAR/... strings explicitly now since
I don't know how to use autofree in this setup
On Tue, 2022-12-06 at 11:32 +0100, Pierre Morel wrote:
>
> On 12/6/22 10:31, Janis Schoetterl-Glausch wrote:
> > On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
> > > We will need a Topology device to transfer the topology
> > > during migration and to implement machine reset.
> > >
> > >
On 6/12/22 09:18, Longpeng(Mike) via wrote:
From: Longpeng
This allows the vhost device to batch the setup of all its host notifiers.
This significantly reduces the device starting time, e.g. the time spend
on enabling notifiers reduce from 376ms to 9.1ms for a VM with 64 vCPUs
and 3
On Tue, 2022-12-06 at 09:16 +0100, Philippe Mathieu-Daudé wrote:
> +Thomas
>
> On 6/12/22 02:10, David Woodhouse wrote:
> > On Mon, 2022-12-05 at 23:11 +0100, Philippe Mathieu-Daudé wrote:
> > > On 5/12/22 18:31, David Woodhouse wrote:
> > > > +#ifdef CONFIG_XEN
> > >
> > > CONFIG_XEN is set
On 6/12/22 11:28, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
在 2022/12/6 17:07, Philippe Mathieu-Daudé 写道:
On 6/12/22 09:18, Longpeng(Mike) via wrote:
From: Longpeng
This allows the vhost device to batch the setup of all its host
notifiers.
This significantly
On Mon, Dec 05, 2022 at 09:03:11AM +, Fuad Tabba wrote:
> Hi Chao,
>
> On Fri, Dec 2, 2022 at 6:18 AM Chao Peng wrote:
> >
> > In memory encryption usage, guest memory may be encrypted with special
> > key and can be accessed only by the guest itself. We call such memory
> > private memory.
On Mon, Dec 05, 2022 at 02:49:59PM -0800, Isaku Yamahata wrote:
> On Fri, Dec 02, 2022 at 02:13:45PM +0800,
> Chao Peng wrote:
>
> > A large page with mixed private/shared subpages can't be mapped as large
> > page since its sub private/shared pages are from different memory
> > backends and may
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
> +Juan/David/Claudio.
>
> On 6/12/22 03:20, David Woodhouse wrote:
> > On Mon, 2022-12-05 at 23:17 +0100, Philippe Mathieu-Daudé wrote:
> > > On 5/12/22 18:31, David Woodhouse wrote:
> > > > From: Joao Martins
> > > >
> > > > This is done by
On 06.12.22 11:39, Philippe Mathieu-Daudé wrote:
On 6/12/22 11:24, tobias.roeh...@rwth-aachen.de wrote:
From: Tobias Röhmel
v6:
patch 5:
- I'm freeing the PRBAR/... strings explicitly now since
I don't know how to use autofree in this setup correctly.
Maybe {} around the part were
On Mon, 2022-12-05 at 13:58 +0100, Thomas Huth wrote:
> The "MOVE TO PRIMARY/SECONDARY" instructions can also be called
> from problem state. We just should properly check whether the
> secondary-space access key is valid here, too, and inject a
> privileged program exception if it is invalid.
>
Chao Peng writes:
> In confidential computing usages, whether a page is private or shared is
> necessary information for KVM to perform operations like page fault
> handling, page zapping etc. There are other potential use cases for
> per-page memory attributes, e.g. to make memory read-only (or
Hi jason,
On 11/29/22 09:10, Jason Wang wrote:
> Without dt mode, device IOTLB notifier won't work since guest won't
> send device IOTLB invalidation descriptor in this case. Let's fail
> early instead of misbehaving silently.
>
> Signed-off-by: Jason Wang
> ---
> hw/i386/intel_iommu.c | 8
On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
> We will need a Topology device to transfer the topology
> during migration and to implement machine reset.
>
> The device creation is fenced by s390_has_topology().
>
> Signed-off-by: Pierre Morel
> ---
> include/hw/s390x/cpu-topology.h
On Mon, Dec 05, 2022 at 09:23:49AM +, Fuad Tabba wrote:
> Hi Chao,
>
> On Fri, Dec 2, 2022 at 6:19 AM Chao Peng wrote:
> >
> > Currently in mmu_notifier invalidate path, hva range is recorded and
> > then checked against by mmu_notifier_retry_hva() in the page fault
> > handling path.
Hi Peter,
On 12/6/22 00:28, Peter Xu wrote:
> On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
>> On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
>>> It seems not super clear on when iova_tree is used, and why. Add a rich
>>> comment above iova_tree to track why we needed the
On Tue, 2022-12-06 at 12:07 +0100, Philippe Mathieu-Daudé wrote:
> On 6/12/22 10:40, David Woodhouse wrote:
> > On Tue, 2022-12-06 at 09:16 +0100, Philippe Mathieu-Daudé wrote:
> > > +Thomas
> > >
> > > On 6/12/22 02:10, David Woodhouse wrote:
> > > > On Mon, 2022-12-05 at 23:11 +0100, Philippe
On Tue, Dec 06, 2022 at 11:18:03AM +0800, Jason Wang wrote:
> On Tue, Dec 6, 2022 at 7:19 AM Peter Xu wrote:
> >
> > Jason,
> >
> > On Mon, Dec 05, 2022 at 12:12:04PM +0800, Jason Wang wrote:
> > > I'm fine to go without iova-tree. Would you mind to post patches for
> > > fix? I can test and
On 12/6/22 10:48, Janis Schoetterl-Glausch wrote:
On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
The guest uses the STSI instruction to get information on the
CPU topology.
Let us implement the STSI instruction for the basis CPU topology
level, level 2.
Signed-off-by: Pierre Morel
On 6/12/22 11:24, tobias.roeh...@rwth-aachen.de wrote:
From: Tobias Röhmel
v6:
patch 5:
- I'm freeing the PRBAR/... strings explicitly now since
I don't know how to use autofree in this setup correctly.
Maybe {} around the part were the string is created/used,
such that it is
Hi Alex,
On 21/3/22 16:30, Alex Bennée wrote:
At a couple of hundred bytes per notifier allocating one for every
potential queue is very wasteful as most devices only have a few
queues. Instead of having this handled statically dynamically assign
them and track in a GPtrArray.
[AJB: it's hard
On Thu, Dec 01, 2022 at 10:51:50PM -0800, Richard Henderson wrote:
> Add one instead of dropping odd addresses to the constant pool.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target.c.inc | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
Reviewed-by: Ilya
On Thu, Dec 01, 2022 at 10:51:57PM -0800, Richard Henderson wrote:
> Generalize movcond to support pre-computed conditions, and the same
> set of arguments at all times. This will be assumed by a following
> patch, which needs to reuse tgen_movcond_int.
>
> Signed-off-by: Richard Henderson
>
On Thu, Dec 01, 2022 at 10:51:56PM -0800, Richard Henderson wrote:
> Return both regular and inverted condition codes from tgen_cmp2.
> This lets us choose after the fact which comparision we want.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target.c.inc | 25
On Thu, Dec 01, 2022 at 10:51:58PM -0800, Richard Henderson wrote:
> The new select instruction provides two separate register inputs,
> whereas the old load-on-condition instruction overlaps one of the
> register inputs with the destination.
>
> Signed-off-by: Richard Henderson
> ---
>
On Tue, 2022-12-06 at 15:35 +0100, Pierre Morel wrote:
>
> On 12/6/22 14:35, Janis Schoetterl-Glausch wrote:
> > On Tue, 2022-12-06 at 11:32 +0100, Pierre Morel wrote:
> > >
> > > On 12/6/22 10:31, Janis Schoetterl-Glausch wrote:
> > > > On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
> >
On Thu, Dec 01, 2022 at 10:52:00PM -0800, Richard Henderson wrote:
> There is an older form that produces per-byte results,
> and a newer form that produces per-register results,
> and a vector form that produces per-element results.
>
> Signed-off-by: Richard Henderson
> ---
>
在 2022/12/7 0:00, Peter Xu 写道:
Hi, Shivam,
On Tue, Dec 06, 2022 at 11:18:52AM +0530, Shivam Kumar wrote:
[...]
Note
--
--
We understand that there is a good scope of improvement in the current
implementation. Here is a list of things we are working on:
1) Adding dirty
IF addrstr == "[" and websocket is true, hostlen becomes 0 and we try
to access addrstr[hostlen-1] which is bad idea.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
ui/vnc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ui/vnc.c b/ui/vnc.c
index 88f55cbf3c..8830bfe382
On Thu, Dec 01, 2022 at 10:51:51PM -0800, Richard Henderson wrote:
> One has 3 register arguments; the other has 2 plus an m3 field.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target.c.inc | 57 +-
> 1 file changed, 32 insertions(+), 25
On 12/6/22 11:09, Philippe Mathieu-Daudé wrote:
On 6/12/22 16:38, Claudio Fontana wrote:
On 12/6/22 15:53, Claudio Fontana wrote:
On 5/17/21 13:11, Philippe Mathieu-Daudé wrote:
Guard declarations within hwaddr.h against inclusion
from user-mode emulation.
To make it clearer this header is
This was added to support passt:
https://passt.top
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1903470
Title:
qemu 5.1.0: Add UNIX socket support for netdev socket
Status in QEMU:
Expired
On 6/12/22 20:23, Vladimir Sementsov-Ogievskiy wrote:
IF addrstr == "[" and websocket is true, hostlen becomes 0 and we try
to access addrstr[hostlen-1] which is bad idea.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
ui/vnc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On 6/12/22 21:06, Thomas Huth wrote:
The only code that is really, really target dependent is the apic-related
code in rtc_policy_slew_deliver_irq(). By moving this code into the hw/i386/
folder (renamed to rtc_apic_policy_slew_deliver_irq()) and passing this
function as parameter to
On Thu, Dec 01, 2022 at 10:51:53PM -0800, Richard Henderson wrote:
> The MIE2 facility adds 3-operand versions of multiply.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 1 +
> tcg/s390x/tcg-target.h | 1 +
> tcg/s390x/tcg-target.c.inc | 34
On Thu, Dec 01, 2022 at 10:51:54PM -0800, Richard Henderson wrote:
> The MIE2 facility adds a 3-operand signed 64x64->128 multiply.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 1 +
> tcg/s390x/tcg-target.h | 2 +-
> tcg/s390x/tcg-target.c.inc | 8
On Tue, Dec 06, 2022 at 05:28:01PM +0100, Eric Auger wrote:
>
>
> On 12/6/22 17:05, Peter Xu wrote:
> > On Tue, Dec 06, 2022 at 02:16:32PM +0100, Eric Auger wrote:
> >> Hi Peter,
> >> On 12/6/22 00:28, Peter Xu wrote:
> >>> On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
> On
It seems not super clear on when iova_tree is used, and why. Add a rich
comment above iova_tree to track why we needed the iova_tree, and when we
need it.
Also comment for the map/unmap messages, on how they're used and
implications (e.g. unmap can be larger than the mapped ranges).
This will be available in the next QEMU release (7.2) under a sligthly
different form:
"-netdev stream" for TCP socket and "-netdev dgram" for UDP socket.
Both support inet and unix sockets. See qemu(1).
--
You received this bug notification because you are a member of qemu-
devel-ml, which is
The only code that is really, really target dependent is the apic-related
code in rtc_policy_slew_deliver_irq(). By moving this code into the hw/i386/
folder (renamed to rtc_apic_policy_slew_deliver_irq()) and passing this
function as parameter to mc146818_rtc_init(), we can make the RTC
On Thu, Dec 01, 2022 at 10:51:59PM -0800, Richard Henderson wrote:
> Reuse code from movcond to conditionally copy a2 to dest,
> based on the condition codes produced by FLOGR.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 1 +
> tcg/s390x/tcg-target.c.inc |
On Tue, Dec 6, 2022 at 5:32 AM Dr. David Alan Gilbert
wrote:
> From intel arch manual 19.3:
> '..16-bit ports should be aligned to even addresses (0, 2, 4, ...) so
> that all 16 bits can be transferred in a
> single bus cycle. Likewise, 32-bit ports should be aligned to addresses
> that are
On Thu, Dec 01, 2022 at 10:51:49PM -0800, Richard Henderson wrote:
> This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and
> several follow-up patches. The primary motivation is to reduce the
> less-tested code paths, pre-z10. Secondarily, this allows the
> unconditional use of
On Thu, Dec 01, 2022 at 10:51:52PM -0800, Richard Henderson wrote:
> There are multiple variations, with different fields.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target.c.inc | 47 +-
> 1 file changed, 26 insertions(+), 21 deletions(-)
On Thu, Dec 01, 2022 at 10:51:55PM -0800, Richard Henderson wrote:
> This is andc, orc, nand, nor, eqv.
> We can use nor for implementing not.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 1 +
> tcg/s390x/tcg-target.h | 25 +
>
On Tue, 6 Dec 2022, 14:02 Ilya Leoshkevich, wrote:
> On Thu, Dec 01, 2022 at 10:51:53PM -0800, Richard Henderson wrote:
> > The MIE2 facility adds 3-operand versions of multiply.
> >
> > Signed-off-by: Richard Henderson
> > ---
> > tcg/s390x/tcg-target-con-set.h | 1 +
> >
On Tue, Dec 06, 2022 at 05:10:39PM -0500, Peter Xu wrote:
> It seems not super clear on when iova_tree is used, and why. Add a rich
> comment above iova_tree to track why we needed the iova_tree, and when we
> need it.
>
> Also comment for the map/unmap messages, on how they're used and
>
It seems not super clear on when iova_tree is used, and why. Add a rich
comment above iova_tree to track why we needed the iova_tree, and when we
need it.
Also comment for the map/unmap messages, on how they're used and
implications (e.g. unmap can be larger than the mapped ranges).
Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt
document with CANFD command line examples.
Signed-off-by: Vikram Garhwal
---
docs/system/arm/xlnx-versal-virt.rst | 31 ++
hw/arm/xlnx-versal-virt.c| 48
The QTests perform three tests on the Xilinx VERSAL CANFD controller:
Tests the CANFD controllers in loopback.
Tests the CANFD controllers in normal mode with CAN frame.
Tests the CANFD controllers in normal mode with CANFD frame.
Signed-off-by: Vikram Garhwal
Acked-by: Thomas Huth
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