sigh, I've been at it for almost 12 hours today, and am in a rush to
finish up -- so I forgot to pass "-v2" to git-format patch.
So this is actually "v2" (as the Notes section shows); I'm sorry about
the mistake in the subject-line versioning.
Michael, please *do* queue this patch.
Thanks
This adds mfr-id and oob-eth-addr parameters to the userspace netdev backend.
-netdev user,id=[str],mfr-id=[uint32],oob-eth-addr=[MAC address]
I introduced mfr-id and oob-eth-addr to slirp a while ago, as part of Slirp
config version 5, but never managed to get the options exposed in
This adds mfr-id and oob-eth-addr parameters to the userspace netdev backend.
-netdev user,id=[str],mfr-id=[uint32],oob-eth-addr=[MAC address]
Signed-off-by: Peter Delevoryas
---
net/slirp.c | 19 ---
qapi/net.json | 9 -
2 files changed, 24 insertions(+), 4
On Thu, Jan 05, 2023 at 05:29:54PM +0100, Philippe Mathieu-Daudé wrote:
> On 5/1/23 17:01, Laszlo Ersek wrote:
> > On 1/5/23 10:56, Michael S. Tsirkin wrote:
> > > On Thu, Jan 05, 2023 at 04:17:06AM -0500, Michael S. Tsirkin wrote:
> > > > From: Laszlo Ersek
> > >
> > > I noticed v2 is
From: Axel Heider
The CNT register is a read-only register. There is no need to
store it's value, it can be calculated on demand.
The calculated frequency is needed temporarily only.
Note that this is a migration compatibility break for all boards
types that use the EPIT peripheral.
From: Jean-Christophe Dubois
IRQs were not associated to the various GPIO devices inside i.MX7D.
This patch brings the i.MX7D on par with i.MX6.
Signed-off-by: Jean-Christophe Dubois
Message-id: 20221226101418.415170-1-...@tribudubois.net
Reviewed-by: Peter Maydell
Signed-off-by: Peter
(2023-01-04 18:58:33 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230105
for you to fetch changes up to 93c9678de9dc7d2e68f9e8477da072bac30ef132:
hw/net: Fix read of uninitialized memory in imx_fec. (2023-01-05 15:33
On Thu, 5 Jan 2023 at 11:00, Alex Bennée wrote:
>
> Hi Peter,
>
> I discovered that semihosting syscall support got broken and while
> preparing to bisect I ran into a few warts.
>
> Alex Bennée (4):
>semihosting-tests: add timeout support
>Makefile: drop microbit.lds from the
On 5/1/23 17:43, Alex Bennée wrote:
This is a hangover from the original code. addr is misleading as it is
only a really a register id. While len will never exceed
"a really"?
MAX_PACKET_LENGTH I've used size_t as that is what strlen returns.
Signed-off-by: Alex Bennée
---
On 5/1/23 17:43, Alex Bennée wrote:
We unfortunately handle the checking of packet acknowledgement
differently for user and softmmu modes. Abstract the user mode stuff
behind gdb_got_immediate_ack with a stub for softmmu.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 15
Hi Jean,
Thanks for taking the time to look into this.
On Wed, Jan 04, 2023 at 12:29:10PM +, Jean-Philippe Brucker wrote:
> Hi Mostafa,
>
> On Mon, Dec 19, 2022 at 12:57:20PM +, Mostafa Saleh wrote:
> > GBPA register can be used to globally abort all
> > transactions.
> >
> > Only
On 1/5/23 17:50, Peter Maydell wrote:
On Thu, 5 Jan 2023 at 16:46, Cédric Le Goater wrote:
On 1/5/23 16:33, Peter Maydell wrote:
On Wed, 21 Dec 2022 at 18:32, Stephen Longfield wrote:
Size is used at lines 1088/1188 for the loop, which reads the last 4
bytes from the crc_ptr so it does
On 5/1/23 17:43, Alex Bennée wrote:
These inline helpers are all used by target specific code so move them
out of the general header so we don't needlessly pollute the rest of
the API with target specific stuff.
Note we have to include cpu.h in semihosting as it was relying on a
side effect
From: Marco Liebel
Some registers are defined to have immutable bits, this commit
will implement that behavior.
Signed-off-by: Marco Liebel
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id: <20230105102349.2181856-1-quic_mlie...@quicinc.com>
---
target/hexagon/genptr.c
On Wed, 4 Jan 2023 at 21:05, John Snow wrote:
>
> The following changes since commit ecc9a58835f8d4ea4e3ed36832032a71ee08fbb2:
>
> Merge tag 'pull-9p-20221223' of https://github.com/cschoenebeck/qemu into
> staging (2023-01-04 14:53:59 +)
>
> are available in the Git repository at:
>
>
From: "Maciej S. Szmigiero"
This device works like a virtual DIMM stick: it allows inserting extra RAM
into the guest at run time and later removing it without having to
duplicate all of the address space management logic of TYPE_MEMORY_DEVICE
in each memory hot-add protocol driver.
This device
From: "Maciej S. Szmigiero"
This driver is like virtio-balloon on steroids: it allows both changing the
guest memory allocation via ballooning and inserting extra RAM into it by
adding required memory backends and providing them to the driver.
One of advantages of these over ACPI-based PC DIMM
From: "Maciej S. Szmigiero"
This commit adds Hyper-V Dynamic Memory Protocol definitions, taken
from hv_balloon Linux kernel driver, adapted to the QEMU coding style and
definitions.
Signed-off-by: Maciej S. Szmigiero
---
include/hw/hyperv/dynmem-proto.h | 423 +++
On Thu, Jan 05, 2023 at 09:04:37PM +, Peter Maydell wrote:
> On Thu, 5 Jan 2023 at 16:32, Michael S. Tsirkin wrote:
> >
> > On Thu, Jan 05, 2023 at 04:56:39AM -0500, Michael S. Tsirkin wrote:
> > > On Thu, Jan 05, 2023 at 04:14:20AM -0500, Michael S. Tsirkin wrote:
> > > > The following
On 3/1/23 19:16, Richard Henderson wrote:
Wrapper to return the mp affinity bits from the cpu.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
hw/arm/virt-acpi-build.c | 2 +-
hw/arm/virt.c | 6 +++---
hw/arm/xlnx-versal-virt.c | 3 ++-
On 3/1/23 19:16, Richard Henderson wrote:
Streamline new instances of this hook, so that we always go
through arm_cpu_leaf_class_init first, performing common tasks,
and have resolved the ARMCPUClass.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 2 +-
target/arm/cpu.c |
The idef-parser skips the change-of-flow (COF) instructions, so add
overrides
Changes in v2
Add a new generator for analyze_ instructions. Pouplate the
DisasContext ahead of generating code.
Changes in v3
Cleanup of analysis code
Added test updates enabled by new toolchain
The modern ACPI CPU hotplug interface was introduced in the following
series (aa1dd39ca307..679dd1a957df), released in v2.7.0:
1 abd49bc2ed2f docs: update ACPI CPU hotplug spec with new protocol
2 16bcab97eb9f pc: piix4/ich9: add 'cpu-hotplug-legacy' property
3 5e1b5d93887b acpi: cpuhp:
On 5/1/23 16:44, Bernhard Beschow wrote:
Bernhard Beschow (2):
hw/pci-host/bonito: Inline pci_register_root_bus()
hw/pci-host/bonito: Map PCI IRQs in board code
include/hw/pci-host/bonito.h | 2 ++
hw/mips/fuloong2e.c | 22 ++
hw/pci-host/bonito.c
I was motivated to sort this out while working on my register API
which is target agnostic but ran into the weeds when trying to link up
with the gdbstub. This was due to us building gdbstub for every single
target we support due to a few ABI sensitive bits that require CPU
specific information.
This aids subsystems (like gdbstub) that want to trigger a flush
without pulling target specific headers.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v2
- actually include the header and rename to tb-flush.h
- better kerneldoc style comment for the function
---
From: Philippe Mathieu-Daudé
Prototypes using gdb_syscall_complete_cb() or gdb_?et_reg_cb()
don't depend on "cpu.h", thus are not target-specific.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221214143659.62133-1-phi...@linaro.org>
Signed-off-by: Alex
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20221220142520.24094-3-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/nseries.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git
On 5/1/23 17:43, Alex Bennée wrote:
When I started splitting gdbstub apart I was a little too boilerplate
with my file headers. Fix up to carry over Fabrice's copyright and the
LGPL license header.
Fixes: ae7467b1ac (gdbstub: move breakpoint logic to accel ops)
Reviewed-by: Richard Henderson
From: Stephen Longfield
Size is used at lines 1088/1188 for the loop, which reads the last 4
bytes from the crc_ptr so it does need to get increased, however it
shouldn't be increased before the buffer is passed to CRC computation,
or the crc32 function will access uninitialized memory.
This
On 5/1/23 17:43, Alex Bennée wrote:
Use something more specific to avoid name clashes.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 1/4/23 3:47 PM, Chuck Zmudzinski wrote:
> On 1/3/23 10:14 AM, Alex Williamson wrote:
>
>>
>> It's necessary to configure the assigned IGD at slot 2 to make it
>> functional, yes, but I don't really understand this notion of
>> "reserving" slot 2. If something occupies address 00:02.0 in the
On 3/1/23 19:16, Richard Henderson wrote:
There was even a TODO comment that we ought to be using a cpu
property, but we failed to update when the property was added.
Use ARM_AFF1_SHIFT instead of the bare constant 8.
Signed-off-by: Richard Henderson
---
hw/arm/bcm2836.c | 7 +--
1 file
On 3/1/23 19:16, Richard Henderson wrote:
Only qdev_prop_register_global requires a non-null array.
The other instances can simply exit early.
Signed-off-by: Richard Henderson
---
hw/core/qdev-properties.c | 43 ---
1 file changed, 27 insertions(+), 16
Am 5. Januar 2023 13:10:38 UTC schrieb "Philippe Mathieu-Daudé"
:
>RC4030 declarations are not MIPS specific, no need to
>have them in all MIPS boards.
>
>Signed-off-by: Philippe Mathieu-Daudé
>---
>Based-on: <20230105130710.49264-1-phi...@linaro.org>
> "hw/pci-host/bonito:
Replace __builtin_* with inline assembly
The __builtin's are subject to change with different compiler
releases, so might break
Mark arrays as aligned when accessed as HVX vectors
Clean up comments
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/scatter_gather.c | 513
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 14 --
target/hexagon/translate.c | 30 +
target/hexagon/gen_analyze_funcs.py | 17 +---
target/hexagon/gen_tcg_funcs.py | 18 -
4 files
On Thu, Jan 05, 2023 at 03:31:57PM +0100, Bernhard Beschow wrote:
> This series consolidates the implementations of the PIIX3 and PIIX4 south
> bridges and is an extended version of [1]. The motivation is to share as much
> code as possible and to bring both device models to feature parity such
When I started splitting gdbstub apart I was a little too boilerplate
with my file headers. Fix up to carry over Fabrice's copyright and the
LGPL license header.
Fixes: ae7467b1ac (gdbstub: move breakpoint logic to accel ops)
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
Currently we only support replay for softmmu mode so it is a constant
false for user-mode.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 1 +
gdbstub/gdbstub.c | 13 ++---
gdbstub/softmmu.c | 5 +
gdbstub/user.c | 5 +
4 files changed, 13 insertions(+), 11
This is a hangover from the original code. addr is misleading as it is
only a really a register id. While len will never exceed
MAX_PACKET_LENGTH I've used size_t as that is what strlen returns.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 17 ++---
1 file changed, 10
In get_phys_addr_twostage() we set the lg_page_size of the result to
the maximum of the stage 1 and stage 2 page sizes. This works for
the case where we do want to create a TLB entry, because we know the
common TLB code only creates entries of the TARGET_PAGE_SIZE and
asking for a size larger
The underlying call uses vaddr and the comms API uses unsigned long
long which will always fit. We don't need to deal in target_ulong
here.
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gdbstub/gdbstub.c
The check semihosting_enabled() wants to know if the guest is
currently in user mode. Unlike the other cases the test was inverted
causing us to block semihosting calls in non-EL0 modes.
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
Signed-off-by: Alex Bennée
---
From: Tobias Röhmel
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel
Reviewed-by:
From: Fabiano Rosas
Fix the following:
ERROR: spaces required around that '|' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '+' (ctx:VxB)
ERROR: space prohibited between function name and open parenthesis '('
(the last two still have some
From: Philippe Mathieu-Daudé
When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
and building with -Wall we get:
hw/arm/smmu-common.c:173:33: warning: static function
'smmu_hash_remove_by_asid_iova' is used in an inline function with external
linkage [-Wstatic-in-inline]
On Thu, Jan 05, 2023 at 09:35:54AM +0100, David Hildenbrand wrote:
> On 04.01.23 18:23, Peter Xu wrote:
> > On Thu, Dec 22, 2022 at 12:02:10PM +0100, David Hildenbrand wrote:
> > > Migrating device state before we start iterating is currently impossible.
> > > Introduce and use
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: Claudio Fontana
Reviewed-by: Cornelia Huck
Message-id: 20221213190537.511-5-faro...@suse.de
Signed-off-by: Peter Maydell
---
target/arm/m_helper.c | 16
1 file changed, 16 deletions(-)
diff --git
From: Axel Heider
Signed-off-by: Axel Heider
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/timer/imx_epit.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 7af3a8b10e8..39f47222d05
From: Tobias Röhmel
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2
On Wed 04 Jan 2023 12:46:01 PM +01, Thomas Huth wrote:
> "quorum" is required by iotest 312 - if it is not compiled into the
> QEMU binary, the test fails. Thus list "quorum" as required driver
> so that the test gets skipped in case it is not available.
>
> Signed-off-by: Thomas Huth
On Thu, 2023-01-05 at 09:59 -0500, Stefan Berger wrote:
[...]
> > @@ -2658,7 +2646,6 @@ void qemu_init(int argc, char **argv)
> > qemu_add_opts(_boot_opts);
> > qemu_add_opts(_add_fd_opts);
> > qemu_add_opts(_object_opts);
> > - qemu_add_opts(_tpmdev_opts);
> >
Add overrides for
J2_callr
J2_callrt
J2_callrf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 6 ++
target/hexagon/macros.h | 12 +---
target/hexagon/genptr.c | 20
3 files changed, 27 insertions(+), 11 deletions(-)
diff --git
On 5/1/23 17:01, Laszlo Ersek wrote:
On 1/5/23 10:56, Michael S. Tsirkin wrote:
On Thu, Jan 05, 2023 at 04:17:06AM -0500, Michael S. Tsirkin wrote:
From: Laszlo Ersek
I noticed v2 is forthcoming. dropped now.
Yes, thanks.
I'm picking up the "Reviewed-by: Michael S. Tsirkin "
tag from
On Thu, 5 Jan 2023 at 16:24, Taylor Simpson wrote:
>
> Some versions of clang will warn on this with -Wall
> Then, it will be an error with -Werror
I think this has already been fixed by commit 2bc6c79417b89c3306.
thanks
-- PMM
Our GDB syscall support is the last chunk of code that needs target
specific support so move it to a new file. We take the opportunity to
move the syscall state into its own singleton instance and add in a
few helpers for the main gdbstub to interact with the module.
I also moved the gdb_exit()
From: Tobias Röhmel
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
Message-id: 20221206102504.165775-8-tobias.roeh...@rwth-aachen.de
Signed-off-by: Peter Maydell
---
target/arm/cpu_tcg.c | 42
On Mon, 2 Jan 2023 at 11:31, David Hildenbrand wrote:
>
> The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:
>
> Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into
> staging (2022-12-21 18:08:09 +)
>
> are available in the Git repository at:
>
From: Mukilan Thiyagarajan
The patch renames the identifier of the 32bit register
HEX_REG_P3_0 to HEX_REG_P3_0_ALIASED.
This change is to intended to provide some warning that
HEX_REG_P3_0 is an aliased register which has multiple
representations in CPU state and therefore might require
special
From: Alessandro Di Federico
Note: `Makefile` relies on modification dates in the source tree to
detect changes to `meson_options.txt`. However, git does not track
those. Therefore, the following was necessary to regenerate
`meson-buildoptions.sh`:
touch meson_options.txt
cd
Peter,
Applied to target-arm.next, thanks. Sorry it took me so long to> get to this.
No worries. Thanks for picking up the changes, and I really appreciate
all the review feedback.
Axel
On Thu, Jan 05, 2023 at 01:45:23PM +0100, David Hildenbrand wrote:
> Playing with background snapshots in combination with hugetlb and
> virtio-mem, I found two issues and some reasonable optimizations (skip
> unprotecting when unregistering).
>
> With virtio-mem (RamDiscardManager), we now won't
On Thu, Jan 05, 2023 at 09:04:37PM +, Peter Maydell wrote:
> On Thu, 5 Jan 2023 at 16:32, Michael S. Tsirkin wrote:
> >
> > On Thu, Jan 05, 2023 at 04:56:39AM -0500, Michael S. Tsirkin wrote:
> > > On Thu, Jan 05, 2023 at 04:14:20AM -0500, Michael S. Tsirkin wrote:
> > > > The following
On 3/1/23 19:16, Richard Henderson wrote:
The class structure is a plain wrapper around ARMCPUClass. We really
only need the QOM class, TYPE_AARCH64_CPU. The instance init and
fallback class init functions are identical to the same ones over
in cpu.c. Make arm_cpu_post_init static.
On 3/1/23 19:16, Richard Henderson wrote:
If the instance_finalize hook is NULL, the hook is not called.
There is no need to install an empty function.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 5 -
1 file changed, 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Thu, 2023-01-05 at 11:20 -0500, Stefan Berger wrote:
>
>
> On 1/5/23 08:00, James Bottomley wrote:
[...]
> > +The mssim backend supports snapshotting and migration, but the
> > state
> > +of the Microsoft Simulator server must be preserved (or the server
> > +kept running) outside of QEMU for
Am 5. Januar 2023 17:38:26 UTC schrieb "Philippe Mathieu-Daudé"
:
>This argument was added 9 years ago in commit 83d08f2673
>("pc: map PCI address space as catchall region for not mapped
>addresses") and has never been used since, so remove it.
>
>Signed-off-by: Philippe Mathieu-Daudé
On 3/1/23 19:16, Richard Henderson wrote:
We can now store these values into ARMCPUClass instead of into
a temporary ARMHostCPUFeatures structure.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5
target/arm/hvf_arm.h | 2 +-
target/arm/cpu.c | 13 --
These instructions perform a deallocframe+return (jumpr r31)
Add overrides for
L4_return
SL2_return
L4_return_t
L4_return_f
L4_return_tnew_pt
L4_return_fnew_pt
L4_return_tnew_pnt
L4_return_fnew_pnt
SL2_return_t
SL2_return_f
SL2_return_tnew
On 1/5/23 17:02, James Bottomley wrote:
On Thu, 2023-01-05 at 11:20 -0500, Stefan Berger wrote:
On 1/5/23 08:00, James Bottomley wrote:
[...]
+The mssim backend supports snapshotting and migration, but the
state
+of the Microsoft Simulator server must be preserved (or the server
+kept
On 3/1/23 19:16, Richard Henderson wrote:
With the movement of the property, we can remove the field
from the cpu entirely, using only the class.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h| 3 +++
target/arm/cpu.h| 3 ---
hw/arm/aspeed_ast2600.c | 6 +++--
On 1/5/23 08:00, James Bottomley wrote:
From: James Bottomley
The Microsoft Simulator (mssim) is the reference emulation platform
for the TCG TPM 2.0 specification.
https://github.com/Microsoft/ms-tpm-20-ref.git
diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst
index
From: Laszlo Ersek
The modern ACPI CPU hotplug interface was introduced in the following
series (aa1dd39ca307..679dd1a957df), released in v2.7.0:
1 abd49bc2ed2f docs: update ACPI CPU hotplug spec with new protocol
2 16bcab97eb9f pc: piix4/ich9: add 'cpu-hotplug-legacy' property
3
From: Fabiano Rosas
Fix this:
ERROR: braces {} are necessary for all arms of this statement
Signed-off-by: Fabiano Rosas
Reviewed-by: Claudio Fontana
Reviewed-by: Cornelia Huck
Message-id: 20221213190537.511-4-faro...@suse.de
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 67
From: Tobias Röhmel
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.
Signed-off-by: Tobias Röhmel
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
This is needed for handling vcont packets as the way of calculating
max cpus vhanges between user and softmmu mode.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 1 +
gdbstub/gdbstub.c | 11 +--
gdbstub/softmmu.c | 9 +
gdbstub/user.c | 17 +
4
The two implementations are different enough to encourage having a
specialisation and we can move some of the softmmu only stuff out of
gdbstub.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 19
gdbstub/gdbstub.c | 73 +++--
From: Zhuojia Shen
In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed. This patch aligns exposed ID
registers and their fields with what the upstream kernel currently
exposes.
Specifically, the following new ID registers/fields are exposed to
From: Jean-Christophe Dubois
So far the GPT timers were unable to raise IRQs to the processor.
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/arm/fsl-imx7.h | 5 +
hw/arm/fsl-imx7.c | 10 ++
2 files changed,
> -Original Message-
> From: Alex Bennée
> Sent: Thursday, January 5, 2023 10:43 AM
> To: qemu-devel@nongnu.org; alex.ben...@gmail.com
> Cc: David Hildenbrand ; Sunil Muthuswamy
> ; Aurelien Jarno ;
> Michael Rolnik ; Aleksandar Rikalo
> ; Greg Kurz ; Ilya
> Leoshkevich ; Thomas Huth ;
From: Jean-Christophe Dubois
CCM derived clocks will have to be added later.
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/misc/imx7_ccm.c | 49 +-
1 file changed, 40 insertions(+), 9
On 05/01/2023 09.34, Thomas Huth wrote:
On 04/01/2023 23.01, Peter Maydell wrote:
On Wed, 4 Jan 2023 at 12:36, Thomas Huth wrote:
The windows jobs (especially the 32-bit job) recently started to
hit the timeout limit. Bump it a little bit to ease the situation
(80 minutes is quite long
On 3/1/23 19:16, Richard Henderson wrote:
Create a new intermediate abstract class for v7m, like we do for
aarch64. The initialization of ARMCPUClass.info follows the
concrete class, so remove that init from arm_v7m_class_init.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 6
On 3/1/23 19:16, Richard Henderson wrote:
Since kvm32 was removed
Maybe add here:
(see commit 82bf7ae84c: "target/arm: Remove KVM support for 32-bit
Arm hosts")
, all kvm hosts support aarch64.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 6 ++
1 file changed, 2
Am 5. Januar 2023 17:37:02 UTC schrieb "Philippe Mathieu-Daudé"
:
>No need to document magic values when the definition names
>from "standard-headers/linux/pci_regs.h" are self-explicit.
>
>Signed-off-by: Philippe Mathieu-Daudé
>---
> hw/pci-host/grackle.c | 2 +-
> hw/pci-host/raven.c|
From: Philippe Mathieu-Daudé
The pointed MouseTransformInfo structure is accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20221220142520.24094-2-phi...@linaro.org
Signed-off-by: Peter Maydell
---
include/hw/input/tsc2xxx.h | 4 ++--
In both user and softmmu cases we are just replying with a constant.
If the linker is paying attention it may even be able to sort optimise
the call.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 4 +++-
gdbstub/gdbstub.c | 15 ++-
gdbstub/softmmu.c | 5 +
From: Philippe Mathieu-Daudé
This function is not used anywhere outside this file,
so we can make the function "static void".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Message-id: 20221216214924.4711-2-phi...@linaro.org
Signed-off-by: Peter
From: Axel Heider
- fix #1263 for CR writes
- rework compare time handling
- The compare timer has to run even if CR.OCIEN is not set,
as SR.OCIF must be updated.
- The compare timer fires exactly once when the
compare value is less than the current value, but the
reload values
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
Message-id: 20221206102504.165775-6-tobias.roeh...@rwth-aachen.de
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 6 +
target/arm/cpu.c | 28 +++-
target/arm/helper.c | 302 +++
From: Alex Bennée
The check semihosting_enabled() wants to know if the guest is
currently in user mode. Unlike the other cases the test was inverted
causing us to block semihosting calls in non-EL0 modes.
Cc: qemu-sta...@nongnu.org
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config
From: Mukilan Thiyagarajan
This patch fixes the issue originally reported in
this thread:
https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html
The root cause of the issue is a bug in the hexagon specific
logic for saving & restoring context during signal delivery.
The CPU state
From: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
Reviewed-by: Alessandro Di Federico
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
---
target/hexagon/idef-parser/README.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
* David Hildenbrand (da...@redhat.com) wrote:
> We'll make use of both next in the context of virtio-mem.
>
> Signed-off-by: David Hildenbrand
Reviewed-by: Dr. David Alan Gilbert
> ---
> include/migration/vmstate.h | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
>
This argument was added 9 years ago in commit 83d08f2673
("pc: map PCI address space as catchall region for not mapped
addresses") and has never been used since, so remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 2 +-
hw/pci-host/i440fx.c | 3 +--
hw/pci-host/q35.c
The following changes since commit cb9c6a8e5ad6a1f0ce164d352e3102df46986e22:
.gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2
jobs (2023-01-04 18:58:33 +)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20230105
for you
On 1/5/23 16:33, Peter Maydell wrote:
On Wed, 21 Dec 2022 at 18:32, Stephen Longfield wrote:
Size is used at lines 1088/1188 for the loop, which reads the last 4
bytes from the crc_ptr so it does need to get increased, however it
shouldn't be increased before the buffer is passed to CRC
From: "Maciej S. Szmigiero"
This is a continuation of v1 patch series located here:
https://lore.kernel.org/qemu-devel/cover.1600556526.git.maciej.szmigi...@oracle.com/
Since some time has passed since v1 was posted below there's a reminder
what this series is about:
This series adds a Hyper-V
Peter,
There's a couple of minor code-style issues here (block comment
format, variable declarations in the middle of a block); rather
than asking you to re-roll the series I'll just squash in the
fixes for those:
[...]
Thanks, that makes things easier. Seems these still unfortunately
slipped
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