[PATCH 16/27] target/arm: Drop copies in gen_sve_{ldr,str}

Since we now get TEMP_TB temporaries by default, we no longer need to make copies across these loops. These were the only uses of new_tmp_a64_local(), so remove that as well. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 - target/arm/translate-a64.c | 6 --

[PATCH 20/27] target/hppa: Don't use tcg_temp_local_new

This wasn't actually used at all, just some unused macro re-definitions. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 0102cf451b..cee960949f 100644 ---

[PATCH v6 03/36] tcg: Allocate objects contiguously in temp_allocate_frame

When allocating a temp to the stack frame, consider the base type and allocate all parts at once. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 34 ++ 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c

[PATCH v6 06/36] tcg: Introduce tcg_target_call_oarg_reg

Replace the flat array tcg_target_call_oarg_regs[] with a function call including the TCGCallReturnKind. Extend the set of registers for ARM to r0-r3 to match the ABI: https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#result-return Reviewed-by: Alex Bennée Reviewed-by: Daniel

[PATCH v6 05/36] tcg: Add TCG_CALL_{RET,ARG}_BY_REF

These will be used by some hosts, both 32 and 64-bit, to pass and return i128. Not yet used, because allocation is not yet enabled. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 3 + tcg/tcg.c | 135 - 2 files changed, 135

[PATCH v6 36/36] target/i386: Inline cmpxchg16b

Use tcg_gen_atomic_cmpxchg_i128 for the atomic case, and tcg_gen_qemu_ld/st_i128 otherwise. Signed-off-by: Richard Henderson --- Cc: Paolo Bonzini Cc: Eduardo Habkost --- target/i386/helper.h | 4 --- target/i386/tcg/mem_helper.c | 69

[PATCH v6 24/36] target/s390x: Use a single return for helper_divs32/u32

Pack the quotient and remainder into a single uint64_t. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Fix operand ordering; use tcg_extr32_i64. --- target/s390x/helper.h | 2 +- target/s390x/tcg/int_helper.c | 26

[PATCH v6 35/36] target/i386: Inline cmpxchg8b

Use tcg_gen_atomic_cmpxchg_i64 for the atomic case, and tcg_gen_nonatomic_cmpxchg_i64 otherwise. Signed-off-by: Richard Henderson --- Cc: Paolo Bonzini Cc: Eduardo Habkost --- target/i386/helper.h | 2 -- target/i386/tcg/mem_helper.c | 57

[PATCH v6 19/36] target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP

Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-3-richard.hender...@linaro.org> --- target/arm/helper-a64.h| 2 -- target/arm/helper-a64.c| 43 --- target/arm/translate-a64.c | 61

[PATCH v6 14/36] tcg: Add basic data movement for TCGv_i128

Add code generation functions for data movement between TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract). Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 tcg/tcg-internal.h | 13 +

[PATCH v6 02/36] tcg: Handle dh_typecode_i128 with TCG_CALL_{RET, ARG}_NORMAL

Many hosts pass and return 128-bit quantities like sequential 64-bit quantities. Treat this just like we currently break down 64-bit quantities for a 32-bit host. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 37 + 1 file

[PATCH v2 02/23] target/arm: Correct syndrome for ATS12NSO* at Secure EL1

The AArch32 ATS12NSO* address translation operations are supposed to trap to either EL2 or EL3 if they're executed at Secure EL1 (which can only happen if EL3 is AArch64). We implement this, but we got the syndrome value wrong: like other traps to EL2 or EL3 on an AArch32 cpreg access, they

[PATCH v2 16/23] target/arm: Mark up sysregs for HFGITR bits 0..11

Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 0..11. These bits cover various cache maintenance operations. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-17-peter.mayd...@linaro.org --- target/arm/cpregs.h |

[PATCH v2 21/23] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps

Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps. These trap execution of the SVC instruction from AArch32 and AArch64. (As usual, AArch32 can only trap from EL0, as fine grained traps are disabled with an AArch32 EL1.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson

[PATCH v2 12/23] target/arm: Mark up sysregs for HFGRTR bits 24..35

Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 24..35. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-13-peter.mayd...@linaro.org --- target/arm/cpregs.h | 12 target/arm/helper.c | 14 ++

[PATCH v2 20/23] target/arm: Implement the HFGITR_EL2.ERET trap

Implement the HFGITR_EL2.ERET fine-grained trap. This traps execution from AArch64 EL1 of ERET, ERETAA and ERETAB. The trap is reported with a syndrome value of 0x1a. The trap must take precedence over a possible pointer-authentication trap for ERETAA and ERETAB. Signed-off-by: Peter Maydell

[PATCH v2 19/23] target/arm: Mark up sysregs for HFGITR bits 48..63

Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 48..63. Some of these bits are for trapping instructions which are not in the system instruction encoding (i.e. which are not handled by the ARMCPRegInfo mechanism): * ERET, ERETAA, ERETAB * SVC We will have to

[PATCH v2 22/23] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps

FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0, MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their AArch32 equivalents). This trapping is

[PATCH] target/ppc/translate: Add dummy implementation for dcblc instruction

The dcblc instruction is used by u-boot in mpc85xx/start.S. Without it, an illegal istruction exception is generated very early in the boot process where the processor is not yet able to handle exceptions. See: https://github.com/u-boot/u-boot/blob/v2023.01/arch/powerpc/cpu/mpc85xx/start.S#L1840

Re: Please review a important patch abort fix setting of CPUX86State::gdt::base

On 1/30/23 03:12, fa...@mail.ustc.edu.cn wrote: 1. "The memcpy is definitely wrong, because you're casting a guest address into a host address, which is incorrect. You have to use g2h()." There is no need to use g2h(), Because there are both guest address whether source or dest memory. refer

[PULL 30/56] tests: acpi: whitelist DSDT before refactoring acpi based PCI hotplug machinery

From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-21-imamm...@redhat.com> --- tests/qtest/bios-tables-test-allowed-diff.h | 36 + 1 file changed, 36 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h

[PULL 14/56] tests: acpi: extend pcihp with nested bridges

From: Igor Mammedov add nested bridges/root-ports to pcihp tests, to make sure follow up patches don't break nested enumeration of bridges in DSDT. Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-5-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S.

[PULL 04/56] hw/acpi/piix4: No need to #include "hw/southbridge/piix.h"

From: Bernhard Beschow hw/acpi/piix4 has its own header with its structure definition etc. Ammends commit 2bfd0845f0 'hw/acpi/piix4: move PIIX4PMState into separate piix4.h header'. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id:

[PULL 12/56] tests: acpi: cleanup arguments to make them more readable

From: Igor Mammedov no functional change Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-3-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test.c | 17 +++-- 1 file changed, 7 insertions(+), 10

[PULL 15/56] tests: acpi: update expected blobs

From: Igor Mammedov add extra nested bridges/root ports to blobs so it would be posible to check how follow up patches would affect it. Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-6-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin

[PULL 07/56] hw/pci-host: Use register definitions from PCI standard

From: Philippe Mathieu-Daudé No need to document magic values when the definition names from "standard-headers/linux/pci_regs.h" are self-explicit. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20230105173702.56610-1-phi...@linaro.org> Reviewed-by: Michael S. Tsirkin Signed-off-by:

[PULL 49/56] pcihp: generate populated non-hotpluggble slot descriptions on non-hotplug path

From: Igor Mammedov Generating slots descriptions populated by non-hotpluggable devices is akward at best and complicates hotplug path (build_append_pcihp_slots) needlessly, and builds only dynamic _DSM for such slots which is overlkill. Clean it up and let non-hotplug path

[PULL 19/56] pci: acpi hotplug: rename x-native-hotplug to x-do-not-expose-native-hotplug-cap

From: Igor Mammedov When ACPI PCI hotplug for Q35 was introduced (6.1), it was implemented by hiding HPC capability on PCIE slot. That however led to a number of regressions and to fix it, it was decided to keep HPC cap exposed in ACPI PCI hotplug case and force guest in ACPI PCI hotplug mode by

[PULL 33/56] tests: acpi: update expected blobs

From: Igor Mammedov Expected changes: * pc/bridge testcase due to ("pcihp: compose PCNT callchain right before its user _GPE._E01") ... +Scope (\_SB.PCI0) +{ +Scope (S18) +{ +Scope (S08) +{ +Method (PCNT, 0,

[PULL 42/56] tests: acpi: whitelist DSDT before decoupling PCI hotplug code from basic slots description

From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-33-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 14 ++ 1 file changed, 14 insertions(+) diff --git

[PULL 41/56] pcihp: isolate rule whether slot should be described in DSDT

From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-32-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 83 +++- 1 file changed, 43 insertions(+), 40

[PULL 36/56] tests: acpi: update expected blobs

From: Igor Mammedov previous commit added endpoint devices to bridge testcases, which exposes extra non-hotpluggable slot in DSDT on bus where hotplug is not available. It should look like this (numbers may vary): +Device (S28) +{ +Name (_ADR, 0x0005)

[PULL 22/56] x86: pcihp: fix invalid AML PCNT calls to hotplugged bridges

From: Igor Mammedov When QEMU is started with hotplugged bridges (think migration): QEMU -S -monitor stdio \ -device pci-bridge,chassis_nr=1 \ -device pci-bridge,bus=pci.1,addr=1.0,chassis_nr=2 (qemu) device_add pci-bridge,id=hpbr,bus=pci.1,addr=2.0,chassis_nr=3 (qemu)

[PULL 26/56] tests: acpi: add reboot cycle to bridge test

From: Igor Mammedov hotplugged bridges should not be described in DSDT, while it works on cold boot, some ACPPI PCI code are invoked during reboot. This patch will let us catch unexpected AML if hotplug checks are broken. Signed-off-by: Igor Mammedov Message-Id:

[PULL 28/56] pcihp: drop pcihp_bridge_en dependency when composing PCNT method

From: Igor Mammedov .. and use only BSEL presence to decide on how PCNT should be composed. That simplifies possible combinations to consider, but mainly it makes PCIHP AML be governed only by BSEL, which is property of PCIBus (aka part of bridge) and as result it opens possibility to convert

[PULL 40/56] pci: make sure pci_bus_is_express() won't error out with "discards ‘const’ qualifier"

From: Igor Mammedov function doesn't need RW aceess to passed in bus pointer, make it const. Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-31-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/pci/pci.h | 2 +-

[PULL 48/56] tests: acpi: whitelist DSDT before moving non-hotpluggble slots description from hotplug path

From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-39-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 11 +++ 1 file changed, 11 insertions(+) diff --git

[PATCH 10/27] tcg: Add tcg_gen_movi_ptr

Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 839d91c0c7..66b1461caa 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -1285,6 +1285,11 @@ static inline void

[PATCH 22/27] target/mips: Don't use tcg_temp_local_new

Since tcg_temp_new is now identical, use that. Signed-off-by: Richard Henderson --- target/mips/tcg/translate.c | 57 ++-- target/mips/tcg/nanomips_translate.c.inc | 4 +- 2 files changed, 16 insertions(+), 45 deletions(-) diff --git

[PATCH 13/27] accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers

Here we are creating a temp whose value needs to be replaced, but always storing NULL into CPUState.plugin_mem_cbs. Use tcg_constant_ptr(0) explicitly. Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git

[PATCH 12/27] accel/tcg/plugin: Use tcg_temp_ebb_*

All of these uses have quite local scope. Avoid tcg_const_*, because we haven't added a corresponding interface for TEMP_EBB. Use explicit tcg_gen_movi_* instead. Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 24 ++-- 1 file changed, 14 insertions(+), 10

[PATCH 18/27] target/cris: Don't use tcg_temp_local_new

Since tcg_temp_new is now identical, use that. Signed-off-by: Richard Henderson --- target/cris/translate.c | 6 +++--- target/cris/translate_v10.c.inc | 10 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c

[PATCH 00/27] tcg: Simplify temporary usage

Based-on: 20230126043824.54819-1-richard.hender...@linaro.org ("[PATCH v5 00/36] tcg: Support for Int128 with helpers") The biggest pitfall for new users of TCG is the fact that "normal" temporaries die at branches, and we must therefore use a different "local" temporary in that case. The

[PATCH 08/27] tcg: Pass TCGTempKind to tcg_temp_new_internal

While the argument can only be TEMP_EBB or TEMP_TB, it's more obvious this way. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 18 +- tcg/tcg.c | 8 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h

[PATCH 02/27] accel/tcg: Pass max_insn to gen_intermediate_code by pointer

In preparation for returning the number of insns generated via the same pointer. Adjust only the prototypes so far. Signed-off-by: Richard Henderson --- include/exec/translator.h | 4 ++-- accel/tcg/translate-all.c | 2 +- accel/tcg/translator.c| 4 ++--

Re: [PATCH] target/arm: Fix physical address resolution for Stage2

On 1/30/23 10:59, Richard Henderson wrote: Conversion to probe_access_full missed applying the page offset. Cc: qemu-sta...@nongnu.org Reported-by: Sid Manning Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking") Signed-off-by: Richard Henderson --- target/arm/ptw.c |

[PATCH 24/27] target/xtensa: Don't use tcg_temp_local_new_*

Since tcg_temp_new_* is now identical, use those. Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 8d7bf566de..4af0650deb 100644 ---

[PATCH 23/27] target/ppc: Don't use tcg_temp_local_new

Since tcg_temp_new is now identical, use that. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 6 +++--- target/ppc/translate/spe-impl.c.inc | 8 target/ppc/translate/vmx-impl.c.inc | 4 ++-- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git

[PATCH v6 00/36] tcg: Support for Int128 with helpers

Branch: https://gitlab.com/rth7680/qemu/-/tree/tcg-i128 Based-on: 20230124020507.3732200-1-richard.hender...@linaro.org ("[PULL v2 00/15] tcg patch queue") Changes for v6: * R-b applied. Patches lacking review: 05-tcg-Add-TCG_CALL_-RET-ARG-_BY_REF.patch

[PATCH v6 07/36] tcg: Add TCG_CALL_RET_BY_VEC

This will be used by _WIN64 to return i128. Not yet used, because allocation is not yet enabled. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 1 + tcg/tcg.c | 19 +++ 2 files changed, 20 insertions(+) diff --git

[PATCH v6 32/36] target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG

Signed-off-by: Richard Henderson --- Cc: David Hildenbrand Cc: Ilya Leoshkevich --- target/s390x/helper.h| 2 -- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/mem_helper.c| 52 -- target/s390x/tcg/translate.c | 55

[PATCH v2 0/4] block: fix detect-zeroes= with BDRV_REQ_REGISTERED_BUF

v2: - Add comment explaining unbalanced error code path in qemu_io_alloc_from_file() [Eric] - List options alphabetically in help output [Eric] - Add Tested-by/Reviewed-by - CC qemu-stable on the fix The first patch fixes a regression in QEMU 7.2 where detect-zeroes breaks with virtio-blk

Re: [PATCH] target/riscv: set tval for triggered watchpoints

On 1/30/23 00:07, Sergey Matyukevich wrote: From: Sergey Matyukevich According to priviledged spec, if [sm]tval is written with a nonzero value when a breakpoint exception occurs, then [sm]tval will contain the faulting virtual address. Set tval to hit address when breakpoint exception is

[PULL 09/56] intel-iommu: Document iova_tree

From: Peter Xu It seems not super clear on when iova_tree is used, and why. Add a rich comment above iova_tree to track why we needed the iova_tree, and when we need it. Also comment for the map/unmap messages, on how they're used and implications (e.g. unmap can be larger than the mapped

[PULL 02/56] hw/i386/acpi-build: Remove unused attributes

From: Bernhard Beschow Ammends commit 3db119da7915 'pc: acpi: switch to AML API composed DSDT'. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Igor Mammedov Message-Id: <20230121151941.24120-2-shen...@gmail.com> Reviewed-by: Michael S. Tsirkin

[PULL 00/56] virtio,pc,pci: features, cleanups, fixes

The following changes since commit 13356edb87506c148b163b8c7eb0695647d00c2a: Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-01-24 09:45:33 +) are available in the Git repository at: https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git

[PULL 10/56] x86: don't let decompressed kernel image clobber setup_data

From: "Jason A. Donenfeld" The setup_data links are appended to the compressed kernel image. Since the kernel image is typically loaded at 0x10, setup_data lives at `0x10 + compressed_size`, which does not get relocated during the kernel's boot process. The kernel typically decompresses

[PULL 29/56] tests: acpi: update expected blobs

From: Igor Mammedov expected change: Scope (PCI0) ... Method (PCNT, 0, NotSerialized) { } ... } Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-20-imamm...@redhat.com> ---

[PULL 13/56] tests: acpi: whitelist DSDT blobs for tests that use pci-bridges

From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-4-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 4 1 file changed, 4 insertions(+) diff --git

[PULL 01/56] shpc: disallow unplug when power indicator is blinking

From: Vladimir Sementsov-Ogievskiy Pressing attention button has special meaning when power indicator is blinking. Better just not do it. For example, trying to remove device immediately after hotplug leads to both commands succeded but device not actually unrealized. Same thing for PCIE

[PULL 05/56] hw/acpi/acpi_dev_interface: Remove unused parameter from AcpiDeviceIfClass::madt_cpu

From: Bernhard Beschow The only function ever assigned to AcpiDeviceIfClass::madt_cpu is pc_madt_cpu_entry() which doesn't use the AcpiDeviceIf parameter. Signed-off-by: Bernhard Beschow Reviewed-by: Igor Mammedov Message-Id: <20230121151941.24120-5-shen...@gmail.com> Reviewed-by: Michael S.

[PULL 20/56] pcihp: piix4: do not call acpi_pcihp_reset() when ACPI PCI hotplug is disabled

From: Igor Mammedov piix4_pm_reset() is calling acpi_pcihp_reset() when ACPI PCI hotplug is disabled, which leads to assigning BSEL properties to bridges on path acpi_set_bsel() ... if (qbus_is_hotpluggable(BUS(bus))) { // above happens to be true by default (though

[PULL 47/56] tests: acpi: update expected blobs

From: Igor Mammedov expected change is removal of dynamic _DSM bits from slots populated by coldplugged bridges (something like): -Scope (S18) -{ -Name (ASUN, 0x03) -Method (_DSM, 4, Serialized) // _DSM: Device-Specific

[PULL 17/56] pci_bridge: remove whitespace

From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-8-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/pci-bridge/pci_bridge_dev.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/pci-bridge/pci_bridge_dev.c

[PULL 35/56] tests: acpi: add endpoint devices to bridges

From: Igor Mammedov to make sure that they are enumerated or ignored as expected Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-26-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test.c | 37

[PATCH 19/27] target/hexagon: Don't use tcg_temp_local_new_*

Since tcg_temp_new_* is now identical, use those. Signed-off-by: Richard Henderson --- target/hexagon/idef-parser/README.rst | 4 ++-- target/hexagon/gen_tcg.h| 4 ++-- target/hexagon/genptr.c | 16

[PATCH v6 30/36] target/s390x: Use Int128 for returning float128

Acked-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Remove extraneous return_low128. --- target/s390x/helper.h| 22 +++--- target/s390x/tcg/insn-data.h.inc | 20 ++--- target/s390x/tcg/fpu_helper.c| 29

[PATCH v6 04/36] tcg: Introduce tcg_out_addi_ptr

Implement the function for arm, i386, and s390x, which will use it. Add stubs for all other backends. Reviewed-by: Alex Bennée Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/tcg.c| 2 ++ tcg/aarch64/tcg-target.c.inc | 7 +++

[PATCH v6 25/36] target/s390x: Use a single return for helper_divs64/u64

Pack the quotient and remainder into a single Int128. Use the divu128 primitive to remove the cpu_abort on 32-bit hosts. Reviewed-by: Philippe Mathieu-Daudé Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- v2: Extended div test case to cover these insns. ---

[PATCH v6 08/36] include/qemu/int128: Use Int128 structure for TCI

We are about to allow passing Int128 to/from tcg helper functions, but libffi doesn't support __int128_t, so use the structure. In order for atomic128.h to continue working, we must provide a mechanism to frob between real __int128_t and the structure. Provide a new union, Int128Alias, for this.

[PATCH v6 11/36] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128

Fill in the parameters for libffi for Int128. Adjust the interpreter to allow for 16-byte return values. Adjust tcg_out_call to record the return value length. Call parameters are no longer all the same size, so we cannot reuse the same call_slots array for every function. Compute it each time

[PATCH v6 29/36] target/s390x: Copy wout_x1 to wout_x1_P

Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/insn-data.h.inc | 12

[PATCH v6 27/36] target/s390x: Use Int128 for return from CKSM

Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++ target/s390x/tcg/translate.c | 6 -- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git

[PATCH v2 3/4] qemu-io: add -r option to register I/O buffer

The blk_register_buf() API is an optimization hint that allows some block drivers to avoid I/O buffer housekeeping or bounce buffers. Add an -r option to register the I/O buffer so that qemu-io can be used to test the blk_register_buf() API. The next commit will add a test that uses the new

[PATCH v2 2/4] qemu-io: use BdrvRequestFlags instead of int

The block layer APIs use BdrvRequestFlags while qemu-io code uses int. Although the code compiles and runs fine, BdrvRequestFlags is clearer because it differentiates between other types of flags like bdrv_open() flags. This is purely refactoring. Reviewed-by: Eric Blake Signed-off-by: Stefan

[PATCH v2 4/4] iotests/detect-zeroes-registered-buf: add new test

This regression test demonstrates that detect-zeroes works with registered buffers. Bug details: https://gitlab.com/qemu-project/qemu/-/issues/1404 Reviewed-by: Eric Blake Signed-off-by: Stefan Hajnoczi --- .../tests/detect-zeroes-registered-buf| 58 +++

[PATCH v2 1/4] block: fix detect-zeroes= with BDRV_REQ_REGISTERED_BUF

When a write request is converted into a write zeroes request by the detect-zeroes= feature, it is no longer associated with an I/O buffer. The BDRV_REQ_REGISTERED_BUF flag doesn't make sense without an I/O buffer and must be cleared because bdrv_co_do_pwrite_zeroes() fails with -EINVAL when it's

[PATCH v2 08/23] target/arm: Define the FEAT_FGT registers

Define the system registers which are provided by the FEAT_FGT fine-grained trap architectural feature: HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2 All these registers are a set of bit fields, where each bit is set for a trap and clear to not trap on a particular system register

[PATCH v2 04/23] target/arm: Move do_coproc_insn() syndrome calculation earlier

Rearrange the code in do_coproc_insn() so that we calculate the syndrome value for a potential trap early; we're about to add a second check that wants this value earlier than where it is currently determined. (Specifically, a trap to EL2 because of HSTR_EL2 should take priority over an UNDEF to

[PATCH v2 05/23] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps

The HSTR_EL2 register has a collection of trap bits which allow trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor registers. The specification of these bits is that when the bit is set we should trap * EL1 accesses * EL0 accesses, if the access is not UNDEFINED when the trap bit

[PATCH v2 11/23] target/arm: Mark up sysregs for HFGRTR bits 12..23

Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 12..23. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-12-peter.mayd...@linaro.org --- target/arm/cpregs.h | 12 target/arm/helper.c | 12 2

[PATCH v2 15/23] target/arm: Mark up sysregs for HDFGRTR bits 12..63

Mark up the sysreg definitions for the registers trapped by HDFGRTR/HDFGWTR bits 12..x. Bits 12..22 and bit 58 are for PMU registers. The remaining bits in HDFGRTR/HDFGWTR are for traps on registers that are part of features we don't implement: Bits 23..32 and 63 : FEAT_SPE Bits 33..48 :

[PATCH v2 18/23] target/arm: Mark up sysregs for HFGITR bits 18..47

Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 18..47. These bits cover TLBI TLB maintenance instructions. (If we implemented FEAT_XS we would need to trap some of the instructions added by that feature using these bits; but we don't yet, so will need to add the

[PATCH v2 14/23] target/arm: Mark up sysregs for HDFGRTR bits 0..11

Mark up the sysreg definitons for the registers trapped by HDFGRTR/HDFGWTR bits 0..11. These cover various debug related registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-15-peter.mayd...@linaro.org --- target/arm/cpregs.h | 12

[PATCH v2 07/23] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled

The HSTR_EL2 register is not supposed to have an effect unless EL2 is enabled in the current security state. We weren't checking for this, which meant that if the guest set up the HSTR_EL2 register we would incorrectly trap even for accesses from Secure EL0 and EL1. Add the missing checks.

[PATCH v2 23/23] target/arm: Enable FEAT_FGT on '-cpu max'

Update the ID registers for TCG's '-cpu max' to report the presence of FEAT_FGT Fine-Grained Traps support. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230127175507.2895013-24-peter.mayd...@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c

Re: [PATCH] vhost-user-fs: Back up vqs before cleaning up vhost_dev

On Mon, Jan 30, 2023 at 11:02:25PM +0900, Akihiko Odaki wrote: > vhost_dev_cleanup() clears vhost_dev so back up its vqs member to free > the memory pointed by the member. > > Fixes: 98fc1ada4c ("virtio: add vhost-user-fs base device") > Signed-off-by: Akihiko Odaki Reviewed-by: Michael S.

Re: [PATCH 2/2] tcg: use QTree instead of GTree

On 1/29/23 23:27, Daniel P. Berrangé wrote: On Sun, Jan 29, 2023 at 05:38:08PM -0500, Emilio Cota wrote: Since this is a correctness issue, I think we should ship with qtree and use it when configuring with glib <2.76.0. For later glib versions we would just use gtree, e.g. via typedef + inline

Re: [PATCH v2 00/23] target/arm: Implement FEAT_FGT fine-grained traps

Hi, On Mon, Jan 30, 2023 at 6:26 PM Peter Maydell wrote: > > This series implements the FEAT_FGT fine-grained traps architectural > feature. The bulk of this is new system registers HFGRTR_EL2, HFGWTR_EL2, > HFGITR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, which have bits that enable > trapping of system

Re: [PATCH] softmmu: Use memmove in flatview_write_continue

On 230130 2251, Akihiko Odaki wrote: > We found a case where the source passed to flatview_write_continue() may > overlap with the destination when fuzzing igb, a new proposed network > device with sanitizers. > > igb uses pci_dma_map() to get Tx packet, and pci_dma_write() to write Rx > buffer.

[PULL 06/56] vhost-user: Correct a reference of TARGET_AARCH64

From: Akihiko Odaki Presumably TARGET_ARM_64 should be a mistake of TARGET_AARCH64. Signed-off-by: Akihiko Odaki Message-Id: <20230109063130.81296-1-akihiko.od...@daynix.com> Fixes: 27598393a2 ("Lift max memory slots limit imposed by vhost-user") Reviewed-by: Philippe Mathieu-Daudé

[PULL 24/56] tests: acpi: extend bridge tests with hotplugged bridges

From: Igor Mammedov with previous commit fixing malformed PCNT calls to hotplugged bridges, it should be possible add coldplug/hotplug test when describing PCI topology in DSDT without breeaking CI. Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-15-imamm...@redhat.com>

[PULL 53/56] tests/qtest/bios-tables-test: Make the test less verbose by default

From: Thomas Huth We are facing the issues that our test logs in the gitlab CI are too big (and thus cut off). The bios-tables-test is one of the few qtests that prints many lines of output by default when running with V=1, so it contributes to this problem. Almost all other qtests are silent

[PULL 39/56] pcihp: make bridge describe itself using AcpiDevAmlIfClass:build_dev_aml

From: Igor Mammedov simplify build_append_pci_bus_devices() a bit by handling bridge specific logic in bridge dedicated AcpiDevAmlIfClass::build_dev_aml callback. Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-30-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin

[PULL 23/56] tests: boot_sector_test: avoid crashing if status is not available yet

From: Igor Mammedov If test case was started in paused mode (-S CLI option) and then allowed to continue via QMP, boot_sector_test could assert on transient state with following error: assertion failed (qdict_get_try_str(qret, "status") == "running"): (NULL == "running") Instead of

[PULL 56/56] docs/pcie.txt: Replace ioh3420 with pcie-root-port

From: Marcel Apfelbaum Do not mention ioh3420 in the "how to" doc. The device still works and can be used by already existing setups, but no need to be mentioned. Suggested-by: Andrew Jones Reviewed-by: Laszlo Ersek Signed-off-by: Marcel Apfelbaum Signed-off-by: Daniel P. Berrangé

[PULL 45/56] tests: acpi: whitelist DSDT blobs before removing dynamic _DSM on coldplugged bridges

From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20230112140312.3096331-36-imamm...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 4 1 file changed, 4 insertions(+) diff --git

Re: [PATCH] softmmu: Use memmove in flatview_write_continue

On Mon, Jan 30, 2023 at 03:03:00PM -0500, Alexander Bulekov wrote: > On 230130 2251, Akihiko Odaki wrote: > > We found a case where the source passed to flatview_write_continue() may > > overlap with the destination when fuzzing igb, a new proposed network > > device with sanitizers. > > > > igb

[PULL 43/56] pcihp: acpi: decouple hotplug and generic slots description

From: Igor Mammedov Split build_append_pci_bus_devices() onto generic part that builds AML descriptions only for populated slots which is applicable to both hotplug disabled and enabled bridges. And a hotplug only part that complements generic AML with hotplug depended bits (that depend on

[PULL 25/56] tests: boot_sector_test(): make it multi-shot

From: Igor Mammedov if the function is called the 2nd time within the same qtest session, it will prematurely return before boot sector is executed due to remaining signature. Follow up patch will add VM reboot to a test case and will call boot_sector_test() again within the same qtest env,

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