Re: [PATCH v2] softmmu: Use memmove in flatview_write_continue
On 31.01.23 04:01, Akihiko Odaki wrote: We found a case where the source passed to flatview_write_continue() may overlap with the destination when fuzzing igb, a new proposed network device with sanitizers. igb uses pci_dma_map() to get Tx packet, and pci_dma_write() to write Rx buffer. While pci_dma_write() is usually used to write data from memory not mapped to the guest, if igb is configured to perform loopback, the data will be sourced from the guest memory. The source and destination can overlap and the usage of memcpy() will be invalid in such a case. While we do not really have to deal with such an invalid request for igb, detecting the overlap in igb code beforehand requires complex code, and only covers this specific case. Instead, just replace memcpy() with memmove() to tolerate overlaps. Using memmove() will slightly damage the performance as it will need to check overlaps before using SIMD instructions for copying, but the cost should be negligible, considering the inherent complexity of flatview_write_continue(). The test cases generated by the fuzzer is available at: https://patchew.org/QEMU/20230129053316.1071513-1-alx...@bu.edu/ The fixed test case is: fuzz/crash_47dfe62d9f911bf523ff48cd441b61c0013ed805 Signed-off-by: Akihiko Odaki Acked-by: Alexander Bulekov --- Acked-by: David Hildenbrand -- Thanks, David / dhildenb
Re: [PATCH 4/6] gitlab-ci.d/buildtest: Merge the --without-default-* jobs
On 30/01/2023 14.28, Fabiano Rosas wrote: Thomas Huth writes: Let's safe some CI minutes by merging these two jobs. We can now also drop "--disable-capstone" since the capstone submodule has been removed a while ago. We should rather tes --disable-fdt now to test a compilation without the "dtc" submodule (for this we have to drop i386-softmmu from the target list unfortunately). Additionally, the qtests with s390x and sh4 are not read for "--without-default-devices" yet, Fyi, I've been working on a series to make the qtests work with the --without-default-devices build for i386 or aarch64. Great, I'm looking forward to this! There are some qtests explicitly adding devices without checking and hardcoded defaults on vl.c and machine init code without a matching KConfig dependency. Yes, I also noticed this while working on these patches ... many other binaries even don't start since they try to instantiate a default NIC that might not be available ... fixing the whole of QEMU will certainly take some time, but if you get x86 and aarch64 working, that's certainly a good start! so we can only test mips64 and avr here now. Signed-off-by: Thomas Huth Reviewed-by: Fabiano Rosas Thanks! Thomas
Re: [PATCH v9 01/58] include: import Xen public headers to include/standard-headers/
On Mon, 2023-01-30 at 09:41 +0100, Thomas Huth wrote: > > The files in include/standard-headers are created automatically by the > scripts/update-linux-headers.sh script, so I was a little bit surprised that > you don't provide an update to that script first ... if you copy new headers > there manually, that might cause troubles later for the next person who > runs the update-linux-headers.sh script. So I suggest to either adapt the > script for your needs, or put the xen headers in a different location. Thanks; I hadn't clocked that include/standard-headers was in fact just *Linux* headers. I'd previously added the new headers here, done a bunch of header untangling and moving code to use them, and then removed the old ones. It turns out that through some combination of the header cleanups which have already happened in the master branch, various cleanup iterations of this series, and a few more tweaks within the series, I can drop the updated headers directly over the top of the old ones in include/hw/xen/interface. Updated in https://git.infradead.org/users/dwmw2/qemu.git/shortlog/refs/heads/xenfv smime.p7s Description: S/MIME cryptographic signature
Re: [PATCH v3] migration: Remove res_compatible parameter
On 1/30/23 11:06, Juan Quintela wrote: It was only used for RAM, and in that case, it means that this amount of data was sent for memory. Just delete the field in all callers. Could you describe, why it's safe to change the behavior for RAM? Also, I think it would be a lot better to split the change for RAM (s/res_compatible/res_postcopy) in one patch, and then drop the totally unused res_compatible file in the second patch -- Best regards, Vladimir
Re: [PATCH v2 5/8] hw/i386/acpi: Drop duplicate _UID entry for CXL root bridge
On Fri, 27 Jan 2023 21:38:20 -0500
"Michael S. Tsirkin" wrote:
> On Thu, Jan 12, 2023 at 10:26:41AM +, Jonathan Cameron wrote:
> > Noticed as this prevents iASL disasembling the DSDT table.
> >
> > Reviewed-by: Ira Weiny
> > Signed-off-by: Jonathan Cameron
>
> This needed but it looks like you did not bother updating
> expected files for the tests. Did you run make check?
Sorry, that was sloppy of me.
v3 with table update dance for q35/DSDT.cxl sent out.
(I failed to send this email yesterday).
>
> > ---
> > hw/i386/acpi-build.c | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > index 127c4e2d50..a584b62ae2 100644
> > --- a/hw/i386/acpi-build.c
> > +++ b/hw/i386/acpi-build.c
> > @@ -1482,7 +1482,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> > aml_append(pkg, aml_eisaid("PNP0A03"));
> > aml_append(dev, aml_name_decl("_CID", pkg));
> > aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> > -aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
> > build_cxl_osc_method(dev);
> > } else if (pci_bus_is_express(bus)) {
> > aml_append(dev, aml_name_decl("_HID",
> > aml_eisaid("PNP0A08")));
> > --
> > 2.37.2
>
[PATCH] target/i386: fix ADOX followed by ADCX
When ADCX is followed by ADOX or vice versa, the second instruction's
carry comes from EFLAGS. This is handled by this bit of gen_ADCOX:
tcg_gen_extract_tl(carry_in, cpu_cc_src,
ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1);
Unfortunately, in this case cc_op has been overwritten by the previous
"if" statement to CC_OP_ADCOX. This works by chance when the first
instruction is ADCX; however, if the first instruction is ADOX,
ADCX will incorrectly take its carry from OF instead of CF.
Fix by moving the computation of the new cc_op at the end of the function.
The included exhaustive test case fails without this patch and passes
afterwards.
Because ADCX/ADOX need not be invoked through the VEX prefix, this
regression bisects to commit 16fc5726a6e2 ("target/i386: reimplement
0x0f 0x38, add AVX", 2022-10-18). However, the mistake happened a
little earlier, when BMI instructions were rewritten using the new
decoder framework.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1471
Reported-by: Paul Jolly
Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to
new decoder", 2022-10-18)
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/emit.c.inc | 20 +
tests/tcg/i386/Makefile.target | 6 ++-
tests/tcg/i386/test-i386-adcox.c | 75
3 files changed, 91 insertions(+), 10 deletions(-)
create mode 100644 tests/tcg/i386/test-i386-adcox.c
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index e33688f672a2..5a1d3803f901 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -866,6 +866,7 @@ VSIB_AVX(VPGATHERQ, vpgatherq)
static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
{
+int opposite_cc_op;
TCGv carry_in = NULL;
TCGv carry_out = (cc_op == CC_OP_ADCX ? cpu_cc_dst : cpu_cc_src2);
TCGv zero;
@@ -873,14 +874,8 @@ static void gen_ADCOX(DisasContext *s, CPUX86State *env,
MemOp ot, int cc_op)
if (cc_op == s->cc_op || s->cc_op == CC_OP_ADCOX) {
/* Re-use the carry-out from a previous round. */
carry_in = carry_out;
-cc_op = s->cc_op;
-} else if (s->cc_op == CC_OP_ADCX || s->cc_op == CC_OP_ADOX) {
-/* Merge with the carry-out from the opposite instruction. */
-cc_op = CC_OP_ADCOX;
-}
-
-/* If we don't have a carry-in, get it out of EFLAGS. */
-if (!carry_in) {
+} else {
+/* We don't have a carry-in, get it out of EFLAGS. */
if (s->cc_op != CC_OP_ADCX && s->cc_op != CC_OP_ADOX) {
gen_compute_eflags(s);
}
@@ -904,7 +899,14 @@ static void gen_ADCOX(DisasContext *s, CPUX86State *env,
MemOp ot, int cc_op)
tcg_gen_add2_tl(s->T0, carry_out, s->T0, carry_out, s->T1, zero);
break;
}
-set_cc_op(s, cc_op);
+
+opposite_cc_op = cc_op == CC_OP_ADCX ? CC_OP_ADOX : CC_OP_ADCX;
+if (s->cc_op == CC_OP_ADCOX || s->cc_op == opposite_cc_op) {
+/* Merge with the carry-out from the opposite instruction. */
+set_cc_op(s, CC_OP_ADCOX);
+} else {
+set_cc_op(s, cc_op);
+}
}
static void gen_ADCX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
diff --git a/tests/tcg/i386/Makefile.target b/tests/tcg/i386/Makefile.target
index 3273aa8061f8..ac443995447f 100644
--- a/tests/tcg/i386/Makefile.target
+++ b/tests/tcg/i386/Makefile.target
@@ -14,7 +14,7 @@ config-cc.mak: Makefile
I386_SRCS=$(notdir $(wildcard $(I386_SRC)/*.c))
ALL_X86_TESTS=$(I386_SRCS:.c=)
SKIP_I386_TESTS=test-i386-ssse3 test-avx test-3dnow test-mmx
-X86_64_TESTS:=$(filter test-i386-bmi2 $(SKIP_I386_TESTS), $(ALL_X86_TESTS))
+X86_64_TESTS:=$(filter test-i386-adcox test-i386-bmi2 $(SKIP_I386_TESTS),
$(ALL_X86_TESTS))
test-i386-sse-exceptions: CFLAGS += -msse4.1 -mfpmath=sse
run-test-i386-sse-exceptions: QEMU_OPTS += -cpu max
@@ -28,6 +28,10 @@ test-i386-bmi2: CFLAGS=-O2
run-test-i386-bmi2: QEMU_OPTS += -cpu max
run-plugin-test-i386-bmi2-%: QEMU_OPTS += -cpu max
+test-i386-adcox: CFLAGS=-O2
+run-test-i386-adcox: QEMU_OPTS += -cpu max
+run-plugin-test-i386-adcox-%: QEMU_OPTS += -cpu max
+
#
# hello-i386 is a barebones app
#
diff --git a/tests/tcg/i386/test-i386-adcox.c b/tests/tcg/i386/test-i386-adcox.c
new file mode 100644
index ..16169efff823
--- /dev/null
+++ b/tests/tcg/i386/test-i386-adcox.c
@@ -0,0 +1,75 @@
+/* See if various BMI2 instructions give expected results */
+#include
+#include
+#include
+
+#define CC_C 1
+#define CC_O (1 << 11)
+
+#ifdef __x86_64__
+#define REG uint64_t
+#else
+#define REG uint32_t
+#endif
+
+void test_adox_adcx(uint32_t in_c, uint32_t in_o, REG adcx_operand, REG
adox_operand)
+{
+REG flags;
+REG out_adcx, out_adox;
+
+asm("pushf; pop %0" : "=r"(flags));
+flags &= ~(CC_C | CC_O);
+flags |= (in_c ? CC_C : 0);
+flags |= (in_o ? CC_O : 0);
+
+out_adcx = adcx_operand;
+
Re: [PATCH v6 32/36] target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG
On 30.01.23 22:48, Richard Henderson wrote: Signed-off-by: Richard Henderson --- Cc: David Hildenbrand Cc: Ilya Leoshkevich --- Acked-by: David Hildenbrand -- Thanks, David / dhildenb
Re: [PATCH] acpi: Set maximum size to 64k for "etc/acpi/rsdp" blob
Michael S. Tsirkin 于2023年1月30日周一 23:07写道：
>
> On Mon, Jan 30, 2023 at 10:47:25PM +0800, Feng Sun wrote:
> > Igor Mammedov 于2023年1月24日周二 18:30写道：
> > >
> > > On Tue, 17 Jan 2023 19:15:21 +0800
> > > Sun Feng wrote:
> > >
> > > > Migrate from aarch64 host with PAGE_SIZE 64k to 4k failed with
> > > > following errors:
> > > >
> > > > qmp_cmd_name: migrate-incoming, arguments: {"uri": "tcp:[::]:49152"}
> > > > {"timestamp": {"seconds": 1673922775, "microseconds": 534702}, "event":
> > > > "MIGRATION", "data": {"status": "setup"}}
> > > > {"timestamp": {"seconds": 1673922776, "microseconds": 53003}, "event":
> > > > "MIGRATION", "data": {"status": "active"}}
> > > > 2023-01-17T02:32:56.058827Z qemu-system-aarch64: Length too large:
> > > > /rom@etc/acpi/rsdp: 0x1 > 0x1000: Invalid argument
> > >
> > > this should mention/explain why it's happening.
> > >
> > > i.e we now have 4k limit for RSDP, but then source somehow managed to
> > > start with 64k
> > > allocated to for RSDP. It looks like limit isn't working as expected to
> > > me.
> >
> > 4k limit should be romsize limit. I can see Rom '/rom@etc/acpi/rsdp'
> > with romsize:4096, datasize:36.
> > RAMBlock's used_length is set with datasize aligned to PAGE_SIZE, so
> > it become 64k when PAGE_SIZE is 64k.
> > ```
> > static
> > RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
> > void (*resized)(const char*,
> > uint64_t length,
> > void *host),
> > void *host, uint32_t ram_flags,
> > MemoryRegion *mr, Error **errp)
> > {
> > RAMBlock *new_block;
> > Error *local_err = NULL;
> >
> > assert((ram_flags & ~(RAM_SHARED | RAM_RESIZEABLE | RAM_PREALLOC |
> > RAM_NORESERVE)) == 0);
> > assert(!host ^ (ram_flags & RAM_PREALLOC));
> >
> > size = HOST_PAGE_ALIGN(size);
> > max_size = HOST_PAGE_ALIGN(max_size);
> > new_block = g_malloc0(sizeof(*new_block));
> > new_block->mr = mr;
> > new_block->resized = resized;
> > new_block->used_length = size;
> > ```
> > So when migrate to 4k PAGE_SIZE, it will report the errors.
> >
> > ramblock information for PAGE_SIZE 64k and 4k.
> > ```
> > # getconf PAGE_SIZE
> > 65536
> > # virsh qemu-monitor-command testvm --hmp 'info ramblock'
> > Block NamePSize Offset
> > Used Total
> >mach-virt.ram 64 KiB 0x
> > 0x4000 0x4000
> > virt.flash0 64 KiB 0x4000
> > 0x0400 0x0400
> > virt.flash1 64 KiB 0x4400
> > 0x0400 0x0400
> > /rom@etc/acpi/tables 64 KiB 0x4804
> > 0x0002 0x0020
> > :00:01.2:00.0/virtio-net-pci.rom 64 KiB 0x4800
> > 0x0004 0x0004
> >/rom@etc/table-loader 64 KiB 0x4824
> > 0x0001 0x0001
> > /rom@etc/acpi/rsdp 64 KiB 0x4828
> > 0x0001 0x0001
> >
> > # getconf PAGE_SIZE
> > 4096
> > # virsh qemu-monitor-command testvm --hmp 'info ramblock'
> > Block NamePSize Offset
> > Used Total
> >mach-virt.ram4 KiB 0x
> > 0x0008 0x0008
> > virt.flash04 KiB 0x0008
> > 0x0400 0x0400
> > virt.flash14 KiB 0x00080400
> > 0x0400 0x0400
> > /rom@etc/acpi/tables4 KiB 0x00080800
> > 0x0002 0x0020
> >/rom@etc/table-loader4 KiB 0x00080820
> > 0x1000 0x0001
> > /rom@etc/acpi/rsdp4 KiB 0x00080824
> > 0x1000 0x1000
> > ```
>
> Oh interesting. I don't remember why I decided to align in.
> What does the following do (warning: completely untested):
>
>
> diff --git a/softmmu/physmem.c b/softmmu/physmem.c
> index cb998cdf23..5c732101b9 100644
> --- a/softmmu/physmem.c
> +++ b/softmmu/physmem.c
> @@ -2154,7 +2154,7 @@ RAMBlock *qemu_ram_alloc_internal(ram_addr_t size,
> ram_addr_t max_size,
>RAM_NORESERVE)) == 0);
> assert(!host ^ (ram_flags & RAM_PREALLOC));
>
> -size = HOST_PAGE_ALIGN(size);
> +// size = HOST_PAGE_ALIGN(size);
> max_size = HOST_PAGE_ALIGN(max_size);
> new_block = g_malloc0(sizeof(*new_block));
> new_block->mr = mr;
>
With additional change we can see actually used size with 'info ramblock',
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -1837,7 +1837,7 @@ int qemu_ram_resize(RAMBlock *block, ram_addr_t
newsize, Error **errp)
assert(block);
-newsize =
[PATCH v3 5/9] igb: check oversized packets for VMDq
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 48 +++
1 file changed, 40 insertions(+), 8 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 4a1b98bf0e..2f6f30341f 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -912,12 +912,27 @@ igb_rx_l4_cso_enabled(IGBCore *core)
return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
}
+static bool
+igb_rx_is_oversized(IGBCore *core, uint16_t qn, size_t size)
+{
+uint16_t pool = qn % IGB_NUM_VM_POOLS;
+bool lpe = !!(core->mac[VMOLR0 + pool] & E1000_VMOLR_LPE);
+int maximum_ethernet_lpe_size =
+core->mac[VMOLR0 + pool] & E1000_VMOLR_RLPML_MASK;
+int maximum_ethernet_vlan_size = 1522;
+
+return lpe ? size > maximum_ethernet_lpe_size :
+size > maximum_ethernet_vlan_size;
+}
+
static uint16_t igb_receive_assign(IGBCore *core, const struct eth_header
*ehdr,
- E1000E_RSSInfo *rss_info, bool *external_tx)
+ size_t size, E1000E_RSSInfo *rss_info,
+ bool *external_tx)
{
static const int ta_shift[] = { 4, 3, 2, 0 };
uint32_t f, ra[2], *macp, rctl = core->mac[RCTL];
uint16_t queues = 0;
+uint16_t oversized = 0;
uint16_t vid = lduw_be_p(_GET_VLAN_HDR(ehdr)->h_tci) & VLAN_VID_MASK;
bool accepted = false;
int i;
@@ -943,7 +958,7 @@ static uint16_t igb_receive_assign(IGBCore *core, const
struct eth_header *ehdr,
if (core->mac[MRQC] & 1) {
if (is_broadcast_ether_addr(ehdr->h_dest)) {
-for (i = 0; i < 8; i++) {
+for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) {
queues |= BIT(i);
}
@@ -977,7 +992,7 @@ static uint16_t igb_receive_assign(IGBCore *core, const
struct eth_header *ehdr,
f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff;
if (macp[f >> 5] & (1 << (f & 0x1f))) {
-for (i = 0; i < 8; i++) {
+for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) {
queues |= BIT(i);
}
@@ -1000,7 +1015,7 @@ static uint16_t igb_receive_assign(IGBCore *core, const
struct eth_header *ehdr,
}
}
} else {
-for (i = 0; i < 8; i++) {
+for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) {
mask |= BIT(i);
}
@@ -1017,9 +1032,26 @@ static uint16_t igb_receive_assign(IGBCore *core, const
struct eth_header *ehdr,
}
queues &= core->mac[VFRE];
-igb_rss_parse_packet(core, core->rx_pkt, external_tx != NULL,
rss_info);
-if (rss_info->queue & 1) {
-queues <<= 8;
+if (queues) {
+for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
+if ((queues & BIT(i)) && igb_rx_is_oversized(core, i, size)) {
+oversized |= BIT(i);
+}
+}
+/* 8.19.37 increment ROC if packet is oversized for all queues */
+if (oversized == queues) {
+trace_e1000x_rx_oversized(size);
+e1000x_inc_reg_if_not_full(core->mac, ROC);
+}
+queues &= ~oversized;
+}
+
+if (queues) {
+igb_rss_parse_packet(core, core->rx_pkt,
+ external_tx != NULL, rss_info);
+if (rss_info->queue & 1) {
+queues <<= 8;
+}
}
} else {
switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
@@ -1563,7 +1595,7 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
e1000x_vlan_enabled(core->mac),
core->mac[VET] & 0x);
-queues = igb_receive_assign(core, ehdr, _info, external_tx);
+queues = igb_receive_assign(core, ehdr, size, _info, external_tx);
if (!queues) {
trace_e1000e_rx_flt_dropped();
return orig_size;
--
2.34.1
[PATCH v3 4/9] igb: implement VFRE and VFTE registers
Also add checks for RXDCTL/TXDCTL queue enable bits
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 30 +-
hw/net/igb_core.h | 1 +
hw/net/igb_regs.h | 3 +++
3 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index e78bc3611a..4a1b98bf0e 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -780,6 +780,18 @@ igb_txdesc_writeback(IGBCore *core, dma_addr_t base,
return igb_tx_wb_eic(core, txi->idx);
}
+static inline bool
+igb_tx_enabled(IGBCore *core, const E1000E_RingInfo *txi)
+{
+bool vmdq = core->mac[MRQC] & 1;
+uint16_t qn = txi->idx;
+uint16_t pool = qn % IGB_NUM_VM_POOLS;
+
+return (core->mac[TCTL] & E1000_TCTL_EN) &&
+(!vmdq || core->mac[VFTE] & BIT(pool)) &&
+(core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE);
+}
+
static void
igb_start_xmit(IGBCore *core, const IGB_TxRing *txr)
{
@@ -789,8 +801,7 @@ igb_start_xmit(IGBCore *core, const IGB_TxRing *txr)
const E1000E_RingInfo *txi = txr->i;
uint32_t eic = 0;
-/* TODO: check if the queue itself is enabled too. */
-if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
+if (!igb_tx_enabled(core, txi)) {
trace_e1000e_tx_disabled();
return;
}
@@ -1005,6 +1016,7 @@ static uint16_t igb_receive_assign(IGBCore *core, const
struct eth_header *ehdr,
queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT);
}
+queues &= core->mac[VFRE];
igb_rss_parse_packet(core, core->rx_pkt, external_tx != NULL,
rss_info);
if (rss_info->queue & 1) {
queues <<= 8;
@@ -1564,12 +1576,12 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
igb_rx_fix_l4_csum(core, core->rx_pkt);
for (i = 0; i < IGB_NUM_QUEUES; i++) {
-if (!(queues & BIT(i))) {
+if (!(queues & BIT(i)) ||
+!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
continue;
}
igb_rx_ring_init(core, , i);
-
if (!igb_has_rxbufs(core, rxr.i, total_size)) {
icr_bits |= E1000_ICS_RXO;
continue;
@@ -1973,9 +1985,16 @@ static void igb_set_vfmailbox(IGBCore *core, int index,
uint32_t val)
static void igb_vf_reset(IGBCore *core, uint16_t vfn)
{
+uint16_t qn0 = vfn;
+uint16_t qn1 = vfn + IGB_NUM_VM_POOLS;
+
/* disable Rx and Tx for the VF*/
-core->mac[VFTE] &= ~BIT(vfn);
+core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
+core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
+core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
+core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
core->mac[VFRE] &= ~BIT(vfn);
+core->mac[VFTE] &= ~BIT(vfn);
/* indicate VF reset to PF */
core->mac[VFLRE] |= BIT(vfn);
/* VFLRE and mailbox use the same interrupt cause */
@@ -3881,6 +3900,7 @@ igb_phy_reg_init[] = {
static const uint32_t igb_mac_reg_init[] = {
[LEDCTL]= 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24),
[EEMNGCTL] = BIT(31),
+[TXDCTL0] = E1000_TXDCTL_QUEUE_ENABLE,
[RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16),
[RXDCTL1] = 1 << 16,
[RXDCTL2] = 1 << 16,
diff --git a/hw/net/igb_core.h b/hw/net/igb_core.h
index cc3b4d1f2b..9938922598 100644
--- a/hw/net/igb_core.h
+++ b/hw/net/igb_core.h
@@ -47,6 +47,7 @@
#define IGB_MSIX_VEC_NUM(10)
#define IGBVF_MSIX_VEC_NUM (3)
#define IGB_NUM_QUEUES (16)
+#define IGB_NUM_VM_POOLS(8)
typedef struct IGBCore IGBCore;
diff --git a/hw/net/igb_regs.h b/hw/net/igb_regs.h
index ddc0f931d6..4d98079906 100644
--- a/hw/net/igb_regs.h
+++ b/hw/net/igb_regs.h
@@ -160,6 +160,9 @@ union e1000_adv_rx_desc {
#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x0080
#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX0x0100
+/* Additional Transmit Descriptor Control definitions */
+#define E1000_TXDCTL_QUEUE_ENABLE 0x0200 /* Enable specific Tx Queue */
+
/* Additional Receive Descriptor Control definitions */
#define E1000_RXDCTL_QUEUE_ENABLE 0x0200 /* Enable specific Rx Queue */
--
2.34.1
[RFC PATCH] build: deprecate --enable-gprof builds and remove from CI
As gprof relies on instrumentation you rarely get useful data compared
to a real optimised build. Lets deprecate the build option and
simplify the CI configuration as a result.
Signed-off-by: Alex Bennée
Cc: Thomas Huth
---
docs/about/deprecated.rst | 14 ++
meson.build| 7 ++-
.gitlab-ci.d/buildtest.yml | 19 ---
meson_options.txt | 3 ++-
4 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 9f1bbc495d..87b4511535 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -20,6 +20,20 @@ they were first deprecated in the 2.10.0 release.
What follows is a list of all features currently marked as
deprecated.
+Build options
+-
+
+``gprof`` builds (since 8.0)
+
+
+The ``--enable-gprof`` configure setting relies on compiler
+instrumentation to gather its data which can distort the generated
+profile. As other non-instrumenting tools are available that give a
+more holistic view of the system with non-instrumented binaries we are
+deprecating the build option and no longer defend it in CI. The
+``--enable-gcov`` build option remains for analysis test case
+coverage.
+
System emulator command line arguments
--
diff --git a/meson.build b/meson.build
index 56320ae717..ecf44ea534 100644
--- a/meson.build
+++ b/meson.build
@@ -3791,7 +3791,12 @@ summary_info += {'mutex debugging':
get_option('debug_mutex')}
summary_info += {'memory allocator': get_option('malloc')}
summary_info += {'avx2 optimization': config_host_data.get('CONFIG_AVX2_OPT')}
summary_info += {'avx512f optimization':
config_host_data.get('CONFIG_AVX512F_OPT')}
-summary_info += {'gprof enabled': get_option('gprof')}
+if get_option('gprof')
+ gprof_info = 'YES (deprecated)'
+else
+ gprof_info = get_option('gprof')
+endif
+summary_info += {'gprof': gprof_info}
summary_info += {'gcov': get_option('b_coverage')}
summary_info += {'thread sanitizer': config_host.has_key('CONFIG_TSAN')}
summary_info += {'CFI support': get_option('cfi')}
diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml
index 9a6ba1fe3b..dc8fa0a498 100644
--- a/.gitlab-ci.d/buildtest.yml
+++ b/.gitlab-ci.d/buildtest.yml
@@ -468,27 +468,16 @@ tsan-build:
TARGETS: x86_64-softmmu ppc64-softmmu riscv64-softmmu x86_64-linux-user
MAKE_CHECK_ARGS: bench V=1
-# gprof/gcov are GCC features
-build-gprof-gcov:
+# gcov is a GCC features
+gcov:
extends: .native_build_job_template
needs:
job: amd64-ubuntu2004-container
+ timeout: 80m
variables:
IMAGE: ubuntu2004
-CONFIGURE_ARGS: --enable-gprof --enable-gcov
+CONFIGURE_ARGS: --enable-gcov
TARGETS: aarch64-softmmu ppc64-softmmu s390x-softmmu x86_64-softmmu
- artifacts:
-expire_in: 1 days
-paths:
- - build
-
-check-gprof-gcov:
- extends: .native_test_job_template
- needs:
-- job: build-gprof-gcov
- artifacts: true
- variables:
-IMAGE: ubuntu2004
MAKE_CHECK_ARGS: check
after_script:
- cd build
diff --git a/meson_options.txt b/meson_options.txt
index 559a571b6b..53459c15fc 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -316,7 +316,8 @@ option('debug_stack_usage', type: 'boolean', value: false,
option('qom_cast_debug', type: 'boolean', value: false,
description: 'cast debugging support')
option('gprof', type: 'boolean', value: false,
- description: 'QEMU profiling with gprof')
+ description: 'QEMU profiling with gprof',
+ deprecated: true)
option('profiler', type: 'boolean', value: false,
description: 'profiler support')
option('slirp_smbd', type : 'feature', value : 'auto',
--
2.34.1
[PATCH v3 0/9] igb: merge changes from <20221229190817.25500-1-sriram.yagnara...@est.tech>
Based-on: <20230130140809.78262-1-akihiko.od...@daynix.com> ([PATCH v5 0/9] Introduce igb) Rebased on latest changes from Akihiko, and merged changes from my original patchset: https://lists.gnu.org/archive/html/qemu-devel/2022-12/msg04670.html Changes since v2: - Fixed more comments from Akhiko - Reordered the patches to make changes easier to understand Changes since v1: - Fix review comments from Akihiko Sriram Yagnaraman (9): MAINTAINERS: Add Sriram Yagnaraman as a igb reviewer igb: handle PF/VF reset properly igb: add ICR_RXDW igb: implement VFRE and VFTE registers igb: check oversized packets for VMDq igb: respect E1000_VMOLR_RSSE igb: implement VF Tx and Rx stats igb: respect VT_CTL ignore MAC field igb: respect VMVIR and VMOLR for VLAN MAINTAINERS | 1 + hw/net/e1000x_regs.h | 4 + hw/net/igb_core.c| 244 --- hw/net/igb_core.h| 1 + hw/net/igb_regs.h| 6 ++ hw/net/trace-events | 4 + 6 files changed, 197 insertions(+), 63 deletions(-) -- 2.34.1
[PATCH v3 8/9] igb: respect VT_CTL ignore MAC field
Also trace out a warning if replication mode is disabled, since we only
support replication mode enabled.
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 9 +
hw/net/trace-events | 2 ++
2 files changed, 11 insertions(+)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index c5f9c14f47..8115be2d76 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -964,6 +964,10 @@ static uint16_t igb_receive_assign(IGBCore *core, const
struct eth_header *ehdr,
}
if (core->mac[MRQC] & 1) {
+if (!(core->mac[VT_CTL] & E1000_VT_CTL_VM_REPL_EN)) {
+trace_igb_rx_vmdq_replication_mode_disabled();
+}
+
if (is_broadcast_ether_addr(ehdr->h_dest)) {
for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) {
@@ -1010,6 +1014,11 @@ static uint16_t igb_receive_assign(IGBCore *core, const
struct eth_header *ehdr,
}
}
+/* assume a full pool list if IGMAC is set */
+if (core->mac[VT_CTL] & E1000_VT_CTL_IGNORE_MAC) {
+queues = BIT(IGB_MAX_VF_FUNCTIONS) - 1;
+}
+
if (e1000x_vlan_rx_filter_enabled(core->mac)) {
uint16_t mask = 0;
diff --git a/hw/net/trace-events b/hw/net/trace-events
index e94172e748..9bc7658692 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -288,6 +288,8 @@ igb_rx_desc_buff_write(uint64_t addr, uint16_t offset,
const void* source, uint3
igb_rx_metadata_rss(uint32_t rss) "RSS data: 0x%X"
+igb_rx_vmdq_replication_mode_disabled(void) "WARN: Only replication mode
enabled is supported"
+
igb_irq_icr_clear_gpie_nsicr(void) "Clearing ICR on read due to GPIE.NSICR
enabled"
igb_irq_icr_write(uint32_t bits, uint32_t old_icr, uint32_t new_icr) "Clearing
ICR bits 0x%x: 0x%x --> 0x%x"
igb_irq_set_iam(uint32_t icr) "Update IAM: 0x%x"
--
2.34.1
[PATCH v3 6/9] igb: respect E1000_VMOLR_RSSE
RSS for VFs is only enabled if VMOLR[n].RSSE is set.
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 2f6f30341f..31a325d374 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1049,8 +1049,15 @@ static uint16_t igb_receive_assign(IGBCore *core, const
struct eth_header *ehdr,
if (queues) {
igb_rss_parse_packet(core, core->rx_pkt,
external_tx != NULL, rss_info);
+/* Sec 8.26.1: PQn = VFn + VQn*8 */
if (rss_info->queue & 1) {
-queues <<= 8;
+for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
+if ((queues & BIT(i)) &&
+(core->mac[VMOLR0 + i] & E1000_VMOLR_RSSE)) {
+queues |= BIT(i + IGB_NUM_VM_POOLS);
+queues &= ~BIT(i);
+}
+}
}
}
} else {
--
2.34.1
[PATCH v3 1/9] MAINTAINERS: Add Sriram Yagnaraman as a igb reviewer
I would like to review and be informed on changes to igb device Signed-off-by: Sriram Yagnaraman --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index ece23b2b15..7d0e84ce37 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2224,6 +2224,7 @@ F: tests/qtest/libqos/e1000e.* igb M: Akihiko Odaki +R: Sriram Yagnaraman S: Maintained F: docs/system/devices/igb.rst F: hw/net/igb* -- 2.34.1
[PATCH v3 7/9] igb: implement VF Tx and Rx stats
Please note that loopback counters for VM to VM traffic is not
implemented yet: VFGOTLBC, VFGPTLBC, VFGORLBC and VFGPRLBC.
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 31a325d374..c5f9c14f47 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -490,7 +490,7 @@ igb_tx_pkt_send(IGBCore *core, struct igb_tx *tx, int
queue_index)
}
static void
-igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt)
+igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt, int qn)
{
static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
PTC1023, PTC1522 };
@@ -517,6 +517,13 @@ igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt
*tx_pkt)
core->mac[GPTC] = core->mac[TPT];
core->mac[GOTCL] = core->mac[TOTL];
core->mac[GOTCH] = core->mac[TOTH];
+
+if (core->mac[MRQC] & 1) {
+uint16_t pool = qn % IGB_NUM_VM_POOLS;
+
+core->mac[PVFGOTC0 + (pool * 64)] += tot_len;
+core->mac[PVFGPTC0 + (pool * 64)]++;
+}
}
static void
@@ -579,7 +586,7 @@ igb_process_tx_desc(IGBCore *core,
core->mac[VET] & 0x);
}
if (igb_tx_pkt_send(core, tx, queue_index)) {
-igb_on_tx_done_update_stats(core, tx->tx_pkt);
+igb_on_tx_done_update_stats(core, tx->tx_pkt, queue_index);
}
}
@@ -1396,7 +1403,8 @@ igb_write_to_rx_buffers(IGBCore *core,
}
static void
-igb_update_rx_stats(IGBCore *core, size_t data_size, size_t data_fcs_size)
+igb_update_rx_stats(IGBCore *core, const E1000E_RingInfo *rxi,
+size_t data_size, size_t data_fcs_size)
{
e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
@@ -1412,6 +1420,16 @@ igb_update_rx_stats(IGBCore *core, size_t data_size,
size_t data_fcs_size)
default:
break;
}
+
+if (core->mac[MRQC] & 1) {
+uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
+
+core->mac[PVFGORC0 + (pool * 64)] += data_size + 4;
+core->mac[PVFGPRC0 + (pool * 64)]++;
+if (net_rx_pkt_get_packet_type(core->rx_pkt) == ETH_PKT_MCAST) {
+core->mac[PVFMPRC0 + (pool * 64)]++;
+}
+}
}
static inline bool
@@ -1513,7 +1531,7 @@ igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt
*pkt,
} while (desc_offset < total_size);
-igb_update_rx_stats(core, size, total_size);
+igb_update_rx_stats(core, rxi, size, total_size);
}
static inline void
--
2.34.1
[PATCH v3 3/9] igb: add ICR_RXDW
IGB uses RXDW ICR bit to indicate that rx descriptor has been written
back. This is the same as RXT0 bit in older HW.
Signed-off-by: Sriram Yagnaraman
---
hw/net/e1000x_regs.h | 4
hw/net/igb_core.c| 46 +---
2 files changed, 22 insertions(+), 28 deletions(-)
diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h
index fb5b861135..f509db73a7 100644
--- a/hw/net/e1000x_regs.h
+++ b/hw/net/e1000x_regs.h
@@ -335,6 +335,7 @@
#define E1000_ICR_RXDMT00x0010 /* rx desc min. threshold (0) */
#define E1000_ICR_RXO 0x0040 /* rx overrun */
#define E1000_ICR_RXT0 0x0080 /* rx timer intr (ring 0) */
+#define E1000_ICR_RXDW 0x0080 /* rx desc written back */
#define E1000_ICR_MDAC 0x0200 /* MDIO access complete */
#define E1000_ICR_RXCFG 0x0400 /* RX /c/ ordered set */
#define E1000_ICR_GPI_EN0 0x0800 /* GP Int 0 */
@@ -378,6 +379,7 @@
#define E1000_ICS_RXDMT0E1000_ICR_RXDMT0/* rx desc min. threshold */
#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
@@ -407,6 +409,7 @@
#define E1000_IMS_RXDMT0E1000_ICR_RXDMT0/* rx desc min. threshold */
#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
@@ -441,6 +444,7 @@
#define E1000_IMC_RXDMT0E1000_ICR_RXDMT0/* rx desc min. threshold */
#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 9c32ad5e36..e78bc3611a 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1488,7 +1488,7 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4);
uint16_t queues = 0;
-uint32_t n;
+uint32_t icr_bits = 0;
uint8_t min_buf[ETH_ZLEN];
struct iovec min_iov;
struct eth_header *ehdr;
@@ -1561,6 +1561,7 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
e1000x_fcs_len(core->mac);
retval = orig_size;
+igb_rx_fix_l4_csum(core, core->rx_pkt);
for (i = 0; i < IGB_NUM_QUEUES; i++) {
if (!(queues & BIT(i))) {
@@ -1569,43 +1570,32 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
igb_rx_ring_init(core, , i);
-trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
-
if (!igb_has_rxbufs(core, rxr.i, total_size)) {
-retval = 0;
+icr_bits |= E1000_ICS_RXO;
+continue;
}
-}
-if (retval) {
-n = E1000_ICR_RXT0;
-
-igb_rx_fix_l4_csum(core, core->rx_pkt);
-
-for (i = 0; i < IGB_NUM_QUEUES; i++) {
-if (!(queues & BIT(i))) {
-continue;
-}
-
-igb_rx_ring_init(core, , i);
+trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
+igb_write_packet_to_guest(core, core->rx_pkt, , _info);
-igb_write_packet_to_guest(core, core->rx_pkt, , _info);
+/* Check if receive descriptor minimum threshold hit */
+if (igb_rx_descr_threshold_hit(core, rxr.i)) {
+icr_bits |= E1000_ICS_RXDMT0;
+}
-/* Check if receive descriptor minimum threshold hit */
-if (igb_rx_descr_threshold_hit(core, rxr.i)) {
-n |= E1000_ICS_RXDMT0;
-}
+core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
-core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
-}
+icr_bits |= E1000_ICR_RXDW;
+}
-trace_e1000e_rx_written_to_guest(n);
+if (icr_bits & E1000_ICR_RXDW) {
+trace_e1000e_rx_written_to_guest(icr_bits);
} else {
-n = E1000_ICS_RXO;
-trace_e1000e_rx_not_written_to_guest(n);
+trace_e1000e_rx_not_written_to_guest(icr_bits);
}
-trace_e1000e_rx_interrupt_set(n);
-
[PATCH v3 2/9] igb: handle PF/VF reset properly
Use PFRSTD to reset RSTI bit for VFs, and raise VFLRE interrupt when VF
is reset.
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 33 +
hw/net/igb_regs.h | 3 +++
hw/net/trace-events | 2 ++
3 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index bf1bcac747..9c32ad5e36 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1904,14 +1904,6 @@ static void igb_set_eims(IGBCore *core, int index,
uint32_t val)
igb_update_interrupt_state(core);
}
-static void igb_vf_reset(IGBCore *core, uint16_t vfn)
-{
-/* TODO: Reset of the queue enable and the interrupt registers of the VF.
*/
-
-core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
-core->mac[V2PMAILBOX0 + vfn] = E1000_V2PMAILBOX_RSTD;
-}
-
static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn)
{
uint32_t ent = core->mac[VTIVAR_MISC + vfn];
@@ -1989,6 +1981,17 @@ static void igb_set_vfmailbox(IGBCore *core, int index,
uint32_t val)
}
}
+static void igb_vf_reset(IGBCore *core, uint16_t vfn)
+{
+/* disable Rx and Tx for the VF*/
+core->mac[VFTE] &= ~BIT(vfn);
+core->mac[VFRE] &= ~BIT(vfn);
+/* indicate VF reset to PF */
+core->mac[VFLRE] |= BIT(vfn);
+/* VFLRE and mailbox use the same interrupt cause */
+mailbox_interrupt_to_pf(core);
+}
+
static void igb_w1c(IGBCore *core, int index, uint32_t val)
{
core->mac[index] &= ~val;
@@ -2243,14 +2246,20 @@ igb_set_status(IGBCore *core, int index, uint32_t val)
static void
igb_set_ctrlext(IGBCore *core, int index, uint32_t val)
{
-trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
- !!(val & E1000_CTRL_EXT_SPD_BYPS));
-
-/* TODO: PFRSTD */
+trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
+ !!(val & E1000_CTRL_EXT_SPD_BYPS),
+ !!(val & E1000_CTRL_EXT_PFRSTD));
/* Zero self-clearing bits */
val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
core->mac[CTRL_EXT] = val;
+
+if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) {
+for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
+core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
+core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD;
+}
+}
}
static void
diff --git a/hw/net/igb_regs.h b/hw/net/igb_regs.h
index ebf3e95023..ddc0f931d6 100644
--- a/hw/net/igb_regs.h
+++ b/hw/net/igb_regs.h
@@ -240,6 +240,9 @@ union e1000_adv_rx_desc {
/* from igb/e1000_defines.h */
+/* Physical Func Reset Done Indication */
+#define E1000_CTRL_EXT_PFRSTD 0x4000
+
#define E1000_IVAR_VALID 0x80
#define E1000_GPIE_NSICR 0x0001
#define E1000_GPIE_MSIX_MODE 0x0010
diff --git a/hw/net/trace-events b/hw/net/trace-events
index 2f791b9b57..e94172e748 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -281,6 +281,8 @@ igb_core_mdic_read_unhandled(uint32_t addr) "MDIC READ:
PHY[%u] UNHANDLED"
igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u] = 0x%x"
igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLED"
+igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfrstd)
"Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset
done: %d"
+
igb_rx_desc_buff_size(uint32_t b) "buffer size: %u"
igb_rx_desc_buff_write(uint64_t addr, uint16_t offset, const void* source,
uint32_t len) "addr: 0x%"PRIx64", offset: %u, from: %p, length: %u"
--
2.34.1
[PATCH v3 9/9] igb: respect VMVIR and VMOLR for VLAN
Add support for stripping/inserting VLAN for VFs.
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 51 ++-
1 file changed, 42 insertions(+), 9 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 8115be2d76..a697fcf56a 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -386,6 +386,25 @@ igb_rss_parse_packet(IGBCore *core, struct NetRxPkt *pkt,
bool tx,
info->queue = E1000_RSS_QUEUE(>mac[RETA], info->hash);
}
+static inline bool
+igb_tx_insert_vlan(IGBCore *core, uint16_t qn,
+ struct igb_tx *tx, bool desc_vle)
+{
+if (core->mac[MRQC] & 1) {
+uint16_t pool = qn % IGB_NUM_VM_POOLS;
+
+if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_DEFAULT) {
+/* always insert default VLAN */
+desc_vle = true;
+tx->vlan = core->mac[VMVIR0 + pool] & 0x;
+} else if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_NEVER) {
+return false;
+}
+}
+
+return desc_vle && e1000x_vlan_enabled(core->mac);
+}
+
static bool
igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx)
{
@@ -581,7 +600,8 @@ igb_process_tx_desc(IGBCore *core,
if (cmd_type_len & E1000_TXD_CMD_EOP) {
if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
-if (cmd_type_len & E1000_TXD_CMD_VLE) {
+if (igb_tx_insert_vlan(core, queue_index, tx,
+!!(cmd_type_len & E1000_TXD_CMD_VLE))) {
net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, tx->vlan,
core->mac[VET] & 0x);
}
@@ -1543,6 +1563,20 @@ igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt
*pkt,
igb_update_rx_stats(core, rxi, size, total_size);
}
+static bool
+igb_rx_strip_vlan(IGBCore *core, const E1000E_RingInfo *rxi)
+{
+if (core->mac[MRQC] & 1) {
+uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
+/* Sec 7.10.3.8: CTRL.VME is ignored, only VMOLR/RPLOLR is used */
+return (net_rx_pkt_get_packet_type(core->rx_pkt) == ETH_PKT_MCAST) ?
+core->mac[RPLOLR] & E1000_RPLOLR_STRVLAN :
+core->mac[VMOLR0 + pool] & E1000_VMOLR_STRVLAN;
+}
+
+return e1000x_vlan_enabled(core->mac);
+}
+
static inline void
igb_rx_fix_l4_csum(IGBCore *core, struct NetRxPkt *pkt)
{
@@ -1624,10 +1658,7 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
ehdr = PKT_GET_ETH_HDR(filter_buf);
net_rx_pkt_set_packet_type(core->rx_pkt, get_eth_packet_type(ehdr));
-
-net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
- e1000x_vlan_enabled(core->mac),
- core->mac[VET] & 0x);
+net_rx_pkt_set_protocols(core->rx_pkt, filter_buf, size);
queues = igb_receive_assign(core, ehdr, size, _info, external_tx);
if (!queues) {
@@ -1635,11 +1666,8 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
return orig_size;
}
-total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
-e1000x_fcs_len(core->mac);
-
retval = orig_size;
-igb_rx_fix_l4_csum(core, core->rx_pkt);
+total_size = size + e1000x_fcs_len(core->mac);
for (i = 0; i < IGB_NUM_QUEUES; i++) {
if (!(queues & BIT(i)) ||
@@ -1648,6 +1676,11 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
}
igb_rx_ring_init(core, , i);
+net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
+ igb_rx_strip_vlan(core, rxr.i),
+ core->mac[VET] & 0x);
+igb_rx_fix_l4_csum(core, core->rx_pkt);
+
if (!igb_has_rxbufs(core, rxr.i, total_size)) {
icr_bits |= E1000_ICS_RXO;
continue;
--
2.34.1
Re: [PATCH] vhost-user-gpio: Configure vhost_dev when connecting
Akihiko Odaki writes:
> vhost_dev_cleanup(), called from vu_gpio_disconnect(), clears vhost_dev
> so vhost-user-gpio must set the members of vhost_dev each time
> connecting.
>
> do_vhost_user_cleanup() should also acquire the pointer to vqs directly
> from VHostUserGPIO instead of referring to vhost_dev as it can be called
> after vhost_dev_cleanup().
>
> Fixes: 27ba7b027f ("hw/virtio: add boilerplate for vhost-user-gpio device")
> Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
RE: [PATCH v2 00/13] Introduce igb
> -Original Message- > From: Akihiko Odaki > Sent: Monday, 30 January 2023 15:39 > To: Sriram Yagnaraman ; Jason Wang > > Cc: Dmitry Fleytman ; Michael S. Tsirkin > ; Marcel Apfelbaum ; > Alex Bennée ; Philippe Mathieu-Daudé > ; Thomas Huth ; Wainer dos Santos > Moschetta ; Beraldo Leal ; > Cleber Rosa ; Laurent Vivier ; > Paolo Bonzini ; Alexander Bulekov ; > Bandan Das ; Stefan Hajnoczi ; > Darren Kenny ; Qiuhao Li > ; qemu-devel@nongnu.org; qemu- > p...@nongnu.org; de...@daynix.com; Yan Vugenfirer > ; Yuri Benditovich > Subject: Re: [PATCH v2 00/13] Introduce igb > > On 2023/01/29 5:57, Sriram Yagnaraman wrote: > >> -Original Message- > >> From: Akihiko Odaki > >> Sent: Thursday, 26 January 2023 12:32 > >> To: Sriram Yagnaraman ; Jason Wang > >> > >> Cc: Dmitry Fleytman ; Michael S. Tsirkin > >> ; Marcel Apfelbaum ; > Alex > >> Bennée ; Philippe Mathieu-Daudé > >> ; Thomas Huth ; Wainer dos > >> Santos Moschetta ; Beraldo Leal > >> ; Cleber Rosa ; Laurent Vivier > >> ; Paolo Bonzini ; Alexander > >> Bulekov ; Bandan Das ; Stefan > Hajnoczi > >> ; Darren Kenny ; > Qiuhao > >> Li ; qemu-devel@nongnu.org; qemu- > >> p...@nongnu.org; de...@daynix.com; Yan Vugenfirer > >> ; Yuri Benditovich > >> Subject: Re: [PATCH v2 00/13] Introduce igb > >> > >> On 2023/01/26 18:34, Sriram Yagnaraman wrote: > >>> > -Original Message- > From: Sriram Yagnaraman > Sent: Tuesday, 24 January 2023 09:54 > To: Akihiko Odaki ; Jason Wang > > Cc: Dmitry Fleytman ; Michael S. Tsirkin > ; Marcel Apfelbaum > ; > >> Alex > Bennée ; Philippe Mathieu-Daudé > ; Thomas Huth ; Wainer dos > Santos Moschetta ; Beraldo Leal > ; Cleber Rosa ; Laurent Vivier > ; Paolo Bonzini ; > Alexander Bulekov ; Bandan Das ; > Stefan > >> Hajnoczi > ; Darren Kenny ; > >> Qiuhao > Li ; qemu-devel@nongnu.org; qemu- > p...@nongnu.org; de...@daynix.com; Yan Vugenfirer > ; Yuri Benditovich > > Subject: RE: [PATCH v2 00/13] Introduce igb > > > > -Original Message- > > From: Akihiko Odaki > > Sent: Tuesday, 24 January 2023 05:54 > > To: Jason Wang ; Sriram Yagnaraman > > > > Cc: Dmitry Fleytman ; Michael S. > > Tsirkin ; Marcel Apfelbaum > >> ; > Alex > > Bennée ; Philippe Mathieu-Daudé > > ; Thomas Huth ; Wainer dos > Santos > > Moschetta ; Beraldo Leal > ; > > Cleber Rosa ; Laurent Vivier > > ; Paolo Bonzini ; > > Alexander Bulekov ; Bandan Das ; > > Stefan Hajnoczi ; Darren Kenny > > ; > Qiuhao > > Li ; qemu-devel@nongnu.org; qemu- > > p...@nongnu.org; de...@daynix.com; Yan Vugenfirer > > ; Yuri Benditovich > > > > Subject: Re: [PATCH v2 00/13] Introduce igb > > > > On 2023/01/16 17:01, Jason Wang wrote: > >> On Sat, Jan 14, 2023 at 12:10 PM Akihiko Odaki > > wrote: > >>> > >>> Based-on: <20230114035919.35251-1-akihiko.od...@daynix.com> > >>> ([PATCH 00/19] e1000x cleanups (preliminary for IGB)) > >>> > >>> igb is a family of Intel's gigabit ethernet controllers. This > >>> series implements > >>> 82576 emulation in particular. You can see the last patch for > >>> the > > documentation. > >>> > >>> Note that there is another effort to bring 82576 emulation. This > >>> series was developed independently by Sriram Yagnaraman. > >>> https://lists.gnu.org/archive/html/qemu-devel/2022- > >> 12/msg04670.htm > >>> l > >>> > >>> It is possible to merge the work from Sriram Yagnaraman and to > >>> cherry-pick useful changes from this series later. > >>> > >>> I think there are several different ways to get the changes into > >>> the > mainline. > >>> I'm open to any options. > >> > >> I can only do reviews for the general networking part but not the > >> 82576 specific part. It would be better if either of the series > >> can get some ACKs from some ones that they are familiar with > >> 82576, then I can try to merge. > >> > >> Thanks > > > > I have just sent v3 to the list. > > > > Sriram Yagnaraman, who wrote another series for 82576, is the only > > person I know who is familiar with the device. > > > > Sriram, can you take a look at v3 I have just sent? > > I am at best a good interpreter of the 82576 datasheet. I will > review your changes get back here. > >>> > >>> I have reviewed and tested your changes and it looks great to me in > general. > >>> I would like to note some features that I would like to add on top > >>> of your patch, if you have not worked on these already :) > >>> - PFRSTD (PF reset done) > >>> - SRRCTL (Rx desc buf size) > >>> - RLPML (oversized packet handling) > >>> - MAC/VLAN anti-spoof checks > >>> - VMOLR_STRVLAN and RPLOLR_STRVLAN (VLAN stripping for VFs) > >>> - VMVIR (VLAN insertion for VFs) > >>> - VF reset > >>> -
Re: [PATCH v4 3/3] hw/riscv: change riscv_compute_fdt_addr() semantics
On 1/30/23 22:00, Bin Meng wrote:
On Tue, Jan 31, 2023 at 1:16 AM Daniel Henrique Barboza
wrote:
On 1/29/23 02:45, Bin Meng wrote:
On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza
wrote:
As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a
mem_size (which is defaulted to MachineState::ram_size in all boards)
and the FDT pointer. And it makes a very important assumption: the DRAM
interval dram_base + mem_size is contiguous. This is indeed the case for
most boards that uses a FDT.
s/uses/use
The Icicle Kit board works with 2 distinct RAM banks that are separated
by a gap. We have a lower bank with 1GiB size, a gap follows, then at
64GiB the high memory starts. MachineClass::default_ram_size for this
board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM
size, meaning that there we'll always have at least 512 MiB in the Hi
RAM area.
Using riscv_compute_fdt_addr() in this board is weird because not only
the board has sparse RAM, and it's calling it using the base address of
the Lo RAM area, but it's also using a mem_size that we have guarantees
that it will go up to the Hi RAM. All the function assumptions doesn't
work for this board.
In fact, what makes the function works at all in this case is a
coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT,
down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For
the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x8000
(2 Gb) and it has a 1Gb size, so it will fall in the conditions to put
the FDT under a 3Gb address, which happens to be exactly at the end of
DRAM_LO. If the base address of the Lo area started later than 3Gb this
function would be unusable by the board. Changing any assumptions inside
riscv_compute_fdt_addr() can also break it by accident as well.
Let's change riscv_compute_fdt_addr() semantics to be appropriate to the
Icicle Kit board and for future boards that might have sparse RAM
topologies to worry about:
- relieve the condition that the dram_base + mem_size area is contiguous,
since this is already not the case today;
- receive an extra 'dram_size' size attribute that refers to a contiguous
RAM block that the board wants the FDT to reside on.
Together with 'mem_size' and 'fdt', which are now now being consumed by a
MachineState pointer, we're able to make clear assumptions based on the
DRAM block and total mem_size available to ensure that the FDT will be put
in a valid RAM address.
Well written commit message. Thanks!
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/boot.c| 38 ++
hw/riscv/microchip_pfsoc.c | 3 ++-
hw/riscv/sifive_u.c| 3 ++-
hw/riscv/spike.c | 3 ++-
hw/riscv/virt.c| 3 ++-
include/hw/riscv/boot.h| 4 ++--
6 files changed, 36 insertions(+), 18 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index a6f7b8ae8e..8f4991480b 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -284,33 +284,47 @@ out:
}
/*
- * The FDT should be put at the farthest point possible to
- * avoid overwriting it with the kernel/initrd.
+ * This function makes an assumption that the DRAM interval
+ * 'dram_base' + 'dram_size' is contiguous.
*
- * This function makes an assumption that the DRAM is
- * contiguous. It also cares about 32-bit systems and
- * will limit fdt_addr to be addressable by them even for
- * 64-bit CPUs.
+ * Considering that 'dram_end' is the lowest value between
+ * the end of the DRAM block and MachineState->ram_size, the
+ * FDT location will vary according to 'dram_base':
+ *
+ * - if 'dram_base' is less that 3072 MiB, the FDT will be
+ * put at the lowest value between 3072 MiB and 'dram_end';
+ *
+ * - if 'dram_base' is higher than 3072 MiB, the FDT will be
+ * put at 'dram_end'.
*
* The FDT is fdt_packed() during the calculation.
*/
-uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size,
-void *fdt)
+hwaddr riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
Using hwaddr to represent a size looks weird. Although technically
they are the same ... I would leave this as it is.
I'll leave it as it was back in patch 2 (uint64_t).
+ MachineState *ms)
{
-uint64_t temp;
-hwaddr dram_end = dram_base + mem_size;
-int ret = fdt_pack(fdt);
+int ret = fdt_pack(ms->fdt);
+hwaddr dram_end, temp;
int fdtsize;
/* Should only fail if we've built a corrupted tree */
g_assert(ret == 0);
-fdtsize = fdt_totalsize(fdt);
+fdtsize = fdt_totalsize(ms->fdt);
if (fdtsize <= 0) {
error_report("invalid device-tree");
exit(1);
}
+/*
+ * A dram_size == 0, usually from a MemMapEntry[].size element,
+ * means that the DRAM block goes all the way to ms->ram_size.
+ */
+if (dram_size == 0x0) {
+
Re: [PATCH v2] Fix exec migration on Windows (w32+w64).
Hi On Tue, Jan 17, 2023 at 9:07 PM John Berberian, Jr wrote: > > Apologies for the late response, I was traveling most of yesterday. > > On 1/16/23 4:22 AM, Daniel P. Berrangé wrote: > > When we introduce a new QAPI format for migration args though, I've > > suggested we drop support for passing exec via shell, and require an > > explicit argv[] array: > > > >https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg01434.html > > > > For Windows since we don't have back compat to worry about, we > > can avoid passing via cmd.exe from the start. > > I think we should keep the behavior the same on all platforms. If such a > change is to occur, it should happen at the same time on Windows and > Unix-like systems. Platform-dependent ifdefs should be used to overcome > platform-specific differences (e.g. the location of the shell), rather > than give one platform entirely different functionality - otherwise we > introduce needless confusion when someone accustomed to Linux tries to > use an exec migration on Windows and it doesn't work the same way at all. I agree with Daniel, we should make the migrate/exec command take an argv[] (not run through the shell) and deprecate support for "exec:.." in QMP. The "exec:..." form support could later be moved to HMP... Tbh, allowing fork/exec from QEMU is not a great thing in the first place (although with GSpawn using posix_spawn on modern systems, that should help.. and win32 has a different API). Instead, QMP/HMP clients could handle consumer process creation, and passing FDs via 'getfd,' and using the migrate 'fd:fdname' form (that is not really possible on win32 today, but I am adding support for importing sockets in a series on the list. This should do the job now that win32 supports unix sockets. We could also add support for pipes for older windows, and other kind of handles too). I admit this is not as convenient as the current "exec:cmdline" form... I don't know whether we have enough motivation to push those changes... I see it fitting with the goal to make HMP a human-friendly QMP client though. In the meantime, I guess we should take the proposed patch. Stefan, as win32 maintainer, any opinion? -- Marc-André Lureau
Re: [PATCH v2 2/5] parallels: Split image leak handling to separate check and fix helpers
On 1/12/23 16:01, Alexander Ivanov wrote:
We need to fix leak after deduplication in the next patch. Move leak
fixing to a separate helper parallels_fix_leak() and add
parallels_get_leak_size() helper wich used in parallels_fix_leak() and
parallels_check_leak().
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 88 ---
1 file changed, 61 insertions(+), 27 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index ed2cf27abc..da1e75096c 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -475,21 +475,53 @@ static int parallels_check_outside_image(BlockDriverState
*bs,
return 0;
}
+static int64_t parallels_get_leak_size(BlockDriverState *bs,
+ BdrvCheckResult *res)
+{
+int64_t size;
+size = bdrv_getlength(bs->file->bs);
+/*
+ * Before any usage of this function out-of-image corruption has been
+ * fixed. If the function returns a negative value, it means an error.
+ */
+return (size < 0) ? size : (size - res->image_end_offset);
I'd better use normal 'if' here and will add an assert that
'size' >= 'res->image_end_offset' on success path.
+}
+
+static int parallels_fix_leak(BlockDriverState *bs,
+ BdrvCheckResult *res)
+{
+Error *local_err = NULL;
+int64_t size;
+int ret;
+
+size = parallels_get_leak_size(bs, res);
+if (size <= 0) {
+return size;
+}
+
+/*
+ * In order to really repair the image, we must shrink it.
+ * That means we have to pass exact=true.
+ */
+ret = bdrv_co_truncate(bs->file, res->image_end_offset, true,
+ PREALLOC_MODE_OFF, 0, _err);
+if (ret < 0) {
+error_report_err(local_err);
+return ret;
+}
+
+return 0;
+}
+
static int parallels_check_leak(BlockDriverState *bs,
BdrvCheckResult *res,
BdrvCheckMode fix)
{
BDRVParallelsState *s = bs->opaque;
-int64_t size, off, high_off, count;
+int64_t off, high_off, count, leak_size;
uint32_t i;
int ret;
-size = bdrv_getlength(bs->file->bs);
-if (size < 0) {
-res->check_errors++;
-return size;
-}
-
high_off = 0;
for (i = 0; i < s->bat_size; i++) {
off = bat2sect(s, i) << BDRV_SECTOR_BITS;
@@ -499,30 +531,32 @@ static int parallels_check_leak(BlockDriverState *bs,
}
res->image_end_offset = high_off + s->cluster_size;
-if (size > res->image_end_offset) {
-count = DIV_ROUND_UP(size - res->image_end_offset, s->cluster_size);
-fprintf(stderr, "%s space leaked at the end of the image %" PRId64
"\n",
-fix & BDRV_FIX_LEAKS ? "Repairing" : "ERROR",
-size - res->image_end_offset);
-res->leaks += count;
-if (fix & BDRV_FIX_LEAKS) {
-Error *local_err = NULL;
-/*
- * In order to really repair the image, we must shrink it.
- * That means we have to pass exact=true.
- */
-ret = bdrv_co_truncate(bs->file, res->image_end_offset, true,
- PREALLOC_MODE_OFF, 0, _err);
-if (ret < 0) {
-error_report_err(local_err);
-res->check_errors++;
-return ret;
-}
-res->leaks_fixed += count;
+leak_size = parallels_get_leak_size(bs, res);
+if (leak_size < 0) {
+res->check_errors++;
+return leak_size;
+}
+if (leak_size == 0) {
+return 0;
+}
+
+if (fix & BDRV_FIX_LEAKS) {
+ret = parallels_fix_leak(bs, res);
you have changed semantics a bit - with a error here the message
that we do get leak will be lost. I think the code is to be restructured
a bit here:
* move printing above this if
* fill leaks_fixed inside this if on the success path
This will be much straight forward
Den
+if (ret < 0) {
+return ret;
}
}
+count = DIV_ROUND_UP(leak_size, s->cluster_size);
+fprintf(stderr, "%s space leaked at the end of the image %" PRId64 "\n",
+fix & BDRV_FIX_LEAKS ? "Repairing" : "ERROR", leak_size);
+
+res->leaks += count;
+if (fix & BDRV_FIX_LEAKS) {
+res->leaks_fixed += count;
+}
+
return 0;
}
Re: [PATCH v2 0/2] audio: make audiodev introspectable by management apps
On 23/01/2023 09.39, Thomas Huth wrote: Here's a respin from Daniel's audiodev introspection patches from 2021. I've rebased them to the current master branch and addressed the review comments from v1. The Audiodev QAPI type is not introspectable via query-qmp-schema as nothing in QMP uses it. "-audiodev" is not introspectable via query-command-line-options because it avoided legacy QemuOpts. To fix it, introduce a tiny "query-audiodev" QMP command that uses the "Audiodev" QAPI structure, so that it shows up in the schema. Then mark the various backend types with conditionals so that only the ones that were available at compile time show up in the schema. Daniel P. Berrangé (2): qapi, audio: add query-audiodev command qapi, audio: Make introspection reflect build configuration more closely Since there were no objections and since Gerd seems to be pretty busy with other stuff recently, I'll dare to pick these up for my next pull request. Thomas
[PATCH v9 05/12] parallels: Use generic infrastructure for BAT writing in parallels_co_check()
BAT is written in the context of conventional operations over the image
inside bdrv_co_flush() when it calls parallels_co_flush_to_os() callback.
Thus we should not modify BAT array directly, but call
parallels_set_bat_entry() helper and bdrv_co_flush() further on. After
that there is no need to manually write BAT and track its modification.
This makes code more generic and allows to split parallels_set_bat_entry()
for independent pieces.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
---
block/parallels.c | 23 ++-
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index b2e3f5f98f..63bfd7074c 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -425,9 +425,8 @@ static int coroutine_fn parallels_co_check(BlockDriverState
*bs,
{
BDRVParallelsState *s = bs->opaque;
int64_t size, prev_off, high_off;
-int ret;
+int ret = 0;
uint32_t i;
-bool flush_bat = false;
size = bdrv_getlength(bs->file->bs);
if (size < 0) {
@@ -465,9 +464,8 @@ static int coroutine_fn parallels_co_check(BlockDriverState
*bs,
fix & BDRV_FIX_ERRORS ? "Repairing" : "ERROR", i);
res->corruptions++;
if (fix & BDRV_FIX_ERRORS) {
-s->bat_bitmap[i] = 0;
+parallels_set_bat_entry(s, i, 0);
res->corruptions_fixed++;
-flush_bat = true;
}
prev_off = 0;
continue;
@@ -484,15 +482,6 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
prev_off = off;
}
-ret = 0;
-if (flush_bat) {
-ret = bdrv_co_pwrite_sync(bs->file, 0, s->header_size, s->header, 0);
-if (ret < 0) {
-res->check_errors++;
-goto out;
-}
-}
-
if (high_off == 0) {
res->image_end_offset = s->data_end << BDRV_SECTOR_BITS;
} else {
@@ -527,6 +516,14 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
out:
qemu_co_mutex_unlock(>lock);
+
+if (ret == 0) {
+ret = bdrv_co_flush(bs);
+if (ret < 0) {
+res->check_errors++;
+}
+}
+
return ret;
}
--
2.34.1
Re: [PATCH v2 02/20] hw/pci-host/q35: Inline sysbus_add_io()
On 31/01/2023 12.53, Bernhard Beschow wrote: sysbus_add_io() just wraps memory_region_add_subregion() while also obscuring where the memory is attached. So use memory_region_add_subregion() directly and attach it to the existing memory region s->mch.address_space_io which is set as an alias to get_system_io() by the q35 machine. Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 26390863d6..fa05844319 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -50,10 +50,12 @@ static void q35_host_realize(DeviceState *dev, Error **errp) Q35PCIHost *s = Q35_HOST_DEVICE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); -sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, >conf_mem); +memory_region_add_subregion(s->mch.address_space_io, +MCH_HOST_BRIDGE_CONFIG_ADDR, >conf_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); -sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, >data_mem); +memory_region_add_subregion(s->mch.address_space_io, +MCH_HOST_BRIDGE_CONFIG_DATA, >data_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); /* register q35 0xcf8 port as coalesced pio */ Reviewed-by: Thomas Huth
Re: [PATCH v5 7/9] igb: Introduce qtest for igb device
On 31/01/2023 15.34, Akihiko Odaki wrote: On 2023/01/31 22:04, Thomas Huth wrote: On 30/01/2023 15.08, Akihiko Odaki wrote: This change is derived from qtest for e1000e device. Signed-off-by: Akihiko Odaki --- MAINTAINERS | 2 + tests/qtest/fuzz/generic_fuzz_configs.h | 5 + tests/qtest/igb-test.c | 243 tests/qtest/libqos/igb.c | 185 ++ tests/qtest/libqos/meson.build | 1 + tests/qtest/meson.build | 1 + 6 files changed, 437 insertions(+) create mode 100644 tests/qtest/igb-test.c create mode 100644 tests/qtest/libqos/igb.c The igb test code still looks very, very similar to the e1000e test code ... would it be feasible to extend the e1000e code to support the igb device instead of duplicating the code base here? Thomas I doubt it is worth as most of the duplicate code is more like boilerplate like registering qos nodes and tests. While such boilerplate code is currently identical except renamed identifiers, sharing it with e1000e and igb will prevent from changing the device configuration for one device (e.g., adding igbvf) or from adding tests specific to one device. The core of the testing code which e.g. accesses registers is somewhat similar but diverged to the extent that it is hard to extract the commonalities. It is because the design of igb is diverged from e1000e to support more Rx/Tx queues and it changed the format of Rx/Tx descriptor. Ok, fair point. Acked-by: Thomas Huth
Re: Display update issue on M1 Macs
On Tue, 31 Jan 2023, Akihiko Odaki wrote: On 2023/01/31 8:58, BALATON Zoltan wrote: On Sat, 28 Jan 2023, Akihiko Odaki wrote: On 2023/01/23 8:28, BALATON Zoltan wrote: On Thu, 19 Jan 2023, Akihiko Odaki wrote: On 2023/01/15 3:11, BALATON Zoltan wrote: On Sat, 14 Jan 2023, Akihiko Odaki wrote: On 2023/01/13 22:43, BALATON Zoltan wrote: On Thu, 5 Jan 2023, BALATON Zoltan wrote: Hello, I got reports from several users trying to run AmigaOS4 on sam460ex on Apple silicon Macs that they get missing graphics that I can't reproduce on x86_64. With help from the users who get the problem we've narrowed it down to the following: It looks like that data written to the sm501's ram in qemu/hw/display/sm501.c::sm501_2d_operation() is then not seen from sm501_update_display() in the same file. The sm501_2d_operation() function is called when the guest accesses the emulated card so it may run in a different thread than sm501_update_display() which is called by the ui backend but I'm not sure how QEMU calls these. Is device code running in iothread and display update in main thread? The problem is also independent of the display backend and was reproduced with both -display cocoa and -display sdl. We have confirmed it's not the pixman routines that sm501_2d_operation() uses as the same issue is seen also with QEMU 4.x where pixman wasn't used and with all versions up to 7.2 so it's also not some bisectable change in QEMU. It also happens with --enable-debug so it doesn't seem to be related to optimisation either and I don't get it on x86_64 but even x86_64 QEMU builds run on Apple M1 with Rosetta 2 show the problem. It also only seems to affect graphics written from sm501_2d_operation() which AmigaOS4 uses extensively but other OSes don't and just render graphics with the vcpu which work without problem also on the M1 Macs that show this problem with AmigaOS4. Theoretically this could be some missing syncronisation which is something ARM and PPC may need while x86 doesn't but I don't know if this is really the reason and if so where and how to fix it). Any idea what may cause this and what could be a fix to try? Any idea anyone? At least some explanation if the above is plausible or if there's an option to disable the iothread and run everyting in a single thread to verify the theory could help. I've got reports from at least 3 people getting this problem but I can't do much to fix it without some help. (Info on how to run it is here: http://zero.eik.bme.hu/~balaton/qemu/amiga/#amigaos but AmigaOS4 is not freely distributable so it's a bit hard to reproduce. Some Linux X servers that support sm501/sm502 may also use the card's 2d engine but I don't know about any live CDs that readily run on sam460ex.) Thank you, BALATON Zoltan Sorry, I missed the email. Indeed the ui backend should call sm501_update_display() in the main thread, which should be different from the thread calling sm501_2d_operation(). However, if I understand it correctly, both of the functions should be called with iothread lock held so there should be no race condition in theory. But there is an exception: memory_region_snapshot_and_clear_dirty() releases iothread lock, and that broke raspi3b display device: https://lore.kernel.org/qemu-devel/CAFEAcA9odnPo2LPip295Uztri7JfoVnQbkJ=wn+k8dqneb_...@mail.gmail.com/T/ It is unexpected that gfx_update() callback releases iothread lock so it may break things in peculiar ways. Peter, is there any change in the situation regarding the race introduced by memory_region_snapshot_and_clear_dirty()? For now, to workaround the issue, I think you can create another mutex and make the entire sm501_2d_engine_write() and sm501_update_display() critical sections. Interesting thread but not sure it's the same problem so this workaround may not be enough to fix my issue. Here's a video posted by one of the people who reported it showing the problem on M1 Mac: https://www.youtube.com/watch?v=FDqoNbp6PQs and here's how it looks like on other machines: https://www.youtube.com/watch?v=ML7-F4HNFKQ There are also videos showing it running on RPi 4 and G5 Mac without this issue so it seems to only happen on Apple Silicon M1 Macs. What's strange is that graphics elements are not just delayed which I think should happen with missing thread synchronisation where the update callback would miss some pixels rendered during it's running but subsequent update callbacks would eventually draw those, woudn't they? Also setting full_update to 1 in sm501_update_display() callback to disable dirty tracking does not fix the problem. So it looks like as if sm501_2d_operation() running on one CPU core only writes data to the local cache of that core which sm501_update_display() running on other core can't see, so maybe some cache synchronisation is needed in memory_region_set_dirty() or if that's already there maybe I should call it for all changes not only
Re: [PATCH 3/3] migration: save/delete migration thread info
On 2023/1/30 22:04, Juan Quintela wrote: > Jiang Jiacheng wrote: >> On 2023/1/30 12:28, Juan Quintela wrote: >>> Jiang Jiacheng wrote: To support query migration thread infomation, save and delete thread information at thread creation and end. Signed-off-by: Jiang Jiacheng >>> >>> Don't disagree with this, but if we create this on the sending side, why >>> this is not needed for the multifd_recv_threads? >>> >> >> I only add several threads which i'm interested in into the list till >> now, whose information will be used for setting cpu affinity for >> migration thread. >> For consistency, we can add other threads to the list, but those >> information won't be used so far. > > It is just curiosity, why do you want to set cpu affinity on the source > but not on destination? > Mainly considering the application scenarios. To improve the migration performance, I want to set cpu affinity for migration thread when migration a VM whose service threads preempt most of the CPU resources. So the source side can benefit more from cpu affinity. And on the destination side, the pressure is lighter (generally), setting cpu affinity may not be so much useful as source side. Thanks, Jiang Jiacheng > Later, Juan. > >
[PATCH v9 01/12] parallels: Out of image offset in BAT leads to image inflation
data_end field in BDRVParallelsState is set to the biggest offset present
in BAT. If this offset is outside of the image, any further write will
create the cluster at this offset and/or the image will be truncated to
this offset on close. This is definitely not correct.
Raise an error in parallels_open() if data_end points outside the image
and it is not a check (let the check to repaire the image). Set data_end
to the end of the cluster with the last correct offset.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
---
block/parallels.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/block/parallels.c b/block/parallels.c
index bbea2f2221..4af68adc61 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -732,6 +732,7 @@ static int parallels_open(BlockDriverState *bs, QDict
*options, int flags,
BDRVParallelsState *s = bs->opaque;
ParallelsHeader ph;
int ret, size, i;
+int64_t file_size;
QemuOpts *opts = NULL;
Error *local_err = NULL;
char *buf;
@@ -741,6 +742,12 @@ static int parallels_open(BlockDriverState *bs, QDict
*options, int flags,
return ret;
}
+file_size = bdrv_getlength(bs->file->bs);
+if (file_size < 0) {
+return -EINVAL;
+}
+file_size >>= BDRV_SECTOR_BITS;
+
ret = bdrv_pread(bs->file, 0, sizeof(ph), , 0);
if (ret < 0) {
goto fail;
@@ -805,6 +812,16 @@ static int parallels_open(BlockDriverState *bs, QDict
*options, int flags,
for (i = 0; i < s->bat_size; i++) {
int64_t off = bat2sect(s, i);
+if (off >= file_size) {
+if (flags & BDRV_O_CHECK) {
+continue;
+}
+error_setg(errp, "parallels: Offset %" PRIi64 " in BAT[%d] entry "
+ "is larger than file size (%" PRIi64 ")",
+ off, i, file_size);
+ret = -EINVAL;
+goto fail;
+}
if (off >= s->data_end) {
s->data_end = off + s->tracks;
}
--
2.34.1
[PATCH v9 04/12] parallels: create parallels_set_bat_entry_helper() to assign BAT value
This helper will be reused in next patches during parallels_co_check
rework to simplify its code.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/parallels.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index 2ed7cca249..b2e3f5f98f 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -165,6 +165,13 @@ static int64_t block_status(BDRVParallelsState *s, int64_t
sector_num,
return start_off;
}
+static void parallels_set_bat_entry(BDRVParallelsState *s,
+uint32_t index, uint32_t offset)
+{
+s->bat_bitmap[index] = cpu_to_le32(offset);
+bitmap_set(s->bat_dirty_bmap, bat_entry_off(index) / s->bat_dirty_block,
1);
+}
+
static coroutine_fn int64_t allocate_clusters(BlockDriverState *bs,
int64_t sector_num,
int nb_sectors, int *pnum)
@@ -251,10 +258,8 @@ static coroutine_fn int64_t
allocate_clusters(BlockDriverState *bs,
}
for (i = 0; i < to_allocate; i++) {
-s->bat_bitmap[idx + i] = cpu_to_le32(s->data_end / s->off_multiplier);
+parallels_set_bat_entry(s, idx + i, s->data_end / s->off_multiplier);
s->data_end += s->tracks;
-bitmap_set(s->bat_dirty_bmap,
- bat_entry_off(idx + i) / s->bat_dirty_block, 1);
}
return bat2sect(s, idx) + sector_num % s->tracks;
--
2.34.1
Re: [RFC v4 3/3] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)
On Mon, 28 Nov 2022 10:01:57 -0500
Gregory Price wrote:
> From: Gregory Price
>
> This commit enables each CXL Type-3 device to contain one volatile
> memory region and one persistent region.
>
> Two new properties have been added to cxl-type3 device initialization:
> [volatile-memdev] and [persistent-memdev]
>
> The existing [memdev] property has been deprecated and will default the
> memory region to a persistent memory region (although a user may assign
> the region to a ram or file backed region). It cannot be used in
> combination with the new [persistent-memdev] property.
>
> Partitioning volatile memory from persistent memory is not yet supported.
>
> Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped
> at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info.
>
> Signed-off-by: Gregory Price
> Signed-off-by: Jonathan Cameron
I'm taking another look at these and tweaking what I'm carrying as I go
with a plan to post them for merging shortly.
Anyhow, a few more changes I wanted to call out here so they don't come
as a surprise / are things to focus on in reviewing that version
(hopefully post it later today or maybe tomorrow).
Most of this is reducing the diff / duplication of code to make review a
tiny bit easier (hopefully)
...
> /* TODO: Support multiple HDM decoders and DPA skip */
> @@ -663,11 +769,17 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr
> host_addr, uint64_t *data,
> {
> CXLType3Dev *ct3d = CXL_TYPE3(d);
> uint64_t dpa_offset;
> -MemoryRegion *mr;
> +MemoryRegion *vmr = NULL, *pmr = NULL;
> +AddressSpace *as;
We end up with a lot of duplication between cxl_type3_read and cxl_type3_write()
so I've factored out a _get_as_and_dpa() function that deals with establish
where the memory we then read or write is.
>
> -/* TODO support volatile region */
> -mr = host_memory_backend_get_memory(ct3d->hostmem);
> -if (!mr) {
> +if (ct3d->hostvmem) {
> +vmr = host_memory_backend_get_memory(ct3d->hostvmem);
> +}
> +if (ct3d->hostpmem) {
> +pmr = host_memory_backend_get_memory(ct3d->hostpmem);
> +}
> +
> +if (!vmr && !pmr) {
> return MEMTX_ERROR;
> }
>
> @@ -675,11 +787,22 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr
> host_addr, uint64_t *data,
> return MEMTX_ERROR;
> }
>
> -if (dpa_offset > int128_get64(mr->size)) {
> +if (dpa_offset > int128_get64(ct3d->cxl_dstate.mem_size)) {
> return MEMTX_ERROR;
> }
>
> -return address_space_read(>hostmem_as, dpa_offset, attrs, data,
> size);
> +if (vmr) {
> +if (dpa_offset <= int128_get64(vmr->size)) {
> +as = >hostvmem_as;
> +} else {
> +as = >hostpmem_as;
> +dpa_offset -= vmr->size;
> +}
> +}
> +else {
> +as = >hostpmem_as;
> +}
> +return address_space_read(as, dpa_offset, attrs, data, size);
> }
>
> MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
> @@ -687,10 +810,17 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr
> host_addr, uint64_t data,
> {
> CXLType3Dev *ct3d = CXL_TYPE3(d);
> uint64_t dpa_offset;
> -MemoryRegion *mr;
> +MemoryRegion *vmr = NULL, *pmr = NULL;
> +AddressSpace *as;
>
> -mr = host_memory_backend_get_memory(ct3d->hostmem);
> -if (!mr) {
> +if (ct3d->hostvmem) {
> +vmr = host_memory_backend_get_memory(ct3d->hostvmem);
> +}
> +if (ct3d->hostpmem) {
> +pmr = host_memory_backend_get_memory(ct3d->hostpmem);
> +}
> +
> +if (!vmr && !pmr) {
> return MEMTX_OK;
> }
>
> @@ -698,11 +828,22 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr
> host_addr, uint64_t data,
> return MEMTX_OK;
> }
>
> -if (dpa_offset > int128_get64(mr->size)) {
> +if (dpa_offset > int128_get64(ct3d->cxl_dstate.mem_size)) {
> return MEMTX_OK;
> }
> -return address_space_write(>hostmem_as, dpa_offset, attrs,
> - , size);
> +
> +if (vmr) {
> +if (dpa_offset <= int128_get64(vmr->size)) {
> +as = >hostvmem_as;
> +} else {
> +as = >hostpmem_as;
> +dpa_offset -= vmr->size;
> +}
> +}
> +else {
> +as = >hostpmem_as;
> +}
> +return address_space_write(as, dpa_offset, attrs, , size);
> }
>
> static void ct3d_reset(DeviceState *dev)
> @@ -717,7 +858,11 @@ static void ct3d_reset(DeviceState *dev)
>
> static Property ct3_props[] = {
> DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND,
> - HostMemoryBackend *),
> + HostMemoryBackend *), /* for backward compatibility */
> +DEFINE_PROP_LINK("persistent-memdev", CXLType3Dev, hostpmem,
> + TYPE_MEMORY_BACKEND, HostMemoryBackend *),
> +DEFINE_PROP_LINK("volatile-memdev",
[PATCH v2 17/20] hw/i386/ich9: Remove redundant GSI_NUM_PINS
Most code uses IOAPIC_NUM_PINS. The only place where GSI_NUM_PINS defines
the size of an array is ICH9LPCState::gsi which needs to match
IOAPIC_NUM_PINS. Remove GSI_NUM_PINS for consistency.
Signed-off-by: Bernhard Beschow
---
include/hw/i386/ich9.h | 2 +-
include/hw/i386/x86.h | 1 -
hw/i386/pc.c | 6 +++---
hw/i386/pc_q35.c | 3 ++-
hw/isa/lpc_ich9.c | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 433c8942c9..d29090a9b7 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -63,7 +63,7 @@ struct ICH9LPCState {
MemoryRegion rcrb_mem; /* root complex register block */
Notifier machine_ready;
-qemu_irq gsi[GSI_NUM_PINS];
+qemu_irq gsi[IOAPIC_NUM_PINS];
};
#define ICH9_MASK(bit, ms_bit, ls_bit) \
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 62fa5774f8..0becd1460e 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -134,7 +134,6 @@ bool x86_machine_is_acpi_enabled(const X86MachineState
*x86ms);
/* Global System Interrupts */
-#define GSI_NUM_PINS IOAPIC_NUM_PINS
#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
typedef struct GSIState {
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 8898cc9961..cbca3f5db5 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -28,7 +28,7 @@
#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/char/parallel.h"
-#include "hw/i386/apic.h"
+#include "hw/i386/ioapic.h"
#include "hw/i386/topology.h"
#include "hw/i386/fw_cfg.h"
#include "hw/i386/vmport.h"
@@ -406,7 +406,7 @@ GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
if (kvm_ioapic_in_kernel()) {
kvm_pc_setup_irq_routing(pci_enabled);
}
-*irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
+*irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
return s;
}
@@ -1295,7 +1295,7 @@ void pc_basic_device_init(struct PCMachineState *pcms,
sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), _fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
-for (i = 0; i < GSI_NUM_PINS; i++) {
+for (i = 0; i < IOAPIC_NUM_PINS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
}
pit_isa_irq = -1;
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 2b34b88dc2..87f1ff94be 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -43,6 +43,7 @@
#include "hw/i386/ich9.h"
#include "hw/i386/amd_iommu.h"
#include "hw/i386/intel_iommu.h"
+#include "hw/i386/ioapic.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
#include "hw/ide/pci.h"
@@ -265,7 +266,7 @@ static void pc_q35_init(MachineState *machine)
gsi_state = pc_gsi_create(>gsi, pcmc->pci_enabled);
lpc_dev = DEVICE(lpc);
-for (i = 0; i < GSI_NUM_PINS; i++) {
+for (i = 0; i < IOAPIC_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index b2842f2743..808c572ae4 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -717,7 +717,7 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
ICH9_RST_CNT_IOPORT, >rst_cnt_mem,
1);
-qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
+qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, IOAPIC_NUM_PINS);
isa_bus_irqs(isa_bus, lpc->gsi);
--
2.39.1
[PATCH v2 06/20] hw/i386/pc_{q35, piix}: Minimize usage of get_system_memory()
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 7 ---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index ee9d9a4175..5bde4533cc 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -241,7 +241,7 @@ static void pc_init1(MachineState *machine,
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
} else {
pci_bus = NULL;
-isa_bus = isa_bus_new(NULL, get_system_memory(), system_io,
+isa_bus = isa_bus_new(NULL, system_memory, system_io,
_abort);
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index bc4fd06c1e..3ae2f41cf3 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -124,6 +124,7 @@ static void pc_q35_init(MachineState *machine)
DeviceState *lpc_dev;
BusState *idebus[MAX_SATA_PORTS];
ISADevice *rtc_state;
+MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
@@ -191,7 +192,7 @@ static void pc_q35_init(MachineState *machine)
rom_memory = pci_memory;
} else {
pci_memory = NULL;
-rom_memory = get_system_memory();
+rom_memory = system_memory;
}
pc_guest_info_init(pcms);
@@ -214,7 +215,7 @@ static void pc_q35_init(MachineState *machine)
}
/* allocate ram and load rom/bios */
-pc_memory_init(pcms, get_system_memory(), rom_memory, _memory,
+pc_memory_init(pcms, system_memory, rom_memory, _memory,
pci_hole64_size);
object_property_add_child(OBJECT(machine), "q35", phb);
@@ -223,7 +224,7 @@ static void pc_q35_init(MachineState *machine)
object_property_set_link(phb, MCH_HOST_PROP_PCI_MEM,
OBJECT(pci_memory), NULL);
object_property_set_link(phb, MCH_HOST_PROP_SYSTEM_MEM,
- OBJECT(get_system_memory()), NULL);
+ OBJECT(system_memory), NULL);
object_property_set_link(phb, MCH_HOST_PROP_IO_MEM,
OBJECT(system_io), NULL);
object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE,
--
2.39.1
[PATCH v2 19/20] hw/i386/ich9: Clean up includes
Signed-off-by: Bernhard Beschow --- include/hw/i386/ich9.h | 8 +--- hw/i386/acpi-build.c | 1 + hw/isa/lpc_ich9.c | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index d29090a9b7..3125863049 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -1,11 +1,13 @@ #ifndef HW_ICH9_H #define HW_ICH9_H -#include "hw/sysbus.h" -#include "hw/i386/pc.h" #include "hw/isa/apm.h" -#include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" +#include "hw/intc/ioapic.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_device.h" +#include "exec/memory.h" +#include "qemu/notify.h" #include "qom/object.h" void ich9_generate_smi(void); diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 127c4e2d50..266df7a153 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -59,6 +59,7 @@ #include "hw/acpi/pcihp.h" #include "hw/i386/fw_cfg.h" #include "hw/i386/ich9.h" +#include "hw/i386/pc.h" #include "hw/pci/pci_bus.h" #include "hw/pci-host/i440fx.h" #include "hw/pci-host/q35.h" diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 808c572ae4..f508f6071e 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -40,8 +40,8 @@ #include "hw/irq.h" #include "hw/isa/apm.h" #include "hw/pci/pci.h" -#include "hw/pci/pci_bridge.h" #include "hw/i386/ich9.h" +#include "hw/i386/pc.h" #include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" -- 2.39.1
Re: [PATCH v4 00/16] hw/9pfs: Add 9pfs support for Windows
Hi On Tue, Jan 31, 2023 at 6:39 PM Daniel P. Berrangé wrote: > On Tue, Jan 31, 2023 at 06:31:39PM +0400, Marc-André Lureau wrote: > > Hi > > > > On Mon, Jan 30, 2023 at 1:52 PM Bin Meng wrote: > > > > > At present there is no Windows support for 9p file system. > > > This series adds initial Windows support for 9p file system. > > > > > > 'local' file system backend driver is supported on Windows, > > > including open, read, write, close, rename, remove, etc. > > > All security models are supported. The mapped (mapped-xattr) > > > security model is implemented using NTFS Alternate Data Stream > > > (ADS) so the 9p export path shall be on an NTFS partition. > > > > > > 'synth' driver is adapted for Windows too so that we can now > > > run qtests on Windows for 9p related regression testing. > > > > > > Example command line to test: > > > > > > "-fsdev local,path=c:\msys64,security_model=mapped,id=p9 -device > > > virtio-9p-pci,fsdev=p9,mount_tag=p9fs" > > > > > > Base-commit: 13356edb87506c148b163b8c7eb0695647d00c2a > > > > > > Changes in v4: > > > - Fixed 9pfs mounted as read-only issue on Windows host, adding a > > > win32_error_to_posix() to translate Windows native API error to > > > POSIX one. > > > - Fixed errors of handling symbolic links > > > - Added forward declaration to avoid using 'void *' > > > - Implemented Windows specific xxxdir() APIs for safe directory access > > > > > > > > Sorry to look a bit late at this series, I don't know what was discussed > > previously. > > > > My general feeling is that a lot of this FS portability work would be > > better handled by using GIO (even though this may add some extra > > dependency). GIO lacks some features on win32 (for example xattributes on > > win32), but they could have been proposed there too and benefiting other > > apps. > > The currently impl relies on the openat, fstatat, mkdirat, renameat, > utimensat, unlinkat functions. IIRC this was in order to deal with > various security vulnerabilities that exist due to race conditions. > AFAIK, there's no way to achieve the same with GIO as its a higher > level API which doesn't expose this kind of functionality > > Correct me if I am wrong, but that doesn't seem to hold much since the protocol doesn't keep a context (with associated fds) around. But perhaps GIO API alone can't provide safe implementations of the FileOperations callbacks? Also a lot of 9p-unix specific details may not map easily to the GIO API. How they can be ported to win32 is certainly a challenge, mostly duplicating the effort done in GIO to me.
Re: [RFC v6 2/4] virtio-blk: add zoned storage emulation for zoned devices
On Mon, Jan 30, 2023 at 06:30:16PM +, Daniel P. Berrangé wrote:
> On Mon, Jan 30, 2023 at 10:17:48AM -0500, Stefan Hajnoczi wrote:
> > On Mon, 30 Jan 2023 at 07:33, Daniel P. Berrangé
> > wrote:
> > >
> > > On Sun, Jan 29, 2023 at 06:39:49PM +0800, Sam Li wrote:
> > > > This patch extends virtio-blk emulation to handle zoned device commands
> > > > by calling the new block layer APIs to perform zoned device I/O on
> > > > behalf of the guest. It supports Report Zone, four zone oparations
> > > > (open,
> > > > close, finish, reset), and Append Zone.
> > > >
> > > > The VIRTIO_BLK_F_ZONED feature bit will only be set if the host does
> > > > support zoned block devices. Regular block devices(conventional zones)
> > > > will not be set.
> > > >
> > > > The guest os can use blktests, fio to test those commands on zoned
> > > > devices.
> > > > Furthermore, using zonefs to test zone append write is also supported.
> > > >
> > > > Signed-off-by: Sam Li
> > > > ---
> > > > hw/block/virtio-blk-common.c | 2 +
> > > > hw/block/virtio-blk.c| 394 +++
> > > > 2 files changed, 396 insertions(+)
> > > >
> > >
> > > > @@ -949,6 +1311,30 @@ static void virtio_blk_update_config(VirtIODevice
> > > > *vdev, uint8_t *config)
> > > > blkcfg.write_zeroes_may_unmap = 1;
> > > > virtio_stl_p(vdev, _write_zeroes_seg, 1);
> > > > }
> > > > +if (bs->bl.zoned != BLK_Z_NONE) {
> > > > +switch (bs->bl.zoned) {
> > > > +case BLK_Z_HM:
> > > > +blkcfg.zoned.model = VIRTIO_BLK_Z_HM;
> > > > +break;
> > > > +case BLK_Z_HA:
> > > > +blkcfg.zoned.model = VIRTIO_BLK_Z_HA;
> > > > +break;
> > > > +default:
> > > > +g_assert_not_reached();
> > > > +}
> > > > +
> > > > +virtio_stl_p(vdev, _sectors,
> > > > + bs->bl.zone_size / 512);
> > > > +virtio_stl_p(vdev, _active_zones,
> > > > + bs->bl.max_active_zones);
> > > > +virtio_stl_p(vdev, _open_zones,
> > > > + bs->bl.max_open_zones);
> > > > +virtio_stl_p(vdev, _granularity, blk_size);
> > > > +virtio_stl_p(vdev, _append_sectors,
> > > > + bs->bl.max_append_sectors);
> > >
> > > So these are all ABI sensitive frontend device settings, but they are
> > > not exposed as tunables on the virtio-blk device, instead they are
> > > implicitly set from the backend.
> > >
> > > We have done this kind of thing before in QEMU, but several times it
> > > has bitten QEMU maintainers/users, as having a backend affect the
> > > frontend ABI is not to typical. It wouldn't be immediately obvious
> > > when starting QEMU on a target host that the live migration would
> > > be breaking ABI if the target host wasn't using a zoned device with
> > > exact same settings.
> > >
> > > This also limits mgmt flexibility across live migration, if the
> > > mgmt app wants/needs to change the storage backend. eg maybe they
> > > need to evacuate the host for an emergency, but don't have spare
> > > hosts with same kind of storage. It might be desirable to migrate
> > > and switch to a plain block device or raw/qcow2 file, rather than
> > > let the VM die.
> > >
> > > Can we make these virtio setting be explicitly controlled on the
> > > virtio-blk device. If not specified explicitly they could be
> > > auto-populated from the backend for ease of use, but if specified
> > > then simply validate the backend is a match. libvirt would then
> > > make sure these are always explicitly set on the frontend.
> >
> > I think this is a good idea, especially if we streamline the
> > file-posix.c driver by merging --blockdev zoned_host_device into
> > --blockdev host_device. It won't be obvious from the command-line
> > whether this is a zoned or non-zoned device. There should be a
> > --device virtio-blk-pci,drive=drive0,zoned=on option that fails when
> > drive0 isn't zoned. It should probably be on/off/auto where auto is
> > the default and doesn't check anything, on requires a zoned device,
> > and off requires a non-zoned device. That will prevent accidental
> > migration between zoned/non-zoned devices.
> >
> > I want to point out that virtio-blk doesn't have checks for the disk
> > size or other details, so what you're suggesting for zone_sectors, etc
> > is stricter than what QEMU does today. Since the virtio-blk parameters
> > you're proposing are optional, I think it doesn't hurt though.
>
> Yeah, it is slightly different than some of the parameters handling.
> I guess you could say that with disk capacity, matching size is a
> fairly obvious constraint/expectation to manage, and also long standing.
>
> With disk capacity, you can add the 'raw' driver on top of any block
> driver stack, to apply an arbitrary offset+size, to make the storage
> smaller than it otherwise is on disk. Conceptually than could have
> been done on
Re: [PATCH 0/3] VIA PM Improvements
On Sun, 29 Jan 2023, Bernhard Beschow wrote: This series is part of my work to bring the VIA south bridges to the PC machine [1]. First it resolves a fixme in the device model by using the dedicated ACPI interrupt register for SCI routing. It then enables the device model to switch to ACPI. Finally, ACPI shutdown is implemented which guests can take advantage of after switching to ACPI mode. Testing done: - `make check` - `qemu-system-ppc -M pegasos2 \ -rtc base=localtime \ -device ati-vga,guest_hwcursor=true,romfile="" \ -cdrom morphos-3.17.iso \ -kernel morphos-3.17/boot.img` - `qemu-system-ppc -M pegasos2 \ -device ati-vga,romfile="" \ -cdrom morphos-3.17.iso \ -bios pegasos2.rom` I can't review this in detail so I can only give some cosmetic comments, do with it what you like. For testing I think shutdown from MorphOS worked with the pegasos2.rom after this patch: https://lists.nongnu.org/archive/html/qemu-devel/2021-11/msg01871.html but that was not accepted as it was deemed to be an error in memory layer but then that wasn't fixed so probably this workaround is still needed to get it to work with big endian guest on little endian host. Does poweroff work from Linux? Regards, BALATON Zoltan - `qemu-system-x86_64 -M pc -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` on my pc-via branch seems to work without any noticable differences to piix3 except that hotplugging isn't implemented. [1] https://github.com/shentok/qemu/tree/pc-via Bernhard Beschow (3): hw/isa/vt82c686: Fix SCI routing hw/isa/vt82c686: Allow PM controller to switch to ACPI mode hw/isa/vt82c686: Implement ACPI powerdown hw/isa/vt82c686.c | 75 +++ 1 file changed, 62 insertions(+), 13 deletions(-) -- 2.39.1
[PULL 14/27] qemu/bswap: Use compiler __builtin_bswap() on NetBSD
From: Philippe Mathieu-Daudé
Since commit efc6c070aca ("configure: Add a test for the minimum
compiler version") the minimum compiler version required for GCC
is 4.8, which supports __builtin_bswap().
Remove the NetBSD specific ifdef'ry.
This reverts commit 1360677cfe3ca8f945fa1de77823df21a77e4500
("makes NetBSD use the native bswap functions").
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2023063147.71761-7-phi...@linaro.org>
Signed-off-by: Thomas Huth
---
meson.build | 4
include/qemu/bswap.h | 11 ---
2 files changed, 15 deletions(-)
diff --git a/meson.build b/meson.build
index 7e15a010bf..a03d3dbd3a 100644
--- a/meson.build
+++ b/meson.build
@@ -2030,10 +2030,6 @@ config_host_data.set('CONFIG_INOTIFY',
cc.has_header_symbol('sys/inotify.h', 'inotify_init'))
config_host_data.set('CONFIG_INOTIFY1',
cc.has_header_symbol('sys/inotify.h', 'inotify_init1'))
-config_host_data.set('CONFIG_MACHINE_BSWAP_H',
- cc.has_header_symbol('machine/bswap.h', 'bswap32',
- prefix: '''#include
- #include
'''))
config_host_data.set('CONFIG_PRCTL_PR_SET_TIMERSLACK',
cc.has_header_symbol('sys/prctl.h', 'PR_SET_TIMERSLACK'))
config_host_data.set('CONFIG_RTNETLINK',
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index 32d5cdec27..3cbe52246b 100644
--- a/include/qemu/bswap.h
+++ b/include/qemu/bswap.h
@@ -1,27 +1,16 @@
#ifndef BSWAP_H
#define BSWAP_H
-#ifdef CONFIG_MACHINE_BSWAP_H
-# include
-# include
-# else
-#define BSWAP_FROM_FALLBACKS
-#endif /* ! CONFIG_MACHINE_BSWAP_H */
-
#ifdef __cplusplus
extern "C" {
#endif
-#ifdef BSWAP_FROM_FALLBACKS
#undef bswap16
#define bswap16(_x) __builtin_bswap16(_x)
#undef bswap32
#define bswap32(_x) __builtin_bswap32(_x)
#undef bswap64
#define bswap64(_x) __builtin_bswap64(_x)
-#endif
-
-#undef BSWAP_FROM_FALLBACKS
static inline void bswap16s(uint16_t *s)
{
--
2.31.1
[PULL 20/27] tests/qtest/vnc-display-test: Disable on Darwin
From: Philippe Mathieu-Daudé
This test is failing in gtk-vnc on Darwin:
$ make check-qtest-aarch64
...
19/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/vnc-display-test
ERROR **: 10:42:35.488: vnc-error: Unsupported auth type 17973672
While QEMU picks the sigaltstack coroutine backend, gtk-vnc uses
the ucontext coroutine backend, which might be broken on Darwin.
Disable this test (current problem being investigated in this thread:
https://lore.kernel.org/qemu-devel/y8kw6x6keb5l5...@redhat.com/).
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230119120514.28778-4-phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Marc-André Lureau
Signed-off-by: Thomas Huth
---
tests/qtest/vnc-display-test.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/vnc-display-test.c b/tests/qtest/vnc-display-test.c
index df468c7b22..e52a4326ec 100644
--- a/tests/qtest/vnc-display-test.c
+++ b/tests/qtest/vnc-display-test.c
@@ -19,7 +19,7 @@ typedef struct Test {
GMainLoop *loop;
} Test;
-#if !defined(WIN32)
+#if !defined(WIN32) && !defined(CONFIG_DARWIN)
static void on_vnc_error(VncConnection* self,
const char* msg)
@@ -41,6 +41,9 @@ test_setup(Test *test)
#ifdef WIN32
g_test_skip("Not supported on Windows yet");
return false;
+#elif defined(CONFIG_DARWIN)
+g_test_skip("Broken on Darwin");
+return false;
#else
int pair[2];
--
2.31.1
[PULL 02/27] tests/qtest/qom-test: Stop spamming the test log
We are still facing the issues that our test logs in the gitlab CI
are too big (and thus cut off). A huge part is still caused by the
qom-test that prints the path and name of each object it looks at
by default. That's too much. Let's be silent by default, and only
print the object path+name when running with V=2 (and the properties
only with V=3 and higher).
Message-Id: <20230118122557.1668860-1-th...@redhat.com>
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
tests/qtest/qom-test.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c
index d380261f8f..d677f87c8e 100644
--- a/tests/qtest/qom-test.c
+++ b/tests/qtest/qom-test.c
@@ -14,7 +14,7 @@
#include "qemu/cutils.h"
#include "libqtest.h"
-static bool verbose;
+static int verbosity_level;
static void test_properties(QTestState *qts, const char *path, bool recurse)
{
@@ -24,7 +24,9 @@ static void test_properties(QTestState *qts, const char
*path, bool recurse)
QListEntry *entry;
GSList *children = NULL, *links = NULL;
-g_test_message("Obtaining properties of %s", path);
+if (verbosity_level >= 2) {
+g_test_message("Obtaining properties of %s", path);
+}
response = qtest_qmp(qts, "{ 'execute': 'qom-list',"
" 'arguments': { 'path': %s } }", path);
g_assert(response);
@@ -51,7 +53,7 @@ static void test_properties(QTestState *qts, const char
*path, bool recurse)
}
} else {
const char *prop = qdict_get_str(tuple, "name");
-if (verbose) {
+if (verbosity_level >= 3) {
g_test_message("-> %s", prop);
}
tmp = qtest_qmp(qts,
@@ -109,8 +111,8 @@ int main(int argc, char **argv)
{
char *v_env = getenv("V");
-if (v_env && atoi(v_env) >= 2) {
-verbose = true;
+if (v_env) {
+verbosity_level = atoi(v_env);
}
g_test_init(, , NULL);
--
2.31.1
[PULL 26/27] tests/qtest/display-vga-test: Add proper checks if a device is available
display-vga-test currently tries to guess the usable VGA devices
according to the target architecture that is used for the test.
This of course does not work if QEMU has been built with the
"--without-default-devices" configure switch. To fix this, use the
qtest_has_device() function for the decision instead. This way
we can also consolidate most of the test functions into one single
function (that takes a parameter with the device name now), except
for the multihead test that tries to instantiate two devices and
thus is a little bit different.
Message-Id: <20230130104446.1286773-4-th...@redhat.com>
Reviewed-by: Richard Henderson
Signed-off-by: Thomas Huth
---
tests/qtest/display-vga-test.c | 65 +-
1 file changed, 25 insertions(+), 40 deletions(-)
diff --git a/tests/qtest/display-vga-test.c b/tests/qtest/display-vga-test.c
index ace3bb28e0..75b341a9c6 100644
--- a/tests/qtest/display-vga-test.c
+++ b/tests/qtest/display-vga-test.c
@@ -8,61 +8,46 @@
*/
#include "qemu/osdep.h"
-#include "libqtest-single.h"
-
-static void pci_cirrus(void)
-{
-qtest_start("-vga none -device cirrus-vga");
-qtest_end();
-}
-
-static void pci_stdvga(void)
-{
-qtest_start("-vga none -device VGA");
-qtest_end();
-}
-
-static void pci_secondary(void)
-{
-qtest_start("-vga none -device secondary-vga");
-qtest_end();
-}
+#include "libqtest.h"
static void pci_multihead(void)
{
-qtest_start("-vga none -device VGA -device secondary-vga");
-qtest_end();
-}
+QTestState *qts;
-static void pci_virtio_gpu(void)
-{
-qtest_start("-vga none -device virtio-gpu-pci");
-qtest_end();
+qts = qtest_init("-vga none -device VGA -device secondary-vga");
+qtest_quit(qts);
}
-static void pci_virtio_vga(void)
+static void test_vga(gconstpointer data)
{
-qtest_start("-vga none -device virtio-vga");
-qtest_end();
+QTestState *qts;
+
+qts = qtest_initf("-vga none -device %s", (const char *)data);
+qtest_quit(qts);
}
int main(int argc, char **argv)
{
-const char *arch = qtest_get_arch();
+static const char *devices[] = {
+"cirrus-vga",
+"VGA",
+"secondary-vga",
+"virtio-gpu-pci",
+"virtio-vga"
+};
g_test_init(, , NULL);
-if (strcmp(arch, "alpha") == 0 || strcmp(arch, "i386") == 0 ||
-strcmp(arch, "mips") == 0 || strcmp(arch, "x86_64") == 0) {
-qtest_add_func("/display/pci/cirrus", pci_cirrus);
+for (int i = 0; i < ARRAY_SIZE(devices); i++) {
+if (qtest_has_device(devices[i])) {
+char *testpath = g_strdup_printf("/display/pci/%s", devices[i]);
+qtest_add_data_func(testpath, devices[i], test_vga);
+g_free(testpath);
+}
}
-qtest_add_func("/display/pci/stdvga", pci_stdvga);
-qtest_add_func("/display/pci/secondary", pci_secondary);
-qtest_add_func("/display/pci/multihead", pci_multihead);
-qtest_add_func("/display/pci/virtio-gpu", pci_virtio_gpu);
-if (g_str_equal(arch, "i386") || g_str_equal(arch, "x86_64") ||
-g_str_equal(arch, "hppa") || g_str_equal(arch, "ppc64")) {
-qtest_add_func("/display/pci/virtio-vga", pci_virtio_vga);
+
+if (qtest_has_device("secondary-vga")) {
+qtest_add_func("/display/pci/multihead", pci_multihead);
}
return g_test_run();
--
2.31.1
[PULL 05/27] configs/targets/nios2-softmmu: Add TARGET_NEED_FDT=y to the nios2 config
qemu-system-nios2 uses the functions from libfdt in hw/nios2/boot.c, so this target has to be marked with TARGET_NEED_FDT=y in its config file. Message-Id: <20230119125745.2028814-1-th...@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- configs/targets/nios2-softmmu.mak | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/targets/nios2-softmmu.mak b/configs/targets/nios2-softmmu.mak index 1e93b54cd1..5823fc02c8 100644 --- a/configs/targets/nios2-softmmu.mak +++ b/configs/targets/nios2-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=nios2 TARGET_ALIGNED_ONLY=y +TARGET_NEED_FDT=y -- 2.31.1
[PULL 16/27] docs/about/deprecated: Mark HAXM in QEMU as deprecated
The HAXM project has been retired (see https://github.com/intel/haxm#status), so we should mark the code in QEMU as deprecated (and finally remove it unless somebody else picks the project up again - which is quite unlikely since there are now whpx and hvf on these operating systems, too). Message-Id: <20230126121034.1035138-1-th...@redhat.com> Reviewed-by: Daniel P. Berrangé Signed-off-by: Thomas Huth --- docs/about/deprecated.rst | 6 ++ target/i386/hax/hax-all.c | 3 +++ 2 files changed, 9 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 3f4d678eb4..da2e6fe63d 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -93,6 +93,12 @@ form is preferred. The HPET setting has been turned into a machine property. Use ``-machine hpet=off`` instead. +``-accel hax`` (since 8.0) +'' + +The HAXM project has been retired (see https://github.com/intel/haxm#status). +Use "whpx" (on Windows) or "hvf" (on macOS) instead. + QEMU Machine Protocol (QMP) commands diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index b7fb5385b2..3e5992a63b 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -357,6 +357,9 @@ static int hax_accel_init(MachineState *ms) fprintf(stdout, "HAX is %s and emulator runs in %s mode.\n", !ret ? "working" : "not working", !ret ? "fast virt" : "emulation"); +fprintf(stdout, +"NOTE: HAX is deprecated and will be removed in a future release.\n" +" Use 'whpx' (on Windows) or 'hvf' (on macOS) instead.\n"); } return ret; } -- 2.31.1
[PATCH v9 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/csr.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0db2c233e5..6b157806a5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
-static const char valid_vm_1_10_32[16] = {
-[VM_1_10_MBARE] = 1,
-[VM_1_10_SV32] = 1
+static const bool valid_vm_1_10_32[16] = {
+[VM_1_10_MBARE] = true,
+[VM_1_10_SV32] = true
};
-static const char valid_vm_1_10_64[16] = {
-[VM_1_10_MBARE] = 1,
-[VM_1_10_SV39] = 1,
-[VM_1_10_SV48] = 1,
-[VM_1_10_SV57] = 1
+static const bool valid_vm_1_10_64[16] = {
+[VM_1_10_MBARE] = true,
+[VM_1_10_SV39] = true,
+[VM_1_10_SV48] = true,
+[VM_1_10_SV57] = true
};
/* Machine Information Registers */
@@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
-static int validate_vm(CPURISCVState *env, target_ulong vm)
+static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
if (riscv_cpu_mxl(env) == MXL_RV32) {
return valid_vm_1_10_32[vm & 0xf];
@@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int
csrno,
static RISCVException write_satp(CPURISCVState *env, int csrno,
target_ulong val)
{
-target_ulong vm, mask;
+target_ulong mask;
+bool vm;
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
return RISCV_EXCP_NONE;
--
2.37.2
[PATCH v9 4/5] riscv: Introduce satp mode hw capabilities
Currently, the max satp mode is set with the only constraint that it must be
implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].
But we actually need to add another level of constraint: what the hw is
actually capable of, because currently, a linux booting on a sifive-u54
boots in sv57 mode which is incompatible with the cpu's sv39 max
capability.
So add a new bitmap to RISCVSATPMap which contains this capability and
initialize it in every XXX_cpu_init.
Finally:
- valid_vm_1_10_[32|64] constrains which satp mode the CPU can use
- the CPU hw capabilities constrains what the user may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 79 +++---
target/riscv/cpu.h | 8 +++--
2 files changed, 60 insertions(+), 27 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3a7a1746aa..6dd76355ec 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool
is_32_bit)
g_assert_not_reached();
}
-/* Sets the satp mode to the max supported */
-static void set_satp_mode_default_map(RISCVCPU *cpu)
+static void set_satp_mode_max_supported(RISCVCPU *cpu,
+uint8_t satp_mode)
{
bool rv32 = riscv_cpu_mxl(>env) == MXL_RV32;
+const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
-if (riscv_feature(>env, RISCV_FEATURE_MMU)) {
-cpu->cfg.satp_mode.map |=
-(1 << satp_mode_from_str(rv32 ? "sv32" : "sv57"));
-} else {
-cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare"));
+for (int i = 0; i <= satp_mode; ++i) {
+if (valid_vm[i]) {
+cpu->cfg.satp_mode.supported |= (1 << i);
+}
}
}
+/* Set the satp mode to the max supported */
+static void set_satp_mode_default_map(RISCVCPU *cpu)
+{
+cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
+}
+
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = _CPU(obj)->env;
+RISCVCPU *cpu = RISCV_CPU(obj);
+
#if defined(TARGET_RISCV32)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+set_satp_mode_max_supported(cpu, VM_1_10_SV32);
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+set_satp_mode_max_supported(cpu, VM_1_10_SV57);
#endif
set_priv_version(env, PRIV_VERSION_1_12_0);
register_cpu_props(obj);
@@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj)
static void rv64_base_cpu_init(Object *obj)
{
CPURISCVState *env = _CPU(obj)->env;
+RISCVCPU *cpu = RISCV_CPU(obj);
+
/* We set this in the realise function */
set_misa(env, MXL_RV64, 0);
register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
+set_satp_mode_max_supported(cpu, VM_1_10_SV57);
}
static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = _CPU(obj)->env;
+RISCVCPU *cpu = RISCV_CPU(obj);
+
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
+set_satp_mode_max_supported(cpu, VM_1_10_SV39);
}
static void rv64_sifive_e_cpu_init(Object *obj)
@@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
+set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
}
static void rv128_base_cpu_init(Object *obj)
@@ -354,28 +371,36 @@ static void rv128_base_cpu_init(Object *obj)
exit(EXIT_FAILURE);
}
CPURISCVState *env = _CPU(obj)->env;
+RISCVCPU *cpu = RISCV_CPU(obj);
/* We set this in the realise function */
set_misa(env, MXL_RV128, 0);
register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
+set_satp_mode_max_supported(cpu, VM_1_10_SV57);
}
#else
static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = _CPU(obj)->env;
+RISCVCPU *cpu = RISCV_CPU(obj);
+
/* We set this in the realise function */
set_misa(env, MXL_RV32, 0);
register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
+set_satp_mode_max_supported(cpu, VM_1_10_SV32);
}
static void rv32_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = _CPU(obj)->env;
+RISCVCPU *cpu = RISCV_CPU(obj);
+
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
+set_satp_mode_max_supported(cpu, VM_1_10_SV32);
}
static void rv32_sifive_e_cpu_init(Object *obj)
@@ -386,6 +411,7 @@ static void
[PATCH v9 3/5] riscv: Allow user to set the satp mode
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).
As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply setting the
"highest" supported mode and the bare mode is always supported.
You can set the satp mode using the new properties "sv32", "sv39", "sv48",
"sv57" and "sv64" as follows:
-cpu rv64,sv57=on # Linux will boot using sv57 scheme
-cpu rv64,sv39=on # Linux will boot using sv39 scheme
-cpu rv64,sv57=off # Linux will boot using sv48 scheme
-cpu rv64 # Linux will boot using sv57 scheme by default
We take the highest level set by the user:
-cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme
We make sure that invalid configurations are rejected:
-cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are
# enabled
We accept "redundant" configurations:
-cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme
And contradictory configurations:
-cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 207 +
target/riscv/cpu.h | 19 +
target/riscv/csr.c | 12 ++-
3 files changed, 231 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7181b34f86..3a7a1746aa 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -27,6 +27,7 @@
#include "time_helper.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "qemu/error-report.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
@@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int
vext_ver)
env->vext_ver = vext_ver;
}
+static uint8_t satp_mode_from_str(const char *satp_mode_str)
+{
+if (!strncmp(satp_mode_str, "mbare", 5)) {
+return VM_1_10_MBARE;
+}
+
+if (!strncmp(satp_mode_str, "sv32", 4)) {
+return VM_1_10_SV32;
+}
+
+if (!strncmp(satp_mode_str, "sv39", 4)) {
+return VM_1_10_SV39;
+}
+
+if (!strncmp(satp_mode_str, "sv48", 4)) {
+return VM_1_10_SV48;
+}
+
+if (!strncmp(satp_mode_str, "sv57", 4)) {
+return VM_1_10_SV57;
+}
+
+if (!strncmp(satp_mode_str, "sv64", 4)) {
+return VM_1_10_SV64;
+}
+
+g_assert_not_reached();
+}
+
+uint8_t satp_mode_max_from_map(uint32_t map)
+{
+/* map here has at least one bit set, so no problem with clz */
+return 31 - __builtin_clz(map);
+}
+
+const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
+{
+if (is_32_bit) {
+switch (satp_mode) {
+case VM_1_10_SV32:
+return "sv32";
+case VM_1_10_MBARE:
+return "none";
+}
+} else {
+switch (satp_mode) {
+case VM_1_10_SV64:
+return "sv64";
+case VM_1_10_SV57:
+return "sv57";
+case VM_1_10_SV48:
+return "sv48";
+case VM_1_10_SV39:
+return "sv39";
+case VM_1_10_MBARE:
+return "none";
+}
+}
+
+g_assert_not_reached();
+}
+
+/* Sets the satp mode to the max supported */
+static void set_satp_mode_default_map(RISCVCPU *cpu)
+{
+bool rv32 = riscv_cpu_mxl(>env) == MXL_RV32;
+
+if (riscv_feature(>env, RISCV_FEATURE_MMU)) {
+cpu->cfg.satp_mode.map |=
+(1 << satp_mode_from_str(rv32 ? "sv32" : "sv57"));
+} else {
+cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare"));
+}
+}
+
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = _CPU(obj)->env;
@@ -619,6 +695,83 @@ static void riscv_cpu_disas_set_info(CPUState *s,
disassemble_info *info)
}
}
+static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
+{
+bool rv32 = riscv_cpu_mxl(>env) == MXL_RV32;
+const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
+uint8_t satp_mode_max;
+
+if (cpu->cfg.satp_mode.map == 0) {
+if (cpu->cfg.satp_mode.init == 0) {
+/* If unset by the user, we fallback to the default satp mode. */
+set_satp_mode_default_map(cpu);
+} else {
+/*
+ * Find the lowest level that was disabled and then enable the
+ * first valid level below which can be found in
+ * valid_vm_1_10_32/64.
+ */
+for (int i = 1; i < 16; ++i) {
+if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) {
+for (int j = i - 1; j >= 0; --j) {
+if (valid_vm[j]) {
+cpu->cfg.satp_mode.map |= (1 << j);
+break;
+}
+
Re: [PULL 5/5] migration: simplify migration_iteration_run()
On 30.01.23 11:03, Juan Quintela wrote:
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
---
migration/migration.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/migration/migration.c b/migration/migration.c
index 594a42f085..644c61e91d 100644
--- a/migration/migration.c
+++ b/migration/migration.c
@@ -3764,23 +3764,23 @@ static MigIterateState
migration_iteration_run(MigrationState *s)
pend_pre, pend_compat, pend_post);
}
-if (pending_size && pending_size >= s->threshold_size) {
-/* Still a significant amount to transfer */
-if (!in_postcopy && pend_pre <= s->threshold_size &&
-qatomic_read(>start_postcopy)) {
-if (postcopy_start(s)) {
-error_report("%s: postcopy failed to start", __func__);
-}
-return MIG_ITERATE_SKIP;
-}
-/* Just another iteration step */
-qemu_savevm_state_iterate(s->to_dst_file, in_postcopy);
-} else {
+if (pending_size < s->threshold_size) {
to keep the logic, formally it should be "if (!pending_size || pending_size <
s->threshold_size)"...
Actually, could s->threshold_size be 0 here? Or, worth an assertion
assert(s->threshold_size) ?
trace_migration_thread_low_pending(pending_size);
migration_completion(s);
return MIG_ITERATE_BREAK;
}
+/* Still a significant amount to transfer */
+if (!in_postcopy && pend_pre <= s->threshold_size &&
+qatomic_read(>start_postcopy)) {
+if (postcopy_start(s)) {
+error_report("%s: postcopy failed to start", __func__);
+}
+return MIG_ITERATE_SKIP;
+}
+
+/* Just another iteration step */
+qemu_savevm_state_iterate(s->to_dst_file, in_postcopy);
return MIG_ITERATE_RESUME;
}
--
Best regards,
Vladimir
Re: [PATCH 2/2] linux-user: Allow sendmsg() without IOV
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Applications do call sendmsg() without any IOV, e.g.:
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=NULL, msg_iovlen=0,
msg_control=[{cmsg_len=36, cmsg_level=SOL_ALG, cmsg_type=0x2}],
msg_controllen=40, msg_flags=0}, MSG_MORE) = 0
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=[{iov_base="The quick brown fox
jumps over t"..., iov_len=183}],
msg_iovlen=1, msg_control=[{cmsg_len=20, cmsg_level=SOL_ALG,
cmsg_type=0x3}],
msg_controllen=24, msg_flags=0}, 0) = 183
The function do_sendrecvmsg_locked() is used for sndmsg() and recvmsg()
and calls lock_iovec() to lock the IOV into memory. For the first
sendmsg() above it returns NULL and thus wrongly skips the call the host
sendmsg() syscall, which will break the calling application.
Fix this issue by:
- allowing sendmsg() even with empty IOV
- skip recvmsg() if IOV is NULL
- skip both if the return code of do_sendrecvmsg_locked() != 0, which
indicates some failure like EFAULT on the IOV
Tested with the debian "ell" package with hppa guest on x86_64 host.
Signed-off-by: Helge Deller
---
linux-user/syscall.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index a365903a3a..9e2c0a18fc 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -3330,7 +3330,10 @@ static abi_long do_sendrecvmsg_locked(int fd, struct
target_msghdr *msgp,
target_vec, count, send);
if (vec == NULL) {
ret = -host_to_target_errno(errno);
-goto out2;
+/* allow sending packet without any iov, e.g. with MSG_MORE flag */
why don't you check only for count is 0?
Somehing like:
if (vec == NULL && (count || !send)) {
...
Thanks,
Laurent
Re: [PATCH v8 3/5] riscv: Allow user to set the satp mode
Hi Bin,
On Mon, Jan 30, 2023 at 5:22 AM Bin Meng wrote:
>
> On Thu, Jan 26, 2023 at 12:23 AM Alexandre Ghiti
> wrote:
> >
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done in
> > csr.c:validate_vm).
> >
> > As per the specification, sv64 must support sv57, which in turn must
> > support sv48...etc. So we can restrict machine support by simply setting the
> > "highest" supported mode and the bare mode is always supported.
> >
> > You can set the satp mode using the new properties "sv32", "sv39", "sv48",
> > "sv57" and "sv64" as follows:
> > -cpu rv64,sv57=on # Linux will boot using sv57 scheme
> > -cpu rv64,sv39=on # Linux will boot using sv39 scheme
> > -cpu rv64,sv57=off # Linux will boot using sv48 scheme
> > -cpu rv64 # Linux will boot using sv57 scheme by default
> >
> > We take the highest level set by the user:
> > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme
> >
> > We make sure that invalid configurations are rejected:
> > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are
> ># enabled
> >
> > We accept "redundant" configurations:
> > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme
> >
> > And contradictory configurations:
> > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
> >
> > Co-Developed-by: Ludovic Henry
> > Signed-off-by: Ludovic Henry
> > Signed-off-by: Alexandre Ghiti
> > ---
> > target/riscv/cpu.c | 206 +
> > target/riscv/cpu.h | 19 +
> > target/riscv/csr.c | 12 ++-
> > 3 files changed, 230 insertions(+), 7 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 7181b34f86..54494a72be 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -27,6 +27,7 @@
> > #include "time_helper.h"
> > #include "exec/exec-all.h"
> > #include "qapi/error.h"
> > +#include "qapi/visitor.h"
> > #include "qemu/error-report.h"
> > #include "hw/qdev-properties.h"
> > #include "migration/vmstate.h"
> > @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int
> > vext_ver)
> > env->vext_ver = vext_ver;
> > }
> >
> > +static uint8_t satp_mode_from_str(const char *satp_mode_str)
> > +{
> > +if (!strncmp(satp_mode_str, "mbare", 5)) {
> > +return VM_1_10_MBARE;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv32", 4)) {
> > +return VM_1_10_SV32;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv39", 4)) {
> > +return VM_1_10_SV39;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv48", 4)) {
> > +return VM_1_10_SV48;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv57", 4)) {
> > +return VM_1_10_SV57;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv64", 4)) {
> > +return VM_1_10_SV64;
> > +}
> > +
> > +g_assert_not_reached();
> > +}
> > +
> > +uint8_t satp_mode_max_from_map(uint32_t map)
> > +{
> > +/* map here has at least one bit set, so no problem with clz */
> > +return 31 - __builtin_clz(map);
> > +}
> > +
> > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
> > +{
> > +if (is_32_bit) {
> > +switch (satp_mode) {
> > +case VM_1_10_SV32:
> > +return "sv32";
> > +case VM_1_10_MBARE:
> > +return "none";
> > +}
> > +} else {
> > +switch (satp_mode) {
> > +case VM_1_10_SV64:
> > +return "sv64";
> > +case VM_1_10_SV57:
> > +return "sv57";
> > +case VM_1_10_SV48:
> > +return "sv48";
> > +case VM_1_10_SV39:
> > +return "sv39";
> > +case VM_1_10_MBARE:
> > +return "none";
> > +}
> > +}
> > +
> > +g_assert_not_reached();
> > +}
> > +
> > +/* Sets the satp mode to the max supported */
> > +static void set_satp_mode_default(RISCVCPU *cpu)
>
> This function is better named as set_satp_mode_default_map
>
Indeed, fixed in v9.
> > +{
> > +bool rv32 = riscv_cpu_mxl(>env) == MXL_RV32;
> > +
> > +if (riscv_feature(>env, RISCV_FEATURE_MMU)) {
> > +cpu->cfg.satp_mode.map |=
> > +(1 << satp_mode_from_str(rv32 ? "sv32" : "sv57"));
> > +} else {
> > +cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare"));
> > +}
>
> I believe the "mbare" bit should always be set, so this can be:
>
> cpu->cfg.satp_mode.map = 1 << satp_mode_from_str("mbare");
> if (riscv_feature(>env, RISCV_FEATURE_MMU)) {
>cpu->cfg.satp_mode.map |=
> (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57"));
Actually, at the end of riscv_cpu_satp_mode_finalize, the map is
"expanded" so that all supported modes are set in the bitmap.
>
> > +}
> > +
> > static void riscv_any_cpu_init(Object *obj)
> > {
> > CPURISCVState *env =
[PATCH v9 5/5] riscv: Correctly set the device-tree entry 'mmu-type'
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 94ff2a1584..48d034a5f7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
int cpu;
uint32_t cpu_phandle;
MachineState *mc = MACHINE(s);
-char *name, *cpu_name, *core_name, *intc_name;
+uint8_t satp_mode_max;
+char *name, *cpu_name, *core_name, *intc_name, *sv_name;
for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
cpu_phandle = (*phandle)++;
@@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(mc->fdt, cpu_name);
-if (riscv_feature(>soc[socket].harts[cpu].env,
- RISCV_FEATURE_MMU)) {
-qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
-(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
-} else {
-qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
-"riscv,none");
-}
+
+satp_mode_max = satp_mode_max_from_map(
+s->soc[socket].harts[cpu].cfg.satp_mode.map);
+sv_name = g_strdup_printf("riscv,%s",
+ satp_mode_str(satp_mode_max, is_32_bit));
+qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name);
+g_free(sv_name);
+
name = riscv_isa_string(>soc[socket].harts[cpu]);
qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
g_free(name);
--
2.37.2
Re: [PATCH v2 08/20] hw/i386/ich9: Rename Q35_MASK to ICH9_MASK
On 31/01/2023 12.53, Bernhard Beschow wrote: The Q35_MASK macro is already defined by TYPE_Q35_HOST_DEVICE, so let TYPE_ICH9_LPC_DEVICE have its own one to prevent potential name clash. Ouch, good catch! Signed-off-by: Bernhard Beschow --- include/hw/i386/ich9.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Thomas Huth
Re: [PATCH v8 3/5] riscv: Allow user to set the satp mode
On Wed, Jan 25, 2023 at 5:52 PM Andrew Jones wrote:
>
> On Wed, Jan 25, 2023 at 05:20:08PM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done in
> > csr.c:validate_vm).
> >
> > As per the specification, sv64 must support sv57, which in turn must
> > support sv48...etc. So we can restrict machine support by simply setting the
> > "highest" supported mode and the bare mode is always supported.
> >
> > You can set the satp mode using the new properties "sv32", "sv39", "sv48",
> > "sv57" and "sv64" as follows:
> > -cpu rv64,sv57=on # Linux will boot using sv57 scheme
> > -cpu rv64,sv39=on # Linux will boot using sv39 scheme
> > -cpu rv64,sv57=off # Linux will boot using sv48 scheme
> > -cpu rv64 # Linux will boot using sv57 scheme by default
> >
> > We take the highest level set by the user:
> > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme
> >
> > We make sure that invalid configurations are rejected:
> > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are
> ># enabled
> >
> > We accept "redundant" configurations:
> > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme
> >
> > And contradictory configurations:
> > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
> >
> > Co-Developed-by: Ludovic Henry
> > Signed-off-by: Ludovic Henry
> > Signed-off-by: Alexandre Ghiti
> > ---
> > target/riscv/cpu.c | 206 +
> > target/riscv/cpu.h | 19 +
> > target/riscv/csr.c | 12 ++-
> > 3 files changed, 230 insertions(+), 7 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 7181b34f86..54494a72be 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -27,6 +27,7 @@
> > #include "time_helper.h"
> > #include "exec/exec-all.h"
> > #include "qapi/error.h"
> > +#include "qapi/visitor.h"
> > #include "qemu/error-report.h"
> > #include "hw/qdev-properties.h"
> > #include "migration/vmstate.h"
> > @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int
> > vext_ver)
> > env->vext_ver = vext_ver;
> > }
> >
> > +static uint8_t satp_mode_from_str(const char *satp_mode_str)
> > +{
> > +if (!strncmp(satp_mode_str, "mbare", 5)) {
> > +return VM_1_10_MBARE;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv32", 4)) {
> > +return VM_1_10_SV32;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv39", 4)) {
> > +return VM_1_10_SV39;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv48", 4)) {
> > +return VM_1_10_SV48;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv57", 4)) {
> > +return VM_1_10_SV57;
> > +}
> > +
> > +if (!strncmp(satp_mode_str, "sv64", 4)) {
> > +return VM_1_10_SV64;
> > +}
> > +
> > +g_assert_not_reached();
> > +}
> > +
> > +uint8_t satp_mode_max_from_map(uint32_t map)
> > +{
> > +/* map here has at least one bit set, so no problem with clz */
> > +return 31 - __builtin_clz(map);
> > +}
> > +
> > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
> > +{
> > +if (is_32_bit) {
> > +switch (satp_mode) {
> > +case VM_1_10_SV32:
> > +return "sv32";
> > +case VM_1_10_MBARE:
> > +return "none";
> > +}
> > +} else {
> > +switch (satp_mode) {
> > +case VM_1_10_SV64:
> > +return "sv64";
> > +case VM_1_10_SV57:
> > +return "sv57";
> > +case VM_1_10_SV48:
> > +return "sv48";
> > +case VM_1_10_SV39:
> > +return "sv39";
> > +case VM_1_10_MBARE:
> > +return "none";
> > +}
> > +}
> > +
> > +g_assert_not_reached();
> > +}
> > +
> > +/* Sets the satp mode to the max supported */
> > +static void set_satp_mode_default(RISCVCPU *cpu)
> > +{
> > +bool rv32 = riscv_cpu_mxl(>env) == MXL_RV32;
> > +
> > +if (riscv_feature(>env, RISCV_FEATURE_MMU)) {
> > +cpu->cfg.satp_mode.map |=
> > +(1 << satp_mode_from_str(rv32 ? "sv32" : "sv57"));
> > +} else {
> > +cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare"));
> > +}
> > +}
> > +
> > static void riscv_any_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = _CPU(obj)->env;
> > @@ -619,6 +695,82 @@ static void riscv_cpu_disas_set_info(CPUState *s,
> > disassemble_info *info)
> > }
> > }
> >
> > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
> > +{
> > +bool rv32 = riscv_cpu_mxl(>env) == MXL_RV32;
> > +const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
> > +uint8_t satp_mode_max;
> > +
> > +if (cpu->cfg.satp_mode.map == 0) {
> > +if (cpu->cfg.satp_mode.init == 0) {
> > +/* If unset by the user,
[PULL 03/27] tests/qtest/bios-tables-test: Make the test less verbose by default
We are facing the issues that our test logs in the gitlab CI are
too big (and thus cut off). The bios-tables-test is one of the few
qtests that prints many lines of output by default when running with
V=1, so it contributes to this problem. Almost all other qtests are
silent with V=1 and only print debug messages with V=2 and higher.
Thus let's change the bios-tables-test to behave more like the
other tests and only print the debug messages with V=2 (or higher).
Message-Id: <20230118125132.1694469-1-th...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Thomas Huth
---
tests/qtest/bios-tables-test.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 8608408213..355d0c3d56 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -24,7 +24,7 @@
* You will also notice that tests/qtest/bios-tables-test-allowed-diff.h lists
* a bunch of files. This is your hint that you need to do the below:
* 4. Run
- * make check V=1
+ * make check V=2
* this will produce a bunch of warnings about differences
* beween actual and expected ACPI tables. If you have IASL installed,
* they will also be disassembled so you can look at the disassembled
@@ -108,6 +108,8 @@ static const char *iasl = CONFIG_IASL;
static const char *iasl;
#endif
+static int verbosity_level;
+
static bool compare_signature(const AcpiSdtTable *sdt, const char *signature)
{
return !memcmp(sdt->aml, signature, 4);
@@ -368,7 +370,7 @@ static GArray *load_expected_aml(test_data *data)
gsize aml_len;
GArray *exp_tables = g_array_new(false, true, sizeof(AcpiSdtTable));
-if (getenv("V")) {
+if (verbosity_level >= 2) {
fputc('\n', stderr);
}
for (i = 0; i < data->tables->len; ++i) {
@@ -383,7 +385,7 @@ static GArray *load_expected_aml(test_data *data)
try_again:
aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
sdt->aml, ext);
-if (getenv("V")) {
+if (verbosity_level >= 2) {
fprintf(stderr, "Looking for expected file '%s'\n", aml_file);
}
if (g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
@@ -395,7 +397,7 @@ try_again:
goto try_again;
}
g_assert(exp_sdt.aml_file);
-if (getenv("V")) {
+if (verbosity_level >= 2) {
fprintf(stderr, "Using expected file '%s'\n", aml_file);
}
ret = g_file_get_contents(aml_file, (gchar **)_sdt.aml,
@@ -503,7 +505,7 @@ static void test_acpi_asl(test_data *data)
exp_sdt->aml, sdt->asl_file, sdt->aml_file,
exp_sdt->asl_file, exp_sdt->aml_file);
fflush(stderr);
-if (getenv("V")) {
+if (verbosity_level >= 1) {
const char *diff_env = getenv("DIFF");
const char *diff_cmd = diff_env ? diff_env : "diff -U 16";
char *diff = g_strdup_printf("%s %s %s", diff_cmd,
@@ -1974,8 +1976,13 @@ int main(int argc, char *argv[])
const char *arch = qtest_get_arch();
const bool has_kvm = qtest_has_accel("kvm");
const bool has_tcg = qtest_has_accel("tcg");
+char *v_env = getenv("V");
int ret;
+if (v_env) {
+verbosity_level = atoi(v_env);
+}
+
g_test_init(, , NULL);
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
--
2.31.1
[PULL 00/27] qtest and misc patches
Hi Peter! The following changes since commit 13356edb87506c148b163b8c7eb0695647d00c2a: Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-01-24 09:45:33 +) are available in the Git repository at: https://gitlab.com/thuth/qemu.git tags/pull-request-2023-01-31 for you to fetch changes up to e030d08c2fc02743dd37e3d2e6e28fdd739590b9: gitlab-ci.d/buildtest: Merge the --without-default-* jobs (2023-01-31 09:05:26 +0100) * qtest improvements * Remove the deprecated OTP config of sifive_u * Add libfdt to some of our CI jobs that were still missing it * Use __builtin_bswap() everywhere (all compiler versions support it now) * Deprecate the HAXM accelerator * Document PCI devices handling on s390x * Make Audiodev introspectable * Improve the runtime of some CI jobs Daniel P. Berrangé (2): qapi, audio: add query-audiodev command qapi, audio: Make introspection reflect build configuration more closely Fabiano Rosas (1): tests/tcg: Do not build/run TCG tests if TCG is disabled Laurent Vivier (1): tests/qtest: netdev: test stream and dgram backends Philippe Mathieu-Daudé (10): qemu/bswap: Replace bswapXX() by compiler __builtin_bswap() qemu/bswap: Replace bswapXXs() by compiler __builtin_bswap() qemu/bswap: Remove dependency qemu/bswap: Use compiler __builtin_bswap() on Haiku qemu/bswap: Use compiler __builtin_bswap() on FreeBSD qemu/bswap: Use compiler __builtin_bswap() on NetBSD tests/qtest/vnc-display-test: Suppress build warnings on Windows tests/qtest/vnc-display-test: Use the 'none' machine tests/qtest/vnc-display-test: Disable on Darwin tests/qtest/boot-serial-test: Constify tests[] array Sebastian Mitterle (1): docs/s390x/pcidevices: document pci devices on s390x Thomas Huth (11): tests/qtest/qom-test: Stop spamming the test log tests/qtest/bios-tables-test: Make the test less verbose by default hw/misc/sifive_u_otp: Remove the deprecated OTP config with '-drive if=none' configs/targets/nios2-softmmu: Add TARGET_NEED_FDT=y to the nios2 config travis.yml: Use the libfdt from the distro instead of the submodule travis.yml: Remove the generic addons section tests/docker/dockerfiles: Add libfdt to the i386 and to the riscv64 container docs/about/deprecated: Mark HAXM in QEMU as deprecated gitlab-ci.d/buildtest: Remove ppc-softmmu from the clang-system job tests/qtest/display-vga-test: Add proper checks if a device is available gitlab-ci.d/buildtest: Merge the --without-default-* jobs Wenchao Wang (1): MAINTAINERS: Abort HAXM maintenance MAINTAINERS| 5 +- docs/about/deprecated.rst | 12 +- docs/about/removed-features.rst| 7 + docs/system/s390x/pcidevices.rst | 41 ++ docs/system/target-s390x.rst | 1 + configure | 6 +- configs/targets/nios2-softmmu.mak | 1 + meson.build| 6 - qapi/audio.json| 57 ++- audio/audio_template.h | 20 + include/qemu/bswap.h | 83 +--- audio/audio.c | 32 ++ audio/audio_legacy.c | 41 +- hw/misc/sifive_u_otp.c | 7 - target/i386/hax/hax-all.c | 3 + tests/qtest/bios-tables-test.c | 17 +- tests/qtest/boot-serial-test.c | 2 +- tests/qtest/display-vga-test.c | 65 ++- tests/qtest/netdev-socket.c| 448 + tests/qtest/qom-test.c | 12 +- tests/qtest/vnc-display-test.c | 9 +- .gitlab-ci.d/buildtest.yml | 20 +- .travis.yml| 59 +-- .../docker/dockerfiles/debian-riscv64-cross.docker | 1 + tests/docker/dockerfiles/fedora-i386-cross.docker | 1 + tests/qtest/meson.build| 2 + 26 files changed, 743 insertions(+), 215 deletions(-) create mode 100644 docs/system/s390x/pcidevices.rst create mode 100644 tests/qtest/netdev-socket.c
[PULL 08/27] tests/docker/dockerfiles: Add libfdt to the i386 and to the riscv64 container
No need to recompile the dtc submodule here again and again, we can use the pre-built binary from the distribution instead. (And this will also help in case we finally get rid of the dtc submodule in QEMU one day) Message-Id: <20230124143824.844040-1-th...@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- tests/docker/dockerfiles/debian-riscv64-cross.docker | 1 + tests/docker/dockerfiles/fedora-i386-cross.docker| 1 + 2 files changed, 2 insertions(+) diff --git a/tests/docker/dockerfiles/debian-riscv64-cross.docker b/tests/docker/dockerfiles/debian-riscv64-cross.docker index 9715791e0b..3daf93968a 100644 --- a/tests/docker/dockerfiles/debian-riscv64-cross.docker +++ b/tests/docker/dockerfiles/debian-riscv64-cross.docker @@ -42,6 +42,7 @@ RUN apt update && \ apt install -y --no-install-recommends \ gcc-riscv64-linux-gnu \ libc6-dev-riscv64-cross \ + libfdt-dev:riscv64 \ libffi-dev:riscv64 \ libglib2.0-dev:riscv64 \ libpixman-1-dev:riscv64 diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker index 7eec648d2d..f58b64dc3e 100644 --- a/tests/docker/dockerfiles/fedora-i386-cross.docker +++ b/tests/docker/dockerfiles/fedora-i386-cross.docker @@ -9,6 +9,7 @@ ENV PACKAGES \ findutils \ gcc \ git \ +libfdt-devel.i686 \ libffi-devel.i686 \ libselinux-devel.i686 \ libtasn1-devel.i686 \ -- 2.31.1
[PULL 10/27] qemu/bswap: Replace bswapXXs() by compiler __builtin_bswap()
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2023063147.71761-3-phi...@linaro.org>
Signed-off-by: Thomas Huth
---
include/qemu/bswap.h | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index ca2b4c3f15..d2dafdc54c 100644
--- a/include/qemu/bswap.h
+++ b/include/qemu/bswap.h
@@ -50,29 +50,31 @@ static inline uint64_t bswap64(uint64_t x)
static inline void bswap16s(uint16_t *s)
{
-*s = bswap16(*s);
+*s = __builtin_bswap16(*s);
}
static inline void bswap32s(uint32_t *s)
{
-*s = bswap32(*s);
+*s = __builtin_bswap32(*s);
}
static inline void bswap64s(uint64_t *s)
{
-*s = bswap64(*s);
+*s = __builtin_bswap64(*s);
}
#if HOST_BIG_ENDIAN
#define be_bswap(v, size) (v)
-#define le_bswap(v, size) glue(bswap, size)(v)
+#define le_bswap(v, size) glue(__builtin_bswap, size)(v)
#define be_bswaps(v, size)
-#define le_bswaps(p, size) do { *p = glue(bswap, size)(*p); } while(0)
+#define le_bswaps(p, size) \
+do { *p = glue(__builtin_bswap, size)(*p); } while (0)
#else
#define le_bswap(v, size) (v)
-#define be_bswap(v, size) glue(bswap, size)(v)
+#define be_bswap(v, size) glue(__builtin_bswap, size)(v)
#define le_bswaps(v, size)
-#define be_bswaps(p, size) do { *p = glue(bswap, size)(*p); } while(0)
+#define be_bswaps(p, size) \
+do { *p = glue(__builtin_bswap, size)(*p); } while (0)
#endif
/**
--
2.31.1
[PULL 17/27] tests/tcg: Do not build/run TCG tests if TCG is disabled
From: Fabiano Rosas The tests under tests/tcg depend on the TCG accelerator. Do not build them if --disable-tcg was given in the configure line. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20230120184825.31626-7-faro...@suse.de> Signed-off-by: Thomas Huth --- configure | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configure b/configure index 9e407ce2e3..64960c6000 100755 --- a/configure +++ b/configure @@ -2483,7 +2483,11 @@ for target in $target_list; do tcg_tests_targets="$tcg_tests_targets $target" fi done -echo "TCG_TESTS_TARGETS=$tcg_tests_targets" >> config-host.mak) + +if test "$tcg" = "enabled"; then +echo "TCG_TESTS_TARGETS=$tcg_tests_targets" >> config-host.mak +fi +) if test "$skip_meson" = no; then cross="config-meson.cross.new" -- 2.31.1
Re: [RFC PATCH] build: deprecate --enable-gprof builds and remove from CI
On 31/1/23 10:42, Alex Bennée wrote: As gprof relies on instrumentation you rarely get useful data compared to a real optimised build. Lets deprecate the build option and simplify the CI configuration as a result. Signed-off-by: Alex Bennée Cc: Thomas Huth --- docs/about/deprecated.rst | 14 ++ meson.build| 7 ++- .gitlab-ci.d/buildtest.yml | 19 --- meson_options.txt | 3 ++- 4 files changed, 26 insertions(+), 17 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v2] linux-user: Improve strace output of pread64() and pwrite64()
Le 30/01/2023 à 23:11, Helge Deller a écrit :
On 1/30/23 10:26, Laurent Vivier wrote:
Le 27/01/2023 à 21:58, Helge Deller a écrit :
Make the strace look nicer for those two syscalls.
Signed-off-by: Helge Deller
---
v2: Use regpairs_aligned() and target_offset64(), noticed by Laurent Vivier
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 82dc1a1e20..379536f5c9 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -3824,6 +3824,25 @@ print_rlimit64(abi_ulong rlim_addr, int last)
}
}
+#if defined(TARGET_NR_pread64) || defined(TARGET_NR_pwrite64)
+static void
+print_preadwrite64(CPUArchState *cpu_env, const struct syscallname *name,
+ abi_long arg0, abi_long arg1, abi_long arg2,
+ abi_long arg3, abi_long arg4, abi_long arg5)
+{
+ if (regpairs_aligned(cpu_env, TARGET_NR_pread64)) {
+ arg3 = arg4;
+ arg4 = arg5;
+ }
+ print_syscall_prologue(name);
+ print_raw_param("%d", arg0, 0);
+ print_pointer(arg1, 0);
+ print_raw_param("%d", arg2, 0);
+ qemu_log("%lld", (long long)target_offset64(arg3, arg4));
better to use:
print_raw_param("%" PRIu64, target_offset64(arg3, arg4), 1);
I thought of that as well, but that won't work, as print_raw_param()
takes an "abi_long" value, which is just a 32-bit value on 32-bit targets.
See print_rlimit64(), it's used there with qemu_log() as well.
Yes, you're right.
But even with qemu_log() I would prefer you use "%"PRIu64 rather than %lld.
Or better define a print_raw_param64() (or similar) and update print_fallocate(), print_truncate64()
and print_ftruncate64().
Thanks,
Laurent
[PATCH v2 14/20] hw/i386/pc_q35: Allow for setting properties before realizing TYPE_ICH9_LPC_DEVICE
This is a preparation to make the next patch cleaner. Signed-off-by: Bernhard Beschow --- hw/i386/pc_q35.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index fab8e57913..27a1fe351d 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -232,10 +232,11 @@ static void pc_q35_init(MachineState *machine) /* pci */ sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), _fatal); host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); + /* create ISA bus */ -lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, - ICH9_LPC_FUNC), true, - TYPE_ICH9_LPC_DEVICE); +lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, +TYPE_ICH9_LPC_DEVICE); +pci_realize_and_unref(lpc, host_bus, _fatal); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, -- 2.39.1
[PATCH v2 00/20] PC and ICH9 cleanups
This series contains some cleanups I came across when working on the PC
machines. It consists of reducing the usage of global variables and
eliminating some redundancies.
The ICH9 cleanups include further QOM'ification, making it more self-contained,
and reducing its x86/pc dependencies.
Testing done:
* `make check`
' `make check-avocado`
* `qemu-system-x86_64 -M q35 -m 2G -cdrom \
manjaro-kde-21.3.2-220704-linux515.iso`
* `qemu-system-x86_64 -M pc -m 2G -cdrom manjaro-kde-21.3.2-220704-linux515.iso`
v2:
* Factor out 'hw/i386/pc_q35: Reuse machine parameter' from 'hw/i386/pc_q35:
Resolve redundant q35_host variable' (Zoltan)
* Lower type of phb to Object in 'hw/i386/pc_q35: Resolve redundant q35_host
variable' (Zoltan)
* Add ICH9 cleanups
Bernhard Beschow (20):
hw/pci-host/i440fx: Inline sysbus_add_io()
hw/pci-host/q35: Inline sysbus_add_io()
hw/i386/pc_q35: Reuse machine parameter
hw/i386/pc_q35: Resolve redundant q35_host variable
hw/i386/pc_{q35,piix}: Reuse MachineClass::desc as SMB product name
hw/i386/pc_{q35,piix}: Minimize usage of get_system_memory()
hw/i386/pc: Initialize ram_memory variable directly
hw/i386/ich9: Rename Q35_MASK to ICH9_MASK
hw/isa/lpc_ich9: Unexport PIRQ functions
hw/isa/lpc_ich9: Eliminate ICH9LPCState::isa_bus
hw/isa/lpc_ich9: Reuse memory and io address space of PCI bus
hw/i2c/smbus_ich9: Move ich9_smb_set_irq() in front of
ich9_smbus_realize()
hw/i2c/smbus_ich9: Inline ich9_smb_init() and remove it
hw/i386/pc_q35: Allow for setting properties before realizing
TYPE_ICH9_LPC_DEVICE
hw/isa/lpc_ich9: Connect pm stuff to lpc internally
hw/isa/lpc_ich9: Remove redundant ich9_lpc_reset() invocation
hw/i386/ich9: Remove redundant GSI_NUM_PINS
hw: Move ioapic*.h to intc/
hw/i386/ich9: Clean up includes
hw: Move ich9.h to southbridge/
MAINTAINERS | 2 +
include/hw/acpi/ich9.h | 6 +-
include/hw/i386/pc.h| 1 -
include/hw/i386/x86.h | 3 +-
include/hw/{i386 => intc}/ioapic.h | 6 +-
include/hw/{i386 => intc}/ioapic_internal.h | 8 +--
include/hw/{i386 => southbridge}/ich9.h | 35 --
hw/acpi/ich9.c | 10 +--
hw/acpi/ich9_tco.c | 2 +-
hw/i2c/smbus_ich9.c | 39 +--
hw/i386/acpi-build.c| 3 +-
hw/i386/kvm/ioapic.c| 3 +-
hw/i386/pc.c| 8 +--
hw/i386/pc_piix.c | 8 +--
hw/i386/pc_q35.c| 73 ++---
hw/intc/apic.c | 2 +-
hw/intc/ioapic.c| 4 +-
hw/intc/ioapic_common.c | 4 +-
hw/isa/lpc_ich9.c | 40 +--
hw/pci-bridge/i82801b11.c | 2 +-
hw/pci-host/i440fx.c| 5 +-
hw/pci-host/q35.c | 6 +-
target/i386/whpx/whpx-all.c | 2 +-
tests/qtest/tco-test.c | 2 +-
24 files changed, 127 insertions(+), 147 deletions(-)
rename include/hw/{i386 => intc}/ioapic.h (93%)
rename include/hw/{i386 => intc}/ioapic_internal.h (96%)
rename include/hw/{i386 => southbridge}/ich9.h (91%)
--
2.39.1
[PATCH v2 18/20] hw: Move ioapic*.h to intc/
The ioapic sources reside in hw/intc already. Move the headers there as
well.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 1 +
include/hw/i386/x86.h | 2 +-
include/hw/{i386 => intc}/ioapic.h | 6 +++---
include/hw/{i386 => intc}/ioapic_internal.h | 8
hw/i386/kvm/ioapic.c| 3 +--
hw/i386/pc.c| 2 +-
hw/i386/pc_q35.c| 2 +-
hw/intc/apic.c | 2 +-
hw/intc/ioapic.c| 4 ++--
hw/intc/ioapic_common.c | 4 ++--
target/i386/whpx/whpx-all.c | 2 +-
11 files changed, 18 insertions(+), 18 deletions(-)
rename include/hw/{i386 => intc}/ioapic.h (93%)
rename include/hw/{i386 => intc}/ioapic_internal.h (96%)
diff --git a/MAINTAINERS b/MAINTAINERS
index c581c11a64..f96e86c57b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1703,6 +1703,7 @@ F: include/hw/char/parallel.h
F: include/hw/dma/i8257.h
F: include/hw/i2c/pm_smbus.h
F: include/hw/input/i8042.h
+F: include/hw/intc/ioapic*
F: include/hw/isa/i8259_internal.h
F: include/hw/isa/superio.h
F: include/hw/timer/hpet.h
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 0becd1460e..7eeac10e74 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -23,8 +23,8 @@
#include "hw/i386/topology.h"
#include "hw/boards.h"
#include "hw/nmi.h"
+#include "hw/intc/ioapic.h"
#include "hw/isa/isa.h"
-#include "hw/i386/ioapic.h"
#include "qom/object.h"
struct X86MachineClass {
diff --git a/include/hw/i386/ioapic.h b/include/hw/intc/ioapic.h
similarity index 93%
rename from include/hw/i386/ioapic.h
rename to include/hw/intc/ioapic.h
index ef37b8a9fd..aa122e25e3 100644
--- a/include/hw/i386/ioapic.h
+++ b/include/hw/intc/ioapic.h
@@ -17,8 +17,8 @@
* License along with this library; if not, see
[PATCH v2 16/20] hw/isa/lpc_ich9: Remove redundant ich9_lpc_reset() invocation
ich9_lpc_reset() is the dc->reset callback which is called
automatically. No need to call it explicitly during k->realize.
Signed-off-by: Bernhard Beschow
---
hw/isa/lpc_ich9.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 7d21857d53..b2842f2743 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -57,8 +57,6 @@
/*/
/* ICH9 LPC PCI to ISA bridge */
-static void ich9_lpc_reset(DeviceState *qdev);
-
/* chipset configuration register
* to access chipset configuration registers, pci_[sg]et_{byte, word, long}
* are used.
@@ -439,8 +437,6 @@ static void ich9_lpc_pm_init(ICH9LPCState *lpc)
sizeof lpc->smi_features_ok,
true);
}
-
-ich9_lpc_reset(DEVICE(lpc));
}
/* APM */
--
2.39.1
[PATCH v2 10/20] hw/isa/lpc_ich9: Eliminate ICH9LPCState::isa_bus
By using qdev_get_child_bus() we can eliminate ICH9LPCState::isa_bus and
spare the ich9_lpc variable in pc_q35, too.
Signed-off-by: Bernhard Beschow
---
include/hw/i386/ich9.h | 3 ---
hw/i386/pc_q35.c | 4 +---
hw/isa/lpc_ich9.c | 5 +
3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 921e4c7ef6..05464f6965 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -1,7 +1,6 @@
#ifndef HW_ICH9_H
#define HW_ICH9_H
-#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "hw/i386/pc.h"
#include "hw/isa/apm.h"
@@ -64,8 +63,6 @@ struct ICH9LPCState {
* triggers feature lockdown */
uint64_t smi_negotiated_features; /* guest-invisible, host endian */
-/* isa bus */
-ISABus *isa_bus;
MemoryRegion rcrb_mem; /* root complex register block */
Notifier machine_ready;
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 83e4fb7868..a4d5c89409 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -132,7 +132,6 @@ static void pc_q35_init(MachineState *machine)
GSIState *gsi_state;
ISABus *isa_bus;
int i;
-ICH9LPCState *ich9_lpc;
PCIDevice *ahci;
ram_addr_t lowmem;
DriveInfo *hd[MAX_SATA_PORTS];
@@ -262,12 +261,11 @@ static void pc_q35_init(MachineState *machine)
/* irq lines */
gsi_state = pc_gsi_create(>gsi, pcmc->pci_enabled);
-ich9_lpc = ICH9_LPC_DEVICE(lpc);
lpc_dev = DEVICE(lpc);
for (i = 0; i < GSI_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
-isa_bus = ich9_lpc->isa_bus;
+isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
pc_i8259_create(isa_bus, gsi_state->i8259_irq);
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index b444faacd2..9ab966ef88 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -710,8 +710,6 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
memory_region_init_io(>rcrb_mem, OBJECT(d), _mmio_ops, lpc,
"lpc-rcrb-mmio", ICH9_CC_SIZE);
-lpc->isa_bus = isa_bus;
-
ich9_cc_init(lpc);
apm_init(d, >apm, ich9_apm_ctrl_changed, lpc);
@@ -819,8 +817,7 @@ static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml
*scope)
{
Aml *field;
BusChild *kid;
-ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
-BusState *bus = BUS(s->isa_bus);
+BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
Aml *sb_scope = aml_scope("\\_SB");
/* ICH9 PCI to ISA irq remapping */
--
2.39.1
[PATCH v2 04/20] hw/i386/pc_q35: Resolve redundant q35_host variable
The variable is redundant to "phb" and is never used by its real type.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_q35.c | 26 --
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 351ef25f69..88324af91f 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -118,8 +118,7 @@ static void pc_q35_init(MachineState *machine)
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
X86MachineState *x86ms = X86_MACHINE(machine);
-Q35PCIHost *q35_host;
-PCIHostState *phb;
+Object *phb;
PCIBus *host_bus;
PCIDevice *lpc;
DeviceState *lpc_dev;
@@ -206,10 +205,10 @@ static void pc_q35_init(MachineState *machine)
}
/* create pci host bus */
-q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
+phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE));
if (pcmc->pci_enabled) {
-pci_hole64_size = object_property_get_uint(OBJECT(q35_host),
+pci_hole64_size = object_property_get_uint(phb,
PCI_HOST_PROP_PCI_HOLE64_SIZE,
_abort);
}
@@ -218,23 +217,22 @@ static void pc_q35_init(MachineState *machine)
pc_memory_init(pcms, get_system_memory(), rom_memory, _memory,
pci_hole64_size);
-object_property_add_child(OBJECT(machine), "q35", OBJECT(q35_host));
-object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
+object_property_add_child(OBJECT(machine), "q35", phb);
+object_property_set_link(phb, MCH_HOST_PROP_RAM_MEM,
OBJECT(ram_memory), NULL);
-object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM,
+object_property_set_link(phb, MCH_HOST_PROP_PCI_MEM,
OBJECT(pci_memory), NULL);
-object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM,
+object_property_set_link(phb, MCH_HOST_PROP_SYSTEM_MEM,
OBJECT(get_system_memory()), NULL);
-object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM,
+object_property_set_link(phb, MCH_HOST_PROP_IO_MEM,
OBJECT(system_io), NULL);
-object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE,
+object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE,
x86ms->below_4g_mem_size, NULL);
-object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE,
+object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE,
x86ms->above_4g_mem_size, NULL);
/* pci */
-sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), _fatal);
-phb = PCI_HOST_BRIDGE(q35_host);
-host_bus = phb->bus;
+sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), _fatal);
+host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0"));
/* create ISA bus */
lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
ICH9_LPC_FUNC), true,
--
2.39.1
[PATCH v2 08/20] hw/i386/ich9: Rename Q35_MASK to ICH9_MASK
The Q35_MASK macro is already defined by TYPE_Q35_HOST_DEVICE, so let
TYPE_ICH9_LPC_DEVICE have its own one to prevent potential name clash.
Signed-off-by: Bernhard Beschow
---
include/hw/i386/ich9.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 222781e8b9..36e0ccd16a 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -75,7 +75,7 @@ struct ICH9LPCState {
qemu_irq gsi[GSI_NUM_PINS];
};
-#define Q35_MASK(bit, ms_bit, ls_bit) \
+#define ICH9_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
/* ICH9: Chipset Configuration Registers */
@@ -137,13 +137,13 @@ struct ICH9LPCState {
#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
#define ICH9_LPC_PMBASE 0x40
-#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
+#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7)
#define ICH9_LPC_PMBASE_RTE 0x1
#define ICH9_LPC_PMBASE_DEFAULT 0x1
#define ICH9_LPC_ACPI_CTRL 0x44
#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
-#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
+#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0)
#define ICH9_LPC_ACPI_CTRL_90x0
#define ICH9_LPC_ACPI_CTRL_10 0x1
#define ICH9_LPC_ACPI_CTRL_11 0x2
@@ -162,7 +162,7 @@ struct ICH9LPCState {
#define ICH9_LPC_PIRQH_ROUT 0x6b
#define ICH9_LPC_PIRQ_ROUT_IRQEN0x80
-#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
+#define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0)
#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
#define ICH9_LPC_GEN_PMCON_10xa0
@@ -172,7 +172,7 @@ struct ICH9LPCState {
#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
#define ICH9_LPC_RCBA 0xf0
-#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
+#define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14)
#define ICH9_LPC_RCBA_EN0x1
#define ICH9_LPC_RCBA_DEFAULT 0x0
--
2.39.1
[PATCH v2 02/20] hw/pci-host/q35: Inline sysbus_add_io()
sysbus_add_io() just wraps memory_region_add_subregion() while also obscuring where the memory is attached. So use memory_region_add_subregion() directly and attach it to the existing memory region s->mch.address_space_io which is set as an alias to get_system_io() by the q35 machine. Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 26390863d6..fa05844319 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -50,10 +50,12 @@ static void q35_host_realize(DeviceState *dev, Error **errp) Q35PCIHost *s = Q35_HOST_DEVICE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); -sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, >conf_mem); +memory_region_add_subregion(s->mch.address_space_io, +MCH_HOST_BRIDGE_CONFIG_ADDR, >conf_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); -sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, >data_mem); +memory_region_add_subregion(s->mch.address_space_io, +MCH_HOST_BRIDGE_CONFIG_DATA, >data_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); /* register q35 0xcf8 port as coalesced pio */ -- 2.39.1
[PATCH v2 07/20] hw/i386/pc: Initialize ram_memory variable directly
Going through pc_memory_init() seems quite complicated for a simple
assignment.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 2 --
hw/i386/pc_piix.c| 4 ++--
hw/i386/pc_q35.c | 5 ++---
4 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 88a120bc23..5331b9a5c5 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -163,7 +163,6 @@ void xen_load_linux(PCMachineState *pcms);
void pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
MemoryRegion *rom_memory,
-MemoryRegion **ram_memory,
uint64_t pci_hole64_size);
uint64_t pc_pci_hole64_start(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 6e592bd969..8898cc9961 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -936,7 +936,6 @@ static hwaddr pc_max_used_gpa(PCMachineState *pcms,
uint64_t pci_hole64_size)
void pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
MemoryRegion *rom_memory,
-MemoryRegion **ram_memory,
uint64_t pci_hole64_size)
{
int linux_boot, i;
@@ -994,7 +993,6 @@ void pc_memory_init(PCMachineState *pcms,
* Split single memory region and use aliases to address portions of it,
* done for backwards compatibility with older qemus.
*/
-*ram_memory = machine->ram;
ram_below_4g = g_malloc(sizeof(*ram_below_4g));
memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
0, x86ms->below_4g_mem_size);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 5bde4533cc..00ba725656 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -143,6 +143,7 @@ static void pc_init1(MachineState *machine,
if (xen_enabled()) {
xen_hvm_init_pc(pcms, _memory);
} else {
+ram_memory = machine->ram;
if (!pcms->max_ram_below_4g) {
pcms->max_ram_below_4g = 0xe000; /* default: 3.5G */
}
@@ -205,8 +206,7 @@ static void pc_init1(MachineState *machine,
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
-pc_memory_init(pcms, system_memory,
- rom_memory, _memory, hole64_size);
+pc_memory_init(pcms, system_memory, rom_memory, hole64_size);
} else {
pc_system_flash_cleanup_unused(pcms);
if (machine->kernel_filename != NULL) {
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 3ae2f41cf3..50fa5aa9bc 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -128,7 +128,7 @@ static void pc_q35_init(MachineState *machine)
MemoryRegion *system_io = get_system_io();
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
-MemoryRegion *ram_memory;
+MemoryRegion *ram_memory = machine->ram;
GSIState *gsi_state;
ISABus *isa_bus;
int i;
@@ -215,8 +215,7 @@ static void pc_q35_init(MachineState *machine)
}
/* allocate ram and load rom/bios */
-pc_memory_init(pcms, system_memory, rom_memory, _memory,
- pci_hole64_size);
+pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size);
object_property_add_child(OBJECT(machine), "q35", phb);
object_property_set_link(phb, MCH_HOST_PROP_RAM_MEM,
--
2.39.1
Re: [PATCH v2] linux-user: Show 4th argument of rt_sigprocmask() in strace
Le 30/01/2023 à 23:20, Helge Deller a écrit :
Add output for the missing 4th parameter (size_t sigsetsize).
Signed-off-by: Helge Deller
---
v2: Use %u instead of %d, as suggested by Laurent Vivier
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 3157e4b420..f0f6ada8cb 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -3146,7 +3146,8 @@ print_rt_sigprocmask(CPUArchState *cpu_env, const struct
syscallname *name,
}
qemu_log("%s,", how);
print_pointer(arg1, 0);
-print_pointer(arg2, 1);
+print_pointer(arg2, 0);
+print_raw_param("%u", arg3, 1);
print_syscall_epilogue(name);
}
#endif
Applied to my linux-user-for-8.0 branch.
Thanks,
Laurent
[PATCH v2 05/20] hw/i386/pc_{q35, piix}: Reuse MachineClass::desc as SMB product name
No need to repeat the descriptions.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index df64dd8dcc..ee9d9a4175 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -197,7 +197,7 @@ static void pc_init1(MachineState *machine,
if (pcmc->smbios_defaults) {
MachineClass *mc = MACHINE_GET_CLASS(machine);
/* These values are guest ABI, do not change */
-smbios_set_defaults("QEMU", "Standard PC (i440FX + PIIX, 1996)",
+smbios_set_defaults("QEMU", mc->desc,
mc->name, pcmc->smbios_legacy_mode,
pcmc->smbios_uuid_encoded,
pcms->smbios_entry_point_type);
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 88324af91f..bc4fd06c1e 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -198,7 +198,7 @@ static void pc_q35_init(MachineState *machine)
if (pcmc->smbios_defaults) {
/* These values are guest ABI, do not change */
-smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
+smbios_set_defaults("QEMU", mc->desc,
mc->name, pcmc->smbios_legacy_mode,
pcmc->smbios_uuid_encoded,
pcms->smbios_entry_point_type);
--
2.39.1
Re: [PATCH 01/18] vfio/migration: Add VFIO migration pre-copy support
On 27/01/2023 1:52, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Thu, 26 Jan 2023 20:49:31 +0200
Avihai Horon wrote:
Pre-copy support allows the VFIO device data to be transferred while the
VM is running. This helps to accommodate VFIO devices that have a large
amount of data that needs to be transferred, and it can reduce migration
downtime.
Pre-copy support is optional in VFIO migration protocol v2.
Implement pre-copy of VFIO migration protocol v2 and use it for devices
that support it. Full description of it can be found here [1].
[1]
https://lore.kernel.org/kvm/20221206083438.37807-3-yish...@nvidia.com/
Signed-off-by: Avihai Horon
---
docs/devel/vfio-migration.rst | 29 ++---
include/hw/vfio/vfio-common.h | 3 +
hw/vfio/common.c | 8 ++-
hw/vfio/migration.c | 112 --
hw/vfio/trace-events | 5 +-
5 files changed, 140 insertions(+), 17 deletions(-)
diff --git a/docs/devel/vfio-migration.rst b/docs/devel/vfio-migration.rst
index 1d50c2fe5f..51f5e1a537 100644
--- a/docs/devel/vfio-migration.rst
+++ b/docs/devel/vfio-migration.rst
@@ -7,12 +7,14 @@ the guest is running on source host and restoring this saved
state on the
destination host. This document details how saving and restoring of VFIO
devices is done in QEMU.
-Migration of VFIO devices currently consists of a single stop-and-copy phase.
-During the stop-and-copy phase the guest is stopped and the entire VFIO device
-data is transferred to the destination.
-
-The pre-copy phase of migration is currently not supported for VFIO devices.
-Support for VFIO pre-copy will be added later on.
+Migration of VFIO devices consists of two phases: the optional pre-copy phase,
+and the stop-and-copy phase. The pre-copy phase is iterative and allows to
+accommodate VFIO devices that have a large amount of data that needs to be
+transferred. The iterative pre-copy phase of migration allows for the guest to
+continue whilst the VFIO device state is transferred to the destination, this
+helps to reduce the total downtime of the VM. VFIO devices can choose to skip
+the pre-copy phase of migration by not reporting the VFIO_MIGRATION_PRE_COPY
+flag in VFIO_DEVICE_FEATURE_MIGRATION ioctl.
A detailed description of the UAPI for VFIO device migration can be found in
the comment for the ``vfio_device_mig_state`` structure in the header file
@@ -29,6 +31,12 @@ VFIO implements the device hooks for the iterative approach
as follows:
driver, which indicates the amount of data that the vendor driver has yet to
save for the VFIO device.
+* An ``is_active_iterate`` function that indicates ``save_live_iterate`` is
+ active only if the VFIO device is in pre-copy states.
+
+* A ``save_live_iterate`` function that reads the VFIO device's data from the
+ vendor driver during iterative phase.
+
* A ``save_state`` function to save the device config space if it is present.
* A ``save_live_complete_precopy`` function that sets the VFIO device in
@@ -91,8 +99,10 @@ Flow of state changes during Live migration
===
Below is the flow of state change during live migration.
-The values in the brackets represent the VM state, the migration state, and
+The values in the parentheses represent the VM state, the migration state, and
the VFIO device state, respectively.
+The text in the square brackets represents the flow if the VFIO device supports
+pre-copy.
Live migration save path
@@ -104,11 +114,12 @@ Live migration save path
|
migrate_init spawns migration_thread
Migration thread then calls each device's .save_setup()
- (RUNNING, _SETUP, _RUNNING)
+ (RUNNING, _SETUP, _RUNNING [_PRE_COPY])
|
- (RUNNING, _ACTIVE, _RUNNING)
+ (RUNNING, _ACTIVE, _RUNNING [_PRE_COPY])
If device is active, get pending_bytes by .save_live_pending()
If total pending_bytes >= threshold_size, call .save_live_iterate()
+ [Data of VFIO device for pre-copy phase is copied]
Iterate till total pending bytes converge and are less than threshold
|
On migration completion, vCPU stops and calls .save_live_complete_precopy
for
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index 5f8e7a02fe..88c2194fb9 100644
--- a/include/hw/vfio/vfio-common.h
+++ b/include/hw/vfio/vfio-common.h
@@ -67,7 +67,10 @@ typedef struct VFIOMigration {
int data_fd;
void *data_buffer;
size_t data_buffer_size;
+uint64_t mig_flags;
uint64_t stop_copy_size;
+uint64_t precopy_init_size;
+uint64_t precopy_dirty_size;
} VFIOMigration;
typedef struct VFIOAddressSpace {
diff --git
[PATCH v9 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
---
target/riscv/cpu.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc75ca7667..7181b34f86 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] = {
"reserved"
};
-static void register_cpu_props(DeviceState *dev);
+static void register_cpu_props(Object *obj);
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
{
@@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
set_priv_version(env, PRIV_VERSION_1_12_0);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
}
#if defined(TARGET_RISCV64)
@@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj)
CPURISCVState *env = _CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV64, 0);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
}
@@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj)
CPURISCVState *env = _CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV128, 0);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
}
@@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj)
CPURISCVState *env = _CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV32, 0);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
}
@@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, 0);
#endif
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
}
#endif
@@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static void register_cpu_props(DeviceState *dev)
+static void register_cpu_props(Object *obj)
{
Property *prop;
+DeviceState *dev = DEVICE(obj);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
qdev_property_add_static(dev, prop);
--
2.37.2
Re: [PATCH 00/17] audio: improve callback interface for audio frontends
Hi On Sun, Jan 15, 2023 at 5:10 PM Volker Rümelin wrote: > > Based-on: <3b1404eb-a7c5-f64c-3e47-1397c54c4...@t-online.de> > ([PATCH 00/11] audio: more improvements) > Something didn't work with patchew (https://patchew.org/QEMU/61bd351f-0683-7f58-b746-66c9578a7...@t-online.de/). If you could rebase/resend, or share git branch that would be great. Thanks -- Marc-André Lureau
Re: [PATCH v9 03/12] parallels: Fix image_end_offset and data_end after out-of-image check
On 1/31/23 11:27, Alexander Ivanov wrote:
Set data_end to the end of the last cluster inside the image. In such a
way we can be sure that corrupted offsets in the BAT can't affect on the
image size. If there are no allocated clusters set image_end_offset by
data_end.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/block/parallels.c b/block/parallels.c
index 436b36bbd9..2ed7cca249 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -488,7 +488,13 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
}
}
-res->image_end_offset = high_off + s->cluster_size;
+if (high_off == 0) {
+res->image_end_offset = s->data_end << BDRV_SECTOR_BITS;
+} else {
+res->image_end_offset = high_off + s->cluster_size;
+s->data_end = res->image_end_offset >> BDRV_SECTOR_BITS;
+}
+
if (size > res->image_end_offset) {
int64_t count;
count = DIV_ROUND_UP(size - res->image_end_offset, s->cluster_size);
Reviewed-by: Denis V. Lunev
[PATCH v9 11/12] parallels: Replace qemu_co_mutex_lock by WITH_QEMU_LOCK_GUARD
Replace the way we use mutex in parallels_co_check() for simplier
and less error prone code.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
---
block/parallels.c | 33 ++---
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index 23c9ba7b7b..e4faa14add 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -556,30 +556,25 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
BDRVParallelsState *s = bs->opaque;
int ret;
-qemu_co_mutex_lock(>lock);
+WITH_QEMU_LOCK_GUARD(>lock) {
+parallels_check_unclean(bs, res, fix);
-parallels_check_unclean(bs, res, fix);
+ret = parallels_check_outside_image(bs, res, fix);
+if (ret < 0) {
+return ret;
+}
-ret = parallels_check_outside_image(bs, res, fix);
-if (ret < 0) {
-goto out;
-}
+ret = parallels_check_leak(bs, res, fix);
+if (ret < 0) {
+return ret;
+}
-ret = parallels_check_leak(bs, res, fix);
-if (ret < 0) {
-goto out;
+parallels_collect_statistics(bs, res, fix);
}
-parallels_collect_statistics(bs, res, fix);
-
-out:
-qemu_co_mutex_unlock(>lock);
-
-if (ret == 0) {
-ret = bdrv_co_flush(bs);
-if (ret < 0) {
-res->check_errors++;
-}
+ret = bdrv_co_flush(bs);
+if (ret < 0) {
+res->check_errors++;
}
return ret;
--
2.34.1
[PATCH v9 07/12] parallels: Move check of cluster outside image to a separate function
We will add more and more checks so we need a better code structure in
parallels_co_check. Let each check performs in a separate loop in a
separate helper.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 81 ++-
1 file changed, 52 insertions(+), 29 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index 02fbaee1f2..f9acee1fa8 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -438,14 +438,13 @@ static void parallels_check_unclean(BlockDriverState *bs,
}
}
-static int coroutine_fn parallels_co_check(BlockDriverState *bs,
- BdrvCheckResult *res,
- BdrvCheckMode fix)
+static int parallels_check_outside_image(BlockDriverState *bs,
+ BdrvCheckResult *res,
+ BdrvCheckMode fix)
{
BDRVParallelsState *s = bs->opaque;
-int64_t size, prev_off, high_off;
-int ret = 0;
uint32_t i;
+int64_t off, high_off, size;
size = bdrv_getlength(bs->file->bs);
if (size < 0) {
@@ -453,23 +452,9 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
return size;
}
-qemu_co_mutex_lock(>lock);
-
-parallels_check_unclean(bs, res, fix);
-
-res->bfi.total_clusters = s->bat_size;
-res->bfi.compressed_clusters = 0; /* compression is not supported */
-
high_off = 0;
-prev_off = 0;
for (i = 0; i < s->bat_size; i++) {
-int64_t off = bat2sect(s, i) << BDRV_SECTOR_BITS;
-if (off == 0) {
-prev_off = 0;
-continue;
-}
-
-/* cluster outside the image */
+off = bat2sect(s, i) << BDRV_SECTOR_BITS;
if (off > size) {
fprintf(stderr, "%s cluster %u is outside image\n",
fix & BDRV_FIX_ERRORS ? "Repairing" : "ERROR", i);
@@ -478,19 +463,11 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
parallels_set_bat_entry(s, i, 0);
res->corruptions_fixed++;
}
-prev_off = 0;
continue;
}
-
-res->bfi.allocated_clusters++;
-if (off > high_off) {
+if (high_off < off) {
high_off = off;
}
-
-if (prev_off != 0 && (prev_off + s->cluster_size) != off) {
-res->bfi.fragmented_clusters++;
-}
-prev_off = off;
}
if (high_off == 0) {
@@ -500,6 +477,52 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
s->data_end = res->image_end_offset >> BDRV_SECTOR_BITS;
}
+return 0;
+}
+
+static int coroutine_fn parallels_co_check(BlockDriverState *bs,
+ BdrvCheckResult *res,
+ BdrvCheckMode fix)
+{
+BDRVParallelsState *s = bs->opaque;
+int64_t size, prev_off;
+int ret;
+uint32_t i;
+
+size = bdrv_getlength(bs->file->bs);
+if (size < 0) {
+res->check_errors++;
+return size;
+}
+
+qemu_co_mutex_lock(>lock);
+
+parallels_check_unclean(bs, res, fix);
+
+ret = parallels_check_outside_image(bs, res, fix);
+if (ret < 0) {
+goto out;
+}
+
+res->bfi.total_clusters = s->bat_size;
+res->bfi.compressed_clusters = 0; /* compression is not supported */
+
+prev_off = 0;
+for (i = 0; i < s->bat_size; i++) {
+int64_t off = bat2sect(s, i) << BDRV_SECTOR_BITS;
+if (off == 0) {
+prev_off = 0;
+continue;
+}
+
+res->bfi.allocated_clusters++;
+
+if (prev_off != 0 && (prev_off + s->cluster_size) != off) {
+res->bfi.fragmented_clusters++;
+}
+prev_off = off;
+}
+
if (size > res->image_end_offset) {
int64_t count;
count = DIV_ROUND_UP(size - res->image_end_offset, s->cluster_size);
--
2.34.1
[PATCH v9 03/12] parallels: Fix image_end_offset and data_end after out-of-image check
Set data_end to the end of the last cluster inside the image. In such a
way we can be sure that corrupted offsets in the BAT can't affect on the
image size. If there are no allocated clusters set image_end_offset by
data_end.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/block/parallels.c b/block/parallels.c
index 436b36bbd9..2ed7cca249 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -488,7 +488,13 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
}
}
-res->image_end_offset = high_off + s->cluster_size;
+if (high_off == 0) {
+res->image_end_offset = s->data_end << BDRV_SECTOR_BITS;
+} else {
+res->image_end_offset = high_off + s->cluster_size;
+s->data_end = res->image_end_offset >> BDRV_SECTOR_BITS;
+}
+
if (size > res->image_end_offset) {
int64_t count;
count = DIV_ROUND_UP(size - res->image_end_offset, s->cluster_size);
--
2.34.1
[PATCH v9 08/12] parallels: Fix statistics calculation
Exclude out-of-image clusters from allocated and fragmented clusters
calculation.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/parallels.c b/block/parallels.c
index f9acee1fa8..7382c01191 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -510,7 +510,7 @@ static int coroutine_fn parallels_co_check(BlockDriverState
*bs,
prev_off = 0;
for (i = 0; i < s->bat_size; i++) {
int64_t off = bat2sect(s, i) << BDRV_SECTOR_BITS;
-if (off == 0) {
+if (off == 0 || off + s->cluster_size > res->image_end_offset) {
prev_off = 0;
continue;
}
--
2.34.1
[PATCH v9 00/11] parallels: Refactor the code of images checks and fix a bug
Fix image inflation when offset in BAT is out of image. Replace whole BAT syncing by flushing only dirty blocks. Move all the checks outside the main check function in separate functions Use WITH_QEMU_LOCK_GUARD for simplier code. Fix incorrect condition in out-of-image check. v9: 3: Add (high_off == 0) case handling. 7: Move res->image_end_offset setting to parallels_check_outside_image(). 8: Add a patch with a statistics calculation fix. 9: Remove redundant high_off calculation. 12: Change the condition to (off + s->cluster_size > size). v8: Rebase on the top of the current master branch. v7: 1,2: Fix string lengths in the commit messages. 3: Fix a typo in the commit message. v6: 1: Move the error check inside the loop. Move file size getting to the function beginning. Skip out-of-image offsets. 2: A new patch - don't let high_off be more than the end of the last cluster. 3: Set data_end without any condition. 7: Move data_end setting to parallels_check_outside_image(). 8: Remove s->data_end setting from parallels_check_leak(). Fix 'i' type. v5: 2: Change the way of data_end fixing. 6,7: Move data_end check to parallels_check_leak(). v4: 1: Move s->data_end fix to parallels_co_check(). Split the check in parallels_open() and the fix in parallels_co_check() to two patches. 2: A new patch - a part of the patch 1. Add a fix for data_end to parallels_co_check(). 3: Move offset convertation to parallels_set_bat_entry(). 4: Fix 'ret' rewriting by bdrv_co_flush() results. 7: Keep 'i' as uint32_t. v3: 1-8: Fix commit message. v2: 2: A new patch - a part of the splitted patch 2. 3: Patch order was changed so the replacement is done in parallels_co_check. Now we use a helper to set BAT entry and mark the block dirty. 4: Revert the condition with s->header_unclean. 5: Move unrelated helper parallels_set_bat_entry creation to a separate patch. 7: Move fragmentation counting code to this function too. 8: Fix an incorrect usage of WITH_QEMU_LOCK_GUARD. Alexander Ivanov (12): parallels: Out of image offset in BAT leads to image inflation parallels: Fix high_off calculation in parallels_co_check() parallels: Fix image_end_offset and data_end after out-of-image check parallels: create parallels_set_bat_entry_helper() to assign BAT value parallels: Use generic infrastructure for BAT writing in parallels_co_check() parallels: Move check of unclean image to a separate function parallels: Move check of cluster outside image to a separate function parallels: Fix statistics calculation parallels: Move check of leaks to a separate function parallels: Move statistic collection to a separate function parallels: Replace qemu_co_mutex_lock by WITH_QEMU_LOCK_GUARD parallels: Incorrect condition in out-of-image check block/parallels.c | 189 -- 1 file changed, 133 insertions(+), 56 deletions(-) -- 2.34.1
[PATCH v9 12/12] parallels: Incorrect condition in out-of-image check
All the offsets in the BAT must be lower than the file size.
Fix the check condition for correct check.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/parallels.c b/block/parallels.c
index e4faa14add..e469fe3f78 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -455,7 +455,7 @@ static int parallels_check_outside_image(BlockDriverState
*bs,
high_off = 0;
for (i = 0; i < s->bat_size; i++) {
off = bat2sect(s, i) << BDRV_SECTOR_BITS;
-if (off > size) {
+if (off + s->cluster_size > size) {
fprintf(stderr, "%s cluster %u is outside image\n",
fix & BDRV_FIX_ERRORS ? "Repairing" : "ERROR", i);
res->corruptions++;
--
2.34.1
[PATCH v9 10/12] parallels: Move statistic collection to a separate function
We will add more and more checks so we need a better code structure
in parallels_co_check. Let each check performs in a separate loop
in a separate helper.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/parallels.c | 52 +++
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index eb39db53ec..23c9ba7b7b 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -522,47 +522,55 @@ static int parallels_check_leak(BlockDriverState *bs,
return 0;
}
-static int coroutine_fn parallels_co_check(BlockDriverState *bs,
- BdrvCheckResult *res,
- BdrvCheckMode fix)
+static void parallels_collect_statistics(BlockDriverState *bs,
+ BdrvCheckResult *res,
+ BdrvCheckMode fix)
{
BDRVParallelsState *s = bs->opaque;
-int64_t prev_off;
-int ret;
+int64_t off, prev_off;
uint32_t i;
-qemu_co_mutex_lock(>lock);
-
-parallels_check_unclean(bs, res, fix);
-
-ret = parallels_check_outside_image(bs, res, fix);
-if (ret < 0) {
-goto out;
-}
-
-ret = parallels_check_leak(bs, res, fix);
-if (ret < 0) {
-goto out;
-}
-
res->bfi.total_clusters = s->bat_size;
res->bfi.compressed_clusters = 0; /* compression is not supported */
prev_off = 0;
for (i = 0; i < s->bat_size; i++) {
-int64_t off = bat2sect(s, i) << BDRV_SECTOR_BITS;
+off = bat2sect(s, i) << BDRV_SECTOR_BITS;
if (off == 0 || off + s->cluster_size > res->image_end_offset) {
prev_off = 0;
continue;
}
-res->bfi.allocated_clusters++;
-
if (prev_off != 0 && (prev_off + s->cluster_size) != off) {
res->bfi.fragmented_clusters++;
}
prev_off = off;
+res->bfi.allocated_clusters++;
}
+}
+
+static int coroutine_fn parallels_co_check(BlockDriverState *bs,
+ BdrvCheckResult *res,
+ BdrvCheckMode fix)
+{
+BDRVParallelsState *s = bs->opaque;
+int ret;
+
+qemu_co_mutex_lock(>lock);
+
+parallels_check_unclean(bs, res, fix);
+
+ret = parallels_check_outside_image(bs, res, fix);
+if (ret < 0) {
+goto out;
+}
+
+ret = parallels_check_leak(bs, res, fix);
+if (ret < 0) {
+goto out;
+}
+
+parallels_collect_statistics(bs, res, fix);
out:
qemu_co_mutex_unlock(>lock);
--
2.34.1
[PATCH v9 09/12] parallels: Move check of leaks to a separate function
We will add more and more checks so we need a better code structure
in parallels_co_check. Let each check performs in a separate loop
in a separate helper.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 85 ---
1 file changed, 50 insertions(+), 35 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index 7382c01191..eb39db53ec 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -480,14 +480,13 @@ static int parallels_check_outside_image(BlockDriverState
*bs,
return 0;
}
-static int coroutine_fn parallels_co_check(BlockDriverState *bs,
- BdrvCheckResult *res,
- BdrvCheckMode fix)
+static int parallels_check_leak(BlockDriverState *bs,
+BdrvCheckResult *res,
+BdrvCheckMode fix)
{
BDRVParallelsState *s = bs->opaque;
-int64_t size, prev_off;
+int64_t size;
int ret;
-uint32_t i;
size = bdrv_getlength(bs->file->bs);
if (size < 0) {
@@ -495,34 +494,6 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
return size;
}
-qemu_co_mutex_lock(>lock);
-
-parallels_check_unclean(bs, res, fix);
-
-ret = parallels_check_outside_image(bs, res, fix);
-if (ret < 0) {
-goto out;
-}
-
-res->bfi.total_clusters = s->bat_size;
-res->bfi.compressed_clusters = 0; /* compression is not supported */
-
-prev_off = 0;
-for (i = 0; i < s->bat_size; i++) {
-int64_t off = bat2sect(s, i) << BDRV_SECTOR_BITS;
-if (off == 0 || off + s->cluster_size > res->image_end_offset) {
-prev_off = 0;
-continue;
-}
-
-res->bfi.allocated_clusters++;
-
-if (prev_off != 0 && (prev_off + s->cluster_size) != off) {
-res->bfi.fragmented_clusters++;
-}
-prev_off = off;
-}
-
if (size > res->image_end_offset) {
int64_t count;
count = DIV_ROUND_UP(size - res->image_end_offset, s->cluster_size);
@@ -542,12 +513,57 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
if (ret < 0) {
error_report_err(local_err);
res->check_errors++;
-goto out;
+return ret;
}
res->leaks_fixed += count;
}
}
+return 0;
+}
+
+static int coroutine_fn parallels_co_check(BlockDriverState *bs,
+ BdrvCheckResult *res,
+ BdrvCheckMode fix)
+{
+BDRVParallelsState *s = bs->opaque;
+int64_t prev_off;
+int ret;
+uint32_t i;
+
+qemu_co_mutex_lock(>lock);
+
+parallels_check_unclean(bs, res, fix);
+
+ret = parallels_check_outside_image(bs, res, fix);
+if (ret < 0) {
+goto out;
+}
+
+ret = parallels_check_leak(bs, res, fix);
+if (ret < 0) {
+goto out;
+}
+
+res->bfi.total_clusters = s->bat_size;
+res->bfi.compressed_clusters = 0; /* compression is not supported */
+
+prev_off = 0;
+for (i = 0; i < s->bat_size; i++) {
+int64_t off = bat2sect(s, i) << BDRV_SECTOR_BITS;
+if (off == 0 || off + s->cluster_size > res->image_end_offset) {
+prev_off = 0;
+continue;
+}
+
+res->bfi.allocated_clusters++;
+
+if (prev_off != 0 && (prev_off + s->cluster_size) != off) {
+res->bfi.fragmented_clusters++;
+}
+prev_off = off;
+}
+
out:
qemu_co_mutex_unlock(>lock);
@@ -561,7 +577,6 @@ out:
return ret;
}
-
static int coroutine_fn parallels_co_create(BlockdevCreateOptions* opts,
Error **errp)
{
--
2.34.1
[PATCH v9 06/12] parallels: Move check of unclean image to a separate function
We will add more and more checks so we need a better code structure
in parallels_co_check. Let each check performs in a separate loop
in a separate helper.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/parallels.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index 63bfd7074c..02fbaee1f2 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -418,6 +418,25 @@ static coroutine_fn int
parallels_co_readv(BlockDriverState *bs,
return ret;
}
+static void parallels_check_unclean(BlockDriverState *bs,
+BdrvCheckResult *res,
+BdrvCheckMode fix)
+{
+BDRVParallelsState *s = bs->opaque;
+
+if (!s->header_unclean) {
+return;
+}
+
+fprintf(stderr, "%s image was not closed correctly\n",
+fix & BDRV_FIX_ERRORS ? "Repairing" : "ERROR");
+res->corruptions++;
+if (fix & BDRV_FIX_ERRORS) {
+/* parallels_close will do the job right */
+res->corruptions_fixed++;
+s->header_unclean = false;
+}
+}
static int coroutine_fn parallels_co_check(BlockDriverState *bs,
BdrvCheckResult *res,
@@ -435,16 +454,8 @@ static int coroutine_fn
parallels_co_check(BlockDriverState *bs,
}
qemu_co_mutex_lock(>lock);
-if (s->header_unclean) {
-fprintf(stderr, "%s image was not closed correctly\n",
-fix & BDRV_FIX_ERRORS ? "Repairing" : "ERROR");
-res->corruptions++;
-if (fix & BDRV_FIX_ERRORS) {
-/* parallels_close will do the job right */
-res->corruptions_fixed++;
-s->header_unclean = false;
-}
-}
+
+parallels_check_unclean(bs, res, fix);
res->bfi.total_clusters = s->bat_size;
res->bfi.compressed_clusters = 0; /* compression is not supported */
--
2.34.1
Re: [PATCH v5 6/9] tests/qtest/libqos/e1000e: Export macreg functions
On 30/01/2023 15.08, Akihiko Odaki wrote: They will be useful for igb testing. Signed-off-by: Akihiko Odaki --- tests/qtest/libqos/e1000e.c | 12 tests/qtest/libqos/e1000e.h | 12 2 files changed, 12 insertions(+), 12 deletions(-) Reviewed-by: Thomas Huth
[PATCH v2 20/20] hw: Move ich9.h to southbridge/
ICH9 is a south bridge which doesn't necessarily depend on x86, so move
it into the southbridge folder, analoguous to PIIX.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 1 +
include/hw/{i386 => southbridge}/ich9.h | 6 +++---
hw/acpi/ich9.c | 2 +-
hw/acpi/ich9_tco.c | 2 +-
hw/i2c/smbus_ich9.c | 2 +-
hw/i386/acpi-build.c| 2 +-
hw/i386/pc_q35.c| 2 +-
hw/isa/lpc_ich9.c | 2 +-
hw/pci-bridge/i82801b11.c | 2 +-
tests/qtest/tco-test.c | 2 +-
10 files changed, 12 insertions(+), 11 deletions(-)
rename include/hw/{i386 => southbridge}/ich9.h (99%)
diff --git a/MAINTAINERS b/MAINTAINERS
index f96e86c57b..8753fc066c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1670,6 +1670,7 @@ F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
F: hw/acpi/ich9*.c
F: include/hw/acpi/ich9*.h
+F: include/hw/southbridge/ich9.h
F: include/hw/southbridge/piix.h
F: hw/misc/sga.c
F: hw/isa/apm.c
diff --git a/include/hw/i386/ich9.h b/include/hw/southbridge/ich9.h
similarity index 99%
rename from include/hw/i386/ich9.h
rename to include/hw/southbridge/ich9.h
index 3125863049..7004eecbf9 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/southbridge/ich9.h
@@ -1,5 +1,5 @@
-#ifndef HW_ICH9_H
-#define HW_ICH9_H
+#ifndef HW_SOUTHBRIDGE_ICH9_H
+#define HW_SOUTHBRIDGE_ICH9_H
#include "hw/isa/apm.h"
#include "hw/acpi/ich9.h"
@@ -242,4 +242,4 @@ struct ICH9LPCState {
#define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1
#define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2
-#endif /* HW_ICH9_H */
+#endif /* HW_SOUTHBRIDGE_ICH9_H */
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 54bb3d83b3..d23bfcaa6b 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -36,7 +36,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9_tco.h"
-#include "hw/i386/ich9.h"
+#include "hw/southbridge/ich9.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
diff --git a/hw/acpi/ich9_tco.c b/hw/acpi/ich9_tco.c
index fbf97f81f4..1540f4fd46 100644
--- a/hw/acpi/ich9_tco.c
+++ b/hw/acpi/ich9_tco.c
@@ -9,7 +9,7 @@
#include "qemu/osdep.h"
#include "sysemu/watchdog.h"
-#include "hw/i386/ich9.h"
+#include "hw/southbridge/ich9.h"
#include "migration/vmstate.h"
#include "hw/acpi/ich9_tco.h"
diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c
index c7fdf32db0..b3eb82bc2e 100644
--- a/hw/i2c/smbus_ich9.c
+++ b/hw/i2c/smbus_ich9.c
@@ -27,7 +27,7 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
-#include "hw/i386/ich9.h"
+#include "hw/southbridge/ich9.h"
#include "qom/object.h"
#include "hw/acpi/acpi_aml_interface.h"
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 266df7a153..44ed879c8a 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -55,10 +55,10 @@
#include "hw/hyperv/vmbus-bridge.h"
/* Supported chipsets: */
+#include "hw/southbridge/ich9.h"
#include "hw/southbridge/piix.h"
#include "hw/acpi/pcihp.h"
#include "hw/i386/fw_cfg.h"
-#include "hw/i386/ich9.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/i440fx.h"
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index cd61d801c7..2c8c43834c 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -40,7 +40,6 @@
#include "hw/qdev-properties.h"
#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
-#include "hw/i386/ich9.h"
#include "hw/i386/amd_iommu.h"
#include "hw/i386/intel_iommu.h"
#include "hw/display/ramfb.h"
@@ -48,6 +47,7 @@
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/intc/ioapic.h"
+#include "hw/southbridge/ich9.h"
#include "hw/usb.h"
#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index f508f6071e..2699dc574a 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -40,7 +40,7 @@
#include "hw/irq.h"
#include "hw/isa/apm.h"
#include "hw/pci/pci.h"
-#include "hw/i386/ich9.h"
+#include "hw/southbridge/ich9.h"
#include "hw/i386/pc.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c
index f3b4a14611..0e83cd11b2 100644
--- a/hw/pci-bridge/i82801b11.c
+++ b/hw/pci-bridge/i82801b11.c
@@ -45,7 +45,7 @@
#include "hw/pci/pci_bridge.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
-#include "hw/i386/ich9.h"
+#include "hw/southbridge/ich9.h"
/*/
/* ICH9 DMI-to-PCI bridge */
diff --git a/tests/qtest/tco-test.c b/tests/qtest/tco-test.c
index d865e95dfc..0547d41173 100644
--- a/tests/qtest/tco-test.c
+++ b/tests/qtest/tco-test.c
@@ -14,7 +14,7 @@
#include "libqos/pci-pc.h"
#include "qapi/qmp/qdict.h"
#include "hw/pci/pci_regs.h"
-#include "hw/i386/ich9.h"
+#include "hw/southbridge/ich9.h"
#include "hw/acpi/ich9.h"
#include "hw/acpi/ich9_tco.h"
--
2.39.1
[PATCH v2 12/20] hw/i2c/smbus_ich9: Move ich9_smb_set_irq() in front of ich9_smbus_realize()
This is a preparation for the next commit to make it cleaner.
Signed-off-by: Bernhard Beschow
---
hw/i2c/smbus_ich9.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c
index ee50ba1f2c..06d97ac942 100644
--- a/hw/i2c/smbus_ich9.c
+++ b/hw/i2c/smbus_ich9.c
@@ -80,6 +80,18 @@ static void ich9_smbus_write_config(PCIDevice *d, uint32_t
address,
}
}
+static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
+{
+ICH9SMBState *s = pmsmb->opaque;
+
+if (enabled == s->irq_enabled) {
+return;
+}
+
+s->irq_enabled = enabled;
+pci_set_irq(>dev, enabled);
+}
+
static void ich9_smbus_realize(PCIDevice *d, Error **errp)
{
ICH9SMBState *s = ICH9_SMB_DEVICE(d);
@@ -128,18 +140,6 @@ static void ich9_smb_class_init(ObjectClass *klass, void
*data)
adevc->build_dev_aml = build_ich9_smb_aml;
}
-static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
-{
-ICH9SMBState *s = pmsmb->opaque;
-
-if (enabled == s->irq_enabled) {
-return;
-}
-
-s->irq_enabled = enabled;
-pci_set_irq(>dev, enabled);
-}
-
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
{
PCIDevice *d =
--
2.39.1
Re: [PATCH 2/2] linux-user: Allow sendmsg() without IOV
On 1/31/23 14:34, Helge Deller wrote:
On 1/31/23 13:28, Laurent Vivier wrote:
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Applications do call sendmsg() without any IOV, e.g.:
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=NULL, msg_iovlen=0,
msg_control=[{cmsg_len=36, cmsg_level=SOL_ALG, cmsg_type=0x2}],
msg_controllen=40, msg_flags=0}, MSG_MORE) = 0
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=[{iov_base="The quick brown fox
jumps over t"..., iov_len=183}],
msg_iovlen=1, msg_control=[{cmsg_len=20, cmsg_level=SOL_ALG,
cmsg_type=0x3}],
msg_controllen=24, msg_flags=0}, 0) = 183
The function do_sendrecvmsg_locked() is used for sndmsg() and recvmsg()
and calls lock_iovec() to lock the IOV into memory. For the first
sendmsg() above it returns NULL and thus wrongly skips the call the host
sendmsg() syscall, which will break the calling application.
Fix this issue by:
- allowing sendmsg() even with empty IOV
- skip recvmsg() if IOV is NULL
- skip both if the return code of do_sendrecvmsg_locked() != 0, which
indicates some failure like EFAULT on the IOV
Tested with the debian "ell" package with hppa guest on x86_64 host.
Signed-off-by: Helge Deller
---
linux-user/syscall.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index a365903a3a..9e2c0a18fc 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -3330,7 +3330,10 @@ static abi_long do_sendrecvmsg_locked(int fd, struct
target_msghdr *msgp,
target_vec, count, send);
if (vec == NULL) {
ret = -host_to_target_errno(errno);
- goto out2;
+ /* allow sending packet without any iov, e.g. with MSG_MORE flag */
why don't you check only for count is 0?
Somehing like:
if (vec == NULL && (count || !send)) {
You mean:
if (vec == NULL && (!count || !send)) {
goto out2;
lock_iovec() sets errno=0 if count==0, but for invalid addresses it sets
errno!=0,
so my current check (for which ret is the same as errno):
if (!send || ret) {
goto out2;
exits on memfaults too, while a check for just count==0 would succeed.
forget the above...
Maybe just checking for count==0 would be sufficient. I don't know yet if
there are any other corner cases where replacing the check of
if (!send || ret) {
with
if (!send || count==0) {
would behave different.
Checking against errno which is reported back from lock_iovec() seemed more
logical for me. This patch has been as-is in the buildd trees now since weeks
without any problems so far at least.
Helge
[PULL 12/27] qemu/bswap: Use compiler __builtin_bswap() on Haiku
From: Philippe Mathieu-Daudé
Since commit efc6c070aca ("configure: Add a test for the minimum
compiler version") the minimum compiler version required for GCC
is 4.8, which supports __builtin_bswap().
Remove the Haiku specific ifdef'ry.
This reverts commit 652a46ebba970017c7a23767dcc983265cdb8eb7
("bswap.h: Include on Haiku for bswap operations").
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2023063147.71761-5-phi...@linaro.org>
Signed-off-by: Thomas Huth
---
include/qemu/bswap.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index fd5a98125a..8cd5a2b02e 100644
--- a/include/qemu/bswap.h
+++ b/include/qemu/bswap.h
@@ -6,8 +6,6 @@
# include
#elif defined(__FreeBSD__)
# include
-#elif defined(__HAIKU__)
-# include
# else
#define BSWAP_FROM_FALLBACKS
#endif /* ! CONFIG_MACHINE_BSWAP_H */
--
2.31.1
[PULL 06/27] travis.yml: Use the libfdt from the distro instead of the submodule
No need to compile-test third party submodules over and over again if
we can simply use the pre-build library from the distribution instead.
By also adding --enable-fdt=system to the configure options, we can
also avoid to check out the "dtc" submodule here.
Message-Id: <20230120075330.2076773-1-th...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
.travis.yml | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index fb3baabca9..788e14c08c 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -128,6 +128,7 @@ jobs:
- libbrlapi-dev
- libcacard-dev
- libcap-ng-dev
+ - libfdt-dev
- libgcrypt20-dev
- libgnutls28-dev
- libgtk-3-dev
@@ -149,7 +150,8 @@ jobs:
- genisoimage
env:
- TEST_CMD="make check check-tcg V=1"
-- CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}
--cxx=/bin/false"
+- CONFIG="--disable-containers --enable-fdt=system
+ --target-list=${MAIN_SOFTMMU_TARGETS} --cxx=/bin/false"
- UNRELIABLE=true
- name: "[ppc64] GCC check-tcg"
@@ -162,6 +164,7 @@ jobs:
- libbrlapi-dev
- libcacard-dev
- libcap-ng-dev
+ - libfdt-dev
- libgcrypt20-dev
- libgnutls28-dev
- libgtk-3-dev
@@ -183,7 +186,8 @@ jobs:
- genisoimage
env:
- TEST_CMD="make check check-tcg V=1"
-- CONFIG="--disable-containers
--target-list=ppc64-softmmu,ppc64le-linux-user"
+- CONFIG="--disable-containers --enable-fdt=system
+ --target-list=ppc64-softmmu,ppc64le-linux-user"
- name: "[s390x] GCC check-tcg"
arch: s390x
@@ -195,6 +199,7 @@ jobs:
- libbrlapi-dev
- libcacard-dev
- libcap-ng-dev
+ - libfdt-dev
- libgcrypt20-dev
- libgnutls28-dev
- libgtk-3-dev
@@ -216,7 +221,8 @@ jobs:
- genisoimage
env:
- TEST_CMD="make check check-tcg V=1"
-- CONFIG="--disable-containers
--target-list=${MAIN_SOFTMMU_TARGETS},s390x-linux-user"
+- CONFIG="--disable-containers --enable-fdt=system
+ --target-list=${MAIN_SOFTMMU_TARGETS},s390x-linux-user"
- UNRELIABLE=true
script:
- BUILD_RC=0 && make -j${JOBS} || BUILD_RC=$?
@@ -237,6 +243,7 @@ jobs:
- libattr1-dev
- libcacard-dev
- libcap-ng-dev
+ - libfdt-dev
- libgnutls28-dev
- libiscsi-dev
- liblttng-ust-dev
@@ -255,8 +262,8 @@ jobs:
# Tests dependencies
- genisoimage
env:
-- CONFIG="--disable-containers --audio-drv-list=sdl --disable-user
- --target-list-exclude=${MAIN_SOFTMMU_TARGETS}"
+- CONFIG="--disable-containers --enable-fdt=system --audio-drv-list=sdl
+ --disable-user --target-list-exclude=${MAIN_SOFTMMU_TARGETS}"
- name: "[s390x] GCC (user)"
arch: s390x
@@ -281,6 +288,7 @@ jobs:
- libbrlapi-dev
- libcacard-dev
- libcap-ng-dev
+ - libfdt-dev
- libgcrypt20-dev
- libgnutls28-dev
- libgtk-3-dev
@@ -300,6 +308,6 @@ jobs:
- ninja-build
env:
- TEST_CMD="make check-unit"
-- CONFIG="--disable-containers --disable-tcg --enable-kvm
- --disable-tools --host-cc=clang --cxx=clang++"
+- CONFIG="--disable-containers --disable-tcg --enable-kvm
--disable-tools
+ --enable-fdt=system --host-cc=clang --cxx=clang++"
- UNRELIABLE=true
--
2.31.1
[PULL 24/27] qapi, audio: Make introspection reflect build configuration more closely
From: Daniel P. Berrangé
Currently the -audiodev accepts any audiodev type regardless of what is
built in to QEMU. An error only occurs later at runtime when a sound
device tries to use the audio backend.
With this change QEMU will immediately reject -audiodev args that are
not compiled into the binary. The QMP schema will also be introspectable
to identify what is compiled in.
This also helps to avoid compiling code that is not required in the
binary. Note: When building the audiodevs as modules, the patch only
compiles out code for modules that we don't build at all.
Signed-off-by: Daniel P. Berrangé
[thuth: Rebase, take sndio and dbus devices into account]
Message-Id: <20230123083957.20349-3-th...@redhat.com>
Signed-off-by: Thomas Huth
---
qapi/audio.json| 44 ++
audio/audio_template.h | 20 +++
audio/audio.c | 20 +++
audio/audio_legacy.c | 41 ++-
4 files changed, 112 insertions(+), 13 deletions(-)
diff --git a/qapi/audio.json b/qapi/audio.json
index c7aafa2763..4e54c00f51 100644
--- a/qapi/audio.json
+++ b/qapi/audio.json
@@ -408,8 +408,18 @@
# Since: 4.0
##
{ 'enum': 'AudiodevDriver',
- 'data': [ 'none', 'alsa', 'coreaudio', 'dbus', 'dsound', 'jack', 'oss', 'pa',
-'sdl', 'sndio', 'spice', 'wav' ] }
+ 'data': [ 'none',
+{ 'name': 'alsa', 'if': 'CONFIG_AUDIO_ALSA' },
+{ 'name': 'coreaudio', 'if': 'CONFIG_AUDIO_COREAUDIO' },
+{ 'name': 'dbus', 'if': 'CONFIG_DBUS_DISPLAY' },
+{ 'name': 'dsound', 'if': 'CONFIG_AUDIO_DSOUND' },
+{ 'name': 'jack', 'if': 'CONFIG_AUDIO_JACK' },
+{ 'name': 'oss', 'if': 'CONFIG_AUDIO_OSS' },
+{ 'name': 'pa', 'if': 'CONFIG_AUDIO_PA' },
+{ 'name': 'sdl', 'if': 'CONFIG_AUDIO_SDL' },
+{ 'name': 'sndio', 'if': 'CONFIG_AUDIO_SNDIO' },
+{ 'name': 'spice', 'if': 'CONFIG_SPICE' },
+'wav' ] }
##
# @Audiodev:
@@ -432,16 +442,26 @@
'discriminator': 'driver',
'data': {
'none': 'AudiodevGenericOptions',
-'alsa': 'AudiodevAlsaOptions',
-'coreaudio': 'AudiodevCoreaudioOptions',
-'dbus': 'AudiodevGenericOptions',
-'dsound':'AudiodevDsoundOptions',
-'jack': 'AudiodevJackOptions',
-'oss': 'AudiodevOssOptions',
-'pa':'AudiodevPaOptions',
-'sdl': 'AudiodevSdlOptions',
-'sndio': 'AudiodevSndioOptions',
-'spice': 'AudiodevGenericOptions',
+'alsa': { 'type': 'AudiodevAlsaOptions',
+ 'if': 'CONFIG_AUDIO_ALSA' },
+'coreaudio': { 'type': 'AudiodevCoreaudioOptions',
+ 'if': 'CONFIG_AUDIO_COREAUDIO' },
+'dbus': { 'type': 'AudiodevGenericOptions',
+ 'if': 'CONFIG_DBUS_DISPLAY' },
+'dsound':{ 'type': 'AudiodevDsoundOptions',
+ 'if': 'CONFIG_AUDIO_DSOUND' },
+'jack': { 'type': 'AudiodevJackOptions',
+ 'if': 'CONFIG_AUDIO_JACK' },
+'oss': { 'type': 'AudiodevOssOptions',
+ 'if': 'CONFIG_AUDIO_OSS' },
+'pa':{ 'type': 'AudiodevPaOptions',
+ 'if': 'CONFIG_AUDIO_PA' },
+'sdl': { 'type': 'AudiodevSdlOptions',
+ 'if': 'CONFIG_AUDIO_SDL' },
+'sndio': { 'type': 'AudiodevSndioOptions',
+ 'if': 'CONFIG_AUDIO_SNDIO' },
+'spice': { 'type': 'AudiodevGenericOptions',
+ 'if': 'CONFIG_SPICE' },
'wav': 'AudiodevWavOptions' } }
##
diff --git a/audio/audio_template.h b/audio/audio_template.h
index 720a32e57e..42b4712acb 100644
--- a/audio/audio_template.h
+++ b/audio/audio_template.h
@@ -326,27 +326,47 @@ AudiodevPerDirectionOptions *glue(audio_get_pdo_,
TYPE)(Audiodev *dev)
switch (dev->driver) {
case AUDIODEV_DRIVER_NONE:
return dev->u.none.TYPE;
+#ifdef CONFIG_AUDIO_ALSA
case AUDIODEV_DRIVER_ALSA:
return qapi_AudiodevAlsaPerDirectionOptions_base(dev->u.alsa.TYPE);
+#endif
+#ifdef CONFIG_AUDIO_COREAUDIO
case AUDIODEV_DRIVER_COREAUDIO:
return qapi_AudiodevCoreaudioPerDirectionOptions_base(
dev->u.coreaudio.TYPE);
+#endif
+#ifdef CONFIG_DBUS_DISPLAY
case AUDIODEV_DRIVER_DBUS:
return dev->u.dbus.TYPE;
+#endif
+#ifdef CONFIG_AUDIO_DSOUND
case AUDIODEV_DRIVER_DSOUND:
return dev->u.dsound.TYPE;
+#endif
+#ifdef CONFIG_AUDIO_JACK
case AUDIODEV_DRIVER_JACK:
return qapi_AudiodevJackPerDirectionOptions_base(dev->u.jack.TYPE);
+#endif
+#ifdef CONFIG_AUDIO_OSS
case AUDIODEV_DRIVER_OSS:
return qapi_AudiodevOssPerDirectionOptions_base(dev->u.oss.TYPE);
+#endif
+#ifdef CONFIG_AUDIO_PA
case AUDIODEV_DRIVER_PA:
return qapi_AudiodevPaPerDirectionOptions_base(dev->u.pa.TYPE);
+#endif
+#ifdef CONFIG_AUDIO_SDL
case AUDIODEV_DRIVER_SDL:
return
[PULL 11/27] qemu/bswap: Remove dependency
From: Philippe Mathieu-Daudé
Since commit efc6c070aca ("configure: Add a test for the minimum
compiler version") the minimum compiler version required for GCC
is 4.8, which supports __builtin_bswap().
Drop the dependency.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2023063147.71761-4-phi...@linaro.org>
Signed-off-by: Thomas Huth
---
meson.build | 2 --
include/qemu/bswap.h | 21 -
2 files changed, 23 deletions(-)
diff --git a/meson.build b/meson.build
index 6d3b665629..7e15a010bf 100644
--- a/meson.build
+++ b/meson.build
@@ -2013,8 +2013,6 @@ if rdma.found()
endif
# has_header_symbol
-config_host_data.set('CONFIG_BYTESWAP_H',
- cc.has_header_symbol('byteswap.h', 'bswap_32'))
config_host_data.set('CONFIG_EPOLL_CREATE1',
cc.has_header_symbol('sys/epoll.h', 'epoll_create1'))
config_host_data.set('CONFIG_FALLOCATE_PUNCH_HOLE',
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index d2dafdc54c..fd5a98125a 100644
--- a/include/qemu/bswap.h
+++ b/include/qemu/bswap.h
@@ -8,9 +8,6 @@
# include
#elif defined(__HAIKU__)
# include
-#elif defined(CONFIG_BYTESWAP_H)
-# include
-#define BSWAP_FROM_BYTESWAP
# else
#define BSWAP_FROM_FALLBACKS
#endif /* ! CONFIG_MACHINE_BSWAP_H */
@@ -19,23 +16,6 @@
extern "C" {
#endif
-#ifdef BSWAP_FROM_BYTESWAP
-static inline uint16_t bswap16(uint16_t x)
-{
-return bswap_16(x);
-}
-
-static inline uint32_t bswap32(uint32_t x)
-{
-return bswap_32(x);
-}
-
-static inline uint64_t bswap64(uint64_t x)
-{
-return bswap_64(x);
-}
-#endif
-
#ifdef BSWAP_FROM_FALLBACKS
#undef bswap16
#define bswap16(_x) __builtin_bswap16(_x)
@@ -45,7 +25,6 @@ static inline uint64_t bswap64(uint64_t x)
#define bswap64(_x) __builtin_bswap64(_x)
#endif
-#undef BSWAP_FROM_BYTESWAP
#undef BSWAP_FROM_FALLBACKS
static inline void bswap16s(uint16_t *s)
--
2.31.1
[PULL 22/27] docs/s390x/pcidevices: document pci devices on s390x
From: Sebastian Mitterle Add some documentation about the zpci device and how to use it with pci devices on s390x. Used source: Cornelia Huck's blog post https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s390x.html Signed-off-by: Sebastian Mitterle Reviewed-by: Cédric Le Goater Message-Id: <20230127123349.55294-1-smitt...@redhat.com> Reviewed-by: Cornelia Huck Signed-off-by: Thomas Huth --- docs/system/s390x/pcidevices.rst | 41 docs/system/target-s390x.rst | 1 + 2 files changed, 42 insertions(+) create mode 100644 docs/system/s390x/pcidevices.rst diff --git a/docs/system/s390x/pcidevices.rst b/docs/system/s390x/pcidevices.rst new file mode 100644 index 00..628effa2f4 --- /dev/null +++ b/docs/system/s390x/pcidevices.rst @@ -0,0 +1,41 @@ +PCI devices on s390x + + +PCI devices on s390x work differently than on other architectures and need to +be configured in a slightly different way. + +Every PCI device is linked with an additional ``zpci`` device. +While the ``zpci`` device will be autogenerated if not specified, it is +recommended to specify it explicitly so that you can pass s390-specific +PCI configuration. + +For example, in order to pass a PCI device ``:00:00.0`` through to the +guest, you would specify:: + + qemu-system-s390x ... \ + -device zpci,uid=1,fid=0,target=hostdev0,id=zpci1 \ + -device vfio-pci,host=:00:00.0,id=hostdev0 + +Here, the zpci device is joined with the PCI device via the ``target`` property. + +Note that we don't set bus, slot or function here for the guest as is common in +other PCI implementations. Topology information is not available on s390x, and +the guest will not see any of the bus, slot or function information specified +on the command line. + +Instead, ``uid`` and ``fid`` determine how the device is presented to the guest +operating system. + +In case of Linux, ``uid`` will be used in the ``domain`` part of the PCI +identifier, and ``fid`` identifies the physical slot, i.e.:: + + qemu-system-s390x ... \ + -device zpci,uid=7,fid=8,target=hostdev0,id=zpci1 \ + ... + +will be presented in the guest as:: + + # lspci -v + 0007:00:00.0 ... + Physical Slot: 0008 + ... diff --git a/docs/system/target-s390x.rst b/docs/system/target-s390x.rst index c636f64113..f6f11433c7 100644 --- a/docs/system/target-s390x.rst +++ b/docs/system/target-s390x.rst @@ -26,6 +26,7 @@ or vfio-ap is also available. s390x/css s390x/3270 s390x/vfio-ccw + s390x/pcidevices Architectural features == -- 2.31.1
[PULL 18/27] tests/qtest/vnc-display-test: Suppress build warnings on Windows
From: Philippe Mathieu-Daudé
While this test is skipped on Windows, we still get when building:
tests/qtest/vnc-display-test.c:22:20: warning: unused function 'on_vnc_error'
[-Wunused-function]
static inline void on_vnc_error(VncConnection* self,
^
tests/qtest/vnc-display-test.c:28:20: warning: unused function
'on_vnc_auth_failure' [-Wunused-function]
static inline void on_vnc_auth_failure(VncConnection *self,
^
2 warnings generated.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230119120514.28778-2-phi...@linaro.org>
Reviewed-by: Richard Henderson
Reviewed-by: Marc-André Lureau
Signed-off-by: Thomas Huth
---
tests/qtest/vnc-display-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/vnc-display-test.c b/tests/qtest/vnc-display-test.c
index e2a9d682bb..fd63e3a881 100644
--- a/tests/qtest/vnc-display-test.c
+++ b/tests/qtest/vnc-display-test.c
@@ -19,6 +19,8 @@ typedef struct Test {
GMainLoop *loop;
} Test;
+#if !defined(WIN32)
+
static void on_vnc_error(VncConnection* self,
const char* msg)
{
@@ -31,6 +33,8 @@ static void on_vnc_auth_failure(VncConnection *self,
g_error("vnc-auth-failure: %s", msg);
}
+#endif
+
static bool
test_setup(Test *test)
{
--
2.31.1
[PULL 13/27] qemu/bswap: Use compiler __builtin_bswap() on FreeBSD
From: Philippe Mathieu-Daudé
Since commit efc6c070aca ("configure: Add a test for the minimum
compiler version") the minimum compiler version required for GCC
is 4.8, which supports __builtin_bswap().
Remove the FreeBSD specific ifdef'ry.
This reverts commit de03c3164accc21311c39327601fcdd95da301f3
("bswap: Fix build on FreeBSD 10.0").
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2023063147.71761-6-phi...@linaro.org>
Signed-off-by: Thomas Huth
---
include/qemu/bswap.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index 8cd5a2b02e..32d5cdec27 100644
--- a/include/qemu/bswap.h
+++ b/include/qemu/bswap.h
@@ -4,8 +4,6 @@
#ifdef CONFIG_MACHINE_BSWAP_H
# include
# include
-#elif defined(__FreeBSD__)
-# include
# else
#define BSWAP_FROM_FALLBACKS
#endif /* ! CONFIG_MACHINE_BSWAP_H */
--
2.31.1
[PULL 15/27] MAINTAINERS: Abort HAXM maintenance
From: Wenchao Wang Abort the maintenance of Guest CPU Cores (HAXM). * Clean up the maintainer list of X86 HAXM CPUs * Remove the web page URL and the mailing list * Change the status to Orphan Reviewed-by: Hang Yuan Signed-off-by: Wenchao Wang Message-Id: Signed-off-by: Thomas Huth --- MAINTAINERS | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c581c11a64..307a9d5d4c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -500,10 +500,7 @@ F: stubs/xen-hw-stub.c Guest CPU Cores (HAXM) - X86 HAXM CPUs -M: Wenchao Wang -L: haxm-t...@intel.com -W: https://github.com/intel/haxm/issues -S: Maintained +S: Orphan F: accel/stubs/hax-stub.c F: include/sysemu/hax.h F: target/i386/hax/ -- 2.31.1
[PULL 25/27] gitlab-ci.d/buildtest: Remove ppc-softmmu from the clang-system job
We are also compile-testing ppc64-softmmu with clang in the "tsan-build" job, and ppc64-softmmu covers pretty much the same code as ppc-softmmu, so we should not lose much test coverage here by removing ppc-softmmu from the "clang-system" job. Message-Id: <20230130104446.1286773-2-th...@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- .gitlab-ci.d/buildtest.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index f09a898c3e..406608e5fc 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -316,8 +316,7 @@ clang-system: IMAGE: fedora CONFIGURE_ARGS: --cc=clang --cxx=clang++ --extra-cflags=-fsanitize=undefined --extra-cflags=-fno-sanitize-recover=undefined -TARGETS: alpha-softmmu arm-softmmu m68k-softmmu mips64-softmmu - ppc-softmmu s390x-softmmu +TARGETS: alpha-softmmu arm-softmmu m68k-softmmu mips64-softmmu s390x-softmmu MAKE_CHECK_ARGS: check-qtest check-tcg clang-user: -- 2.31.1
[PULL 21/27] tests/qtest/boot-serial-test: Constify tests[] array
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230120082341.59913-2-phi...@linaro.org>
Signed-off-by: Thomas Huth
---
tests/qtest/boot-serial-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index b216519b62..3aef3a97a9 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -139,7 +139,7 @@ typedef struct testdef {
const uint8_t *bios;/* Set in case we use our own mini bios */
} testdef_t;
-static testdef_t tests[] = {
+static const testdef_t tests[] = {
{ "alpha", "clipper", "", "PCI:" },
{ "avr", "arduino-duemilanove", "", "T", sizeof(bios_avr), NULL, bios_avr
},
{ "avr", "arduino-mega-2560-v3", "", "T", sizeof(bios_avr), NULL,
bios_avr},
--
2.31.1
[PULL 27/27] gitlab-ci.d/buildtest: Merge the --without-default-* jobs
Let's safe some CI minutes by merging these two jobs. We can now also drop "--disable-capstone" since the capstone submodule has been removed a while ago. We should rather test --disable-fdt now to check a compilation without the "dtc" submodule (for this we have to drop i386-softmmu from the target list unfortunately). Additionally, the qtests with s390x and sh4 are not read for "--without-default-devices" yet, so we can only test mips64 and avr here now. Message-Id: <20230130104446.1286773-5-th...@redhat.com> Reviewed-by: Alex Bennée Reviewed-by: Fabiano Rosas Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- .gitlab-ci.d/buildtest.yml | 17 + 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 406608e5fc..1c35cbfa10 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -557,29 +557,22 @@ build-coroutine-sigaltstack: MAKE_CHECK_ARGS: check-unit # Check our reduced build configurations -build-without-default-devices: +build-without-defaults: extends: .native_build_job_template needs: job: amd64-centos8-container variables: IMAGE: centos8 -CONFIGURE_ARGS: --without-default-devices --disable-user - -build-without-default-features: - extends: .native_build_job_template - needs: -job: amd64-fedora-container - variables: -IMAGE: fedora CONFIGURE_ARGS: + --without-default-devices --without-default-features - --disable-capstone + --disable-fdt --disable-pie --disable-qom-cast-debug --disable-strip -TARGETS: avr-softmmu i386-softmmu mips64-softmmu s390x-softmmu sh4-softmmu +TARGETS: avr-softmmu mips64-softmmu s390x-softmmu sh4-softmmu sparc64-softmmu hexagon-linux-user i386-linux-user s390x-linux-user -MAKE_CHECK_ARGS: check-unit check-qtest SPEED=slow +MAKE_CHECK_ARGS: check-unit check-qtest-avr check-qtest-mips64 build-libvhost-user: extends: .base_job_template -- 2.31.1
