Am 02.03.23 um 17:31 schrieb Vladimir Sementsov-Ogievskiy:
> On 02.03.23 15:34, Fiona Ebner wrote:
>> Am 02.03.23 um 11:13 schrieb Vladimir Sementsov-Ogievskiy:
>>> On 02.03.23 13:00, Fiona Ebner wrote:
Am 01.03.23 um 17:31 schrieb Vladimir Sementsov-Ogievskiy:
> On 24.02.23 17:48, Fiona
On 03/03/2023 06:58, David Woodhouse wrote:
On 2 March 2023 22:40:40 GMT, "Philippe Mathieu-Daudé"
wrote:
Since v2: rebased
I'm posting this series as it to not block Bernhard's PIIX
cleanup work. I don't have code change planned, but eventually
reword / improve commit descriptions.
Tested
From: Cédric Le Goater
Simply revert 'x8' to fix the typo and remove the ending '8'
Fixes: e61a424f05 ("vfio: Create device specific region info helper")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1526
Signed-off-by: Cédric Le Goater
---
hw/vfio/trace-events | 2 +-
1 file
On 02/03/2023 18.22, Peter Maydell wrote:
migration-test has been flaky for a long time, both in CI and
otherwise
Acked-by: Thomas Huth
Do you want to apply it directly as a CI fix, or shall I queue it for my
next pull request?
Thomas
On 02/03/2023 23.16, Philippe Mathieu-Daudé wrote:
On 2/3/23 17:31, Thomas Huth wrote:
qemu-system-aarch64 is a proper superset of qemu-system-arm,
and the latter was mainly still required for 32-bit KVM support.
But this 32-bit KVM arm support has been dropped in the Linux
kernel a couple of
On Thu, Mar 02, 2023 at 06:26:12PM -0800, Haitao Shan wrote:
> Add the configure support for the Android Emulator hypervisor driver
> accelerator. The Android Emulator hypervisor driver is a Windows
> driver made by porting the KVM from kernel 4.9-rc7.
>
> Signed-off-by: Haitao Shan
Replying on
On Fri, Mar 03, 2023 at 03:02:24PM +0800, zhenwei pi wrote:
>
>
> On 3/1/23 19:05, Daniel P. Berrangé wrote:
> > On Wed, Mar 01, 2023 at 06:58:44PM +0800, zhenwei pi wrote:
> > > Account OPS/BPS for crypto device, this will be used for 'query-stats'
> > > QEMU monitor command and QoS in the next
On 3/1/23 19:05, Daniel P. Berrangé wrote:
On Wed, Mar 01, 2023 at 06:58:44PM +0800, zhenwei pi wrote:
Account OPS/BPS for crypto device, this will be used for 'query-stats'
QEMU monitor command and QoS in the next step.
Note that a crypto device may support symmetric mode, asymmetric mode,
Intel platforms Granite Rapids/Sierra Forest introduce below new
instructions and CPUID leaves:
- CMPccXADD CPUID.(EAX=7,ECX=1):EAX[bit 7]
- AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
- AVX-IFMA CPUID.(EAX=7,ECX=1):EAX[bit 23]
- AVX-VNNI-INT8 CPUID.(EAX=7,ECX=1):EDX[bit 4]
- AVX-NE-CONVERT
From: Jiaxi Chen
Latest Intel platform Granite Rapids has introduced a new instruction -
AMX-FP16, which performs dot-products of two FP16 tiles and accumulates
the results into a packed single precision tile. AMX-FP16 adds FP16
capability and allows a FP16 GPU trained model to run faster
From: Jiaxi Chen
AVX-NE-CONVERT is a new set of instructions which can convert low
precision floating point like BF16/FP16 to high precision floating point
FP32, as well as convert FP32 elements to BF16. This instruction allows
the platform to have improved AI capabilities and better
From: Jiaxi Chen
CMPccXADD is a new set of instructions in the latest Intel platform
Sierra Forest. This new instruction set includes a semaphore operation
that can compare and add the operands if condition is met, which can
improve database performance.
The bit definition:
From: Jiaxi Chen
Latest Intel platform Granite Rapids has introduced a new instruction -
PREFETCHIT0/1, which moves code to memory (cache) closer to the
processor depending on specific hints.
The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 14]
Add CPUID definition for PREFETCHIT0/1.
From: Jiaxi Chen
AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform
Sierra Forest, aims for the platform to have superior AI capabilities.
This instruction multiplies the individual bytes of two unsigned or
unsigned source operands, then adds and accumulates the results into
From: Jiaxi Chen
AVX-IFMA is a new instruction in the latest Intel platform Sierra
Forest. This instruction packed multiplies unsigned 52-bit integers and
adds the low/high 52-bit products to Qword Accumulators.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 23]
Add CPUID definition for
On 2 March 2023 22:40:40 GMT, "Philippe Mathieu-Daudé"
wrote:
>Since v2: rebased
>
>I'm posting this series as it to not block Bernhard's PIIX
>cleanup work. I don't have code change planned, but eventually
>reword / improve commit descriptions.
>
>Tested commit after commit to be sure it is
Add basic implementation of the AC'97 sound part used in VIA south
bridge chips. Not all features of the device is emulated, only one
playback channel is supported for now but this is enough to get sound
output from some guests using this device on pegasos2.
Signed-off-by: BALATON Zoltan
---
Qemu_get_cpu uses the logical CPU id assigned during init to fetch the
CPU state. However APLIC, IMSIC and ACLINT contain registers and states
which are specific to physical hart Ids. The hart Ids in any given system
might be sparse and hence calls to qemu_get_cpu need to be replaced by
Currently a Risc-V platform cannot realizes multiple CPUs with non contiguous
hart IDs because the APLIC, IMSIC and ACLINT emulation code uses the
contiguous logical CPU ID to fetch per CPU state.
This patchset implements cpu_by_arch_id for Risc-V to get the CPU state
by hart ID which may be
Implement the callback for getting the architecture-dependent CPU ID ie
mhartid.
Signed-off-by: Mayuresh Chitale
Signed-off-by: Anup Patel
---
target/riscv/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dd2f0c753..467d8467a3
在 2023/3/2 03:32, Eugenio Perez Martin 写道:
On Mon, Feb 27, 2023 at 9:20 AM Jason Wang wrote:
On Mon, Feb 27, 2023 at 4:15 PM Jason Wang wrote:
在 2023/2/24 23:54, Eugenio Pérez 写道:
A vdpa net device must initialize with SVQ in order to be migratable at
this moment, and initialization code
在 2023/3/2 03:26, Eugenio Perez Martin 写道:
On Mon, Feb 27, 2023 at 9:08 AM Jason Wang wrote:
在 2023/2/24 23:54, Eugenio Pérez 写道:
This allows net to restart the device backend to configure SVQ on it.
Ideally, these changes should not be net specific. However, the vdpa net
backend is the
在 2023/3/1 15:01, Eugenio Perez Martin 写道:
On Mon, Feb 27, 2023 at 8:04 AM Jason Wang wrote:
在 2023/2/24 23:54, Eugenio Pérez 写道:
Only create iova_tree if and when it is needed.
The cleanup keeps being responsible of last VQ but this change allows it
to merge both cleanup functions.
From: Alex Bennée
We unfortunately handle the checking of packet acknowledgement
differently for user and softmmu modes. Abstract the user mode stuff
behind gdb_got_immediate_ack with a stub for softmmu.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex
From: Alex Bennée
This is needed for handling vcont packets as the way of calculating
max cpus vhanges between user and softmmu mode.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20230302190846.2593720-17-alex.ben...@linaro.org>
---
gdbstub/internals.h | 1 +
From: Alex Bennée
Otherwise checkpatch will throw a hissy fit on the later patches that
split this function up.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20230302190846.2593720-5-alex.ben...@linaro.org>
---
gdbstub/gdbstub.c | 28 ++--
1
From: Alex Bennée
Now we have removed any target specific bits from the core gdbstub
code we only need to build it twice. We have to jump a few meson hoops
to manually define the CONFIG_USER_ONLY symbol but it seems to work.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
From: Alex Bennée
This aids subsystems (like gdbstub) that want to trigger a flush
without pulling target specific headers.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20230302190846.2593720-8-alex.ben...@linaro.org>
---
MAINTAINERS | 1 +
From: Philippe Mathieu-Daudé
Prototypes using gdb_syscall_complete_cb() or gdb_?et_reg_cb()
don't depend on "cpu.h", thus are not target-specific.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221214143659.62133-1-phi...@linaro.org>
Signed-off-by: Alex
From: Alex Bennée
Currently we only support replay for softmmu mode so it is a constant
false for user-mode.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20230302190846.2593720-18-alex.ben...@linaro.org>
---
gdbstub/internals.h
From: Alex Bennée
Our GDB syscall support is the last chunk of code that needs target
specific support so move it to a new file. We take the opportunity to
move the syscall state into its own singleton instance and add in a
few helpers for the main gdbstub to interact with the module.
I also
From: Alex Bennée
While we will continue to include this via cpu-defs it is useful to be
able to define this separately for 32 and 64 bit versions of an
otherwise target independent compilation unit.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id:
From: Alex Bennée
The process was pretty similar to the softmmu move except we take the
time to split stuff between user.c and user-target.c to avoid as much
target specific compilation as possible. We also start to make use of
our shiny new header scheme so the user-only helpers can be included
From: Alex Bennée
This is a hangover from the original code. addr is misleading as it is
only really a register id. While len will never exceed
MAX_PACKET_LENGTH I've used size_t as that is what strlen returns.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by:
From: Mads Ynddal
Continuing the refactor of a48e7d9e52 (gdbstub: move guest debug support
check to ops) by removing hardcoded kvm_enabled() from generic cpu.c
code, and replace it with a property of AccelOpsClass.
Signed-off-by: Mads Ynddal
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
Pass %x as uint32_t and %lx as uint64_t; pass the address
of %s as uint64_t and the length as uint32_t.
Add casts in semihosting/syscalls.c from target_ulong to
uint64_t; add casts from int to uint32_t for clarity.
Signed-off-by: Richard Henderson
---
gdbstub/syscalls.c | 12 ++--
From: Alex Bennée
Currently when we encounter a gdb that is old or not built with
multiarch in mind we fail rather messily. Try and improve the
situation by probing ahead of time and setting
HOST_GDB_SUPPORTS_ARCH=y in the relevant tcg configs. We can then skip
and give a more meaningful message
This function is unused, except to implement gdb_do_syscall.
Fold the implementations together.
Signed-off-by: Richard Henderson
---
include/gdbstub/syscalls.h | 11 ---
gdbstub/syscalls.c | 26 ++
2 files changed, 10 insertions(+), 27 deletions(-)
diff
From: Alex Bennée
In both user and softmmu cases we are just replying with a constant.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20230302190846.2593720-15-alex.ben...@linaro.org>
---
gdbstub/internals.h | 4 +++-
There is no longer anything target specific.
Signed-off-by: Richard Henderson
---
gdbstub/syscalls.c | 5 +
gdbstub/meson.build | 3 +--
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/gdbstub/syscalls.c b/gdbstub/syscalls.c
index b7d85c41c7..4391d124e2 100644
---
From: Alex Bennée
When I started splitting gdbstub apart I was a little too boilerplate
with my file headers. Fix up to carry over Fabrice's copyright and the
LGPL license header.
Fixes: ae7467b1ac (gdbstub: move breakpoint logic to accel ops)
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by:
From: Alex Bennée
The two implementations are different enough to encourage having a
specialisation and we can move some of the softmmu only stuff out of
gdbstub.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20230302190846.2593720-16-alex.ben...@linaro.org>
---
From: Alex Bennée
These inline helpers are all used by target specific code so move them
out of the general header so we don't needlessly pollute the rest of
the API with target specific stuff.
Note we have to include cpu.h in semihosting as it was relying on a
side effect before.
Reviewed-by:
From: Alex Bennée
We don't really need a table for mapping two symbols.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20230302190846.2593720-13-alex.ben...@linaro.org>
---
gdbstub/softmmu.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
From: Alex Bennée
Use something more specific to avoid name clashes.
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20230302190846.2593720-2-alex.ben...@linaro.org>
---
gdbstub/internals.h | 6 +++---
1 file
From: Alex Bennée
This is mostly code motion but a number of things needed to be done
for this minimal patch set:
- move shared structures to internals.h
- splitting some functions into user and softmmu versions
- fixing a few casting issues to keep softmmu common
More CONFIG_USER_ONLY
From: Alex Bennée
We are about to split softmmu and user mode helpers into different
files. To facilitate this we will need to share access to the GDBState
between those files.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id:
From: Alex Bennée
Most of the syscall code is config agnostic aside from the size of
target_ulong. In preparation for the next patch move the final bits
of specialisation into the appropriate user and softmmu helpers.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id:
From: Alex Bennée
The underlying call uses vaddr and the comms API uses unsigned long
long which will always fit. We don't need to deal in target_ulong
here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id:
From: Alex Bennée
We will be needing to use these helpers between the user and softmmu
files so declare them in the headers, add a system prefix and remove
static from the implementations.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
From: Alex Bennée
These will be needed from multiple places in the code. They are
declared as inline so move to the header and fix up to modern coding
style.
The only other place that messes with hex stuff at the moment is the
URI handling in utils but that would be more code churn so leave for
Hi Alex,
This is what I came up with when thinking about your user/softmmu
and syscall split.
r~
Alex Bennée (24):
gdbstub/internals.h: clean up include guard
gdbstub: fix-up copyright and license files
gdbstub: clean-up indent on gdb_exit
gdbstub: define separate user/system
From: Alex Bennée
In preparation for moving user/softmmu specific bits from the main
gdbstub file we need to separate the connection details into a
user/softmmu state. As these will eventually be defined in their own
files we move them out of the common GDBState structure.
Reviewed-by: Richard
LoongArch has enabled CONFIG_SMBIOS, but didn't enable CLI '-smbios'.
Fixes: 3efa6fa1e629 ("hw/loongarch: Add smbios support")
Acked-by: Michael S. Tsirkin
Reviewed-by: Markus Armbruster
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id:
The following changes since commit 262312d7ba6e2966acedb4f9c134fd19176b4083:
Merge tag 'pull-testing-next-010323-1' of https://gitlab.com/stsquad/qemu
into staging (2023-03-02 13:02:53 +)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git
For loongarch virt machine, add powerdown notification callback
and send ACPI_POWER_DOWN_STATUS event by acpi ged. Also add
acpi dsdt table for ACPI_POWER_BUTTON_DEVICE device in this
patch.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Song Gao
Message-Id:
According to the 3A5000 manual 4.1 implement Chip Configuration
Version Register(0x).
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20230227071046.1445572-1-gaos...@loongson.cn>
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 1 +
2 files changed, 3
Since the EDK2 had already support LoongArch, update build bios,
and update cpu type, cross-tools.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230227035905.1290953-1-gaos...@loongson.cn>
---
.../loongarch/{loongson3.rst => virt.rst} | 97 ---
1
From: Bibo Mao
In theory gsi base can start from 0 on loongarch virt machine,
however gsi base is hard-coded in linux kernel loongarch system,
else system fails to boot.
This patch renames macro PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE,
keeps value unchanged. GSI base is common concept in acpi
The aehd-apic device type represents the AEHD in kernel APIC.
The irqchips should be always in kernel when AEHD is used.
Signed-off-by: Haitao Shan
---
MAINTAINERS | 2 +
hw/i386/aehd/apic.c | 204 +++
hw/i386/aehd/meson.build | 4 +
Implement the AEHD accelerator including the AEHD AccelClass,
AccelCPUClass, AccelOpsClass.
Signed-off-by: Haitao Shan
---
hw/i386/x86.c |2 +-
include/exec/ram_addr.h |2 -
include/sysemu/aehd.h | 87 ++
include/sysemu/hw_accel.h |
aehd-interface.h AEHD DeviceIoControl Definitions
aehd.h AEHD generic header with only aehd_enabled defined.
To be expanded later by following patches.
Signed-off-by: Haitao Shan
---
MAINTAINERS | 10 +
Add the configure support for the Android Emulator hypervisor driver
accelerator. The Android Emulator hypervisor driver is a Windows
driver made by porting the KVM from kernel 4.9-rc7.
Signed-off-by: Haitao Shan
---
accel/Kconfig | 3 +++
docs/about/build-platforms.rst | 2
The aehd-i8259 device type represents the AEHD in kernel PICs.
The irqchips should be always in kernel when AEHD is used.
Signed-off-by: Haitao Shan
---
hw/i386/aehd/i8259.c | 165 +++
hw/i386/aehd/meson.build | 1 +
hw/i386/pc.c | 2 +
The aehd-ioapic device type represents the AEHD in kernel IO-APIC.
The irqchips should be always in kernel when AEHD is used.
Signed-off-by: Haitao Shan
---
hw/i386/aehd/ioapic.c | 164
hw/i386/aehd/meson.build| 1 +
hw/i386/pc.c|
Hi, qemu maintainers and community members,
The following 6 patches implemented a new x86_64 CPU accelerator called
the Android Emulator hypervisor driver (AEHD).
The Android Emulator hypervisor driver is a hypervisor for Windows (7
or later), made by porting the KVM from the linux kernel
Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
> ---
> v2:
> - Endian fix
> ---
> hw/cxl/cxl-mailbox-utils.c | 79 +
For loongarch virt machine, add powerdown notification callback
and send ACPI_POWER_DOWN_STATUS event by acpi ged. Also add
acpi dsdt table for ACPI_POWER_BUTTON_DEVICE device in this
patch.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Song Gao
---
hw/loongarch/acpi-build.c | 1 +
On Thu, 2023-03-02 at 17:31 +0100, Thomas Huth wrote:
> Hardly anybody still uses 32-bit arm environments for running QEMU,
> so let's stop wasting our scarce CI minutes with these jobs.
>
> Signed-off-by: Thomas Huth
> ---
> .gitlab-ci.d/crossbuilds.yml | 14 --
> 1 file changed,
On Thu, 2023-03-02 at 17:31 +0100, Thomas Huth wrote:
> For running QEMU in system emulation mode, the user needs a rather
> strong host system, i.e. not only an embedded low-frequency
> controller.
> All recent beefy arm host machines should support 64-bit now, it's
> unlikely that anybody is
On Thu, 2023-03-02 at 17:31 +0100, Thomas Huth wrote:
> qemu-system-aarch64 is a proper superset of qemu-system-arm,
> and the latter was mainly still required for 32-bit KVM support.
> But this 32-bit KVM arm support has been dropped in the Linux
> kernel a couple of years ago already, so we
On Thu, 2023-03-02 at 17:31 +0100, Thomas Huth wrote:
> Hardly anybody still uses 32-bit x86 environments for running QEMU,
> so let's stop wasting our scarce CI minutes with these jobs.
>
> Signed-off-by: Thomas Huth
> ---
> .gitlab-ci.d/crossbuilds.yml | 16
> 1 file changed,
On Thu, 2023-03-02 at 17:31 +0100, Thomas Huth wrote:
> Hardly anybody still uses 32-bit x86 hosts today, so we should start
> deprecating them to stop wasting our time and CI minutes here.
> For example, there are also still some unresolved problems with
> these:
> When emulating 64-bit binaries
Jonathan Cameron wrote:
> Very simple implementation to allow testing of corresponding
> kernel code. Note that for now we track each 64 byte section
> independently. Whilst a valid implementation choice, it may
> make sense to fuse entries so as to prove out more complex
> corners of the kernel
Jonathan Cameron wrote:
> Inject poison using qmp command cxl-inject-poison to add an entry to the
> poison list.
>
> For now, the poison is not returned CXL.mem reads, but only via the
> mailbox command Get Poison List.
>
> See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
>
>
On Thu, 2023-03-02 at 18:05 +, Daniel P. Berrangé wrote:
> On Thu, Mar 02, 2023 at 05:31:01PM +0100, Thomas Huth wrote:
> > Hardly anybody really requires the i386 binary anymore, since the
> > qemu-system-x86_64 binary is a proper superset. So let's deprecate
> > the 32-bit variant now, so
On 3/2/23 09:25, Alex Bennée wrote:
Instead of building gdb syscalls for every target only build what
really matters, 64 or 32 bit support.
Since the *only* usage of target_ulong is in the va_list for gdb_do_syscall, and as that
passes on to printf, we could just adjust the interface to
On 02/03/2023 18:42, Alex Williamson wrote:
> On Thu, 2 Mar 2023 00:07:35 +
> Joao Martins wrote:
>> On 28/02/2023 20:36, Alex Williamson wrote:
>>> On Tue, 28 Feb 2023 12:11:06 +
>>> Joao Martins wrote:
On 23/02/2023 21:50, Alex Williamson wrote:
> On Thu, 23 Feb 2023
On Thu, Mar 02, 2023 at 02:49:56PM +0300, Michael Tokarev wrote:
> There are some url'ifications slipped into this one:
>
> 02.03.2023 11:26, Michael S. Tsirkin пишет:
> ..
>
> > Message-Id: <20230214021430.3638579-1-yaj...@nvidia.com>
> > Reviewed-by: Marc-André Lureau
> > Signed-off-by: Yajun
On Thu, Mar 02, 2023 at 02:34:02PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 02.03.23 11:26, Michael S. Tsirkin wrote:
> > From: Vladimir Sementsov-Ogievskiy
> >
> > It should be zero, the only valid values are ON, OFF and BLINK.
>
> At any chance, fix s/should be/should not be/
fixed
On Thu, Mar 02, 2023 at 03:24:28AM -0500, Michael S. Tsirkin wrote:
> The following changes since commit 627634031092e1514f363fd8659a579398de0f0e:
>
> Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu
> into staging (2023-02-28 15:09:18 +)
>
> are available in
On Thu, Mar 02, 2023 at 11:40:40PM +0100, Philippe Mathieu-Daudé wrote:
> Since v2: rebased
>
> I'm posting this series as it to not block Bernhard's PIIX
> cleanup work. I don't have code change planned, but eventually
> reword / improve commit descriptions.
>
> Tested commit after commit to be
On 3/2/23 13:21, Richard Henderson wrote:
On 3/2/23 09:25, Alex Bennée wrote:
-# These have to built to the target ABI
-specific_ss.add(files('syscalls.c'))
+# These have to built to the target ABI but are otherwise target
+# independent
+gdb32_ss = ss.source_set()
+gdb64_ss = ss.source_set()
+
On Thu, Mar 02, 2023 at 03:47:48PM +0100, Eugenio Perez Martin wrote:
> On Thu, Mar 2, 2023 at 12:43 PM Michael S. Tsirkin wrote:
> >
> > On Thu, Mar 02, 2023 at 12:30:52PM +0100, Eugenio Perez Martin wrote:
> > > > You need to pass this to guest. My point is that there is no reason to
> > > >
On Thu, Mar 02, 2023 at 03:16:24PM +0300, Michael Tokarev wrote:
> 02.03.2023 11:24, Michael S. Tsirkin wrote:
> ..
> >https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
>
> It looks like this series contains quite a few changes which should be
> applied to -stable as
On 3/2/23 09:25, Alex Bennée wrote:
-# These have to built to the target ABI
-specific_ss.add(files('syscalls.c'))
+# These have to built to the target ABI but are otherwise target
+# independent
+gdb32_ss = ss.source_set()
+gdb64_ss = ss.source_set()
+
+gdb32_ss.add(files('syscalls.c'))
On Thu, Mar 02, 2023 at 01:07:16PM +0100, Igor Mammedov wrote:
> On Thu, 2 Mar 2023 05:59:16 -0500
> "Michael S. Tsirkin" wrote:
>
> > On Fri, Feb 24, 2023 at 04:37:39PM +0100, Igor Mammedov wrote:
> > > Series extends acpi-index support to host-bridge(s) and bridges
> > > with disabled hotplug
> No RUNC is defined in config-host.mak now because it can be docker or
podman.
I feel $(RUNC) isn't the right variable name as it can't be set to "runc".
If $(DOCKER) is not preferable either, $(CONTAINER_ENGINE) might be a
better name.
Mechanical change doing:
$ sed -i -e 's/PIIX4_PCI_DEVICE/PIIX4_ISA/g' $(git grep -l PIIX4_PCI_DEVICE)
$ sed -i -e 's/PIIX3_XEN_DEVICE/PIIX3_ISA_XEN/g' $(git grep -l
PIIX3_XEN_DEVICE)
$ sed -i -e 's/PIIX3_DEVICE/PIIX3_ISA/g' $(git grep -l PIIX3_DEVICE)
$ sed -i -e
Since pc_init1() has access to the ISABus*, retrieve the
ISA IRQs with isa_bus_get_irq().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc_piix.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 126b6c11df..1e90b9ff0d
We don't have any caller passing a NULL device argument,
so we can simplify, avoiding to access the global 'isabus'.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/isa-bus.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
Since v2: rebased
I'm posting this series as it to not block Bernhard's PIIX
cleanup work. I don't have code change planned, but eventually
reword / improve commit descriptions.
Tested commit after commit to be sure it is bisectable. Sadly
this was before Zoltan & Thomas report a problem with
Rename ide_init_ioport() as ide_bus_init_ioport_isa() to make
explicit it expects an ISA device. Move the declaration to
"hw/ide/isa.h" where it belongs.
Message-Id: <20230215161641.32663-13-phi...@linaro.org>
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
We always follow the same pattern when registering
coalesced portio:
- portio_list_init()
- portio_list_set_flush_coalesced()
- portio_list_add()
Factor these 3 operations in a single helper named
portio_list_register_flush_coalesced().
Drop portio_list_set_flush_coalesced() which is now
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ide/piix.c | 14 --
include/hw/ide/piix.h | 4
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index 41d60921e3..a36dac8469 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@
Unify PIIX ISA (PCI function #0) as:
pci-piix3 -> piix-isa (abstract base class)
PIIX3 -> piix3-isa (PIIX3 implementation)
PIIX3-xen -> piix3-isa-xen (PIIX3 implementation with Xen extensions)
piix4-isa -> piix4-isa (PIIX4 implementation)
Alias previous names in the
Last commit removed the last use of isa_get_irq(NULL).
Add an assertion to ensure we won't use that hack again.
Deprecate in favor of the BUS API: isa_bus_get_irq().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/isa-bus.c | 6 +++---
include/hw/isa/isa.h | 3 ++-
2 files changed, 5
We always follow the same pattern when registering
non-coalesced portio:
- portio_list_init()
- portio_list_add()
Factor these 2 operations in a single helper named
portio_list_register(). Since both calls become local
to ioport.c, reduce their scope by declaring them static.
Reviewed-by:
See rationale in commit 38b5d79b2e ("qom: add helper
macro DEFINE_TYPES()").
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/piix3.c | 53 +-
1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index
Previous commit ensured when entering isa_register_portio_list(),
'dev' is not NULL. Being a TYPE_ISA_DEVICE, the device must sit
on a ISA bus. This means isa_bus_new() as already been called
and 'isabus' can not be NULL.
Simplify by removing the 'isabus' NULL check in
isa_register_portio_list().
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