Re: [PATCH] qed: remove spurious BDRV_POLL_WHILE()

Am 09.03.2023 um 17:31 hat Stefan Hajnoczi geschrieben: > This looks like a copy-paste or merge error. BDRV_POLL_WHILE() is > already called above. It's not needed in the qemu_in_coroutine() case. > > Fixes: 9fb4dfc570ce ("qed: make bdrv_qed_do_open a coroutine_fn") > Signed-off-by: Stefan

[PULL v2 11/91] target/s390x: Drop tcg_temp_free from translate_vx.c.inc

Translators are no longer required to free tcg temporaries. Acked-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate_vx.c.inc | 143 1 file changed, 143

[PULL v2 06/91] target/mips: Drop tcg_temp_free from translate_addr_const.c

Translators are no longer required to free tcg temporaries. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/translate_addr_const.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/target/mips/tcg/translate_addr_const.c

[PULL v2 36/91] target/tricore: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-22-a...@rev.ng> Signed-off-by: Richard Henderson --- target/tricore/cpu-param.h | 1 - 1 file changed, 1

[PULL v2 37/91] target/xtensa: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-23-a...@rev.ng> Signed-off-by: Richard Henderson --- target/xtensa/cpu-param.h | 1 - 1 file changed, 1

[PULL v2 39/91] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS

The use of separate data/port variables is existing practice elsewhere, e.g. SBI, CBI. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/avr/translate.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/target/avr/translate.c

[PULL v2 12/91] target/s390x: Drop tcg_temp_free from translate.c

Translators are no longer required to free tcg temporaries. Acked-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 105 --- 1 file changed, 105

[PULL v2 53/91] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/translate/vmx-impl.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index ee656d6a44..7af6d7217d 100644 ---

[PULL v2 81/91] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc

All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/translate/vmx-impl.c.inc | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[PULL v2 05/91] target/mips: Drop tcg_temp_free from octeon_translate.c

Translators are no longer required to free tcg temporaries. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/octeon_translate.c | 23 --- 1 file changed, 23 deletions(-) diff --git a/target/mips/tcg/octeon_translate.c

[PULL v2 49/91] target/mips: Split out gen_lxr

Common subroutine for LDR and LWR. Use tcg_constant_tl of ~1 instead of tcg_const_tl of 0x..fe. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/translate.c | 116 +--- 1 file changed, 40 insertions(+), 76 deletions(-)

[PATCH v8 11/11] target/arm: gdbstub: Guard pauth code with CONFIG_TCG

We currently don't have the reading of pauth regs implemented for KVM so wrap the pauth registration with CONFIG_TCG. This avoids the build error when using --disable-tcg: libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub64.c.o: in function `aarch64_gdb_get_pauth_reg':

[PULL v2 73/91] target/arm: Improve trans_BFCI

Reorg temporary usage so that we can use tcg_constant_i32. tcg_gen_deposit_i32 already has a width == 32 special case, so remove the check here. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate.c | 13 + 1 file changed, 5

[PULL v2 89/91] target/tricore: Use min/max for saturate

Use tcg_constant_i32 for the bounds. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/tricore/translate.c | 14 +++--- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index

[PATCH v8 03/11] target/arm: Move aa32_max_features out of cpu_tcg.c

In preparation to moving the cpu_tcg.c code into a 32-bit, tcg-only file, move the aa32_max_features function which is shared between 32/64/tcg/non-tcg into cpu.c. Signed-off-by: Fabiano Rosas --- target/arm/cpu.c | 69 target/arm/cpu_tcg.c | 69

[PATCH v2 1/2] target/m68k: Reject immediate as destination in gen_ea_mode

In theory this should never happen, as all such instructions are illegal. This is checked in e.g. gen_lea_mode and gen_ea_mode_fp but not here. In case something higher up isn't checking modes properly, return NULL_QREG. This will result in an illegal instruction exception being raised.

Re: [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig

On 3/9/23 04:13, Weiwei Li wrote: Use riscv_cpu_cfg(env) instead of env_archcpu().cfg. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu_helper.c | 9 - target/riscv/csr.c| 40

Re: [PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState

On 3/9/23 04:13, Weiwei Li wrote: Use CPURISCVState as argument directly in riscv_cpu_update_mip and riscv_timer_write_timecmp, since type converts from CPURISCVState to RISCVCPU in many caller of them and then back to CPURISCVState in them. Signed-off-by: Weiwei Li Signed-off-by: Junqiang

Re: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env

On 3/9/23 04:13, Weiwei Li wrote: Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- Reviewed-by: Daniel Henrique Barboza target/riscv/pmu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[PATCH v7 0/6] migration: reduce time of loading non-iterable vmstate

In this version: - introduce address_space_to_flatview_rcu() - squash peter's fix into patch 1 - rebase to latest upstream - update test results The duration of loading non-iterable vmstate accounts for a significant portion of downtime (starting with the timestamp of source qemu stop and

[PATCH v7 3/6] memory: Introduce memory_region_transaction_do_commit()

Split memory_region_transaction_do_commit() from memory_region_transaction_commit(). We'll call do_commit() in address_space_to_flatview() in the later patch. Signed-off-by: Chuang Xu --- softmmu/memory.c | 47 +++ 1 file changed, 27 insertions(+),

[PATCH v7 1/6] memory: Reference as->current_map directly in memory commit

From: Peter Xu Calling RCU variance of address_space_get|to_flatview() during memory commit (flatview updates, triggering memory listeners, or updating ioeventfds, etc.) is not 100% accurate, because commit() requires BQL rather than RCU read lock, so the context exclusively owns current_map and

[PATCH v7 5/6] migration: Reduce time of loading non-iterable vmstate

The duration of loading non-iterable vmstate accounts for a significant portion of downtime (starting with the timestamp of source qemu stop and ending with the timestamp of target qemu start). Most of the time is spent committing memory region changes repeatedly. This patch packs all the changes

[PATCH v7 4/6] memory: Add sanity check in address_space_to_flatview

Before using any flatview, sanity check whether BQL or rcu is held. And if we're during a memory region transaction, try to immediately update mappings, or the map can be invalid. Signed-off-by: Chuang Xu --- include/exec/memory.h | 23 +++ softmmu/memory.c | 5 +

[PATCH v7 2/6] rcu: Introduce rcu_read_is_locked()

Add rcu_read_is_locked() to detect holding of rcu lock. Signed-off-by: Chuang Xu --- include/qemu/rcu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/qemu/rcu.h b/include/qemu/rcu.h index 313fc414bc..7bf45602e1 100644 --- a/include/qemu/rcu.h +++ b/include/qemu/rcu.h @@

[PATCH v7 6/6] memory: Introduce address_space_to_flatview_rcu()

In last patch, we wrap vm_load with begin/commit, here we introduce address_space_to_flatview_rcu() to avoid unnecessary enforce commit during vm_load. Signed-off-by: Chuang Xu --- include/exec/memory-internal.h | 2 +- include/exec/memory.h | 20 softmmu/memory.c

Re: [PATCH v15 15/60] i386/xen: add pc_machine_kvm_type to initialize XEN_EMULATE mode

On 3/1/2023 9:51 PM, David Woodhouse wrote: From: David Woodhouse The xen_overlay device (and later similar devices for event channels and grant tables) need to be instantiated. Do this from a kvm_type method on the PC machine derivatives, since KVM is only way to support Xen emulation for

Re: [PATCH] Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions

On Tue, Feb 28, 2023 at 12:53 AM Mikhail Tyutin wrote: > > Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg > instructions > > Signed-off-by: Mikhail Tyutin It looks like this needs to be rebased. Do you mind rebasing it and sending a v2? Alistair > --- > disas/riscv.c

Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap

On 2023/3/8 20:34, chenyi2...@zju.edu.cn wrote: From: Yi Chen Trap accesses to hgatp if MSTATUS_TVM is enabled. Don't trap accesses to vsatp even if MSTATUS_TVM is enabled. By the way, do you know why mstatus_tvm and hstatus_tvm are needed? The specification said, The TVM mechanism

Re: [PATCH] Fix slli_uw decoding

On Mon, Feb 27, 2023 at 7:06 PM Ivan Klokov wrote: > > The decoding of the slli_uw currently contains decoding > error: shamt part of opcode has six bits, not five. > > Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw") > > Signed-off-by: Ivan Klokov Acked-by: Alistair

Re: [PATCH v2 14/18] ui/sdl: add optional logging when _SDL_DEBUG is set

Hi (adding Sam Lantinga, SDL maintainer, in CC. I noticed he worked on QEMU SDL backend yesterday! ;) On Thu, Mar 9, 2023 at 8:40 PM Philippe Mathieu-Daudé wrote: > On 7/3/23 12:56, marcandre.lur...@redhat.com wrote: > > From: Marc-André Lureau > > > > Apparently, there is no environment

Re: [PATCH] Fix slli_uw decoding

On Mon, Feb 27, 2023 at 7:06 PM Ivan Klokov wrote: > > The decoding of the slli_uw currently contains decoding > error: shamt part of opcode has six bits, not five. > > Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw") > > Signed-off-by: Ivan Klokov Thanks! Applied

Re: [RFC PATCH 1/2] gtk: Make sure widget is realized before updating

On Wed, Mar 8, 2023 at 8:26 PM Damian Hobson-Garcia wrote: > Check that a widget has a window before trying > to update its contents. > --- > ui/gtk.c | 4 > 1 file changed, 4 insertions(+) > Reviewed-by: Marc-André Lureau > > diff --git a/ui/gtk.c b/ui/gtk.c > index

Re: [PULL 3/3] edk2: update firmware binaries

On Thu, Mar 09, 2023 at 02:09:30PM -0800, Simon Glass wrote: > Hi Gerd, > > Where did these binaries come from? What commit and how were they built? See patch 1/3 for the source (edk2 submodule) update and patch 2/3 for the build scripts. take care, Gerd

Re: [PATCH] hvf: arm: Add support for GICv3

On Mon, Dec 19, 2022 at 2:08 PM Alexander Graf wrote: > > We currently only support GICv2 emulation. To also support GICv3, we will > need to pass a few system registers into their respective handler functions. > > This patch adds support for HVF to call into the TCG callbacks for GICv3 > system

Re: [PATCH 1/2] hw/intc/arm_gicv3: Make ITT entry size configurable

On Fri, Dec 23, 2022 at 12:50 AM Alexander Graf wrote: > > An ITT entry is opaque to the OS. The only thing it does get told by HW is > its size. In theory, that size can be any byte aligned number, in practice > HW will always use power of 2s to simplify offset calculation. We currently > expose

RE: [PATCH] intel-iommu: Set status bit after operation completed

Hi Peter >-Original Message- >From: Peter Xu >Sent: Thursday, March 9, 2023 10:56 PM >To: Duan, Zhenzhong >Cc: qemu-devel@nongnu.org; m...@redhat.com; jasow...@redhat.com; >pbonz...@redhat.com; richard.hender...@linaro.org; edua...@habkost.net; >marcel.apfelb...@gmail.com >Subject: Re:

Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB

On Sun, Mar 5, 2023 at 7:43 PM Jim Shu wrote: > > This patch also enables debugger to set current privilege mode to > VU/VS-mode. > > Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to > support H-extension. I'm not sure we want this. What is the use case for this? Changing the

Re: [PATCH v7] audio/pwaudio.c: Add Pipewire audio backend for QEMU

Hi Dorinda, I've started to write down my suggestions and comments. After more than one page of text, I think that without sample code, the text is not very understandable. Therefore I will write three mails. In this mail I describe the problem with the QEMU Pipewire audio backend. My next

[PULL v2 75/91] target/arm: Avoid tcg_const_* in translate-mve.c

All uses are in the context of an accumulator conditionally having a zero input. Split the rda variable to rda_{i,o}, and set rda_i to tcg_constant_foo(0) when required. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-mve.c | 54

[PULL v2 48/91] target/mips: Split out gen_lxl

Common subroutine for LDL and LWL. Use tcg_constant_tl instead of tcg_const_tl and t2. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/translate.c | 106 1 file changed, 36 insertions(+), 70 deletions(-) diff --git

[PULL v2 52/91] target/ppc: Split out gen_vx_vmul10

Move the body out of this large macro. Use tcg_constant_i64. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/translate/vmx-impl.c.inc | 95 +++-- 1 file changed, 49 insertions(+), 46 deletions(-) diff --git

[PULL v2 63/91] target/tricore: Rename t_off10 and use tcg_constant_i32

While temp3 could simply be initialized with tcg_constant_i32, the renaming makes the purpose clearer. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/tricore/translate.c | 56 ++ 1 file changed, 27 insertions(+), 29

[PULL v2 68/91] target/arm: Use rmode >= 0 for need_rmode

Initialize rmode to -1 instead of keeping two variables. This is already used elsewhere in translate-a64.c. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 34 ++ 1 file changed, 6 insertions(+), 28

[PULL v2 27/91] target/mips: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-13-a...@rev.ng> Signed-off-by: Richard Henderson --- target/mips/cpu-param.h | 1 - 1 file changed, 1

[PULL v2 77/91] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn

It is easy enough to use mov instead of or-with-zero and relying on the optimizer to fold away the or. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git

[PULL v2 61/91] tcg/sparc: Avoid tcg_const_tl in gen_edge

Push tcg_constant_tl into the shift argument directly. Since t1 no longer exists as a temp, replace with lo1, whose last use was just above. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 14 ++ 1 file changed, 6 insertions(+), 8

[PATCH v2 1/6] block: don't acquire AioContext lock in bdrv_drain_all()

There is no need for the AioContext lock in bdrv_drain_all() because nothing in AIO_WAIT_WHILE() needs the lock and the condition is atomic. AIO_WAIT_WHILE_UNLOCKED() has no use for the AioContext parameter other than performing a check that is nowadays already done by the

[PULL v2 56/91] target/rx: Avoid tcg_const_i32 when new temp needed

These three cases use a constant as first input, and then overwrite the temp in the output. Separate them. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/rx/translate.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git

[PULL v2 71/91] target/arm: Consistently use ARMFPRounding during translation

In preparation for extracting new helpers, ensure that the rounding mode is represented as ARMFPRounding and not FloatRoundMode. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 16 target/arm/tcg/translate-sve.c | 18

[PULL v2 64/91] target/tricore: Use setcondi instead of explicit allocation

This removes the only use of temp. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/tricore/translate.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 19cf4b6cc7..6b2065803f

[PULL v2 42/91] target/hppa: Avoid tcg_const_i64 in trans_fid_f

Use a C test instead of a pre-processor test for the id. Use tcg_constant_i64 instead of tcg_const_i64. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git

[PULL v2 21/91] target/hexagon: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-7-a...@rev.ng> Signed-off-by: Richard Henderson --- target/hexagon/cpu-param.h | 2 -- 1 file changed, 2

[PULL v2 74/91] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}

This hides the implicit initialization of a variable. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-sve.c

[PULL v2 17/91] target/alpha: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-3-a...@rev.ng> Signed-off-by: Richard Henderson --- target/alpha/cpu-param.h | 2 -- 1 file changed, 2

[PULL v2 29/91] target/openrisc: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-15-a...@rev.ng> Signed-off-by: Richard Henderson --- target/openrisc/cpu-param.h | 1 - 1 file changed, 1

[PULL v2 76/91] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn

It is easy enough to use mov instead of or-with-zero and relying on the optimizer to fold away the or. Use an array for the output, rather than separate tcg_res{l,h} variables. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 41

[PATCH v8 10/11] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG

This code is only relevant when TCG is present in the build. If we try to build with --disable-tcg we currently get: libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_ptr': ../target/arm/gdbstub.c:356: undefined reference to `arm_v7m_get_sp_ptr' Signed-off-by: Fabiano

[PULL v2 87/91] target/ppc: Fix gen_tlbsx_booke206

Fix incorrect read from rD. Avoid adding 0 when rA == 0. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/translate.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index

Re: [PATCH] Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions

On Tue, Feb 28, 2023 at 12:53 AM Mikhail Tyutin wrote: > > Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg > instructions > > Signed-off-by: Mikhail Tyutin Reviewed-by: Alistair Francis Alistair > --- > disas/riscv.c | 19 ++- > 1 file changed, 10

[PATCH v8 02/11] target/arm: Move 64-bit TCG CPUs into tcg/

Move the 64-bit CPUs that are TCG-only: - cortex-a35 - cortex-a55 - cortex-a72 - cortex-a76 - a64fx - neoverse-n1 Keep the CPUs that can be used with KVM: - cortex-a57 - cortex-a53 - max - host For the special case "max" CPU, there's a nuance that while KVM/HVF use the "host" model instead, we

[PULL v2 51/91] target/mips: Avoid tcg_const_* throughout

All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/mxu_translate.c | 4 +- target/mips/tcg/translate.c | 56 +++ target/mips/tcg/tx79_translate.c | 4 +-

[PULL v2 88/91] target/ppc: Avoid tcg_const_* in translate.c

All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/translate.c | 142 + 1 file changed, 72 insertions(+), 70 deletions(-) diff --git

[PULL v2 59/91] target/sh4: Avoid tcg_const_i32 for TAS.B

Since we're assigning to cpu_sr_t in the end, use that as the intermediate temp as well. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/translate.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/sh4/translate.c

[PULL v2 82/91] target/ppc: Avoid tcg_const_* in xxeval

Initialize a new temp instead of tcg_const_*. Fix a pasto in a comment. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/translate/vsx-impl.c.inc | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git

[PULL v2 84/91] target/ppc: Avoid tcg_const_* in fp-impl.c.inc

All uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/translate/fp-impl.c.inc | 26 -- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git

[PATCH v2 2/2] linux-user/m68k: Handle EXCP_ADDRESS in cpu_loop

This exception can be raised by illegal instructions. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 5 - tests/tcg/m68k/excp-address.c | 32 tests/tcg/m68k/Makefile.target | 1 + 3 files changed, 37 insertions(+), 1 deletion(-)

[PULL v2 86/91] target/ppc: Rewrite trans_ADDG6S

Compute all carry bits in parallel instead of a loop. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/translate/fixedpoint-impl.c.inc | 44 +++--- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git

[PULL v2 79/91] target/m68k: Use tcg_constant_i32 in gen_ea_mode

Return a constant for an immediate input. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 44c3ac0bc3..422f4652f1 100644

Re: [PATCH v6 2/4] qapi: add DEVICE_ON and query-hotplug infrastructure

On 07.03.23 20:31, Michael S. Tsirkin wrote: On Tue, Mar 07, 2023 at 07:05:35PM +0300, Vladimir Sementsov-Ogievskiy wrote: We have DEVICE_DELETED event, that signals that device_del command is actually completed. But we don't have a counter-part for device_add. Still it's sensible for SHPC and

Re: [PATCH for-8.0] ide: Fix manual in-flight count for TRIM BH

Am 09.03.2023 um 14:59 hat Paolo Bonzini geschrieben: > On 3/9/23 13:31, Hanna Czenczek wrote: > > On 09.03.23 13:08, Paolo Bonzini wrote: > > > On Thu, Mar 9, 2023 at 1:05 PM Paolo Bonzini wrote: > > > > I think having to do this is problematic, because the blk_drain should > > > > leave no

[PATCH v2 3/6] block: convert bdrv_graph_wrlock() to AIO_WAIT_WHILE_UNLOCKED()

The following conversion is safe and does not change behavior: GLOBAL_STATE_CODE(); ... - AIO_WAIT_WHILE(qemu_get_aio_context(), ...); + AIO_WAIT_WHILE_UNLOCKED(NULL, ...); Since we're in GLOBAL_STATE_CODE(), qemu_get_aio_context() is our home thread's AioContext. Thus

[PATCH v2 2/6] block: convert blk_exp_close_all_type() to AIO_WAIT_WHILE_UNLOCKED()

There is no change in behavior. Switch to AIO_WAIT_WHILE_UNLOCKED() instead of AIO_WAIT_WHILE() to document that this code has already been audited and converted. The AioContext argument is already NULL so aio_context_release() is never called anyway. Reviewed-by: Philippe Mathieu-Daudé

[PATCH v2 6/6] monitor: convert monitor_cleanup() to AIO_WAIT_WHILE_UNLOCKED()

monitor_cleanup() is called from the main loop thread. Calling AIO_WAIT_WHILE(qemu_get_aio_context(), ...) from the main loop thread is equivalent to AIO_WAIT_WHILE_UNLOCKED(NULL, ...) because neither unlocks the AioContext and the latter's assertion that we're in the main loop succeeds.

[PATCH v2 5/6] hmp: convert handle_hmp_command() to AIO_WAIT_WHILE_UNLOCKED()

The HMP monitor runs in the main loop thread. Calling AIO_WAIT_WHILE(qemu_get_aio_context(), ...) from the main loop thread is equivalent to AIO_WAIT_WHILE_UNLOCKED(NULL, ...) because neither unlocks the AioContext and the latter's assertion that we're in the main loop succeeds. Reviewed-by:

[PATCH v2 0/6] block: switch to AIO_WAIT_WHILE_UNLOCKED() where possible

v2: - Clarify NULL ctx argument in Patch 1 commit description [Kevin] AIO_WAIT_WHILE_UNLOCKED() is the future replacement for AIO_WAIT_WHILE(). Most callers haven't been converted yet because they rely on the AioContext lock. I looked through the code and found the easy cases that can be

[PATCH v2 4/6] block: convert bdrv_drain_all_begin() to AIO_WAIT_WHILE_UNLOCKED()

Since the AioContext argument was already NULL, AIO_WAIT_WHILE() was never going to unlock the AioContext. Therefore it is possible to replace AIO_WAIT_WHILE() with AIO_WAIT_WHILE_UNLOCKED(). Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Kevin Wolf

Re: [PATCH] hw/intc/ioapic: Update KVM routes before redelivering IRQ, on RTE update

On Thu, 2023-03-09 at 11:55 -0500, Peter Xu wrote: > On Thu, Mar 09, 2023 at 09:16:08AM +, David Woodhouse wrote: > > The only IRQs that are handled fully in the kernel are events arriving > > on some eventfd which is bound as an IRQFD to some IRQ in the KVM > > routing table. (Mostly MSIs

[PULL v2 20/91] target/cris: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-6-a...@rev.ng> Signed-off-by: Richard Henderson --- target/cris/cpu-param.h | 1 - 1 file changed, 1 deletion(-)

[PULL v2 35/91] target/sparc: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-21-a...@rev.ng> Signed-off-by: Richard Henderson --- target/sparc/cpu-param.h | 2 -- 1 file changed, 2

[PULL v2 34/91] target/sh4: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-20-a...@rev.ng> Signed-off-by: Richard Henderson --- target/sh4/cpu-param.h | 1 - 1 file changed, 1 deletion(-)

[PULL v2 19/91] target/avr: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-5-a...@rev.ng> Signed-off-by: Richard Henderson --- target/avr/cpu-param.h | 1 - 1 file changed, 1 deletion(-)

[PULL v2 33/91] target/s390x: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-19-a...@rev.ng> Signed-off-by: Richard Henderson --- target/s390x/cpu-param.h | 1 - 1 file changed, 1

[PULL v2 26/91] target/microblaze: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-12-a...@rev.ng> Signed-off-by: Richard Henderson --- target/microblaze/cpu-param.h | 1 -

[PULL v2 13/91] target/s390x: Remove assert vs g_in2

These were trying to determine if o->in2 was available for use as a temporary. It's better to just allocate a new one. Acked-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 20

[PULL v2 18/91] target/arm: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-4-a...@rev.ng> Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 -- 1 file changed, 2

[PULL v2 16/91] include/exec: Set default `NB_MMU_MODES` to 16

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-2-a...@rev.ng> Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 11 --- 1 file changed, 8

[PULL v2 28/91] target/nios2: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-14-a...@rev.ng> Signed-off-by: Richard Henderson --- target/nios2/cpu-param.h | 1 - 1 file changed, 1

[PULL v2 24/91] target/loongarch: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-10-a...@rev.ng> Signed-off-by: Richard Henderson --- target/loongarch/cpu-param.h | 1 - 1 file changed, 1

[PULL v2 02/91] target/mips: Drop tcg_temp_free from msa_translate.c

Translators are no longer required to free tcg temporaries. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/msa_translate.c | 9 - 1 file changed, 9 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c

[PULL v2 23/91] target/i386: Remove `NB_MMU_MODES` define

From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20230306175230.7110-9-a...@rev.ng> Signed-off-by: Richard Henderson --- target/i386/cpu-param.h | 1 - 1 file changed, 1 deletion(-)

[PULL v2 60/91] target/sh4: Avoid tcg_const_i32

All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/translate.c | 26 +- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index

[PATCH v8 01/11] target/arm: Move cortex sysregs into a separate file

The file cpu_tcg.c is about to be moved into the tcg/ directory, so move the register definitions into a new file. Also move the function declaration to the more appropriate cpregs.h. Reviewed-by: Richard Henderson Signed-off-by: Fabiano Rosas --- target/arm/cortex-regs.c | 69

[PATCH v8 06/11] arm/Kconfig: Do not build TCG-only boards on a KVM-only build

Move all the CONFIG_FOO=y from default.mak into "default y if TCG" statements in Kconfig. That way they won't be selected when CONFIG_TCG=n. I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to keep the two default.mak files not empty and keep aarch64-default.mak including

[PATCH v8 04/11] target/arm: move cpu_tcg to tcg/cpu32.c

From: Claudio Fontana move the module containing cpu models definitions for 32bit TCG-only CPUs to tcg/ and rename it for clarity. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Acked-by: Thomas Huth Signed-off-by: Fabiano Rosas --- hw/arm/virt.c | 2

[PATCH v8 09/11] tests/avocado: Pass parameters to migration test

The migration tests are currently broken for an aarch64 host because the tests pass no 'machine' and 'cpu' options on the QEMU command line. Add a separate class to each architecture so that we can specify 'machine' and 'cpu' options instead of relying on defaults. Add a skip decorator to keep

[PULL v2 83/91] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc

All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/translate/vsx-impl.c.inc | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git

[PATCH v2 0/2] target/m68k: Reject immediate as destination

The translate.c fix is extracted from a larger patch set. I then add a test case and fix cpu_loop to raise the proper signal. r~ Richard Henderson (2): target/m68k: Reject immediate as destination in gen_ea_mode linux-user/m68k: Handle EXCP_ADDRESS in cpu_loop linux-user/m68k/cpu_loop.c

[PULL v2 78/91] target/arm: Avoid tcg_const_ptr in handle_rev

Here it is not trivial to notice first initialization, so explicitly zero the temps. Use an array for the output, rather than separate tcg_rd/tcg_rd_hi variables. Fixes a bug by adding a missing clear_vec_high. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson ---

[PATCH v8 00/11] target/arm: Allow CONFIG_TCG=n builds

Changes since v7: - patch 8: moved calls to qtest_has_accel after g_test_init to avoid the TAP error; - moved the avocado patch towards the end of the series so we can merge the rest without it if needed; - two new patches to fix regressions due to gdbstub changes. CI run:

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