On 6/2/23 08:52, Peter Maydell wrote:
Convert the MSR (immediate) insn to decodetree. Our implementation
has basically no commonality between the different destinations,
so we decode the destination register in a64.decode.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 13
On 2023/6/3 1:47, Eugenio Perez Martin wrote:
> On Fri, Jun 2, 2023 at 1:52 PM Hawkins Jiawei wrote:
>>
>> This series enables shadowed CVQ to intercept Offloads commands
>> through shadowed CVQ, update the virtio NIC device model so qemu
>> send it in a migration, and the restore of that
在 2023/5/23 21:07, Philippe Mathieu-Daudé 写道:
> On 23/5/23 13:18, Jiaxun Yang wrote:
>>
>>
>>> 2023年5月23日 11:01，Song Gao 写道：
>>>
>>>
>>>
>>> 在 2023/5/23 上午11:22, Jiaxun Yang 写道:
>> [...]
>
Is totally the same on MIPS and LoongArch. I’m guarding them out because
We have
02.06.2023 01:02, Eric Blake пишет:
While we were matching 32-bit strtol in qemu_strtoi, our use of a
64-bit parse was leaking through for some inaccurate answers in
qemu_strtoui in comparison to a 32-bit strtoul (see the unit test for
examples). The comment for that function even described
在 2023/5/21 下午6:23, Jiaxun Yang 写道:
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
Loongson 3A5000's IPI implementation have 4 mailboxes per
core.
However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
percpu device"), the number of IPI mailboxes was reduced to
one, which
On 6/2/23 08:52, Peter Maydell wrote:
Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are
all essentially the same instruction (system register access).
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 8
target/arm/tcg/translate-a64.c | 32
> 2023年6月3日 01:28，Peter Maydell 写道：
>
> On Sun, 21 May 2023 at 11:24, Jiaxun Yang wrote:
>>
>> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
>> Loongson 3A5000's IPI implementation have 4 mailboxes per
>> core.
>>
>> However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
On 6/2/23 08:52, Peter Maydell wrote:
Convert the exception generation instructions SVC, HVC, SMC, BRK and
HLT to decodetree.
The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and
DCPS3 just in order to then make them UNDEF; as with DRPS, we don't
bother to decode them, but document
在 2023/6/3 下午3:06, Jiaxun Yang 写道:
2023年6月3日 01:28，Peter Maydell 写道：
On Sun, 21 May 2023 at 11:24, Jiaxun Yang wrote:
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
Loongson 3A5000's IPI implementation have 4 mailboxes per
core.
However, in 78464f023b54
- PI_FIRMWARE_*_RATE constsnts were moved to raspberrypi-fw-defs.h
(seems more suitable place for them)
- inclusion of "qemu/osdep.h" has been removed
- year in copyright header has been updated
Signed-off-by: Sergey Kambalin
---
hw/misc/bcm2835_property.c| 120
On Sat, 3 Jun 2023 at 04:34, Richard Henderson
wrote:
>
> Start adding infrastructure for accelerating guest AES.
> Begin with a SubBytes + ShiftRows primitive.
>
> Signed-off-by: Richard Henderson
> ---
> host/include/generic/host/aes-round.h | 15 +
> include/crypto/aes-round.h
On Sat, 3 Jun 2023 at 04:34, Richard Henderson
wrote:
>
> Inspired by Ard Biesheuvel's RFC patches for accelerating AES
> under emulation, provide a set of primitives that maps between
> the guest and host fragments.
>
> There is a small guest correctness test case.
>
> I think the end result is
On 3/6/23 06:09, Richard Henderson wrote:
On 6/2/23 14:17, Philippe Mathieu-Daudé wrote:
On 31/5/23 06:03, Richard Henderson wrote:
Create helper-gen-common.h without the target specific portion.
Use that in tcg-op-common.h. Reorg headers in target/arm to
ensure that helper-gen.h is included
On 3/6/23 06:04, Richard Henderson wrote:
On 6/2/23 14:29, Philippe Mathieu-Daudé wrote:
On 31/5/23 06:02, Richard Henderson wrote:
Create tcg/tcg-op-common.h, moving everything that does not concern
TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header
instead of tcg-op.h, in
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 10 --
1 file changed, 4 insertions(+), 6
On 6/3/23 05:45, Ard Biesheuvel wrote:
On Sat, 3 Jun 2023 at 04:34, Richard Henderson
wrote:
We do not currently have a table in crypto/ for
just MixColumns. Move both tables for consistency.
Signed-off-by: Richard Henderson
---
include/crypto/aes.h | 6 ++
crypto/aes.c
On 6/3/23 06:15, Ard Biesheuvel wrote:
diff --git a/crypto/aes.c b/crypto/aes.c
index 1309a13e91..708838315a 100644
--- a/crypto/aes.c
+++ b/crypto/aes.c
@@ -29,6 +29,7 @@
*/
#include "qemu/osdep.h"
#include "crypto/aes.h"
+#include "crypto/aes-round.h"
typedef uint32_t u32;
typedef
On Fri, Jun 02, 2023 at 07:58:30PM -0700, Richard Henderson wrote:
> On 6/2/23 07:02, Andrew Jones wrote:
> > > +struct riscv_hwprobe {
> > > +int64_t key;
> > > +uint64_t value;
> > > +};
> >
> > The above is all uapi so Linux's arch/riscv/include/uapi/asm/hwprobe.h
> > should be picked
On 6/3/23 05:50, Ard Biesheuvel wrote:
On Sat, 3 Jun 2023 at 04:34, Richard Henderson
wrote:
Detect AES in cpuinfo; implement the accel hooks.
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/aes-round.h | 204 ++
host/include/aarch64/host/cpuinfo.h
Fixes an assert in tcg_gen_code that we don't accidentally
eliminate an insn_start during optimization.
Signed-off-by: Richard Henderson
---
Test case is tests/tcg/multiarch/testthread.c; the assert for
equality is new with
On 6/3/23 10:46, Michael Tokarev wrote:
03.06.2023 18:03, Guenter Roeck wrote:
Hi,
On Tue, May 02, 2023 at 01:14:55PM +0100, Peter Maydell wrote:
The Allwinner PIC model uses set_bit() and clear_bit() to update the
values in its irq_pending[] array when an interrupt arrives. However
it is
On Sat, 3 Jun 2023 at 04:34, Richard Henderson
wrote:
>
> We do not currently have a table in crypto/ for
> just MixColumns. Move both tables for consistency.
>
> Signed-off-by: Richard Henderson
> ---
> include/crypto/aes.h | 6 ++
> crypto/aes.c | 142
On 3/6/23 06:34, Richard Henderson wrote:
On 6/2/23 14:25, Philippe Mathieu-Daudé wrote:
On 31/5/23 06:02, Richard Henderson wrote:
133 files changed, 3022 insertions(+), 2728 deletions(-)
create mode 100644 include/exec/helper-gen-common.h
create mode 100644
On 2023/6/3 05:01, Richard Henderson wrote:
On 6/1/23 18:31, Weiwei Li wrote:
Even though MPRV normally can be set to 1 in M mode, it seems
possible to set it to 1 in other mode by gdbstub.
That would seem to be a gdbstub bug, since it is cleared on exit from
M-mode, and cannot be set
Hi,
On Tue, May 02, 2023 at 01:14:55PM +0100, Peter Maydell wrote:
> The Allwinner PIC model uses set_bit() and clear_bit() to update the
> values in its irq_pending[] array when an interrupt arrives. However
> it is using these functions wrongly: they work on an array of type
> 'long', and it
On Fri, 2 Jun 2023 at 21:51, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 2/6/23 17:52, Peter Maydell wrote:
> > Convert the LDR and STR instructions which use a 12-bit immediate
> > offset to decodetree. We can reuse the existing LDR and STR
> > trans functions for these.
> >
> >
02.06.2023 20:48, Peter Maydell wrote:
@@ -11574,7 +11574,7 @@ static abi_long do_syscall1(CPUArchState *cpu_env, int
num, abi_long arg1,
g_autofree gid_t *grouplist = NULL;
int i;
-if (gidsetsize > NGROUPS_MAX) {
+if (gidsetsize >
There are 2 paits of identical code (with different types)
for TARGET_NR_setgroups and TARGET_NR_setgroups32, and
for TARGET_NR_getgroups and TARGET_NR_getgroups32. Add
comments stating this fact, so that further modifications
are done in two places.
Signed-off-by: Michael Tokarev
---
Please
On 6/3/23 08:50, Andrew Jones wrote:
On Fri, Jun 02, 2023 at 07:58:30PM -0700, Richard Henderson wrote:
On 6/2/23 07:02, Andrew Jones wrote:
+struct riscv_hwprobe {
+int64_t key;
+uint64_t value;
+};
The above is all uapi so Linux's arch/riscv/include/uapi/asm/hwprobe.h
should be
03.06.2023 18:03, Guenter Roeck wrote:
Hi,
On Tue, May 02, 2023 at 01:14:55PM +0100, Peter Maydell wrote:
The Allwinner PIC model uses set_bit() and clear_bit() to update the
values in its irq_pending[] array when an interrupt arrives. However
it is using these functions wrongly: they work on
On Sat, 3 Jun 2023 at 04:34, Richard Henderson
wrote:
>
> Detect AES in cpuinfo; implement the accel hooks.
>
> Signed-off-by: Richard Henderson
> ---
> host/include/aarch64/host/aes-round.h | 204 ++
> host/include/aarch64/host/cpuinfo.h | 1 +
>
Upon MRET or explicit memory access with MPRV=1, MPV should be ignored
when MPP=PRV_M.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 3 ++-
target/riscv/op_helper.c | 3 ++-
2 files
This patchset tries to fix some problems in the fields of mstatus, such as make
MPV only work when MPP != PRM.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-mpv-upstream-v2
v2:
* Drop patch 3 (remove check on mode M for MPRV)
* rebase on apply-to-riscv.next
Weiwei
SXL is initialized as env->misa_mxl which is also the mxl value.
So we can just remain it unchanged to keep it read-only.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 4
1 file changed,
02.06.2023 20:48, Peter Maydell wrote:
Coverity doesn't like the way we might end up calling getgroups()
with a NULL grouplist pointer. This is fine for the special case
of gidsetsize == 0, but we will also do it if the guest passes
us a negative gidsetsize. (CID 1512465)
Explicitly fail the
On 31/05/2023 21:35, Philippe Mathieu-Daudé wrote:
Introduce the ARM_TIMER sysbus device.
arm_timer_new() is converted as QOM instance init()/finalize()
handlers. Note in arm_timer_finalize() we release a ptimer handle
which was previously leaked.
ArmTimerState is directly embedded into
On 03/06/2023 19:07, Mark Cave-Ayland wrote:
On 31/05/2023 21:35, Philippe Mathieu-Daudé wrote:
Introduce the ARM_TIMER sysbus device.
arm_timer_new() is converted as QOM instance init()/finalize()
handlers. Note in arm_timer_finalize() we release a ptimer handle
which was previously leaked.
On 6/2/23 08:52, Peter Maydell wrote:
+# Load/store single structure
+
+%ldst_single_selem 13:1 21:1 !function=plus_1
+# The index is made up from bits Q, S and the size; we may then need to scale
+# it down by the size.
+%ldst_single_index q:1 s:1 sz:2
+%ldst_single_index_scaled q:1 s:1 sz:2
On 6/2/23 08:52, Peter Maydell wrote:
Convert the instructions in the load/store memory tags instruction
group to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 25 +++
target/arm/tcg/translate-a64.c | 352 -
2 files changed,
Still missing review: 1, 20, 25, 27.
r~
On 5/30/23 21:02, Richard Henderson wrote:
The goal here is only tcg/, leaving accel/tcg/ for future work.
Changes for v3:
* Prerequisites and 3 patches merged.
r~
Richard Henderson (48):
tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL
On Fri, 2023-06-02 at 18:21 +0100, Peter Maydell wrote:
> On Mon, 16 Jan 2023 at 22:36, Richard Henderson
> wrote:
> >
> > From: Ilya Leoshkevich
> >
> > Add ability to dump /tmp/perf-.map and jit-.dump.
> > The first one allows the perf tool to map samples to each
> > individual
> >
On 31/05/2023 18:43, Philippe Mathieu-Daudé wrote:
On 31/5/23 14:53, Mark Cave-Ayland wrote:
Also change the instantiation of the CPU to use object_initialize_child()
followed by a separate realisation.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 13 -
On 31/05/2023 14:55, Philippe Mathieu-Daudé wrote:
On 31/5/23 14:53, Mark Cave-Ayland wrote:
Also change the instantiation of the macfb device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 6 --
include/hw/m68k/q800.h | 2 ++
2 files
On 01/06/2023 10:00, Markus Armbruster wrote:
Mark Cave-Ayland writes:
On 31/05/2023 16:00, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
On 31/5/23 14:53, Mark Cave-Ayland wrote:
Also change the instantiation of the CPU to use object_initialize_child()
followed by a separate
On 6/3/23 14:43, Paolo Bonzini wrote:
scripts/test-driver.py was used when "make check" was already using meson
introspection data, but it did not execute "meson test". It is dead since
commit 3d2f73ef75e ("build: use "meson test" as the test harness", 2021-12-23).
Signed-off-by: Paolo Bonzini
Be careful not to change linux_dirent64, which is a host structure.
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 72 +++
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 20986bd1d3..45ebacd4b4 100644
--- a/linux-user/syscall_defs.h
+++
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 21ca03b0f4..9dc41828cf 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@
Be careful not to change linux_dirent64, which is a host structure.
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 60 +++
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 414d88a9ec..caaa895bec 100644
--- a/linux-user/syscall_defs.h
On 6/2/23 08:52, Peter Maydell wrote:
Convert the instructions in the load/store exclusive (STXR,
STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR,
LDAR, LDLAR) to decodetree.
Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding
in the legacy decoder where we were not
On 6/2/23 08:52, Peter Maydell wrote:
+# CASP, CASPA, CASPAL, CASPL
+CASP0 . 001000 0 a:1 1 rs:5 lasr:1 1 rn:5 rt:5 sz=%imm1_30_p2
+# CAS, CASA, CASAL, CASL
+CAS sz:2 001000 1 a:1 1 rs:5 lasr:1 1 rn:5 rt:5
Drop decode of a + lasr? Or rename lasr to l? Anyhow,
On 6/2/23 08:52, Peter Maydell wrote:
Convert the load and store instructions which use a 9-bit
immediate offset to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 69
target/arm/tcg/translate-a64.c | 198 +
2 files
On 6/2/23 08:52, Peter Maydell wrote:
Convert the LDR and STR instructions which take a register
plus register offset to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 22 +
target/arm/tcg/translate-a64.c | 163 +++--
2 files
On 6/2/23 08:52, Peter Maydell wrote:
Convert the instructions in the load/store register (pointer
authentication) group ot decodetree: LDRAA, LDRAB.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 7 +++
target/arm/tcg/translate-a64.c | 83
On 31/05/2023 14:52, Philippe Mathieu-Daudé wrote:
On 31/5/23 14:53, Mark Cave-Ayland wrote:
Also change the instantiation of the mac-nubus-bridge device to use
object_initialize_child().
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 5 -
include/hw/m68k/q800.h | 2 ++
scripts/test-driver.py was used when "make check" was already using meson
introspection data, but it did not execute "meson test". It is dead since
commit 3d2f73ef75e ("build: use "meson test" as the test harness", 2021-12-23).
Signed-off-by: Paolo Bonzini
---
scripts/test-driver.py | 35
Untabify and re-indent.
We had a mix of 2, 3, 4, and 8 space indentation.
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 1948 ++---
1 file changed, 974 insertions(+), 974 deletions(-)
diff --git a/linux-user/syscall_defs.h
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 216 +++---
1 file changed, 108 insertions(+), 108 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index e4fcbd16d2..442a8aefe3 100644
--- a/linux-user/syscall_defs.h
Based on gcc's microblaze.h setting BIGGEST_ALIGNMENT to 32 bits.
Signed-off-by: Richard Henderson
---
include/exec/user/abitypes.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/exec/user/abitypes.h b/include/exec/user/abitypes.h
index 743b8bb9ea..beba0a48c7
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 108 +++---
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index a4e4df8d3e..414d88a9ec 100644
--- a/linux-user/syscall_defs.h
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 90 +++
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 442a8aefe3..21ca03b0f4 100644
--- a/linux-user/syscall_defs.h
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 290 +++---
1 file changed, 145 insertions(+), 145 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 2846a8cfa5..20986bd1d3 100644
--- a/linux-user/syscall_defs.h
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 45ebacd4b4..e4fcbd16d2 100644
--- a/linux-user/syscall_defs.h
+++
Testing clang -fsanitize=undefined -fno-sanitize-recover=undefined yields
../src/linux-user/syscall.c:1241:5: runtime error: member access within \
misaligned address 0x4081007c for type \
'struct target__kernel_timespec', which requires 8 byte alignment
etc, for sh4, microblaze, and
These definitions are in sparc/signal.c.
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 24
1 file changed, 24 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index e80d54780b..a4e4df8d3e 100644
---
Signed-off-by: Richard Henderson
---
linux-user/syscall_defs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 9dc41828cf..c8ffb4f785 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@
Based on gcc's nios2.h setting BIGGEST_ALIGNMENT to 32 bits.
Signed-off-by: Richard Henderson
---
include/exec/user/abitypes.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/exec/user/abitypes.h b/include/exec/user/abitypes.h
index beba0a48c7..6191ce9f74 100644
On 6/2/23 08:52, Peter Maydell wrote:
Convert the "Load register (literal)" instruction class to
decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 13 ++
target/arm/tcg/translate-a64.c | 73 ++
2 files changed, 33
On 6/2/23 08:52, Peter Maydell wrote:
+%imms7 15:s7
+ rt2 rt rn imm sz sign w p
+@ldstpair .. ... . ... . ... rt2:5 rn:5 rt:5 imm=%imms7
FYI, you don't need to extract imms7 -- imm:s7 inline will do.
Anyway,
Reviewed-by: Richard Henderson
r~
On 6/2/23 08:52, Peter Maydell wrote:
Convert the LDR and STR instructions which use a 12-bit immediate
offset to decodetree. We can reuse the existing LDR and STR
trans functions for these.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 25
On 6/2/23 08:52, Peter Maydell wrote:
Convert the insns in the atomic memory operations group to
decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 15
target/arm/tcg/translate-a64.c | 148 -
2 files changed, 67 insertions(+),
The chiptod is a pervasive facility which can keep TOD (time-of-day),
synchronise it across multiple chips, and can move that TOD to or from
the core timebase units.
This driver implements basic emulation of chiptod registers sufficient
to successfully run the skiboot chiptod synchronisation
This adds support for chiptod and core timebase state machine models in
the powernv POWER9 and POWER10 models.
This does not actually change the time or the value in TB registers
(because they are alrady synced in QEMU), but it does go through the
motions. It is enough to be able to run skiboot's
This implements the core timebase state machine, which is the core side
of the time-of-day system in POWER processors. This facility is operated
by control fields in the TFMR register, which also contains status
fields.
The core timebase interacts with the chiptod hardware, primarily to
receive
POWER book4 (implementation-specific) SPRs are sometimes in their own
functions, but in other cases are mixed with architected SPRs. Do some
spring cleaning on these.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 92 ---
1 file changed, 60
TFMR is the Time Facility Management Register which is specific to POWER
CPUs, and used for the purpose of timebase management (generally by
firmware, not the OS).
This adds an initial simple TFMR register, which will form part of the
core timebase facility model in the next patch.
On 6/2/23 08:52, Peter Maydell wrote:
Convert the instructions in the LDAPR/STLR (unscaled immediate)
group to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 10 +++
target/arm/tcg/translate-a64.c | 129 +++--
2 files changed, 54
On 6/2/23 08:52, Peter Maydell wrote:
Convert the instructions in the ASIMD load/store multiple structures
instruction classes to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 20 +++
target/arm/tcg/translate-a64.c | 220 -
2
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