Re: [PATCH 15/19] parallels: Remove unnecessary data_end field

On 10/6/23 21:43, Mike Maslenkin wrote: On Mon, Oct 2, 2023 at 12:01 PM Alexander Ivanov wrote: Since we have used bitmap, field data_end in BDRVParallelsState is redundant and can be removed. Add parallels_data_end() helper and remove data_end handling. Signed-off-by: Alexander Ivanov

Re: [PATCH] libvduse: Fix compiler warning with -Wshadow=local

On Fri, Oct 6, 2023 at 8:08 PM Thomas Huth wrote: > > No need to declare a new variable with the same name here, > we can simple re-use the one from the top of the function. > With this change, the file now compiles fine with -Wshadow=local. > > Signed-off-by: Thomas Huth > --- Reviewed-by: Xie

Re: [PATCH] hw/virtio/vhost: Silence compiler warnings in vhost code when using -Wshadow

06.10.2023 14:24, Michael S. Tsirkin: On Fri, Oct 06, 2023 at 01:45:51PM +0300, Michael Tokarev wrote: 06.10.2023 11:55, Markus Armbruster пишет: Michael Tokarev writes: Applied to my trivial-patches tree, thanks! Marcus, you picked up previous patches of this theme, -- you can continue

Re: [PATCH 2/3] hw/pci-host: Add emulation of Mai Logic Articia S

On Fri, 6 Oct 2023, Volker Rümelin wrote: Am 06.10.23 um 00:13 schrieb BALATON Zoltan: The Articia S is a generic chipset supporting several different CPUs that were used on some PPC boards. This is a minimal emulation of the parts needed for emulating the AmigaOne board. Signed-off-by:

[PATCH] target/riscv: Use a direct cast for better performance

RISCV_CPU(cs) uses a checked cast. When QOM cast debugging is enabled this adds about 5% total overhead when emulating RV64 on x86-64 host. Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk disk. The guest has a copy of the qemu source tree. The test involves compiling the

Re: [PATCH] target/riscv: Use a direct cast for better performance

If you're interested in how I found this problem, it was done using 'perf report -a -g' & flamegraphs. This is the flamegraph of qemu (on the host) when the guest is running the parallel compile: http://oirase.annexia.org/tmp/qemu-riscv.svg If you click into 'CPU_0/TCG' at the bottom left

Re: [PULL 00/21] vfio queue

Hello Eric, If you are ok with the above, I will squash the change in the related patch and send a v2. Unfortunately this is not sufficient. There is another regression (crash) on a double free of vbasedev->name as I reported before. I was able to hit it on a failing hotplug. How do you want

[PATCH] docs/about: Deprecate the 'next-cube' m68k machine

The machine is incomplete, and unfortunately the hoped-for improvements never happened. So it's maybe best if we mark this machine as deprecated and finally remove it again in case it gets into the way of a code refactoring or other reasons. Signed-off-by: Thomas Huth ---

Re: [PATCH v11 02/10] migration: convert migration 'uri' into 'MigrateAddress'

On 10/4/2023 8:13 PM, Fabiano Rosas wrote: Het Gala writes: This patch parses 'migrate' and 'migrate-incoming' QAPI's 'uri' string containing migration connection related information and stores them inside well defined 'MigrateAddress' struct. Suggested-by: Aravind Retnakaran Signed-off-by:

Re: [PATCH 15/19] parallels: Remove unnecessary data_end field

On Sat, Oct 7, 2023 at 1:18 PM Alexander Ivanov wrote: > > > > On 10/6/23 21:43, Mike Maslenkin wrote: > > On Mon, Oct 2, 2023 at 12:01 PM Alexander Ivanov > > wrote: > >> Since we have used bitmap, field data_end in BDRVParallelsState is > >> redundant and can be removed. > >> > >> Add

Re: [PATCH v11 02/10] migration: convert migration 'uri' into 'MigrateAddress'

On 10/4/2023 11:42 PM, Fabiano Rosas wrote: Daniel P. Berrangé writes: On Wed, Oct 04, 2023 at 11:43:12AM -0300, Fabiano Rosas wrote: Het Gala writes: This patch parses 'migrate' and 'migrate-incoming' QAPI's 'uri' string containing migration connection related information and stores

Re: [PATCH v2 1/2] migration: Fix rdma migration failed

On 04/10/2023 02:57, Juan Quintela wrote: > commit c638f66121ce30063fbf68c3eab4d7429cf2b209 > Author: Juan Quintela > Date: Tue Oct 3 20:53:38 2023 +0200 > > migration: Non multifd migration don't care about multifd flushes > > RDMA was having trouble because >

[PATCH] i386/pc: Drop pc_machine_kvm_type()

pc_machine_kvm_type() was introduced by commit e21be724eaf5 ("i386/xen: add pc_machine_kvm_type to initialize XEN_EMULATE mode") to do Xen specific initialization by utilizing kvm_type method. commit eeedfe6c6316 ("hw/xen: Simplify emulated Xen platform init") moves the Xen specific

Re: [PATCH v4 7/8] vdpa: Introduce cursors to vhost_vdpa_net_loadx()

在 2023/10/4 15:21, Eugenio Perez Martin 写道: > On Tue, Aug 29, 2023 at 7:55 AM Hawkins Jiawei wrote: >> >> This patch introduces two new arugments, `out_cursor` >> and `in_cursor`, to vhost_vdpa_net_loadx(). Addtionally, >> it includes a helper function >> vhost_vdpa_net_load_cursor_reset() for

Re: [PATCH v4 8/8] vdpa: Send cvq state load commands in parallel

在 2023/10/4 15:33, Eugenio Perez Martin 写道: > On Tue, Aug 29, 2023 at 7:55 AM Hawkins Jiawei wrote: >> >> This patch enables sending CVQ state load commands >> in parallel at device startup by following steps: >> >>* Refactor vhost_vdpa_net_load_cmd() to iterate through >> the control

Re: [PULL 00/21] vfio queue

07.10.2023 13:14, Cédric Le Goater wrote: Please send a v5 for "Prerequisite changes for IOMMUFD support" with the fixes we talked about. I will rebuild a PR next week. Can you push the first bugfix at least, so it will not miss stable-8.1.2? Thanks, /mjt

[PATCH] target/riscv: deprecate capital 'Z' CPU properties

At this moment there are eleven CPU extension properties that starts with capital 'Z': Zifencei, Zicsr, Zihintntl, Zihintpause, Zawrs, Zfa, Zfh, Zfhmin, Zve32f, Zve64f and Zve64d. All other extensions are named with lower-case letters. We want all properties to be named with lower-case letters

Re: [PATCH 15/19] parallels: Remove unnecessary data_end field

On Sat, Oct 7, 2023 at 5:30 PM Alexander Ivanov wrote: > > > > On 10/7/23 13:21, Mike Maslenkin wrote: > > On Sat, Oct 7, 2023 at 1:18 PM Alexander Ivanov > > wrote: > >> > >> On 10/6/23 21:43, Mike Maslenkin wrote: > >>> On Mon, Oct 2, 2023 at 12:01 PM Alexander Ivanov > >>> wrote: >

Re: [PATCH v3] hw/cxl: Add QTG _DSM support for ACPI0017 device

On Fri, Oct 06, 2023 at 01:09:39PM +0100, Jonathan Cameron wrote: > On Thu, 5 Oct 2023 12:32:11 -0400 > "Michael S. Tsirkin" wrote: > > > On Thu, Oct 05, 2023 at 09:11:15AM -0700, Dave Jiang wrote: > > > > > > > > > On 10/4/23 20:36, Michael S. Tsirkin wrote: > > > > > > > > On Wed, Oct 04,

Re: [Virtio-fs] [PATCH v4 2/8] vhost-user.rst: Improve [GS]ET_VRING_BASE doc

On Fri, Oct 06, 2023 at 03:58:44PM +0200, Hanna Czenczek wrote: > On 06.10.23 15:55, Hanna Czenczek wrote: > > On 06.10.23 10:49, Michael S. Tsirkin wrote: > > > On Fri, Oct 06, 2023 at 09:53:53AM +0200, Hanna Czenczek wrote: > > > > On 05.10.23 19:38, Stefan Hajnoczi wrote: > > > > > On Wed, Oct

Re: [PATCH v4 4/8] vdpa: Avoid using vhost_vdpa_net_load_*() outside vhost_vdpa_net_load()

在 2023/10/4 01:48, Eugenio Perez Martin 写道: > On Tue, Aug 29, 2023 at 7:55 AM Hawkins Jiawei wrote: >> >> Next patches in this series will refactor vhost_vdpa_net_load_cmd() >> to iterate through the control commands shadow buffers, allowing QEMU >> to send CVQ state load commands in parallel at

Re: [Virtio-fs] [PATCH v4 2/8] vhost-user.rst: Improve [GS]ET_VRING_BASE doc

On Fri, Oct 06, 2023 at 03:55:56PM +0200, Hanna Czenczek wrote: > On 06.10.23 10:49, Michael S. Tsirkin wrote: > > On Fri, Oct 06, 2023 at 09:53:53AM +0200, Hanna Czenczek wrote: > > > On 05.10.23 19:38, Stefan Hajnoczi wrote: > > > > On Wed, Oct 04, 2023 at 02:58:58PM +0200, Hanna Czenczek wrote:

Re: On integrating LoongArch EDK2 firmware into QEMU build process

Hi Xuerui,     Sorry for late reply. In fact the EDK2 repo is ready for submit, in a few days I will commit the patch set in kilaterlee/edk2 repo and execute the EDK2 CI testing. I will notify some people to review them, you are also welcome to review the patch set. And then, I'll submit the

Re: [PATCH v4 3/8] vhost: Expose vhost_svq_available_slots()

在 2023/10/4 01:44, Eugenio Perez Martin 写道: > On Tue, Aug 29, 2023 at 7:55 AM Hawkins Jiawei wrote: >> >> Next patches in this series will delay the polling >> and checking of buffers until either the SVQ is >> full or control commands shadow buffers are full, >> no longer perform an immediate

Re: [RFC PATCH v2 02/21] RAMBlock: Add support of KVM private gmem

On 9/22/2023 3:08 PM, David Hildenbrand wrote: On 22.09.23 02:22, Xiaoyao Li wrote: On 9/21/2023 4:55 PM, David Hildenbrand wrote: On 14.09.23 05:50, Xiaoyao Li wrote: From: Chao Peng Add KVM gmem support to RAMBlock so both normal hva based memory and kvm gmem fd based private memory can

Re: [PATCH] target/riscv: Use a direct cast for better performance

On 10/7/23 06:02, Richard W.M. Jones wrote: RISCV_CPU(cs) uses a checked cast. When QOM cast debugging is enabled this adds about 5% total overhead when emulating RV64 on x86-64 host. Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk disk. The guest has a copy of the qemu

[PATCH v8 03/29] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize()

Unlike its PIIX4 counterpart, TYPE_PIIX3_DEVICE doesn't instantiate a PIC itself. Instead, it relies on the board to do so. This means that the board needs to wire the ISA IRQs to the PIIX3 device model. As long as the board assigns the ISA IRQs after PIIX3's realize(), internal devices can't be

[PATCH v8 11/29] hw/isa/piix3: Create IDE controller in host device

The IDE controller is an integral part of PIIX3 (function 1). So create it as part of the south bridge. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- include/hw/southbridge/piix.h | 2 ++ hw/i386/pc_piix.c | 13 ++--- hw/isa/piix3.c|

[PATCH v8 10/29] hw/i386/pc: Wire RTC ISA IRQs in south bridges

Makes the south bridges a bit more self-contained and aligns PIIX3 more with PIIX4. The latter is needed for consolidating the PIIX south bridges. Signed-off-by: Bernhard Beschow --- hw/i386/pc.c | 7 ++- hw/isa/lpc_ich9.c | 3 +++ hw/isa/piix3.c| 3 +++ 3 files changed, 8

[PATCH v8 00/29] Consolidate PIIX south bridges

This series consolidates the implementations of the PIIX3 and PIIX4 south bridges and makes PIIX4 usable in the PC machine via an experimental command line parameter. The motivation is to resolve duplicate code between the device models as well as resolving the "Frankenstein" PIIX4-PM problem in

[PATCH v8 23/29] hw/isa/piix: Share PIIX3's base class with PIIX4

Having a common base class will allow for futher code sharing between PIIX3 and PIIX4. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- hw/isa/piix.c | 85 ++- 1

[PATCH v8 27/29] hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring

Now that both PIIX3 and PIIX4 use piix_set_irq() to trigger PCI IRQs the wiring in the respective realize methods can be shared, too. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- hw/isa/piix.c | 13 ++--- 1 file changed, 2 insertions(+), 11 deletions(-) diff

[PATCH v8 02/29] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge

The next patches will need to take advantage of it. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Michael S. Tsirkin --- hw/i386/pc_piix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index

[PATCH v8 08/29] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize()

When the board assigns the ISA IRQs after the device's realize(), internal devices such as the RTC can't be wired in ich9_lpc_realize() since the qemu_irqs are still NULL. Fix that by assigning the ISA interrupts before realize(). This change is necessary for PIIX consolidation because PIIX4

[PATCH v8 06/29] hw/i386/pc_piix: Remove redundant "piix3" variable

The variable is never used by its declared type. Eliminate it. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 4dc7298c15..cd6c00c0b3 100644 --- a/hw/i386/pc_piix.c +++

[PATCH v8 05/29] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property

Avoid assigning the private member of struct PIIX3State from outside which goes against best QOM practices. Instead, implement best QOM practice by adding an "isa-irqs" array property to TYPE_PIIX3_DEVICE and assign it in board code, i.e. from outside. Signed-off-by: Bernhard Beschow ---

[PATCH v8 15/29] hw/isa/piix4: Remove unused inbound ISA interrupt lines

The Malta board, which is the only user of PIIX4, doesn't connect to the exported interrupt lines. PIIX3 doesn't expose such interrupt lines either, so remove them for PIIX4 for simplicity and consistency. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- hw/isa/piix4.c | 8

Re: [PATCH 15/19] parallels: Remove unnecessary data_end field

On 10/7/23 13:21, Mike Maslenkin wrote: On Sat, Oct 7, 2023 at 1:18 PM Alexander Ivanov wrote: On 10/6/23 21:43, Mike Maslenkin wrote: On Mon, Oct 2, 2023 at 12:01 PM Alexander Ivanov wrote: Since we have used bitmap, field data_end in BDRVParallelsState is redundant and can be

[PATCH v2 2/3] hw/acpi: Implement the SRAT GI affinity structure

From: Ankit Agrawal ACPI spec provides a scheme to associate "Generic Initiators" [1] (e.g. heterogeneous processors and accelerators, GPUs, and I/O devices with integrated compute or DMA engines GPUs) with Proximity Domains. This is achieved using Generic Initiator Affinity Structure in SRAT.

[PATCH v2 1/3] qom: new object to associate device to numa node

From: Ankit Agrawal The CPU cache coherent device memory can be added as NUMA nodes distinct from the system memory nodes. These nodes are associated with the device and Qemu needs a way to maintain this link. Introduce a new acpi-generic-initiator object to allow host admin provide the device

[PATCH v2 0/3] acpi: report numa nodes for device memory using GI

From: Ankit Agrawal There are upcoming devices which allow CPU to cache coherently access their memory. It is sensible to expose such memory as NUMA nodes separate from the sysmem node to the OS. The ACPI spec provides a scheme in SRAT called Generic Initiator Affinity Structure [1] to allow an

[PATCH v8 25/29] hw/isa/piix: Rename functions to be shared for PCI interrupt triggering

PIIX4 will get the same optimizations which are already implemented for PIIX3. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- hw/isa/piix.c | 72 +-- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git

[PATCH v8 26/29] hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4

Speeds up PIIX4 which resolves an old TODO. Also makes PIIX4 compatible with Xen which relies on pci_bus_fire_intx_routing_notifier() to be fired. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- hw/isa/piix.c | 27 +++ 1 file changed, 3

[PATCH v8 18/29] hw/isa/piix4: Reuse struct PIIXState from PIIX3

PIIX4 has its own, private PIIX4State structure. PIIX3 has almost the same structure, provided in a public header. So reuse it and add a cpu_intr attribute to it which is only used by PIIX4. Signed-off-by: Bernhard Beschow --- include/hw/southbridge/piix.h | 1 + hw/isa/piix4.c

[PATCH v8 21/29] hw/isa/piix: Allow for optional PIT creation in PIIX3

In the PC machine, the PIT is created in board code to allow it to be virtualized with various virtualization techniques. So explicitly disable its creation in the PC machine via a property which defaults to enabled. Once the PIIX implementations are consolidated this default will keep Malta

[PATCH v2 3/3] qom: Link multiple numa nodes to device using a new object

From: Ankit Agrawal NVIDIA GPU's support MIG (Mult-Instance GPUs) feature [1], which allows partitioning of the GPU device resources (including device memory) into several (upto 8) isolated instances. Each of the partitioned memory needs a dedicated NUMA node to operate. The partitions are not

Re: [PATCH v11 08/10] migration: Implement MigrateChannelList to qmp migration flow.

On 10/4/2023 8:51 PM, Fabiano Rosas wrote: Het Gala writes: Integrate MigrateChannelList with all transport backends (socket, exec and rdma) for both src and dest migration endpoints for qmp migration. For current series, limit the size of MigrateChannelList to single element (single

Re: [PATCH v11 09/10] migration: Implement MigrateChannelList to hmp migration flow.

On 10/4/2023 8:55 PM, Fabiano Rosas wrote: Het Gala writes: Integrate MigrateChannelList with all transport backends (socket, exec and rdma) for both src and dest migration endpoints for hmp migration. Suggested-by: Aravind Retnakaran Signed-off-by: Het Gala Reviewed-by: Daniel P. Berrangé

Re: [PATCH v11 05/10] migration: convert exec backend to accept MigrateAddress.

On 10/4/2023 8:25 PM, Fabiano Rosas wrote: Het Gala writes: Exec transport backend for 'migrate'/'migrate-incoming' QAPIs accept new wire protocol of MigrateAddress struct. It is achived by parsing 'uri' string and storing migration parameters required for exec connection into strList

[PATCH v8 29/29] hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine

QEMU's PIIX3 implementation actually models the real PIIX4, but with different PCI IDs. Usually, guests deal just fine with it. Still, in order to provide a more consistent illusion to guests, allow QEMU's PIIX4 implementation to be used in the PC machine. Signed-off-by: Bernhard Beschow ---

[PATCH v8 17/29] hw/isa/piix4: Rename reset control operations to match PIIX3

Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin --- hw/isa/piix4.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/isa/piix4.c

[PATCH v8 20/29] hw/isa/piix: Allow for optional PIC creation in PIIX3

In the PC machine, the PIC is created in board code to allow it to be virtualized with various virtualization techniques. So explicitly disable its creation in the PC machine via a property which defaults to enabled. Once the PIIX implementations are consolidated this default will keep Malta

[PATCH v8 22/29] hw/isa/piix: Harmonize names of reset control memory regions

There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin --- hw/isa/piix.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH v8 19/29] hw/isa/piix3: Merge hw/isa/piix4.c

Now that the PIIX3 and PIIX4 device models are sufficiently prepared, their implementations can be merged into one file for further consolidation. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- MAINTAINERS| 6 +- hw/isa/{piix3.c => piix.c} | 190

[PATCH v8 12/29] hw/isa/piix3: Create USB controller in host device

The USB controller is an integral part of PIIX3 (function 2). So create it as part of the south bridge. Note that the USB function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow Reviewed-by: Michael

[PATCH v8 07/29] hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in"

TYPE_PIIX3_DEVICE doesn't instantiate a PIC since it relies on the board to do so. The "pic" attribute, however, suggests that there is one. Rename the attribute to reflect that it represents ISA interrupt lines. Use the same naming convention as in the VIA south bridges as well as in TYPE_I82378.

[PATCH v8 09/29] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device

Thie PIIX3 south bridge implements both the PIC and the ISA bus, so wiring the interrupts there makes the device model more self-contained. Furthermore, this allows the ISA interrupts to be wired to internal child devices in pci_piix3_realize() which will be performed in subsequent patches.

[PATCH v8 13/29] hw/isa/piix3: Create power management controller in host device

The power management controller is an integral part of PIIX3 (function 3). So create it as part of the south bridge. Note that the ACPI function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow

[PATCH v8 01/29] hw/i386/pc: Merge two if statements into one

By being the only entity assigning a non-NULL value to "rtc_irq", the first if statement determines whether the second if statement is executed. So merge the two statements into one. Signed-off-by: Bernhard Beschow --- hw/i386/pc.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-)

[PATCH v8 14/29] hw/isa/piix3: Drop the "3" from PIIX base class name

TYPE_PIIX3_PCI_DEVICE was the former base class of the Xen and non-Xen variants of the PIIX3 ISA device models. It will become the base class for the PIIX3 and PIIX4 device models, so drop the "3" from the type names. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin ---

[PATCH v8 24/29] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4

Resolves duplicate code. Also makes PIIX4 respect the PIIX3 properties which get added, too. This allows for using PIIX4 in the PC machine. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 80 ++--- hw/mips/malta.c | 5 ++-- 2 files changed, 12

[PATCH v8 04/29] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS

PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise inconsistencies can occur. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- include/hw/southbridge/piix.h | 5 ++--- hw/isa/piix3.c| 8 2 files changed, 6 insertions(+), 7

[PATCH v8 28/29] hw/isa/piix: Implement multi-process QEMU support also for PIIX4

So far multi-process QEMU was only implemented for PIIX3. Move the support into the base class to achieve feature parity between both device models. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 9 + 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/isa/piix.c

[PATCH v8 16/29] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in"

Rename the "isa" attribute to align it with PIIX3 for consolidation. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 3c3c7a094c..9c8b6c98ab 100644 --- a/hw/isa/piix4.c +++

Re: [PATCH] target/loongarch: fix ASXE flag conflict

在 2023/9/30 下午11:46, Richard Henderson 写道: On 9/30/23 04:28, Jiajie Chen wrote: HW_FLAGS_EUEN_ASXE acccidentally conflicts with HW_FLAGS_CRMD_PG, enabling LASX instructions even when CSR_EUEN.ASXE=0. Closes: https://gitlab.com/qemu-project/qemu/-/issues/1907 >> Signed-off-by: Jiajie Chen ---

[RFC PATCH 1/4] net: Allow to offload virtio-net hashing

Offloading virtio-net hashing to the client can improve the performance since the performance can reuse the hash calculated for RSS for hash reporting as well. Signed-off-by: Akihiko Odaki --- include/net/net.h | 47 +++ net/tap_int.h | 3 +++

[RFC PATCH 2/4] virtio-net: Offload hashing without eBPF

Offloading virtio-net hashing to the client can improve the performance since the performance can reuse the hash calculated for RSS for hash reporting as well. Signed-off-by: Akihiko Odaki --- include/hw/virtio/virtio-net.h | 5 +- hw/net/virtio-net.c| 164

[RFC PATCH 3/4] virtio-net: Add hash type options

By default, virtio-net limits the hash types that will be advertised to the guest so that all hash types are covered by the offloading capability the client provides. This change allows to override this behavior and to advertise hash types that require user-space hash calculation by specifying

[RFC PATCH 4/4] docs/devel/ebpf_rss.rst: Update for kernel RSS

eBPF RSS virtio-net support was written in assumption that there is only one alternative RSS implementation: 'in-qemu' RSS. It is no longer true, and we now have yet another implementation; namely the kernel RSS. Signed-off-by: Akihiko Odaki --- docs/devel/ebpf_rss.rst | 22

Re: [PATCH] target/riscv: deprecate capital 'Z' CPU properties

That's great! I submitted a patch set to deal with the exact problem: But this one is simpler than mine (and also fits to the latest QEMU). I support this

[PATCH 5/6] virtio-net: Return an error when vhost cannot enable RSS

vhost requires eBPF for RSS. Even when eBPF is not available, virtio-net reported RSS availability, and raised a warning only after the guest requested RSS, and the guest could not know that RSS is not available. Check RSS availability during device realization and return an error if RSS is

[PATCH 1/6] tap: Fix virtio-net header buffer size

The largest possible virtio-net header is struct virtio_net_hdr_v1_hash. Fixes: fbbdbddec0 ("tap: allow extended virtio header with hash info") Signed-off-by: Akihiko Odaki --- net/tap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/tap.c b/net/tap.c index

[PATCH 4/6] virtio-net: Unify the logic to update NIC state for RSS

The code to attach or detach the eBPF program to RSS were duplicated so unify them into one function to save some code. Signed-off-by: Akihiko Odaki --- hw/net/virtio-net.c | 90 ++--- 1 file changed, 36 insertions(+), 54 deletions(-) diff --git

[PATCH 3/6] virtio-net: Disable RSS on reset

RSS is disabled by default. Fixes: 590790297c ("virtio-net: implement RSS configuration command") Signed-off-by: Akihiko Odaki --- hw/net/virtio-net.c | 70 +++-- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/hw/net/virtio-net.c

[PATCH 2/6] virtio-net: Copy header only when necessary

It is necessary to copy the header only for byte swapping. Worse, when byte swapping is not needed, the header can be larger than the buffer due to VIRTIO_NET_F_HASH_REPORT, which results in buffer overflow. Copy the header only when byte swapping is needed. Fixes: e22f0603fb ("virtio-net:

[PATCH 6/6] virtio-net: Do not clear VIRTIO_NET_F_RSS

Even if eBPF is not available, virtio-net can perform RSS on the user-space if vhost is disabled although such a configuration results in a warning. If vhost is enabled, the configuration will be rejected when realizing the device. Therefore, VIRTIO_NET_F_RSS should not be cleared even if eBPF is

Re: [PATCH v2] virtio: use shadow_avail_idx while checking number of heads

On Wed, Sep 27, 2023 at 9:51 PM Ilya Maximets wrote: > > We do not need the most up to date number of heads, we only want to > know if there is at least one. > > Use shadow variable as long as it is not equal to the last available > index checked. This avoids expensive qatomic dereference of the

Re: [PATCH] hw/net/vhost_net: Silence compiler warning when compiling with -Wshadow

On Wed, Oct 4, 2023 at 4:57 PM Michael S. Tsirkin wrote: > > On Wed, Oct 04, 2023 at 10:49:39AM +0200, Thomas Huth wrote: > > Rename the innermost local variables to avoid compiler warnings > > with "-Wshadow". > > > > Signed-off-by: Thomas Huth > > Reviewed-by: Michael S. Tsirkin Acked-by: