On 2/27/24 6:26 PM, Luc Michel wrote:
On 15:09 Tue 27 Feb , Pierrick Bouvier wrote:
On 2/27/24 2:54 PM, Luc Michel wrote:
Hi Pierrick,
On 13:14 Mon 26 Feb , Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
contrib/plugins/hotblocks.c | 50 ++-
Add a fd-bootchk property to PC machine types, so that -no-fd-bootchk
returns an error if the machine does not support booting from floppies
and checking for boot signatures therein.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
include/hw/i386/pc.h | 2 +-
hw/i386/pc.c
The A20 mask is only applied to the final memory access. Nested
page tables are always walked with the raw guest-physical address.
Unlike the previous patch, in this one the masking must be kept, but
it was done too early.
Cc: qemu-sta...@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic o
CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level
paging or PAE paging). Do this in mmu_translate() to remove
the last where get_physical_address() meaningfully drops the high
bits of the address.
Cc: qemu-sta...@nongnu.org
Suggested-by: Richard Henderson
Fixes: 4a1e9d4d11c ("targ
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
include/hw/ide/ide-dev.h | 2 ++
include/sysemu/sysemu.h | 1 -
hw/ide/core.c| 3 ++-
hw/ide/ide-dev.c | 1 +
system/globals.c | 1 -
system/vl.c | 2 +-
qemu-options.hx | 3 ++
The following changes since commit dd88d696ccecc0f3018568f8e281d3d526041e6f:
Merge tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu into
staging (2024-02-24 16:12:51 +)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you t
MSR_VM_HSAVE_PA bits 0-11 are reserved, as are the bits above the
maximum physical address width of the processor. Setting them to
1 causes a #GP (see "15.30.4 VM_HSAVE_PA MSR" in the AMD manual).
The same is true of VMCB addresses passed to VMRUN/VMLOAD/VMSAVE,
even though the manual is not clea
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using PAE
to access memory a
Accesses from a 32-bit environment (32-bit code segment for instruction
accesses, EFER.LMA==0 for processor accesses) have to mask away the
upper 32 bits of the address. While a bit wasteful, the easiest way
to do so is to use separate MMU indexes. These days, QEMU anyway is
compiled with a fixed
Remove knowledge of specific MMU indexes (other than MMU_NESTED_IDX and
MMU_PHYS_IDX) from mmu_translate(). This will make it possible to split
32-bit and 64-bit MMU indexes.
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h| 10 ++
target/i386/tcg/sysemu/excp_helpe
If ptw_translate() does a MMU_PHYS_IDX access, the A20 mask is already
applied in get_physical_address(), which is called via probe_access_full()
and x86_cpu_tlb_fill().
If ptw_translate() on the other hand does a MMU_NESTED_IDX access,
the A20 mask must not be applied to the address that is looke
All calls to ide_init_drive comes from ide_dev_initfn. Just pass down the
IDEDevice (IDEState is kinda obsolete and should be merged into IDEDevice).
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
include/hw/ide/internal.h | 6 +-
hw/ide/core.c | 40 +
On Wed, 21 Feb 2024 19:32:27 +0530
Ani Sinha wrote:
> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow
> up to 4096 vCPUs")
> Linux kernel can support upto a maximum number of 4096 vCPUS when MAXSMP is
> enabled in the kernel. At present, QEMU has been tested to correc
Akihiko Odaki writes:
> romsize is an uint32_t variable. Specifying -1 as an uint32_t value is
> obscure way to denote UINT32_MAX.
>
> Worse, if int is wider than 32-bit, it will change the behavior of a
> construct like the following:
> romsize = -1;
> if (romsize != -1) {
> ...
> }
>
> When
Akihiko Odaki writes:
> vfio determines if rombar is explicitly enabled by inspecting QDict.
> Inspecting QDict is not nice because QDict is untyped and depends on the
> details on the external interface. Add an infrastructure to determine if
> rombar is explicitly enabled to hw/pci.
>
> Signed-o
> Subject: Re: [EXT] Re: [PATCH v3] virtio-pci: correctly set virtio pci queue
> mem
> multiplier
>
> On Wed, Feb 28, 2024 at 06:13:03AM +, Srujana Challa wrote:
> > > Subject: [EXT] Re: [PATCH v3] virtio-pci: correctly set virtio pci
> > > queue mem multiplier
> > >
> > > External Email
> >
Akihiko Odaki writes:
> Use pci_rom_bar_explicitly_enabled() to determine if rombar is explicitly
> enabled.
>
> Signed-off-by: Akihiko Odaki
> ---
> hw/vfio/pci.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
> index 4fa387f0430d..647f
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/targ
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan
---
v4:
- Accept NMI unconditionally for arm_cpu_has_work() but add comment.
- Change from & to && for EXCP_IRQ or EXCP_FIQ.
- Refator nmi mask in arm_excp_unmasked().
- Also handle VNMI in arm_cpu_exec_in
Added properties to enable FEAT_GICv3_NMI feature, setup distributor
and redistributor registers to indicate NMI support.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_dist.c | 2 ++
A PE that implements FEAT_NMI and FEAT_GICv3 also implements
FEAT_GICv3_NMI. A PE that does not implement FEAT_NMI, does not implement
FEAT_GICv3_NMI
So included support FEAT_GICv3_NMI feature as part of virt platform
GIC initialization if FEAT_NMI and FEAT_GICv3 supported.
Signed-off-by: Jinjie
Support ALLINT msr access as follow:
mrs , ALLINT// read allint
msr ALLINT, // write allint with imm
Signed-off-by: Jinjie Ruan
---
v4:
- Remove arm_is_el2_enabled() check in allint_check().
- Change to env->pstate instead of env->allint.
v3:
- Remove EL0 check in
Wire the new NMI and VNMI interrupt line from the GIC to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Also add VNMI wire.
---
hw/arm/virt.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/vi
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is both necessary to check
whether the pendi
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ. However, VNMI can be IRQ or FIQ, FIQ can only come from
hcrx_el2.HCRX_VFNMI bit, IRQ can be raised from the GIC or come from the
hc
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Make the GICD_INMIR implementation more clearer.
- Udpate the commit message.
v3:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_dist.c | 34 ++
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VNMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI set, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan
---
v4;
- Also handle VNMI.
v3:
- CPU_INTERRUPT_NMI do
In vCPU Interface, if the vIRQ has the superpriority property, report
vNMI to the corresponding vPE.
Signed-off-by: Jinjie Ruan
---
hw/intc/arm_gicv3_cpuif.c | 14 --
hw/intc/gicv3_internal.h | 1 +
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_c
Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Add support for VNMI.
---
hw/intc/arm_gicv3_common.c | 6 ++
include/hw/intc/arm_g
Add the NMIAR CPU interface registers which deal with acknowledging NMI.
When introduce NMI interrupt, there are some updates to the semantics for the
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
should return 1022 if the intid has super priority. And for ICC_NMIAR1_EL1
In CPU Interface, if the IRQ has the superpriority property, report
NMI to the corresponding PE.
Signed-off-by: Jinjie Ruan
---
v4:
- Swap the ordering of the IFs.
v3:
- Remove handling nmi_is_irq flag.
---
hw/intc/arm_gicv3_cpuif.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/intc
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Remove nmi_is_irq flag in CPUA
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked.
As Richard suggested, place ALLINT bit in PSTATE in env->pstate.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Signed-off-by: Jinjie
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Adjust to before the MSR patches.
---
target/arm/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
HCRX_EL2.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Update the comment for FEAT_NMI in hcrx_write().
- Update the comm
A SPI, PPI or SGI interrupt can have a superpriority property. So
maintain superpriority information in PendingIrq and GICR/GICD.
Signed-off-by: Jinjie Ruan
Acked-by: Richard Henderson
---
v3:
- Place this ahead of implement GICR_INMIR.
- Add Acked-by.
---
include/hw/intc/arm_gicv3_common.h | 4
Add GICR_INMIR0 register and support access GICR_INMIR0.
Signed-off-by: Jinjie Ruan
---
v4:
- Make the GICR_INMIR0 implementation more clearer.
---
hw/intc/arm_gicv3_redist.c | 19 +++
hw/intc/gicv3_internal.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/hw/intc/arm_
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by: J
Enable FEAT_NMI on the 'max' CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Sorted to last.
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/d
> On 27-Feb-2024, at 21:17, Igor Mammedov wrote:
>
> Cureently it not possible to run SMBIOS test without ACPI one,
> which gets into the way when testing ACPI-less configs.
>
> Extract SMBIOS testing into separate routines that could also
> be run without ACPI dependency and use that for tes
Needs a rebase. But let me have a look at the QAPI schema changes
first.
On 28/02/2024 5:04, Peter Xu wrote:
External email: Use caution opening links or attachments
On Wed, Feb 28, 2024 at 02:00:26AM +0200, Avihai Horon wrote:
On 27/02/2024 9:41, Peter Xu wrote:
External email: Use caution opening links or attachments
On Thu, Feb 22, 2024 at 05:56:27PM +0200,
Hao Xiang writes:
> This new parameter controls where the zero page checking is running.
> 1. If this parameter is set to 'legacy', zero page checking is
> done in the migration main thread.
> 2. If this parameter is set to 'none', zero page checking is disabled.
>
> Signed-off-by: Hao Xiang
[.
Hao Xiang writes:
> 1. Add zero_pages field in MultiFDPacket_t.
> 2. Implements the zero page detection and handling on the multifd
> threads for non-compression, zlib and zstd compression backends.
> 3. Added a new value 'multifd' in ZeroPageDetection enumeration.
> 4. Handle migration QEMU9.0 -
> -Original Message-
> From: Zhao Liu
> Sent: Tuesday, February 20, 2024 5:25 PM
> To: Daniel P . Berrangé ; Eduardo Habkost
> ; Marcel Apfelbaum
> ; Philippe Mathieu-Daudé ;
> Yanan Wang ;
> Michael S . Tsirkin ; Paolo Bonzini ;
> Richard Henderson ;
> Eric Blake ; Markus Armbruster
Because vIOMMU mgaw can be updated based on host IOMMU mgaw, s->aw_bits
does't necessarily represent the final mgaw now but the mgaw field in
s->cap does.
Replace reference to s->aw_bits with a MACRO S_AW_BITS to fetch mgaw
from s->cap. There are two exceptions on this, aw_bits value sanity
check
When there is VFIO device and vIOMMU cap/ecap is updated based on host
IOMMU cap/ecap, migration should be blocked.
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_
Hi,
Based on Joao's suggestion, the iommufd nesting prerequisite series [1]
is further splitted to host IOMMU device abstract part [2] and vIOMMU
check/sync part. This series implements the 2nd part.
This enables vIOMMU to get host IOMMU cap/ecap information by implementing
a new set/unset_iommu_
From: Yi Liu
This adds set/unset_iommu_device() implementation in Intel vIOMMU.
In set call, a pointer to host IOMMU device info is stored in hash
table indexed by PCI BDF.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 8
From: Yi Liu
Add a framework to check and synchronize host IOMMU cap/ecap with
vIOMMU cap/ecap.
The sequence will be:
vtd_cap_init() initializes iommu->cap/ecap.
vtd_check_hdev() update iommu->cap/ecap based on host cap/ecap.
iommu->cap_frozen set when machine create done, iommu->cap/ecap becom
This is a prerequisite for host cap/ecap sync.
No functional change intended.
Reviewed-by: Eric Auger
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 93 ---
1 file changed, 51 insertions(+), 42 deletions(-)
diff --git a/hw/i386/intel_iommu.c
We use cap_frozen to mark cap/ecap read/writable or read-only,
At init stage, we allow to update cap/ecap based on host IOMMU
cap/ecap, but when machine create done, cap_frozen is set and
we only allow checking cap/ecap for compatibility.
Currently only stage-2 translation is supported which is ba
Hao Xiang writes:
> 1. Add zero_pages field in MultiFDPacket_t.
> 2. Implements the zero page detection and handling on the multifd
> threads for non-compression, zlib and zstd compression backends.
> 3. Added a new value 'multifd' in ZeroPageDetection enumeration.
> 4. Handle migration QEMU9.0 -
Hao Xiang writes:
> This change extends the MigrationStatus interface to track zero pages
> and zero bytes counter.
>
> Signed-off-by: Hao Xiang
[...]
> diff --git a/qapi/migration.json b/qapi/migration.json
> index a0a85a0312..171734c07e 100644
> --- a/qapi/migration.json
> +++ b/qapi/migrati
> -Original Message-
> From: Zhao Liu
> Sent: Tuesday, February 20, 2024 5:25 PM
> To: Daniel P . Berrangé ; Eduardo Habkost
> ; Marcel Apfelbaum
> ; Philippe Mathieu-Daudé ;
> Yanan Wang ;
> Michael S . Tsirkin ; Paolo Bonzini ;
> Richard Henderson ;
> Eric Blake ; Markus Armbruster
> On 27-Feb-2024, at 21:17, Igor Mammedov wrote:
>
> Signed-off-by: Igor Mammedov
Empty description is not nice. Other than that,
Reviewed-by: Ani Sinha
> ---
> tests/data/smbios/type11_blob | Bin 0 -> 11 bytes
> tests/qtest/bios-tables-test.c | 17 +
> 2 files changed, 1
On 27/02/2024 5:16, Wang, Lei wrote:
External email: Use caution opening links or attachments
On 2/22/2024 23:56, Avihai Horon wrote:
Currently, migration code serializes device data sending during pre-copy
iterative phase. As noted in the code comment, this is done to prevent
faster changin
Zhao Liu writes:
> From: Zhao Liu
>
> Add "modules" parameter parsing support in -smp.
>
> Suggested-by: Xiaoyao Li
> Tested-by: Yongwei Ma
> Signed-off-by: Zhao Liu
QAPI schema
Acked-by: Markus Armbruster
Zhao Liu writes:
> From: Zhao Liu
>
> Add module-id in CpuInstanceProperties, to locate the CPU with module
> level.
>
> Suggested-by: Xiaoyao Li
> Tested-by: Yongwei Ma
> Signed-off-by: Zhao Liu
QAPI schema
Acked-by: Markus Armbruster
Am 28.02.2024 um 07:43 hat Markus Armbruster geschrieben:
> Yong Huang writes:
>
> > On Wed, Feb 21, 2024 at 4:26 PM Markus Armbruster wrote:
> >
> >> Yong Huang writes:
> >>
> >> > On Wed, Feb 21, 2024 at 2:43 PM Markus Armbruster
> >> wrote:
> >> >
> >> >> Hyman Huang writes:
> >> >>
> >> >
On Wed, Feb 28, 2024 at 11:39:52AM +0200, Avihai Horon wrote:
>
> On 28/02/2024 5:04, Peter Xu wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Wed, Feb 28, 2024 at 02:00:26AM +0200, Avihai Horon wrote:
> > > On 27/02/2024 9:41, Peter Xu wrote:
> > > > External
On Wed, Feb 28, 2024 at 11:17:37AM +0100, Kevin Wolf wrote:
> Am 28.02.2024 um 07:43 hat Markus Armbruster geschrieben:
> > Yong Huang writes:
> >
> > > On Wed, Feb 21, 2024 at 4:26 PM Markus Armbruster
> > > wrote:
> > >
> > >> Yong Huang writes:
> > >>
> > >> > On Wed, Feb 21, 2024 at 2:43 P
On 1/18/24 14:31, Denis V. Lunev wrote:
On 1/16/24 15:45, Denis V. Lunev wrote:
On 12/28/23 11:12, Alexander Ivanov wrote:
Now we support extensions saving and can let to work with them in
read-write mode.
Signed-off-by: Alexander Ivanov
---
block/parallels-ext.c | 4
block/parall
On 28/02/2024 12:17, Peter Xu wrote:
External email: Use caution opening links or attachments
On Wed, Feb 28, 2024 at 11:39:52AM +0200, Avihai Horon wrote:
On 28/02/2024 5:04, Peter Xu wrote:
External email: Use caution opening links or attachments
On Wed, Feb 28, 2024 at 02:00:26AM +0200
Signed-off-by: Paolo Bonzini
---
tcg/optimize.c | 60 +++---
1 file changed, 52 insertions(+), 8 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 3995bc047db..8ea1f287788 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1281,6 +1281,
The variables uext_opc and sext_opc are used without initialization if
TCG_TARGET_extract_i{32,64}_valid returns false. The result, depending
on the compiler, might be the generation of extract and sextract opcodes
with invalid offset and count, or just random data in the TCG opcode
stream.
Fixes
The TSTEQ/TSTNE operations can be useful to evaluate many conditionals.
They can be used to test the sign bit or equality to zero of a partial
register, as well as to check individual bits in EFLAGS.
Paolo
Based-on: <20240228110641.287205-1-pbonz...@redhat.com>
Paolo Bonzini (4):
target/i386:
> On 27-Feb-2024, at 21:17, Igor Mammedov wrote:
>
> Unfortunately having 2.0 machine type deprecated is not enough
> to get rid of legacy SMBIOS handling since 'isapc' also uses
> that and it's staying around.
>
> Hence add test for CLI options handling to be sure that it
> ain't broken duri
Generalize the existing optimization of "TSTNE x,sign" and "TSTNE x,-1".
This can be useful in some cases when the i386 frontend creates opcodes
that test against 0xff or 0x80.
Signed-off-by: Paolo Bonzini
---
tcg/optimize.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
d
With the introduction of TSTEQ and TSTNE the .mask field is always -1,
so remove all the now-unnecessary code.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 81 +
1 file changed, 27 insertions(+), 54 deletions(-)
diff --git a/target/i386/tcg/
When testing the sign bit or equality to zero of a partial register, it
is useful to use a single TSTEQ or TSTNE operation. It can also be used
to test the parity flag, using bit 0 of the population count.
Do not do this for 32- and 64-bit values however, to avoid
large immediates.
Signed-off-by
The new condition obviously come in handy when testing individual bits
of EFLAGS, and they make it possible to remove the .mask field of
CCPrepare.
Lowering to shift+and is done by the optimizer if necessary.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 32
On 28/2/24 12:06, Paolo Bonzini wrote:
The variables uext_opc and sext_opc are used without initialization if
TCG_TARGET_extract_i{32,64}_valid returns false. The result, depending
on the compiler, might be the generation of extract and sextract opcodes
Shouldn't compilers bark?
with invalid
Am 28.02.2024 um 11:23 hat Daniel P. Berrangé geschrieben:
> On Wed, Feb 28, 2024 at 11:17:37AM +0100, Kevin Wolf wrote:
> > Am 28.02.2024 um 07:43 hat Markus Armbruster geschrieben:
> > > Yong Huang writes:
> > >
> > > > On Wed, Feb 21, 2024 at 4:26 PM Markus Armbruster
> > > > wrote:
> > > >
On Wed, Feb 28, 2024 at 12:21:02PM +0100, Kevin Wolf wrote:
> Am 28.02.2024 um 11:23 hat Daniel P. Berrangé geschrieben:
> > On Wed, Feb 28, 2024 at 11:17:37AM +0100, Kevin Wolf wrote:
> > > Am 28.02.2024 um 07:43 hat Markus Armbruster geschrieben:
> > > > Yong Huang writes:
> > > >
> > > > > On
> On 27-Feb-2024, at 21:17, Igor Mammedov wrote:
>
> smbios_get_tables() bails out right away if leagacy mode is enabled
> and won't generate any SMBIOS tables. At the same time x86 specific
> fw_cfg_build_smbios() will genarate legacy tables and then proceed
> to preparing temporary mem_array
On Wed, Feb 28, 2024 at 11:17:37AM +0100, Kevin Wolf wrote:
> Until now, @size has been mandatory for creating images with every
> driver. Maybe we should even have put it into BlockdevCreateOptions's
> base, because without a size, you're not really creating an image.
NB, @size isn't mandatory fo
On 26/2/24 23:48, Alex Bennée wrote:
The old links are dead so even if we have the ISO cached we can't
finish the install. Update to the current stable and tweak the install
strings.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2192
Signed-off-by: Alex Bennée
---
tests/vm/openbsd |
nvme_sriov_pre_write_ctrl() used to directly inspect SR-IOV
configurations to know the number of VFs being disabled due to SR-IOV
configuration writes, but the logic was flawed and resulted in
out-of-bound memory access.
It assumed PCI_SRIOV_NUM_VF always has the number of currently enabled
VFs, b
Disable SR-IOV VF devices by reusing code to power down PCI devices
instead of removing them when the guest requests to disable VFs. This
allows to realize devices and report VF realization errors at PF
realization time.
Signed-off-by: Akihiko Odaki
---
docs/pcie_sriov.txt | 8 ++--
in
Currently there is no way to distinguish the case that rombar is
explicitly specified as 1 and the case that rombar is not specified.
Set rombar UINT32_MAX by default to distinguish these cases just as it
is done for addr and romsize. It was confirmed that changing the default
value to UINT32_MAX
vfio determines if rombar is explicitly enabled by inspecting QDict.
Inspecting QDict is not nice because QDict is untyped and depends on the
details on the external interface. Add an infrastructure to determine if
rombar is explicitly enabled to hw/pci.
This changes the semantics of UINT32_MAX, w
A device gets automatically unrealized when being unparented.
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index e9b23221d713..8b1fd2a89ad7 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie
The renamed state will not only represent powering state of PFs, but
also represent SR-IOV VF enablement in the future.
Signed-off-by: Akihiko Odaki
---
include/hw/pci/pci.h| 7 ++-
include/hw/pci/pci_device.h | 2 +-
hw/pci/pci.c| 14 +++---
hw/pci/pci_host
Call pcie_sriov_pf_reset() from pci_do_device_reset() just as we do
for msi_reset() and msix_reset() to prevent duplicating code for each
SR-IOV PF.
Signed-off-by: Akihiko Odaki
---
hw/net/igb.c | 2 --
hw/nvme/ctrl.c | 4
hw/pci/pci.c | 1 +
3 files changed, 1 insertion(+), 6 deletions
pcie_sriov_pf_disable_vfs() is called when resetting the PF, but it only
disables VFs and does not reset SR-IOV extended capability, leaking the
state and making the VF Enable register inconsistent with the actual
state.
Replace pcie_sriov_pf_disable_vfs() with pcie_sriov_pf_reset(), which
does no
The spec does not NumVFs is reset after disabling VFs except when
resetting the PF. Clearing it is guest visible and out of spec, even
though Linux doesn't rely on this value being preserved, so we never
noticed.
Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization
(SR/IOV)"
pcie_sriov doesn't have code to restore its state after migration, but
igb, which uses pcie_sriov, naively claimed its migration capability.
Add code to register VFs after migration and fix igb migration.
Fixes: 3a977deebe6b ("Intrdocue igb device emulation")
Signed-off-by: Akihiko Odaki
---
in
num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF
instead.
Signed-off-by: Akihiko Odaki
---
include/hw/pci/pcie_sriov.h | 1 -
hw/pci/pcie_sriov.c | 28
hw/pci/trace-events | 2 +-
3 files changed, 21 insertions(+), 10 deletions
romsize is an uint32_t variable. Specifying -1 as an uint32_t value is
obscure way to denote UINT32_MAX.
Worse, if int is wider than 32-bit, it will change the behavior of a
construct like the following:
romsize = -1;
if (romsize != -1) {
...
}
When -1 is assigned to romsize, -1 will be impli
The guest may write NumVFs greater than TotalVFs and that can lead
to buffer overflow in VF implementations.
Cc: qemu-sta...@nongnu.org
Fixes: CVE-2024-26327
Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization
(SR/IOV)")
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.
It is no longer used.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Markus Armbruster
---
include/hw/qdev-core.h | 4
hw/core/qdev.c | 1 -
system/qdev-monitor.c | 12 +++-
3 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/i
Release VFs failed to realize just as we do in unregister_vfs().
Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization
(SR/IOV)")
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sri
I submitted a RFC series[1] to add support for SR-IOV emulation to
virtio-net-pci. During the development of the series, I fixed some
trivial bugs and made improvements that I think are independently
useful. This series extracts those fixes and improvements from the RFC
series.
[1]: https://patche
On Wed, Feb 21, 2024 at 07:32:27PM +0530, Ani Sinha wrote:
> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow
> up to 4096 vCPUs")
> Linux kernel can support upto a maximum number of 4096 vCPUS when MAXSMP is
> enabled in the kernel. At present, QEMU has been tested to c
> On 28-Feb-2024, at 17:12, Gerd Hoffmann wrote:
>
> On Wed, Feb 21, 2024 at 07:32:27PM +0530, Ani Sinha wrote:
>> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow
>> up to 4096 vCPUs")
>> Linux kernel can support upto a maximum number of 4096 vCPUS when MAXSMP is
>
This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix. This color shield can be plugged
on the Arduino board (or the B-L475E-IOT01A board) to drive an 8x8
RGB led matrix. Thi
This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix. The columns of the matrix are
driven by the DM163 and the rows are driven externally.
Acked-by: Alistair Francis
Sign
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/b-l475e-iot01a.c | 44 +
1 file changed, 31 insertions(+), 13 deletions(-)
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index d862aa43fc..2b570b3e09 100644
--- a/hw/arm/b
Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
to the optional DM163 display from the board code (GPIOs outputs need
to be connected to both SYSCFG inputs and DM163 inputs).
STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.
Signed-off-by: Arnaud Minie
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