From: Ilya Leoshkevich
Add a regression test for a recently fixed issue, where shmat()
desynced the guest and the host view of the address space and caused
open("/proc/self/maps") to SEGV.
Signed-off-by: Ilya Leoshkevich
Message-Id:
Signed-off-by: Richard Henderson
---
This is the only case in which we expect to have no host memory backing
for a guest memory page, because in general linux user processes cannot
map any pages in the top half of the 64-bit address space.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2170
Signed-off-by: Richard Henderson
There are multiple issues with the implementation of shmat().
(1) With reserved_va, which is the default for 32-on-64-bit, we mmap the
entire guest address space. Unlike mmap, shmat refuses to replace an
existing mapping without setting SHM_REMAP. This is the original
subject of
Handle combined host and guest alignment requirements.
Handle host and guest page size differences.
Handle SHM_EXEC.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/115
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 172 --
1 file
The kernel abi was changed with
commit d23b77953f5a4fbf94c05157b186aac2a247ae32
Author: Huacai Chen
Date: Wed Jan 17 12:43:08 2024 +0800
LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE
during the v6.8 cycle.
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
Signed-off-by: Richard Henderson
---
linux-user/strace.c| 23 +++
linux-user/strace.list | 2 +-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index cf26e55264..47d6ec3263 100644
--- a/linux-user/strace.c
+++
On 2/28/24 01:11, Paolo Bonzini wrote:
With the introduction of TSTEQ and TSTNE the .mask field is always -1,
so remove all the now-unnecessary code.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 81 +
1 file changed, 27 insertions(+), 54
On 2/28/24 01:11, Paolo Bonzini wrote:
The new condition obviously come in handy when testing individual bits
of EFLAGS, and they make it possible to remove the .mask field of
CCPrepare.
Lowering to shift+and is done by the optimizer if necessary.
Signed-off-by: Paolo Bonzini
---
On Thu, Feb 29, 2024 at 12:37:13AM +0800, Zhao Liu wrote:
> From: Zhao Liu
>
> As the comment in qapi/error, passing @errp to error_prepend() requires
> ERRP_GUARD():
>
> * = Why, when and how to use ERRP_GUARD() =
> *
> * Without ERRP_GUARD(), use of the @errp parameter is restricted:
> ...
>
On 2/28/24 02:20, Paolo Bonzini wrote:
On Wed, Feb 28, 2024 at 12:19 PM Philippe Mathieu-Daudé
wrote:
On 28/2/24 12:06, Paolo Bonzini wrote:
The variables uext_opc and sext_opc are used without initialization if
TCG_TARGET_extract_i{32,64}_valid returns false. The result, depending
on the
Hello everyone,
With QEMU 8.2, guests that:
- use SeaBIOS
- use something different than "-cpu host" OR don't use "host-phys-
bits=on"
- have more than 2815 MB of RAM
have problems with their virtio devices and, hence, malfunction in
various ways (e.g., if they're using a virtio disk, they
The following patches are queued for QEMU stable v8.2.2:
https://gitlab.com/qemu-project/qemu/-/commits/staging-8.2
Patch freeze is 2024-03-02, and the release is planned for 2024-03-04:
https://wiki.qemu.org/Planning/8.2
Please respond here or CC qemu-sta...@nongnu.org on any additional
From: Nicholas Piggin
is_prefix_insn_excp() loads the first word of the instruction address
which caused an exception, to determine whether or not it was prefixed
so the prefix bit can be set in [H]SRR1.
This works if the instruction image can be loaded, but if the exception
was caused by an
From: Klaus Jensen
numcntl is one byte and so is max_vfs. Using cpu_to_le16 on big endian
hosts results in numcntl being set to 0.
Fix by dropping the endian conversion.
Fixes: 99f48ae7ae ("hw/nvme: Add support for Secondary Controller List")
Reported-by: Kevin Wolf
Signed-off-by: Klaus
On 2/28/24 01:11, Paolo Bonzini wrote:
-/* TSTNE x,sign -> LT x,0 */
-if (arg_is_const_val(*p2, (ctx->type == TCG_TYPE_I32
- ? INT32_MIN : INT64_MIN))) {
+/* TSTNE x,i -> LT x,0 if i only includes sign bit copies */
+if (arg_is_const(*p2) &&
Hi Manos,
On Wed, Feb 28, 2024 at 03:27:12PM +0200, Manos Pitsidianakis wrote:
> Hello Vikram,
>
> Series doesn't apply on master. Can you rebase and also provide a
> base-commit with --base= when you use git-format-patch? This
> will help git rebase if there are any conflicts found locally.
I
On 28.02.24 19:39, Peter Maydell wrote:
On Wed, 28 Feb 2024 at 18:28, Heinrich Schuchardt
wrote:
On 28.02.24 16:06, Philippe Mathieu-Daudé wrote:
Hi Heinrich,
On 28/2/24 13:59, Heinrich Schuchardt wrote:
virtqueue_map_desc() is called with values of sz exceeding that may
exceed
On Wed, 28 Feb 2024 10:29:32 -0800
Peter Delevoryas wrote:
> Hey guys,
>
> I’m having a little trouble reading between the lines on various
> docs, mailing list threads, KVM presentations, github forks, etc, so
> I figured I’d just ask:
>
> What is the status of IOMMU virtualization, like in
Hi Zhao,
On 2/27/24 04:32, Zhao Liu wrote:
> From: Zhao Liu
>
> As module-level topology support is added to X86CPU, now we can enable
> the support for the modules parameter on PC machines. With this support,
> we can define a 5-level x86 CPU topology with "-smp":
>
> -smp
On Thu, Feb 29, 2024 at 12:37:16AM +0800, Zhao Liu wrote:
> From: Zhao Liu
>
> As the comment in qapi/error, passing @errp to error_prepend() requires
> ERRP_GUARD():
>
> * = Why, when and how to use ERRP_GUARD() =
> *
> * Without ERRP_GUARD(), use of the @errp parameter is restricted:
> ...
>
On Thu, Feb 29, 2024 at 12:37:20AM +0800, Zhao Liu wrote:
> From: Zhao Liu
>
> As the comment in qapi/error, passing @errp to error_prepend() requires
> ERRP_GUARD():
>
> * = Why, when and how to use ERRP_GUARD() =
> *
> * Without ERRP_GUARD(), use of the @errp parameter is restricted:
> ...
>
Hao Xiang writes:
> 1. Add zero_pages field in MultiFDPacket_t.
> 2. Implements the zero page detection and handling on the multifd
> threads for non-compression, zlib and zstd compression backends.
> 3. Added a new value 'multifd' in ZeroPageDetection enumeration.
> 4. Handle migration QEMU9.0
On 2/27/24 23:29, Jinjie Ruan via wrote:
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked.
As Richard suggested, place ALLINT bit in PSTATE in env->pstate.
With the change to pstate_read/write, exception entry
and return are
From: Klaus Jensen
numcntl is one byte and so is max_vfs. Using cpu_to_le16 on big endian
hosts results in numcntl being set to 0.
Fix by dropping the endian conversion.
Fixes: 99f48ae7ae ("hw/nvme: Add support for Secondary Controller List")
Reported-by: Kevin Wolf
Signed-off-by: Klaus
From: Paolo Bonzini
The A20 mask is only applied to the final memory access. Nested
page tables are always walked with the raw guest-physical address.
Unlike the previous patch, in this one the masking must be kept, but
it was done too early.
Cc: qemu-sta...@nongnu.org
Fixes: 4a1e9d4d11c
From: Paolo Bonzini
CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level
paging or PAE paging). Do this in mmu_translate() to remove
the last where get_physical_address() meaningfully drops the high
bits of the address.
Cc: qemu-sta...@nongnu.org
Suggested-by: Richard Henderson
The following patches are queued for QEMU stable v7.2.10:
https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2
Patch freeze is 2024-03-02, and the release is planned for 2024-03-04:
https://wiki.qemu.org/Planning/7.2
Please respond here or CC qemu-sta...@nongnu.org on any additional
From: Peter Maydell
MSYS2 is dropping support for 32-bit Windows. This shows up for us
as various packages we were using in our CI job no longer being
available to install, which causes the job to fail. In commit
8e31b744fdf we dropped the dependency on libusb and spice, but the
dtc package
From: Alex Bennée
The old links are dead so even if we have the ISO cached we can't
finish the install. Update to the current stable and tweak the install
strings.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2192
Tested-by: Thomas Huth
Reviewed-by: Thomas Huth
Signed-off-by: Alex
From: Paolo Bonzini
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using
From: Paolo Bonzini
If ptw_translate() does a MMU_PHYS_IDX access, the A20 mask is already
applied in get_physical_address(), which is called via probe_access_full()
and x86_cpu_tlb_fill().
If ptw_translate() on the other hand does a MMU_NESTED_IDX access,
the A20 mask must not be applied to
From: Daniel P. Berrangé
Python is transitioning to a world where you're not allowed to use 'pip
install' outside of a virutal env by default. The rationale is to stop
use of pip clashing with distro provided python packages, which creates
a major headache on distro upgrades.
All our CI
From: Alex Bennée
The old links are dead so even if we have the ISO cached we can't
finish the install. Update to the current stable and tweak the install
strings.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2192
Tested-by: Thomas Huth
Reviewed-by: Thomas Huth
Signed-off-by: Alex
From: Peter Maydell
MSYS2 is dropping support for 32-bit Windows. This shows up for us
as various packages we were using in our CI job no longer being
available to install, which causes the job to fail. In commit
8e31b744fdf we dropped the dependency on libusb and spice, but the
dtc package
From: Alex Bennée
The main problem is that "check-venv" is a .PHONY target will always
evaluate and trigger a full re-build of the VM images. While its
tempting to drop it from the dependencies that does introduce a
breakage on freshly configured builds.
Fortunately we do have the otherwise
From: Tianlan Zhou
Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.
Fixes: f8d2c9369b ("sdl: use ctrl-alt-g as grab hotkey")
Signed-off-by: Tianlan Zhou
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
(cherry picked from commit
From: Nicholas Piggin
The move to decodetree flipped the inequality test for the VEC / VSX
MSR facility check.
This caused application crashes under Linux, where these facility
unavailable interrupts are used for lazy-switching of VEC/VSX register
sets. Getting the incorrect interrupt would
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one requires Sscofpmf
to be enabled.
The
This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. It is based on Kevin's earlier work but improves
it by actually implement privilege mode filtering by tracking the privilege
mode switches. This enables the privilege mode filtering for
mhpmeventhX CSRs are available for RV32. The predicate function
should check that first before checking sscofpmf extension.
Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support")
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
From: Kaiwen Xue
QEMU only calculates dummy cycles and instructions, so there is no
actual means to stop the icount in QEMU. Hence this patch merely adds
the functionality of accessing the cfg registers, and cause no actual
effects on the counting of cycle and instret counters.
Signed-off-by:
From: Kaiwen Xue
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 6 ++
target/riscv/cpu_bits.h | 29 +
2 files changed, 35
From: Tianlan Zhou
Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.
Fixes: f8d2c9369b ("sdl: use ctrl-alt-g as grab hotkey")
Signed-off-by: Tianlan Zhou
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
(cherry picked from commit
From: Paolo Bonzini
If ptw_translate() does a MMU_PHYS_IDX access, the A20 mask is already
applied in get_physical_address(), which is called via probe_access_full()
and x86_cpu_tlb_fill().
If ptw_translate() on the other hand does a MMU_NESTED_IDX access,
the A20 mask must not be applied to
From: Paolo Bonzini
MSR_VM_HSAVE_PA bits 0-11 are reserved, as are the bits above the
maximum physical address width of the processor. Setting them to
1 causes a #GP (see "15.30.4 VM_HSAVE_PA MSR" in the AMD manual).
The same is true of VMCB addresses passed to VMRUN/VMLOAD/VMSAVE,
even though
From: Nicholas Piggin
The move to decodetree flipped the inequality test for the VEC / VSX
MSR facility check.
This caused application crashes under Linux, where these facility
unavailable interrupts are used for lazy-switching of VEC/VSX register
sets. Getting the incorrect interrupt would
On 2/27/24 23:29, Jinjie Ruan via wrote:
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use
From: Tianlan Zhou
Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.
Fixes: f8d2c9369b ("sdl: use ctrl-alt-g as grab hotkey")
Signed-off-by: Tianlan Zhou
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
(cherry picked from commit
From: Paolo Bonzini
CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level
paging or PAE paging). Do this in mmu_translate() to remove
the last where get_physical_address() meaningfully drops the high
bits of the address.
Cc: qemu-sta...@nongnu.org
Suggested-by: Richard Henderson
From: Gerd Hoffmann
Signed-off-by: Gerd Hoffmann
(cherry picked from commit 658178c3d4e95b3f4106e25ec5a209356e339032)
Signed-off-by: Michael Tokarev
diff --git a/pc-bios/edk2-aarch64-code.fd.bz2 b/pc-bios/edk2-aarch64-code.fd.bz2
index fdcf89022a..5d0a57173d 100644
Binary files
From: Gerd Hoffmann
Signed-off-by: Gerd Hoffmann
(cherry picked from commit 9c996f3d11f8582ac5d4daf5d17453ac09d4acf8)
Signed-off-by: Michael Tokarev
diff --git a/roms/edk2 b/roms/edk2
index b8a3eec88c..edc6681206 16
--- a/roms/edk2
+++ b/roms/edk2
@@ -1 +1 @@
-Subproject commit
From: Jessica Clarke
The PL031 allows you to read RTCLR, which is meant to give you the last
value written. PL031State has an lr field which is used when reading
from RTCLR, and is present in the VM migration state, but we never
actually update it, so it always reads as its initial 0 value.
Cc:
From: Paolo Bonzini
MSR_VM_HSAVE_PA bits 0-11 are reserved, as are the bits above the
maximum physical address width of the processor. Setting them to
1 causes a #GP (see "15.30.4 VM_HSAVE_PA MSR" in the AMD manual).
The same is true of VMCB addresses passed to VMRUN/VMLOAD/VMSAVE,
even though
From: Paolo Bonzini
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using
From: Thomas Huth
When running "configure" with "--without-default-devices", building
of qemu-system-hppa currently fails with:
/usr/bin/ld: libqemu-hppa-softmmu.fa.p/hw_hppa_machine.c.o: in function
`machine_HP_common_init_tail':
hw/hppa/machine.c:399: undefined reference to `usb_bus_find'
Signed-off-by: Sven Schnelle
---
target/hppa/gdbstub.c | 48 +--
1 file changed, 33 insertions(+), 15 deletions(-)
diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c
index 48a514384f..a5b2c80c07 100644
--- a/target/hppa/gdbstub.c
+++
Hi List,
this patchset allows to debug the hppa target when running in wide (64 bit)
mode. gdb needs a small patch to switch to 64 bit mode. I pushed the
patch to
https://github.com/bminor/binutils-gdb/commit/fd8662ec282d688d1f8100b4365823e57516857b
With this patch gdb will switch to the
Signed-off-by: Sven Schnelle
---
target/hppa/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c
index a5b2c80c07..049b2d6381 100644
--- a/target/hppa/gdbstub.c
+++ b/target/hppa/gdbstub.c
@@ -184,7 +184,7 @@ int
Despite commit e207b4aa718e ("target/hppa: Drop attempted gdbstub
support for hppa64") saying that hppa-linux-gdb doesn't support 64 bit
mode via remote protocol, it is actually working with a small add-on
patch which enables gdb to guess the size from the g protocol:
$ hppa64-linux-gnu-gdb
On 2/27/24 23:29, Jinjie Ruan via wrote:
Support ALLINT msr access as follow:
mrs , ALLINT // read allint
msr ALLINT, // write allint with imm
Signed-off-by: Jinjie Ruan
---
v4:
- Remove arm_is_el2_enabled() check in allint_check().
- Change to env->pstate instead of
Luc Michel writes:
> Hi Pierrick,
>
> On 13:14 Mon 26 Feb , Pierrick Bouvier wrote:
>> Signed-off-by: Pierrick Bouvier
>> ---
>> tests/plugin/mem.c | 40 +---
>> 1 file changed, 25 insertions(+), 15 deletions(-)
>>
>> diff --git a/tests/plugin/mem.c
On 2/28/24 01:11, Paolo Bonzini wrote:
When testing the sign bit or equality to zero of a partial register, it
is useful to use a single TSTEQ or TSTNE operation. It can also be used
to test the parity flag, using bit 0 of the population count.
Do not do this for 32- and 64-bit values however,
From: Paolo Bonzini
The A20 mask is only applied to the final memory access. Nested
page tables are always walked with the raw guest-physical address.
Unlike the previous patch, in this one the masking must be kept, but
it was done too early.
Cc: qemu-sta...@nongnu.org
Fixes: 4a1e9d4d11c
On Wed, Feb 28, 2024 at 1:50 AM Markus Armbruster wrote:
>
> Hao Xiang writes:
>
> > 1. Add zero_pages field in MultiFDPacket_t.
> > 2. Implements the zero page detection and handling on the multifd
> > threads for non-compression, zlib and zstd compression backends.
> > 3. Added a new value
Hi List,
this patchset adds a new -dfilter option and address range matching. With this
execlog can match only a certain range of address for both instruction and
data adresses.
Example usage:
qemu-system-xxx -d plugin -plugin
libexeclog.so,afilter=0x1000-0x2000,dfilter=0x388
This would only
Allow to match memory ranges with the address matches. This
allows to give a range of adresses like '-dfilter=0-0x400'
which would only log memory accesses between 0 and 400.
Signed-off-by: Sven Schnelle
---
contrib/plugins/execlog.c | 65 +++
1 file changed,
HP-UX 10.20 seems to make the lsi53c895a spinning on a memory location
under certain circumstances. As the SCSI controller and CPU are not
running at the same time this loop will never finish. After some
time, the check loop interrupts with a unexpected device disconnect.
This works, but is slow
Hao Xiang writes:
> 1. Add a dedicated handler for MigrationOps::ram_save_target_page in
> multifd live migration.
> 2. Refactor ram_save_target_page_legacy so that the legacy and multifd
> handlers don't have internal functions calling into each other.
>
> Signed-off-by: Hao Xiang
Add a match similar to the afilter address match, but for data
addresses. When an address is specified with '-dfilter=0x12345'
only load/stores to/from address 0x12345 are printed. All other
instructions are hidden.
Signed-off-by: Sven Schnelle
---
contrib/plugins/execlog.c | 23
Add a context structure for future enhancements. No functional
change intended.
Signed-off-by: Sven Schnelle
---
contrib/plugins/execlog.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c
index
Pass the matches array to parse_vaddr_match(), so future address
matches can reuse that function.
Signed-off-by: Sven Schnelle
---
contrib/plugins/execlog.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c
index
From: Alex Bennée
The main problem is that "check-venv" is a .PHONY target will always
evaluate and trigger a full re-build of the VM images. While its
tempting to drop it from the dependencies that does introduce a
breakage on freshly configured builds.
Fortunately we do have the otherwise
From: Jessica Clarke
The PL031 allows you to read RTCLR, which is meant to give you the last
value written. PL031State has an lr field which is used when reading
from RTCLR, and is present in the VM migration state, but we never
actually update it, so it always reads as its initial 0 value.
Cc:
From: Tianlan Zhou
Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.
Fixes: f8d2c9369b ("sdl: use ctrl-alt-g as grab hotkey")
Signed-off-by: Tianlan Zhou
Reviewed-by: Thomas Huth
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
(cherry picked from commit
On 2/27/24 6:26 PM, Luc Michel wrote:
On 15:09 Tue 27 Feb , Pierrick Bouvier wrote:
On 2/27/24 2:54 PM, Luc Michel wrote:
Hi Pierrick,
On 13:14 Mon 26 Feb , Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
contrib/plugins/hotblocks.c | 50
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
include/hw/ide/ide-dev.h | 2 ++
include/sysemu/sysemu.h | 1 -
hw/ide/core.c| 3 ++-
hw/ide/ide-dev.c | 1 +
system/globals.c | 1 -
system/vl.c | 2 +-
qemu-options.hx | 3
The following changes since commit dd88d696ccecc0f3018568f8e281d3d526041e6f:
Merge tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu into
staging (2024-02-24 16:12:51 +)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you
Add a fd-bootchk property to PC machine types, so that -no-fd-bootchk
returns an error if the machine does not support booting from floppies
and checking for boot signatures therein.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
include/hw/i386/pc.h | 2 +-
The A20 mask is only applied to the final memory access. Nested
page tables are always walked with the raw guest-physical address.
Unlike the previous patch, in this one the masking must be kept, but
it was done too early.
Cc: qemu-sta...@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic
CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level
paging or PAE paging). Do this in mmu_translate() to remove
the last where get_physical_address() meaningfully drops the high
bits of the address.
Cc: qemu-sta...@nongnu.org
Suggested-by: Richard Henderson
Fixes: 4a1e9d4d11c
On Wed, 21 Feb 2024 19:32:27 +0530
Ani Sinha wrote:
> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow
> up to 4096 vCPUs")
> Linux kernel can support upto a maximum number of 4096 vCPUS when MAXSMP is
> enabled in the kernel. At present, QEMU has been tested to
MSR_VM_HSAVE_PA bits 0-11 are reserved, as are the bits above the
maximum physical address width of the processor. Setting them to
1 causes a #GP (see "15.30.4 VM_HSAVE_PA MSR" in the AMD manual).
The same is true of VMCB addresses passed to VMRUN/VMLOAD/VMSAVE,
even though the manual is not
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using PAE
to access memory
Accesses from a 32-bit environment (32-bit code segment for instruction
accesses, EFER.LMA==0 for processor accesses) have to mask away the
upper 32 bits of the address. While a bit wasteful, the easiest way
to do so is to use separate MMU indexes. These days, QEMU anyway is
compiled with a
If ptw_translate() does a MMU_PHYS_IDX access, the A20 mask is already
applied in get_physical_address(), which is called via probe_access_full()
and x86_cpu_tlb_fill().
If ptw_translate() on the other hand does a MMU_NESTED_IDX access,
the A20 mask must not be applied to the address that is
All calls to ide_init_drive comes from ide_dev_initfn. Just pass down the
IDEDevice (IDEState is kinda obsolete and should be merged into IDEDevice).
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
include/hw/ide/internal.h | 6 +-
hw/ide/core.c | 40
Remove knowledge of specific MMU indexes (other than MMU_NESTED_IDX and
MMU_PHYS_IDX) from mmu_translate(). This will make it possible to split
32-bit and 64-bit MMU indexes.
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h| 10 ++
On 28/02/2024 5:04, Peter Xu wrote:
External email: Use caution opening links or attachments
On Wed, Feb 28, 2024 at 02:00:26AM +0200, Avihai Horon wrote:
On 27/02/2024 9:41, Peter Xu wrote:
External email: Use caution opening links or attachments
On Thu, Feb 22, 2024 at 05:56:27PM
On 27/02/2024 5:16, Wang, Lei wrote:
External email: Use caution opening links or attachments
On 2/22/2024 23:56, Avihai Horon wrote:
Currently, migration code serializes device data sending during pre-copy
iterative phase. As noted in the code comment, this is done to prevent
faster
> On 27-Feb-2024, at 21:17, Igor Mammedov wrote:
>
> Signed-off-by: Igor Mammedov
Empty description is not nice. Other than that,
Reviewed-by: Ani Sinha
> ---
> tests/data/smbios/type11_blob | Bin 0 -> 11 bytes
> tests/qtest/bios-tables-test.c | 17 +
> 2 files changed,
On Wed, Feb 28, 2024 at 11:39:52AM +0200, Avihai Horon wrote:
>
> On 28/02/2024 5:04, Peter Xu wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Wed, Feb 28, 2024 at 02:00:26AM +0200, Avihai Horon wrote:
> > > On 27/02/2024 9:41, Peter Xu wrote:
> > > > External
Am 28.02.2024 um 07:43 hat Markus Armbruster geschrieben:
> Yong Huang writes:
>
> > On Wed, Feb 21, 2024 at 4:26 PM Markus Armbruster wrote:
> >
> >> Yong Huang writes:
> >>
> >> > On Wed, Feb 21, 2024 at 2:43 PM Markus Armbruster
> >> wrote:
> >> >
> >> >> Hyman Huang writes:
> >> >>
> >>
Signed-off-by: Paolo Bonzini
---
tcg/optimize.c | 60 +++---
1 file changed, 52 insertions(+), 8 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 3995bc047db..8ea1f287788 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1281,6
The variables uext_opc and sext_opc are used without initialization if
TCG_TARGET_extract_i{32,64}_valid returns false. The result, depending
on the compiler, might be the generation of extract and sextract opcodes
with invalid offset and count, or just random data in the TCG opcode
stream.
> On 27-Feb-2024, at 21:17, Igor Mammedov wrote:
>
> smbios_get_tables() bails out right away if leagacy mode is enabled
> and won't generate any SMBIOS tables. At the same time x86 specific
> fw_cfg_build_smbios() will genarate legacy tables and then proceed
> to preparing temporary
On 26/2/24 23:48, Alex Bennée wrote:
The old links are dead so even if we have the ISO cached we can't
finish the install. Update to the current stable and tweak the install
strings.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2192
Signed-off-by: Alex Bennée
---
tests/vm/openbsd
This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix. The columns of the matrix are
driven by the DM163 and the rows are driven externally.
Acked-by: Alistair Francis
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/b-l475e-iot01a.c | 44 +
1 file changed, 31 insertions(+), 13 deletions(-)
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index d862aa43fc..2b570b3e09 100644
---
Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
to the optional DM163 display from the board code (GPIOs outputs need
to be connected to both SYSCFG inputs and DM163 inputs).
STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.
Signed-off-by: Arnaud
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