On 12/21/23 06:49, Chao Du wrote:
This patch implements insert/remove software breakpoint process:
Add an input parameter for kvm_arch_insert_sw_breakpoint() and
kvm_arch_remove_sw_breakpoint() to pass the length information,
which helps us to know whether it is a compressed instruction.
For
Add AST2700 Evaluation board and its boot command.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
docs/system/arm/aspeed.rst | 39 ++
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces
to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of
INT 128 to INT136 combines 32 interrupts.
Introduce a new aspeed_intc class with instance_init and realize handlers.
So far, this model only supports
AST2700 CPU is ARM Cortex-A35 which is 64 bits.
Add TARGET_AARCH64 to build this machine.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL.
Then, CPUs(cortex-a35) execute u-boot, kernel and rofs.
Currently, qemu not support emulate two CPU
On 17:08 Fri 12 Apr , Peter Maydell wrote:
> Some devices and machines need to handle the reset before a vmsave
> snapshot is loaded differently -- the main user is the handling of
> RNG seed information, which does not want to put a new RNG seed into
> a ROM blob when we are doing a snapshot
Add a test case to test Aspeed OpenBMC SDK v09.01 on AST2700 board.
It loads u-boot-nodtb.bin, u-boot.dtb, tfa and optee-os
images to dram first which base address is 0x4.
Then, boot and launch 4 cpu cores.
```
qemu-system-aarch64 -machine ast2700-evb
-device
These macros are no longer used for ASPEED SOCs, so removes them.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 64cd1a81dc..74279bbe8e 100644
---
AST2700 wdt controller is similiar to AST2600's wdt, but
the AST2700 has 8 watchdogs, and they each have 0x80 of registers.
Introduce ast2700 object class and increase the number of regs(offset) of
ast2700 model.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
AST2700 dram size calculation is not back compatible AST2600.
According to the DDR capacity hardware behavior,
if users write the data to address which is beyond the ram size,
it would write the data to address 0.
For example:
a. sdram base address "0x4 "
b. sdram size is 1 GiB
The
DMA length is from 1 byte to 32MB for AST2600 and AST10x0
and DMA length is from 4 bytes to 32MB for AST2500.
In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte
data for AST2600 and AST10x0 and 4 bytes data for AST2500.
To support all ASPEED SOCs, adds dma_start_length parameter
AST2700 fmc/spi controller's address decoding unit is 64KB
and only bits [31:16] are used for decoding. Introduce seg_to_reg
and reg_to_seg handlers for ast2700 fmc/spi controller.
In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler.
Signed-off-by: Troy Lee
Signed-off-by:
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce dummy AST2700 SLI and SLIIO models.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sli.c | 178
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max memory is now 8GiB on the AST2700. Introduce new
AST2700 have two SCU controllers which are SCU and SCUIO.
Both SCU and SCUIO registers are not compatible previous SOCs
, introduces new registers and adds ast2700 scu, sucio class init handler.
The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and
the pclk divider selection of
AST2700 support the maximum dram size is 8GiB
and has a "DMA DRAM Side Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram
address, new features and update trace-event
to support 64 bits dram address.
Signed-off-by: Troy Lee
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/ssi/aspeed_smc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 6e1a84c197..8a8d77b480 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -1448,7 +1448,7
Fix coding style issues from checkpatch.pl
Test command:
scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c
Changes from v1:
The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700 SoC.
Changes from v2:
- replace is_aarch64 with is_bus64bit for sdmc patch review.
- fix incorrect dram size for AST2700
Changes from v3:
- Add AST2700 Evaluation board in ASPEED document
- Add avocado test
Hi Paolo,
Just a friendly ping. Hope this series could get your review!
Thanks,
Zhao
On Thu, Mar 21, 2024 at 10:40:27PM +0800, Zhao Liu wrote:
> Date: Thu, 21 Mar 2024 22:40:27 +0800
> From: Zhao Liu
> Subject: [PATCH v10 00/21] i386: Introduce smp.modules and clean up cache
> topology
>
On 17:08 Fri 12 Apr , Peter Maydell wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> The npcm7xx_clk and npcm7xx_gcr device reset methods look at
> the ResetType argument and only handle
On 17:08 Fri 12 Apr , Peter Maydell wrote:
> We pass a ResetType argument to the Resettable class enter
> phase method, but we don't pass it to hold and exit, even though
> the callsites have it readily available. This means that if
> a device cared about the ResetType it would need to record
On 17:08 Fri 12 Apr , Peter Maydell wrote:
> Update the reset documentation's example code to match the new API
> for the hold and exit phase method APIs where they take a ResetType
> argument.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> docs/devel/reset.rst | 8
Hi Irina
On Mon, Mar 25, 2024 at 10:44 AM Marc-André Lureau
wrote:
>
> Hi
>
> On Sun, Mar 24, 2024 at 7:23 PM Irina Ryapolova
> wrote:
> >
> > After exit Qemu need to return the terminal to the default state.
> >
> > Signed-off-by: Irina Ryapolova
> > ---
> > chardev/char-win-stdio.c | 5
On 17:08 Fri 12 Apr , Peter Maydell wrote:
> We pass a ResetType argument to the Resettable class enter phase
> method, but we don't pass it to hold and exit, even though the
> callsites have it readily available. This means that if a device
> cared about the ResetType it would need to record
On 17:08 Fri 12 Apr , Peter Maydell wrote:
> Rather than directly calling the device's implementation of its 'hold'
> reset phase, call device_cold_reset(). This means we don't have to
> adjust this callsite when we add another argument to the function
> signature for the hold and exit reset
On Mon, 15 Apr 2024 at 19:18, Dorjoy Chowdhury wrote:
>
> On Mon, Apr 15, 2024 at 5:35 PM Peter Maydell
> wrote:
> > This bit of the codebase has got a bit more complicated since
> > I wrote up the bug report. I will look into this and get back
> > to you, but my suspicion is that these calls
On 4/16/2024 4:32 PM, Chenyi Qiang wrote:
On 2/29/2024 2:36 PM, Xiaoyao Li wrote:
Current KVM doesn't support PMU for TD guest. It returns error if TD is
created with PMU bit being set in attributes.
Disable PMU for TD guest on QEMU side.
Signed-off-by: Xiaoyao Li
---
Hi
On Tue, Apr 16, 2024 at 1:00 AM Kim, Dongwon wrote:
>
> Hi Marc-André,
>
> > -Original Message-
> > From: marcandre.lur...@redhat.com
> > Sent: Monday, April 15, 2024 4:16 AM
> > To: qemu-devel@nongnu.org
> > Cc: Kim, Dongwon ; dbas...@redhat.com; Marc-
> > André Lureau ; Michael S.
On Mon, Apr 15, 2024 at 9:42 PM Sahil wrote:
>
> Hi,
>
> Thank you for your reply.
>
> On Monday, April 15, 2024 2:27:36 PM IST Eugenio Perez Martin wrote:
> > [...]
> > > I have one question though. One of the options (use case 1 in [1])
> > >
> > > given to the "qemu-kvm" command is:
> > > >
On Sat, Apr 13, 2024 at 7:23 AM Richard Henderson
wrote:
>
> More sprintf cleanup encouraged by the Apple deprecation.
> Probably there's a more minimal patch. On the other hand,
> there's certainly a larger cleanup possible.
>
>
> r~
On the series:
Reviewed-by: Edgar E. Iglesias
>
>
>
On 2/29/2024 2:36 PM, Xiaoyao Li wrote:
> Current KVM doesn't support PMU for TD guest. It returns error if TD is
> created with PMU bit being set in attributes.
>
> Disable PMU for TD guest on QEMU side.
>
> Signed-off-by: Xiaoyao Li
> ---
> target/i386/kvm/tdx.c | 2 ++
> 1 file changed,
In rtas_nvram_fetch() and rtas_nvram_store() if len is equal
to zero, result of a cpu_physical_memory_map() will be NULL.
It will lead to NULL dereference, since return value using
without check. It could be avoided by making IF condition
more strict.
Found by Linux Verification Center
On 15/4/24 08:56, Thomas Huth wrote:
First patch fixes the problem that the file hw/cpu/Kconfig is
currently ignored and the switches there are duplicated in hw/arm/.
The second patch introduces a proper config switch for the cpu-cluster
device.
v2:
- Don't make core.c depend on the
On Tue, Apr 16, 2024 at 1:43 PM Yuri Benditovich
wrote:
>
> On Tue, Apr 16, 2024 at 7:00 AM Jason Wang wrote:
> >
> > On Mon, Apr 15, 2024 at 10:05 PM Yuri Benditovich
> > wrote:
> > >
> > > On Wed, Apr 3, 2024 at 2:11 PM Akihiko Odaki
> > > wrote:
> > > >
> > > > vhost requires eBPF for RSS.
Hi Cédric,
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
>compatibility check with host IOMMU cap/ecap
>
>On 4/8/24 10:44, Zhenzhong Duan wrote:
>> From: Yi Liu
>>
>> If check fails, the host side device(either vfio or vdpa
Fix bug imported by 27ce0f3afc9dd25d21b43bbce505157afd93d111
(fix Power Management Control Register for PCI Express virtio devices)
Only state of PM_CTRL is writable.
Only when flag VIRTIO_PCI_FLAG_INIT_PM is set, need to reset state.
Signed-off-by: Jiqian Chen
---
hw/virtio/virtio-pci.c | 8
In current code, when guest does S3, virtio-gpu are reset due to the
bit No_Soft_Reset is not set. After resetting, the display resources
of virtio-gpu are destroyed, then the display can't come back and only
show blank after resuming.
Implement No_Soft_Reset bit of PCI_PM_CTRL register, then
Hi all,
This is the v9 patch to support S3.
v9 makes below changes:
* patch#1 no changes
* patch#2 remove unnecessary parentheses.
add some comments to remind we may need to consider SUSPEND bit in
future.
change the commit message to describe which virtio device was tested.
On 2024/04/16 13:00, Jason Wang wrote:
On Mon, Apr 15, 2024 at 10:05 PM Yuri Benditovich
wrote:
On Wed, Apr 3, 2024 at 2:11 PM Akihiko Odaki wrote:
vhost requires eBPF for RSS. When eBPF is not available, virtio-net
implicitly disables RSS even if the user explicitly requests it. Return
an
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i: D-form
isel: A-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same,
Moving the following instructions to decodetree :
mul{ld, ldo, hd, hdu}[.]: XO-form
madd{hd, hdu, ld} : VA-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d
Moving the following instructions to decodetree specification :
mulli : D-form
mul{lw, lwo, hw, hwu}[.]: XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op'
Moving the below instructions to decodetree specification :
divd[u, e, eu][o][.]: XO-form
mod{sd, ud} : X-form
With this patch, all the fixed-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s]: D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d}, prty{w, d}, cmp, bpermd : X-form
The handler methods for divw[u] instructions internally use Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if we move
the above said instructions to decodetree, as the ctx->opcode field is not
popluated in decodetree. Hence, making it decodetree compatible, so
Moving all fixed-point instructions of the following type to decodetree
specification : arithmetic, compare, trap, select and logical.
Chinmay Rath (8):
target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.
target/ppc: Make divw[u] handler method decodetree compatible.
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 08/10] vfio: Create host IOMMU device instance
>
>On 4/8/24 10:12, Zhenzhong Duan wrote:
>> Create host IOMMU device instance and initialize it based on backend.
>>
>> Signed-off-by: Zhenzhong Duan
>> ---
>>
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 09/10] hw/pci: Introduce
>pci_device_set/unset_iommu_device()
>
>On 4/8/24 10:12, Zhenzhong Duan wrote:
>> From: Yi Liu
>>
>> This adds pci_device_set/unset_iommu_device() to set/unset
>> HostIOMMUDevice for a given
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 07/10] backends/iommufd: Implement
>get_host_iommu_info() callback
>
>On 4/8/24 10:12, Zhenzhong Duan wrote:
>> It calls iommufd_backend_get_device_info() to get host IOMMU
>> related information.
>>
>> Define a common
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 06/10] backends/iommufd: Introduce helper
>function iommufd_backend_get_device_info()
>
>On 4/8/24 10:12, Zhenzhong Duan wrote:
>> Introduce a helper function iommufd_backend_get_device_info() to get
>> host IOMMU
201 - 253 of 253 matches
Mail list logo
