On Wed Apr 23, 2025 at 8:09 PM AEST, Ben Dooks wrote:
> In adding a new feature to the riscv target, it turns out the tb_flags
> had already got to the 32-bit limit. Everyone other target has been
> fine with uint32_t (except perhaps arm which does somethng strange to
> extend tb_flags, I think).
>
On 2025/3/26 下午7:40, Xianglai Li wrote:
When only the -kernel parameter is used to load the elf kernel,
the initrd is loaded in the ram. If the initrd size is too large,
the loading fails, resulting in a VM startup failure.
This patch first loads initrd near the kernel.
When the nearby memory
On 4/29/25 14:35, Alistair Francis wrote:
On Sat, Apr 26, 2025 at 3:36 AM Jonathan Cameron via
wrote:
On Tue, 22 Apr 2025 12:26:55 -0700
Richard Henderson wrote:
Recover two bits from the inline flags.
Hi Richard,
Early days but something (I'm fairly sure in this patch) is tripping up m
On 4/29/25 08:39, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (4):
hw/arm/virt: Update comment about Multiprocessor Affinity Register
hw/arm/virt: Remove deprecated virt-3.0 machine
hw/arm/virt: Remove deprecated virt-3.1 machine
hw/arm/virt: Remove deprecated virt-4.0 machin
On 4/29/25 08:56, Nabih Estefan wrote:
v2: used ldl_le_p and lduw_l_p instead of memcpy as per upstream
suggestion.
```
../tests/qtest/libqos/igb.c:106:5: runtime error: load of misaligned address
0x562040be8e33 for type 'uint32_t', which requires 4 byte alignment
```
Instead of straight castin
Hi, all:
Currently info mtre prints the memory-region hierarchy using two spaces as
indentation, which is not very clear when there are too many nodes.
```
(qemu) info mtree
memory-region: system
- (prio 0, i/o): system
1000- (pri
Make the hierarchical relationship between nodes clearer by adding characters
Signed-off-by: Chao Liu
---
system/memory.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/system/memory.c b/system/memory.c
index 71434e7ad0..e723928068 100644
To keep the MCD JSON protocol separate from QMP, a custom monitor has been
implemented in mcd_monitor.c which can be run in parallel to the QMP monitor.
It is responsible for handling the JSON communication and for dispatching
the corresponding functions in mcd_stub.c
The MCD server stub will call
MCD's trigger API functions support multiple triggers by expecting a pointer
to the trigger instance. Each trigger structure reserves the first four bytes
for its size. To get the specific structure, read a uint32_t at passed pointer
and compare it to the sizes of known trigger structures.
This ap
The MCD implementation follows a remote procedure call approach
and will use a client JSON protocol for communication.
While the MCD server implements the MCD API, the server stub will be
responsible for handling the JSON connection and for dispatching the
corresponding server functions.
Signed-o
gdbstub: abort gdb_set_stop_cpu when step is issued by mcdserver
Signed-off-by: Mario Fleischmann
---
gdbstub/gdbstub.c | 6 ++-
mcd/mcd_server.c | 115 ++
mcd/mcd_stub.c| 18
qapi/mcd.json | 38 ++-
4 files changed, 16
This patch series introduces support for the Multi-Core Debug (MCD) API, a
commonly used debug interface by emulators. The MCD API, defined through a
header file, consists of 54 functions for implementing debug and trace.
However, since it is a header-file-only interface, MCD does not specify a
com
The target initialization API ensures that the requested and provided
MCD versions are compatible.
* implement mcd_initialize_f and mcd_qry_error_info_f in mcdserver
* implement QMP stub functionality
* add QTest
Thanks to the QMP integration in QTest, function arguments and results
can be (de)se
The MCD implementation follows a remote procedure call approach:
Each function from mcd_api.h will correspond to one command in mcd.json.
Signed-off-by: Mario Fleischmann
---
MAINTAINERS | 1 +
docs/interop/mcd.rst | 13 +
mcd/meson.build | 27 +
In MCD, the target system is divided into system, devices and cores:
[ system ] 1-* [ devices ] 1-* [cores]
This commit implements the necessary functions to query information
about the target system.
Signed-off-by: Mario Fleischmann
---
mcd/mcd_qapi.c | 48 ++
mcd/mcd_qapi.h
qtest_qmp provides a convenient way to automatically serialize into the
client JSON protocol and to send the command to the QMP socket.
Since qtest has a strong dependency to the QMP monitor, a minimal number
of function has been added to mcd-test.c for interoperability with MCD's
protocol.
Signed
In MCD, core-specific operations require an open connection to the core.
This commit implements the necessary operations to open and close the
connection to cores.
Signed-off-by: Mario Fleischmann
---
mcd/mcd_server.c | 176 +++---
mcd/mcd_stub.c | 129 +
This commit implements the necessary operations required to establish
a connection with the MCD server:
* query information about the server
* connect to "
* disconnect from "
Signed-off-by: Mario Fleischmann
---
mcd/mcd_qapi.c | 13 +++
mcd/mcd_qapi.h | 2 +
mcd/mcd_server.c
Depending on the VM and CPU state, core states can be queried:
* MCD_CORE_STATE_DEBUG: VM halted or CPU artifically stopped
* MCD_CORE_STATE_RUNNING: VM and CPU running
* MCD_CORE_STATE_HALTED: CPU suspended
Signed-off-by: Mario Fleischmann
---
mcd/mcd_qapi.c | 16 ++
mcd/mcd_qa
Currently, only global stop is implemented
Signed-off-by: Mario Fleischmann
---
mcd/mcd_server.c | 74 +--
mcd/mcd_stub.c | 52
qapi/mcd.json| 100 +++
3 files changed, 222 insertions(+),
Signed-off-by: Mario Fleischmann
---
gdbstub/gdbstub.c | 7 ---
include/exec/gdbstub.h | 8 +++-
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 565f6b3..291ac55 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -48,1
Support three main memory space types:
* Physical memory
* Logical memory (MMU)
* GDB Registers
Use custom memory type to mark memory spaces as secure
V=1 QTEST_QEMU_BINARY="./qemu-system-arm -M virt,secure=on -cpu cortex-a15"
tests/qtest/mcd-test
Signed-off-by: Mario Fleischmann
---
mcd/mcd
Signed-off-by: Mario Fleischmann
---
docs/interop/mcd.rst | 6 ++
meson.build | 1 +
meson_options.txt | 3 +++
scripts/meson-buildoptions.sh | 3 +++
4 files changed, 13 insertions(+)
diff --git a/docs/interop/mcd.rst b/docs/interop/mcd.rst
index 9587c
Directly map MCD register groups to GDB features lists
Signed-off-by: Mario Fleischmann
---
mcd/mcd_qapi.c | 48 +++
mcd/mcd_qapi.h | 8 ++
mcd/mcd_server.c | 237 +++--
mcd/mcd_stub.c | 93 +
qapi/mcd.json |
In MCD, all accesses to register or memory are issued over transaction lists.
This commit implements three types of transactions:
* register access
* logical memory access (with MMU)
* physical memory access (no MMU)
In contrast to GDB's remote serial protocol, MCD supports specifying an
access w
Signed-off-by: Mario Fleischmann
---
gdbstub/gdbstub.c | 2 +-
include/exec/gdbstub.h | 10 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 291ac55..6ace944 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -527,7
Provide a system reset vector and handle it similar to hmp_system_reset
We don't use a QMP related shutdown reason because the mcdserver is
implemented independent of the used communication protocol.
(In fact, another communication protocol implementation for MCD already
exists and can be found at
On 29/04/2025 21.48, Pierrick Bouvier wrote:
...
I'm not keen to have a default target set, but it's a personal opinion based
on fear of "implicit smart choice hurts", so I'll be happy to change my mind
with a good argument for it.
No default target, please! We've seen this with the default ma
On Mon, Apr 28, 2025 at 05:39:46PM +0200, Cédric Le Goater wrote:
> > +static void vfio_device_get_all_region_info(VFIODevice *vbasedev)
> > +{
> > +struct vfio_region_info *info;
> > +int i;
> > +
> > +for (i = 0; i < vbasedev->num_regions; i++) {
> > +vfio_device_get_region_i
On Tue, Apr 29, 2025 at 4:20 PM Joel Stanley wrote:
>
> This is a set of cleanups for the riscv virt machine device tree
> generation that apply on top of Daniel's recent series.
>
> Using dumpdtb the old and new device trees are identical for -M virt and
> -M virt,aia=aplic-imsic.
>
> The final p
On 4/29/25 2:14 PM, Pierrick Bouvier wrote:
On 4/29/25 3:28 AM, Alex Bennée wrote:
Pierrick Bouvier writes:
"linux/kvm.h" is not included for code compiled without
COMPILING_PER_TARGET, and headers are different depending architecture
(arm, arm64).
Thus we need to manually expose some definit
On Tue, Apr 29, 2025 at 05:21:40PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> For automatic tests, we need reference files from older QEMU versions.
> QEMU 7.2 is a long term stable release, so it's a good candidate for
> checking whether the migration could still work correctly. Let's add
On Thu Apr 24, 2025 at 6:25 PM AEST, Thomas Huth wrote:
> On 08/04/2025 14.45, Nicholas Piggin wrote:
>> The per-core SCRATCH0-7 registers are shared between big cores, which
>> was missed in the big-core implementation. It is difficult to model
>> well with the big-core == 2xPnvCore scheme we move
With load_elf() api, image load low address and high address is converted
to physical address if parameter translate_fn is provided. However
executing entry address is still virtual address. Here convert entry
address into physical address, since MMU is disabled when system power on,
the first PC i
On 30/04/2025 02.00, Nicholas Piggin wrote:
On Thu Apr 24, 2025 at 6:25 PM AEST, Thomas Huth wrote:
On 08/04/2025 14.45, Nicholas Piggin wrote:
The per-core SCRATCH0-7 registers are shared between big cores, which
was missed in the big-core implementation. It is difficult to model
well with the
On 29/4/25 23:11, Pierrick Bouvier wrote:
On 4/29/25 11:01 AM, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 29/4/25 07:00, Pierrick Bouvier wrote:
Following what we did for hw/, we need target specific common libraries
for target. We need 2 different libraries:
- code common to a base archite
On 30/4/25 00:02, Pierrick Bouvier wrote:
On 4/29/25 2:14 PM, Pierrick Bouvier wrote:
On 4/29/25 3:28 AM, Alex Bennée wrote:
Pierrick Bouvier writes:
"linux/kvm.h" is not included for code compiled without
COMPILING_PER_TARGET, and headers are different depending architecture
(arm, arm64).
T
在 2025/4/30 上午11:04, Bibo Mao 写道:
With load_elf() api, image load low address and high address is converted
to physical address if parameter translate_fn is provided. However
executing entry address is still virtual address. Here convert entry
address into physical address, since MMU is disabled
On Wed Apr 30, 2025 at 7:09 AM AEST, BALATON Zoltan wrote:
> On Tue, 29 Apr 2025, Alex Bennée wrote:
>> BALATON Zoltan writes:
>>> On Tue, 29 Apr 2025, Alex Bennée wrote:
BALATON Zoltan writes:
> On Mon, 28 Apr 2025, Richard Henderson wrote:
>> On 4/28/25 06:26, BALATON Zoltan wrote:
On Tue, Apr 29, 2025 at 05:21:39PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> ghes_addr_le has been renamed to hw_error_le in commit 652f6d86cbb
> ("acpi/ghes: better name the offset of the hardware error firmware").
> Adjust the checker script to allow that changed field name.
>
> Signed
On Tue, Apr 29, 2025 at 05:21:38PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> These files reference QEMU machine types that have already been
> removed and thus are of no use anymore.
>
> Signed-off-by: Thomas Huth
I never noticed these files, but when looking it seems to me these two
d
On 4/29/25 11:06 PM, Philippe Mathieu-Daudé wrote:
On 29/4/25 23:11, Pierrick Bouvier wrote:
On 4/29/25 11:01 AM, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 29/4/25 07:00, Pierrick Bouvier wrote:
Following what we did for hw/, we need target specific common libraries
for target. We need 2
> On 29.4.2025 07:17 CEST Marc-André Lureau wrote:
>
>
> Hi
>
> On Mon, Apr 28, 2025 at 4:08 PM Dietmar Maurer wrote:
> >
> > > In file included from /home/elmarco/src/qemu/include/ui/console.h:4,
> > > from ../system/runstate.c:54:
> > > /home/elmarco/src/qemu/include/ui/q
On 4/29/25 10:40 PM, Thomas Huth wrote:
On 29/04/2025 21.48, Pierrick Bouvier wrote:
...
I'm not keen to have a default target set, but it's a personal opinion based
on fear of "implicit smart choice hurts", so I'll be happy to change my mind
with a good argument for it.
No default target, ple
Hi,
On 13/2/25 13:37, Philippe Mathieu-Daudé wrote:
+AMD folks
On 12/2/25 23:01, Richard Henderson wrote:
Use out-of-line helpers to implement extended address memory ops.
With this, we can reduce TARGET_LONG_BITS to the more natural 32
for this 32-bit cpu.
I thought about something similar
On 2025/4/29 下午10:04, Stefan Hajnoczi wrote:
Please take a look at the following CI failure:
Fail: The memory reads and writes count does not match.
Expected Reads: 114688, Actual Reads: 0
Expected Writes: 63488, Actual Writes: 32768
make[1]: *** [Makefile:202: run-plugin-memory-with-libmem.s
Hi Pierrick,
On 29/4/25 06:59, Pierrick Bouvier wrote:
On MacOS x86_64:
In file included from ../target/i386/hvf/x86_task.c:13:
/Users/runner/work/qemu/qemu/include/system/hvf.h:42:5: error: unknown type
name 'vaddr'
vaddr pc;
^
/Users/runner/work/qemu/qemu/include/system/hvf.h:43:5:
Hi Vivek
On Tue, Apr 29, 2025 at 10:19 AM Vivek Kasireddy
wrote:
>
> In the specific case where the display layer (virtio-gpu) is using
> dmabuf, and if remote clients are enabled (-spice gl=on,port=),
> it makes sense to limit the maximum (streaming) rate to 60 FPS
> using the GUI timer. Thi
On 4/24/25 09:51, Jamin Lin wrote:
v1:
Add initial support for AST27x0
The purpose of vbootrom here is to simulate the work of BootMCU SPL (riscv)
in AST2700, because QEMU doesn't support heterogenous architecture yet.
ast27x0_bootrom.bin is a simplified, free (Apache 2.0) boot ROM f
On 4/29/25 08:28, Jamin Lin wrote:
The boot ROM is a minimal implementation designed to load an AST27x0 boot image.
Its source code is available at:
https://github.com/google/vbootrom
Commit id: d6e3386709b3e49322a94ffadc2aaab9944ab77b
Build Information:
```
Build Date : Apr 29 2025 01:23:18
FW V
On 4/29/25 07:22, Thomas Huth wrote:
On 29/04/2025 02.17, Alexey Kardashevskiy wrote:
The recent kernel update 8a141be3233af7d broke the headers update,
fix it in the script.
Thanks, but the same patch is already on the list:
https://lore.kernel.org/qemu-devel/20250425052401.8287-2-rre...@lin
On 29/4/25 11:32, Daniel P. Berrangé wrote:
On Tue, Apr 29, 2025 at 11:20:59AM +0200, Thomas Huth via Devel wrote:
On 29/04/2025 10.23, Markus Armbruster wrote:
...
I don't wish to derail this thread, but we've been dancing around the
question of how to best fix the target for some time. I thi
On Mon, Apr 28 2025, Eric Auger wrote:
> Hi Connie,
>
> On 4/9/25 4:42 PM, Cornelia Huck wrote:
>> From: Eric Auger
>>
>> Also add kvm add accessors for storing host features into idregs.
> nit: add kvm add?
Too much adding, will substract one add :)
>>
>> Reviewed-by: Richard Henderson
>> Re
On Tue, Apr 29, 2025 at 11:20:59AM +0200, Thomas Huth via Devel wrote:
> On 29/04/2025 10.23, Markus Armbruster wrote:
> ...
> > I don't wish to derail this thread, but we've been dancing around the
> > question of how to best fix the target for some time. I think we should
> > talk about it for r
Fixes: c901905ea670 ("target/i386/emulate: remove flags_mask")
In c901905ea670 rflags have been removed from `x86_decode`, but there
were some leftovers.
Signed-off-by: Magnus Kulke
---
target/i386/emulate/x86_decode.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
di
On 29/4/25 10:23, Markus Armbruster wrote:
Pierrick Bouvier writes:
On 4/28/25 4:07 AM, Markus Armbruster wrote:
Peter Krempa writes:
So what should libvirt do once multiple targets are supported?
How do we query CPUs for each of the supported targets?
It's kind of a similar question w
On Mon, Apr 28 2025, Eric Auger wrote:
> On 4/9/25 4:42 PM, Cornelia Huck wrote:
>> From: Eric Auger
>>
>> Reviewed-by: Richard Henderson
>> Reviewed-by: Sebastian Ott
>> Signed-off-by: Eric Auger
>> Signed-off-by: Cornelia Huck
>> ---
>> target/arm/cpu-features.h | 40 -
On Thu, Apr 24, 2025 at 01:51:55PM +0800, Xiaoyao Li wrote:
> Date: Thu, 24 Apr 2025 13:51:55 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v8 31/55] i386/cpu: introduce
> x86_confidential_guest_cpu_instance_init()
>
> Hi Paolo,
>
> On 4/1/2025 9:01 PM, Xiaoyao Li wrote:
> ...
> > diff --git a
On Tue, Apr 29, 2025 at 11:35:52AM +0200, Philippe Mathieu-Daudé wrote:
> On 29/4/25 10:23, Markus Armbruster wrote:
> > Pierrick Bouvier writes:
> >
> > > On 4/28/25 4:07 AM, Markus Armbruster wrote:
> > > > Peter Krempa writes:
> > > >
> > > > > So what should libvirt do once multiple targets
On Tue, Apr 01, 2025 at 09:01:43AM -0400, Xiaoyao Li wrote:
> Date: Tue, 1 Apr 2025 09:01:43 -0400
> From: Xiaoyao Li
> Subject: [PATCH v8 33/55] i386/cpu: Introduce enable_cpuid_0x1f to force
> exposing CPUID 0x1f
> X-Mailer: git-send-email 2.34.1
>
> Currently, QEMU exposes CPUID 0x1f to gues
On Mon, Apr 28 2025, Eric Auger wrote:
> On 4/9/25 4:42 PM, Cornelia Huck wrote:
>> From: Eric Auger
>>
>> Reviewed-by: Richard Henderson
>> Reviewed-by: Sebastian Ott
>> Signed-off-by: Eric Auger
>> Signed-off-by: Cornelia Huck
>> ---
>> target/arm/cpu-features.h | 16
>>
On Tue, Apr 01, 2025 at 09:01:44AM -0400, Xiaoyao Li wrote:
> Date: Tue, 1 Apr 2025 09:01:44 -0400
> From: Xiaoyao Li
> Subject: [PATCH v8 34/55] i386/tdx: Force exposing CPUID 0x1f
> X-Mailer: git-send-email 2.34.1
>
> TDX uses CPUID 0x1f to configure TD guest's CPU topology. So set
> enable_cp
On Mon, Apr 28 2025, Eric Auger wrote:
> On 4/9/25 4:42 PM, Cornelia Huck wrote:
>> From: Eric Auger
>>
>> Reviewed-by: Richard Henderson
>> Reviewed-by: Sebastian Ott
>> Signed-off-by: Eric Auger
>> Signed-off-by: Cornelia Huck
>> ---
>> hw/intc/armv7m_nvic.c | 12 ++--
>> target/arm/
On Tue, Apr 01, 2025 at 09:01:45AM -0400, Xiaoyao Li wrote:
> Date: Tue, 1 Apr 2025 09:01:45 -0400
> From: Xiaoyao Li
> Subject: [PATCH v8 35/55] i386/tdx: Set kvm_readonly_mem_enabled to false
> for TDX VM
> X-Mailer: git-send-email 2.34.1
>
> TDX only supports readonly for shared memory but n
Remove an unused 'KVMScratchCPU' pointer argument in
kvm_riscv_check_sbi_dbcn_support().
Put kvm_riscv_reset_regs_csr() after kvm_riscv_put_regs_csr(). This will
make a future patch diff easier to read, when changes in
kvm_riscv_reset_regs_csr() and kvm_riscv_get_regs_csr() will be made.
Fixes: a
We're going to add support for scounteren in the next patch. KVM defines
as a target_ulong CSR, while QEMU defines env->scounteren as a 32 bit
field. This will cause the current code to read/write a 64 bit CSR in a
32 bit field when running in a 64 bit CPU.
To prevent that, change the current logi
Add support for the scounteren KVM CSR. Note that env->scounteren is a
32 bit and all KVM CSRs are target_ulong, so scounteren will be capped
to 32 bits read/writes.
Reported-by: Andrew Jones
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 2 ++
We need the reg_id_ulong() helper to be a macro to be able to create a
static array of KVMCPUConfig that will hold CSR information.
Despite the amount of changes all of them are tedious/trivial:
- replace instances of "kvm_riscv_reg_id_ulong" with
"KVM_RISCV_REG_ID_ULONG";
- RISCV_CORE_REG(),
We're missing the senvcfg CSRs which is already present in the
KVM UAPI.
Reported-by: Andrew Jones
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm
'reglist' is being g-malloc'ed but never freed.
Reported-by: Andrew Jones
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
target/riscv/kvm/kvm-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/kvm/kvm-cpu.
Joel,
I'll make these changes in this patch to be consistent with what we've
been discussing:
- change addr to hwaddr
- use HWADDR_PRIx instead of PRIx64
i.e. this diff:
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 1eae84db15..0020d8f404 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt
Hi,
This version has a fix on patch 8 where I did use an extra variable and
happened to set the wrong mask too.
We'll let the compiler cast the uint32_t from an uint64_t reg. A cast
was added for extra clarity when reading the code, although some picky
toolchains might require an explicit cast in
At this moment we're not checking if the host has support for any
specific CSR before doing get/put regs. This will cause problems if the
host KVM doesn't support it (see [1] as an example).
We'll use the same approach done with the CPU extensions: read all known
KVM CSRs during init() to check fo
[1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6.
This happens because the kernel does not know 'senvcfg', making it
unable to boot because QEMU is reading/wriiting it without any checks.
After converting the CSRs to do "automated" get/put reg procedures in
the previous patc
This change is motivated by a future change w.r.t CSRs management. We
want to handle them the same way as KVM extensions, i.e. a static array
with KVMCPUConfig objs that will be read/write during init and so on.
But to do that properly we must be able to declare a static array that
hold KVM regs.
On Tue, Apr 29, 2025 at 02:27:21PM +0200, Paolo Bonzini wrote:
> Il mar 29 apr 2025, 14:17 Magnus Kulke ha
> scritto:
>
> > Yes, I'm using the generalized emulator in the context of adding the MSHV
> > accelerator. (I'll probably get around sending an RFC patchset this week
> > for
> > it). There
Hi,
> On Thu, Apr 17, 2025 at 01:05:37PM -0300, Fabiano Rosas wrote:
> > It's not that page faults happen during multifd. The page was already
> > sent during precopy, but multifd-recv didn't write to it, it just marked
> > the receivedmap. When postcopy starts, the page gets accessed and
> > faul
We should use s->memmap instead of virt_memmap to be able to use an
updated memmap when we start versioning the board.
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/virt.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/virt.c b/
Hi,
In this new version a small change was made in patch 9 after
discussions with Joel during v1 [1]. The idea is that we want to be
consistent (as close as we can) with the idea that a
memory address is a hwaddr type.
This new version does not conflict with "hw/riscv/virt: device tree reg
cleanu
create_fdt_virtio() can use s->memmap instead of having an extra
argument for it.
While we're at it rewrite it a little bit to avoid the clunky line in
'name' and code repetition:
- declare 'virtio_base' out of the loop since it never changes;
- declare a 'size' variable. Use it to calculate the
Change create_fdt_pcie(), create_fdt_reset(), create_fdt_uart() and
create_fdt_rtc() to use s->memmap in their logic.
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/virt.c | 44 ++--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/r
On 4/29/25 3:12 AM, Joel Stanley wrote:
The address is a hardware address, so use hwaddr for consistency with
the rest of the machine.
Signed-off-by: Joel Stanley
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
dif
The function can receive the value via s->memmap[VIRT_FW_CFG].base from
the caller, avoiding the use of virt_memmap.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/virt.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/v
create_fdt(), create_fdt_flash() and create_fdt_fw_cfg() can access the
memmap via their RISCVVirtState pointers.
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/virt.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index b4a6916abb..f324777161 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1429,9 +1429,8 @@ static void virt_m
Throughout the code we're accessing the board memmap, most of the time,
by accessing it statically via 'virt_memmap'. This static map is also
assigned in the machine state in s->memmap.
We're also passing it as a variable to some fdt functions, which is
unorthodox since we can spare a function arg
create_fdt_sockets() and all its fdt helpers (create_fdt_socket_aplic(),
create_fdt_imsic(), create_fdt_socket_plic(), create_fdt_socket_aclint()
and create_fdt_socket_memory()) can use s->memmap from their
RISCVVirtState pointer instead of having an extra memmap argument.
Signed-off-by: Daniel He
We can avoid the 'long' casts by using PRIx64 and HWADDR_PRIx on the fmt
strings for uint64_t and hwaddr types.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/virt.c | 32 +---
1 file changed, 17 insertions(+), 15 deletions(-)
On Tue, Apr 29, 2025 at 06:21:13PM +0530, Prasad Pandit wrote:
> Hi,
>
> > On Thu, Apr 17, 2025 at 01:05:37PM -0300, Fabiano Rosas wrote:
> > > It's not that page faults happen during multifd. The page was already
> > > sent during precopy, but multifd-recv didn't write to it, it just marked
> > >
When VERSION is set to a development snapshot (micro >= 50), or a release
candidate (micro >= 90) we have an off-by-1 in determining deprecation
and deletion thresholds for versioned machine types. In such cases we need
to use the next major/minor version in threshold checks.
This adapts the depre
This reverts commit c9fd2d9a48ee3c195cf83cc611b87b09f02f0013.
When we introduced the specialized machine type deprecation policy, we
allow automatic deprecation to take effect immediately, but blocked the
automatic deletion of machine types for 2 releases. This ensured we
complied with the histori
If we change the deprecation logic in include/hw/boards.h, we must make
a corresponding change to docs/conf.py and docs/about/deprecated.rst.
Add comments to these files as a warning to future maintainers to keep
these files in sync.
Reviewed-by: Thomas Huth
Signed-off-by: Daniel P. Berrangé
---
We remove versioned machine types on a fixed schedule. This allows us
to auto-generate a paragraph in the removed-features.rst document that
always has accurate version info.
Signed-off-by: Daniel P. Berrangé
---
docs/about/removed-features.rst | 10 ++
docs/conf.py|
Since we deprecate and remove versioned machine types on a fixed
schedule, we can automatically ensure that the docs reflect the
latest version info, rather than requiring manual updates on each
dev cycle.
The first patch in this series removes the hack which postponed
automatic removal of version
We deprecate versioned machine types on a fixed schedule. This allows us
to auto-generate a paragraph in the deprecated.rst document that always
has accurate version info.
Signed-off-by: Daniel P. Berrangé
---
docs/about/deprecated.rst | 7 +++
docs/conf.py | 33 +++
On Fri, 25 Apr 2025 at 15:42, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 17/3/25 15:28, Peter Maydell wrote:
> > Currently we provide an AArch64 gdbstub for CPUs which are
> > TYPE_AARCH64_CPU, and an AArch32 gdbstub for those which are only
> > TYPE_ARM_CPU. This mostly does the right th
On 4/29/25 09:08, Vivek Kasireddy wrote:
> +#ifdef GL_EXT_memory_object_fd
> +glCreateMemoryObjectsEXT(1, &mem_obj);
> +glImportMemoryFdEXT(mem_obj, size, GL_HANDLE_TYPE_OPAQUE_FD_EXT, fd);
> +if (glGetError() != GL_NO_ERROR) {
> +error_report("spice: cannot import memory object
From: Vincent Vanlaer
Signed-off-by: Vincent Vanlaer
Tested-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20241026163010.2865002-6-libvirt-e6954...@volkihar.be>
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/tests/commit-zero-bloc
From: "Dr. David Alan Gilbert"
co_try_get_from_shres hasn't been used since it was added in
55fa54a789 ("co-shared-resource: protect with a mutex")
(Everyone uses the _locked version)
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Message-Id: <20240918124220.27871-1-d...@treblig.org>
Signe
From: Vincent Vanlaer
bdrv_co_common_block_status_above not only returns whether the block is
allocated, but also if it contains zeroes.
Signed-off-by: Vincent Vanlaer
Reviewed-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20241026163010.2865002-2-libvirt-e6954...@volkihar.be>
Signed-off-by: V
1 - 100 of 317 matches
Mail list logo
