Thanks for the patch!
I an waiting for Stefan's comments to be addressed.
Additionally, something to improve:
On Wed, Mar 26, 2025 at 04:25:37PM +0800, [email protected] wrote:
> From: Huaitong Han
>
> The vring call fd is set even when the guest does not use msix (e.g., in the
> case of virtio p
On Tue, Apr 15, 2025 at 10:47:25PM -0400, Haoqian He wrote:
> At the end of the VM live migration, the vhost device will be stopped.
> Currently, if the vhost-user backend crashes, vhost device's set_status()
> would not return failure, live migration won't perceive the disconnection
> with the bac
On Thu, Apr 24, 2025 at 01:24:38PM +0100, Alireza Sanaee wrote:
> From: Yicong Yang
>
> Currently we build the PPTT starting from the socket node and each
> socket will be a separate tree. For a multi-socket system it'll
> be hard for the OS to know the whole system is homogeneous or not
> (actua
On Fri, May 09, 2025 at 12:04:19PM +0200, Thomas Huth wrote:
> Date: Fri, 9 May 2025 12:04:19 +0200
> From: Thomas Huth
> Subject: How to mark internal properties (was: Re: [PATCH v4 12/27]
> target/i386/cpu: Remove CPUX86State::enable_cpuid_0xb field)
>
> On 09/05/2025 09.32, Zhao Liu wrote:
>
Dear KVM Team,
I am currently evaluating different approaches to achieve VM-consistent
snapshots and would appreciate your insights on the matter.
My analysis has identified two main approaches for quiescing a VM:
1. Quiescing by pausing (or suspending) the entire VM - as currently
impleme
This patch fixes two critical issues in QEMU with KVM:
Post-Migration Failure in User Mode: When QEMU with KVM is running in user
mode, the guest may fail to function correctly after migration.
Multi-Core Guest Inconsistency: After migration, only the first CPU (core 0)
remains functional, while
This patch fixes two critical issues in QEMU with KVM:
Post-Migration Failure in User Mode: When QEMU with KVM is running in user
mode, the guest may fail to function correctly after migration.
Multi-Core Guest Inconsistency: After migration, only the first CPU (core 0)
remains functional, while
Recently, we removed ipv6 restriction[0] from RDMA migration, add a
test for it.
[0]
https://lore.kernel.org/qemu-devel/[email protected]/
Cc: Jack Wang
Cc: Michael R. Galaxy
Cc: Peter Xu
Cc: Yu Zhang
Reviewed-by: Jack Wang
Signed-off-by: Li Zhijian
---
V3:
- ski
On 06/05/2025 16.38, Philippe Mathieu-Daudé wrote:
E1000_FLAG_MAC was only used by the hw_compat_2_4[] array,
via the 'extra_mac_registers=off' property. We removed all
machines using that array, lets remove all the code around
E1000_FLAG_MAC, including the MAC_ACCESS_FLAG_NEEDED enum,
similarly
On 09/05/2025 23:32, Peter Xu wrote:
> Does this mean I'll need to setup twice, one for each v?
>
> Even if so, I did this:
>
> ===8<===
> $ sudo ../scripts/rdma-migration-helper.sh setup
> Setup new rdma/rxe wlp0s20f3_rxe for wlp0s20f3 with 192.168.68.123
> $ sudo IP_FAMILY=ipv6 ../scripts/rdm
On Mon, May 12, 2025 at 09:36:51AM +0530, Sairaj Kodilkar wrote:
> From: Vasant Hegde
>
> If vCPUs > 255 then x86 common code (x86_cpus_init()) call
> kvm_enable_x2apic().
> But if vCPUs <= 255 then it won't call kvm_enable_x2apic().
>
> Booting guest in x2apic mode, amd-iommu,xtsup=on and <= 2
On 5/11/2025 11:22 PM, Michael S. Tsirkin wrote:
On Fri, May 09, 2025 at 12:15:24PM +0530, Sairaj Kodilkar wrote:
Fix following two issues in the amd viommu
1. The guest fails to setup the passthrough device when for following setup
because amd iommu enables the no DMA memory region even
++ Philippe Mathieu-Daudé
On 5/9/2025 12:15 PM, Sairaj Kodilkar wrote:
Fix following two issues in the amd viommu
1. The guest fails to setup the passthrough device when for following setup
because amd iommu enables the no DMA memory region even when guest is
using DMA remapping mode.
Hi,
On Fri, 9 May 2025 at 20:41, Peter Xu wrote:
> Isn't that what multifd is doing already?
> typedef struct {
> ...
> /*
> * This array contains the pointers to:
> * - normal pages (initial normal_pages entries)
> * - zero pages (following zero_pages entries)
> */
Thomas Huth writes:
> On 09/05/2025 09.32, Zhao Liu wrote:
>> On Fri, May 09, 2025 at 02:49:27PM +0800, Xiaoyao Li wrote:
>>> Date: Fri, 9 May 2025 14:49:27 +0800
>>> From: Xiaoyao Li
>>> Subject: Re: [PATCH v4 12/27] target/i386/cpu: Remove
>>> CPUX86State::enable_cpuid_0xb field
>>>
>>> On 5
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common error conditions.
Signed-off-by: Alejandro Jimenez
---
hw/i3
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
Add the minimal data structures required to maintain a list of address
spaces (i.e. devices) with registered notifiers, and to update the type of
events that require notifications.
Note that the ability to register for MAP notifications is not avai
On 5/2/2025 7:46 AM, Alejandro Jimenez wrote:
Enable the appropriate memory region for an address space depending on the
address translation mode selected for it. This is currently based on a
generic x86 IOMMMU property, and only done during the address space
s/IOMMMU/IOMMU
initialization.
On Mon, Apr 28, 2025 at 12:07:50PM +0100, Alireza Sanaee wrote:
> Specify which layer (core/cluster/socket) caches found at in the CPU
> topology. Updating cache topology to device tree (spec v0.4).
> Example:
>
> Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
> created, in aggr
On Tue, Apr 29, 2025 at 02:15:21PM +0100, Daniel P. Berrangé wrote:
> Since we deprecate and remove versioned machine types on a fixed
> schedule, we can automatically ensure that the docs reflect the
> latest version info, rather than requiring manual updates on each
> dev cycle.
>
> The first pa
On Fri, May 02, 2025 at 02:15:46AM +, Alejandro Jimenez wrote:
> Invalidating the entire address space (i.e. range of [0, ~0ULL]) is a
> valid and required operation by vIOMMU implementations. However, such
> invalidations currently trigger an assertion unless they originate from
> device IOTLB
On Fri, May 02, 2025 at 02:15:45AM +, Alejandro Jimenez wrote:
> This series adds support for guests using the AMD vIOMMU to enable DMA
> remapping for VFIO devices. In addition to the currently supported
> passthrough (PT) mode, guest kernels are now able to to provide DMA
> address translatio
On Sun, May 11, 2025 at 06:20:41PM +0300, Yan Vugenfirer wrote:
> On Sun, May 11, 2025 at 4:27 PM Michael S. Tsirkin wrote:
> >
> > On Wed, Mar 12, 2025 at 02:43:52PM +0200, Yan Vugenfirer wrote:
> > >
> > >
> > > On Tue, Mar 11, 2025 at 4:02 AM Suthikulpanit, Suravee <
> > > suravee.suthikulpa...
On 5/10/25 09:36, Andreas Schwab wrote:
On Mai 07 2025, Richard Henderson wrote:
+/* Convert the 3 digit decimal exponent to binary. */
+exp = ((hi >> 24) & 0xf)
++ ((hi >> 20) & 0xf) * 10
++ ((hi >> 16) & 0xf) * 100;
This is backwards. An exponent of 123 is stored as
If CPPR is lowered to preclude the pending interrupt, NSR should be
cleared and the qemu_irq should be lowered. This avoids some cases
of supurious interrupts.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
From: Michael Kowal
In a multi chip environment there will be remote/forwarded VSDs. The check
to find a matching INT controller (XIVE) of the remote block number was
checking the INTs chip number. Block numbers are not tied to a chip number.
The matching remote INT is the one that matches the
Rather than functions to return masks to test NSR bits, have functions
to test those bits directly. This should be no functional change, it
just makes the code more readable.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c| 51 +++
include/hw/ppc
From: Michael Kowal
When the END Event Queue wraps the END EQ Generation bit is flipped and the
Generation Flipped bit is set to one. On a END cache Watch read operation,
the Generation Flipped bit needs to be reset.
While debugging an error modified END not valid error messages to include
the
Test that the NSR exception bit field is equal to the pool ring value,
rather than any common bits set, which is more correct (although there
is no practical bug because the LSI NSR type is not implemented and
POOL/PHYS NSR are encoded with exclusive bits).
Fixes: 4c3ccac636 ("pnv/xive: Add specia
From: Glenn Miles
The queue size of an Event Notification Descriptor (END)
is determined by the 'cl' and QsZ fields of the END.
If the cl field is 1, then the queue size (in bytes) will
be the size of a cache line 128B * 2^QsZ and QsZ is limited
to 4. Otherwise, it will be 4096B * 2^QsZ with QsZ
From: Glenn Miles
Add support for XIVE ESB Interrupt Escalation.
Suggested-by: Michael Kowal
[This change was taken from a patch provided by Michael Kowal.]
Signed-off-by: Glenn Miles
---
hw/intc/xive2.c | 62 ++---
include/hw/ppc/xive2.h | 1
The group interrupt delivery flow selects the group backlog scan if
LSMFB < IPB, but that scan may find an interrupt with a priority >=
IPB. In that case, the VP-direct interrupt should be chosen. This
extends to selecting the lowest prio between POOL and PHYS rings.
Implement this just by re-star
On Mon, Apr 07, 2025 at 03:49:21PM +0800, Chenyi Qiang wrote:
> Date: Mon, 7 Apr 2025 15:49:21 +0800
> From: Chenyi Qiang
> Subject: [PATCH v4 01/13] memory: Export a helper to get intersection of a
> MemoryRegionSection with a given range
> X-Mailer: git-send-email 2.43.5
>
> Rename the helper
These changes gets the powernv xive2 to the point it is able to run
PowerVM with good stability.
* Various bug fixes around lost interrupts particularly.
* Major group interrupt work, in particular around redistributing
interrupts. Upstream group support is not in a complete or usable
state as
From: Glenn Miles
According to the XIVE spec, updating the CPPR should also update the
PIPR. The final value of the PIPR depends on other factors, but it
should never be set to a value that is above the CPPR.
Also added support for redistributing an active group interrupt when it
is precluded as
From: Michael Kowal
Writes to the Flush Control registers were logged as invalid
when they are allowed. Clearing the unsupported want_cache_disable
feature is supported, so don't log an error in that case.
Signed-off-by: Michael Kowal
---
hw/intc/pnv_xive2.c | 36 ++
From: Glenn Miles
When an XIVE context is pulled while it has an active, unacknowledged
group interrupt, XIVE will check to see if a context on another thread
can handle the interrupt and, if so, notify that context. If there
are no contexts that can handle the interrupt, then the interrupt is
a
Further split xive_tctx_pipr_update() by splitting out a new function
that is used to re-compute the PIPR from IPB. This is generally only
used with XIVE1, because group interrputs require more logic.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 25 ++---
1 file change
From: Glenn Miles
Change pregs to pool_regs, for clarity.
[npiggin: split from larger patch]
Signed-off-by: Glenn Miles
---
hw/intc/xive2.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 968b698677..ec4b9320b4 100644
---
Implement pool context push TIMA op.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 4
hw/intc/xive2.c| 50 --
include/hw/ppc/xive2.h | 2 ++
3 files changed, 39 insertions(+), 17 deletions(-)
diff --git a/hw/intc/xive.c b/hw/i
From: Glenn Miles
Add support for redistributing a presented group interrupt if it
is precluded as a result of changing the CPPR value. Without this,
group interrupts can be lost.
Signed-off-by: Glenn Miles
---
hw/intc/xive2.c | 82 -
1 file chan
When the pool context is pulled, the shared pool/phys signal is
reset, which loses the qemu irq if a phys interrupt was presented.
Only reset the signal if a poll irq was presented.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 18 ++
1 file changed, 10 insertions(+), 8 d
Have the match_nvt method only perform a TCTX match but don't present
the interrupt, the caller presents. This has no functional change, but
allows for more complicated presentation logic after matching.
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive.c| 16 +++---
hw/intc/pnv_xi
From: Glenn Miles
A problem was seen where uart interrupts would be lost resulting in the
console hanging. Traces showed that a lower priority interrupt was
preempting a higher priority interrupt, which would result in the higher
priority interrupt never being handled.
The new interrupt's priori
From: Glenn Miles
Booting AIX in a PowerVM partition requires the use of the "Acknowledge
O/S Interrupt to even O/S reporting line" special operation provided by
the IBM XIVE interrupt controller. This operation is invoked by writing
a byte (data is irrelevant) to offset 0xC10 of the Thread Inter
In preparation to implement POOL context push, add support for POOL
NVP context save/restore.
The NVP p bit is defined in the spec as follows:
If TRUE, the CPPR of a Pool VP in the NVP is updated during store of
the context with the CPPR of the Hard context it was running under.
It's not
Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC
register, so don't clear it on read.
Don't bother clearing the reads-as-zero CONFLICT bit because it's masked
at write already.
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c | 1 -
1 file changed, 1 deletion(-
The second part of the set CPPR operation is to process (or re-present)
any pending interrupts after CPPR is adjusted.
Split this presentation processing out into a standalone function that
can be used in other places.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 137 +++
The tctx "signaling" registers (PIPR, CPPR, NSR) raise an interrupt on
the target CPU thread. The POOL and PHYS rings both raise hypervisor
interrupts, so they both share one set of signaling registers in the
PHYS ring. The PHYS NSR register contains a field that indicates which
ring has presented
Certain TIMA operations should only be performed when a ring is valid,
others when the ring is invalid, and they are considered undefined if
used incorrectly. Add checks for this condition.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c| 196 +-
From: Glenn Miles
Add more tracing around notification, redistribution, and escalation.
Signed-off-by: Glenn Miles
---
hw/intc/trace-events | 6 ++
hw/intc/xive.c | 3 +++
hw/intc/xive2.c | 13 -
3 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/hw/in
Pushing a context and loading IPB from NVP is defined to merge ('or')
that IPB into the TIMA IPB register. PIPR should therefore be calculated
based on the final IPB value, not just the NVP value.
Fixes: 9d2b6058c5b ("ppc/xive2: Add grouping level to notification")
Signed-off-by: Nicholas Piggin
When pushing a context, the lower-level context becomes valid if it
had V=1, and so on. Iterate lower level contexts and send them
pending interrupts if they become enabled.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 36
1 file changed, 28 insertion
This is needed by the next patch which will re-send on all lower
rings when pushing a context.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 24
hw/intc/xive2.c | 28
2 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/hw/
A group interrupt that gets preempted by a higher priority interrupt
delivery must be redistributed otherwise it would get lost.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.
xive_tctx_pipr_present() as implemented with xive_tctx_pipr_update()
causes VP-directed (group==0) interrupt to be presented in PIPR and NSR
despite being a lower priority than the currently presented group
interrupt.
This must not happen. The IPB bit should record the low priority VP
interrupt, b
Have xive_tctx_notify() also set the new PIPR value and rename it to
xive_tctx_pipr_set(). This can replace the last xive_tctx_pipr_update()
caller because it does not need to update IPB (it already sets it).
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c| 39 +++--
xive2 must take into account redistribution of group interrupts if
the VP directed priority exceeds the group interrupt priority after
this operation. The xive1 code is not group aware so implement this
for xive2.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 2 ++
hw/intc/xive2.c
From: Glenn Miles
Adds support for extracting additional configuration flags from
the XIVE configuration register that are needed for redistribution
of group interrupts.
Signed-off-by: Glenn Miles
---
hw/intc/pnv_xive2.c | 16
hw/intc/pnv_xive2_regs.h | 1 +
include/hw/p
From: Glenn Miles
When disabling (pulling) an xive interrupt context, we need
to redistribute any active group interrupts to other threads
that can handle the interrupt if possible. This support had
already been added for the OS context but had not yet been
added to the pool or physical context.
The relationship between an interrupt signaled in the TIMA and the QEMU
irq line to the processor to be 1:1, so they should be raised and
lowered together and "just in case" lowering should be avoided (it could
mask
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 3 +--
1 file changed, 1 ins
Typo, IBP should be IPB.
Signed-off-by: Nicholas Piggin
---
hw/intc/trace-events | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 0ba9a02e73..f77f9733c9 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -274
From: Michael Kowal
This can make it easier to see what the target system is trying to
do.
[npiggin: split from larger patch]
Signed-off-by: Michael Kowal
---
hw/intc/pnv_xive2.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/hw/intc/pnv_xive2.c b
Implement the phys (aka hard) VP push. PowerVM uses this operation.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 2 ++
hw/intc/xive2.c| 11 +++
include/hw/ppc/xive2.h | 2 ++
3 files changed, 15 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 80
OS-push operation must re-present pending interrupts. Use the
newly created xive2_tctx_process_pending() function instead of
duplicating the logic.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 42 ++
1 file changed, 10 insertions(+), 32 deletions(-
After pulling the pool context, if a pool irq had been presented and
was cleared in the process, there could be a pending irq in phys that
should be presented. Process the phys irq ring after pulling pool ring
to catch this case and avoid losing irqs.
Signed-off-by: Nicholas Piggin
---
hw/intc/x
When CPPR priority is decreased, pending interrupts do not need to be
re-checked if one is already presented because by definition that will
be the highest priority.
This prevents a presented group interrupt from being lost.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 4 +++-
1 file ch
On 5/9/2025 5:03 PM, Baolu Lu wrote:
> On 4/7/2025 3:49 PM, Chenyi Qiang wrote:
>> With the introduction of the RamBlockAttribute object to manage
>> RAMBlocks with guest_memfd and the implementation of
>> PrivateSharedManager interface to convey page conversion events, it is
>> more elegant to
Have xive_tctx_accept clear NSR in one shot rather than masking out bits
as they are tested, which makes it clear it's reset to 0, and does not
have a partial NSR value in the register.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
Group interrupts should not be taken from the backlog and presented
if they are precluded by CPPR.
Fixes: 855434b3b8 ("ppc/xive2: Process group backlog when pushing an OS
context")
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
This improves the implementation of pulling pool and phys contexts in
XIVE1, by following closer the OS pulling code.
In particular, the old ring data is returned rather than the modified,
and irq signals are reset on pull.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 66
When pushing a context, any presented group interrupt should be
redistributed before processing pending interrupts to present
highest priority.
This can occur when pushing the POOL ring when the valid PHYS
ring has a group interrupt presented, because they share signal
registers.
Signed-off-by: N
Add some assertions to try to ensure presented group interrupts do
not get lost without being redistributed, if they become precluded
by CPPR or preempted by a higher priority interrupt.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 2 ++
hw/intc/xive2.c | 1 +
2 files changed, 3 insertio
Implement set LGS for the POOL ring.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index dc64edf13d..807a1c1c34 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -532,6 +532,12 @@ static void xive_t
From: Glenn Miles
The current xive algorithm for finding a matching group vCPU
target always uses the first vCPU found. And, since it always
starts the search with thread 0 of a core, thread 0 is almost
always used to handle group interrupts. This can lead to additional
interrupt latency and po
Report access size in XIVE TM operation error logs.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 3eb28c2265..80b07a0afe 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -326,
xive_tctx_pipr_update() is used for multiple things. In an effort
to make things simpler and less overloaded, split out the function
that is used to present a new interrupt to the tctx.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c| 8 +++-
hw/intc/xive2.c | 2 +-
include/h
Dear QEMU Developers,
I am Soumyajyotii Ssarkar, a sophomore Computer Science student from India.
It is truly an honor for me to be a part of this community. I look forward
to a productive summer with our community.
For the first half of my summer, I will be working on thoroughly testing
and debug
Hi Cédric
> From: Cédric Le Goater
>
> Subject: Re: [PATCH v1 11/22] hw/misc/aspeed_hace: Add trace-events for
> better debugging
>
> On 3/21/25 10:26, Jamin Lin wrote:
> > Introduced "trace_aspeed_hace_addr", "trace_aspeed_hace_sg",
> > "trace_aspeed_hace_read", and "trace_aspeed_hace_write" tr
Hi Peter,
Sorry about that. When I ran this qtest and I found an error then I
tried to modify npcm_pspi driver to make data register read/write test
pass.
[R +0.080118] writew 0xf0201002 0x4
[S +0.080126] OK
[R +0.080148] readw 0xf0201002
[S +0.080153] OK 0x0004
[R +0.080168] writew 0x
Hi Cédric, Peter,
> -Original Message-
> From: Peter Maydell
> Sent: Friday, May 9, 2025 11:28 PM
> To: Cédric Le Goater
> Cc: [email protected]; [email protected]; Steven Lee
>
> Subject: Re: [PULL 22/23] tests/function/aspeed: Add functional test for
> ast2700fc
>
> On Fri, 9 M
On Sun, May 11, 2025 at 4:27 PM Michael S. Tsirkin wrote:
>
> On Wed, Mar 12, 2025 at 02:43:52PM +0200, Yan Vugenfirer wrote:
> >
> >
> > On Tue, Mar 11, 2025 at 4:02 AM Suthikulpanit, Suravee <
> > [email protected]> wrote:
> >
> >
> >
> > On 3/9/2025 8:44 PM, Michael S. Tsirkin w
On Fri, May 09, 2025 at 12:15:24PM +0530, Sairaj Kodilkar wrote:
> Fix following two issues in the amd viommu
> 1. The guest fails to setup the passthrough device when for following setup
>because amd iommu enables the no DMA memory region even when guest is
>using DMA remapping mode.
>
>
On 25/04/2025 10:35, Clément Chigot wrote:
(added Richard on CC)
FSR_NVA should be set when one of the operands is a signaling NaN or
when using FCMPEx instructions. But those cases are already handled
within check_ieee_exception or floatxx_compare functions.
Otherwise, it should be left untouc
On 11/05/2025 08:38, Volker Rümelin wrote:
There is no need to allocate initialized memory with g_malloc0()
if it's directly followed by a memset() function call. g_malloc()
is sufficient.
Signed-off-by: Volker Rümelin
---
hw/audio/asc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 11/05/2025 08:38, Volker Rümelin wrote:
AUD_open_out() may fail and return NULL. This may then lead to
a segmentation fault in memset() below. The memset() behaviour
is undefined if the pointer to the destination object is a null
pointer.
Add the missing error handling code.
Signed-off-by:
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for xtensa targets.
Signed-off-by: Julian Ganz
---
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for ARM (and Aarch64) targets. We decided to
treat th
The plugin API allows registration of callbacks for a variety of VCPU
related events, such as VCPU reset, idle and resume. However, traps of
any kind, i.e. interrupts or exceptions, were previously not covered.
These kinds of events are arguably quite significant and usually go hand
in hand with a
We recently introduced plugin API for the registration of callbacks for
discontinuity events, specifically for interrupts, exceptions and host
call events. The callback receives various bits of information,
including the VCPU index and PCs.
This change introduces a test plugin asserting the correc
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for loongarch targets. This architecture
has one spec
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for RISC-V targets.
Signed-off-by: Julian Ganz
---
On Fri, Feb 28, 2025 at 05:27:23PM +0800, Bibo Mao wrote:
> This patchset add bios-tables-test for LoongArch64 virt machine
> system. It works with UEFI bios, with uefi-test-tools LoongArch64
> support is added to build bios-tables-test.loongarch64.iso.
>
> Also with test case bios-tables-test, Lo
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for Motorola 68000 targets.
Signed-off-by: Julian Ga
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places the hook for AVR targets. That architecture appears
to only
The plugin API allows registration of callbacks for a variety of VCPU
related events, such as VCPU reset, idle and resume. In addition, we
recently introduced API for registering callbacks for discontinuity
events, specifically for interrupts, exceptions and host calls.
This change introduces the
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for Renesas Xtreme targets.
Signed-off-by: Julian Ga
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for SPARC (32bit and 64bit) targets. We treat
any int
Some analysis greatly benefits, or depends on, information about
certain types of dicontinuities such as interrupts. For example, we may
need to handle the execution of a new translation block differently if
it is not the result of normal program flow but of an interrupt.
Even with the existing in
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places the hook for MicroBlaze targets. This architecture
has one
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