CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 07:07:08
Modified files:
. : cpu-defs.h cpu-exec.c exec-all.h exec.c
softmmu_exec.h softmmu_header.h
softmmu_template.h
On 10/13/07, Robert Reif [EMAIL PROTECTED] wrote:
I'm trying to add SuperSparc II MXCC support and need some feedback.
Is there a better way to read and write physical memory in 64bit chunks?
I'm not sure what I'm doing is portable between 32/64 and big/little endian.
Thank you for your
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 08:18:12
Modified files:
target-alpha : op.c op_helper.c
Log message:
Generate micro-ops for Alpha executive and supervisor modes.
CVSWeb URLs:
On 10/14/07, J. Mayer [EMAIL PROTECTED] wrote:
On Sat, 2007-10-13 at 16:17 +0200, J. Mayer wrote:
On Sat, 2007-10-13 at 16:07 +0300, Blue Swirl wrote:
On 10/13/07, J. Mayer [EMAIL PROTECTED] wrote:
On Sat, 2007-10-13 at 13:47 +0300, Blue Swirl wrote:
On 10/13/07, J. Mayer [EMAIL
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 08:38:29
Modified files:
. : Makefile.target configure
Log message:
Provision for PowerPC 64 with hypervisor mode support - not enabled for
now.
For
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 08:48:24
Modified files:
hw : ppc.c
target-ppc : helper.c
Log message:
Do not allow PowerPC CPU restart after entering checkstop mode.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 08:50:17
Modified files:
target-alpha : translate.c
Log message:
Allow Alpha target to use supervisor and executive mode micro-ops.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 08:52:44
Modified files:
hw : prep_pci.c
Log message:
Fix memory corruption reported by Julian Seward
(still more bugs to fix in PreP emulation).
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 09:06:19
Modified files:
target-ppc : helper.c
Log message:
Implement PowerPC 64 SLB invalidation helpers.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 09:14:09
Modified files:
target-ppc : cpu.h helper.c translate_init.c
Log message:
There is no need of a specific MMU model for PowerPC 601.
CVSWeb URLs:
Hi list!
Just wanted to know how far the progress on alpha target is? I would be
happy if I have some 'virtual alpha' to test new isos.
If I can help some way (I have a few alphas around). Let me know.
Best,
Oliver
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 09:27:16
Modified files:
target-ppc : cpu.h
Log message:
Merge PowerPC 620 input bus definitions with standard PowerPC 6xx.
Avoid hardcoding PowerPC interrupts
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 09:35:30
Modified files:
hw : ppc.c
Log message:
Implement time-base start/stop helpers.
Implement PowerPC 6xx time-base enable input pin.
CVSWeb URLs:
On Sun, 2007-10-14 at 11:19 +0300, Blue Swirl wrote:
On 10/14/07, J. Mayer [EMAIL PROTECTED] wrote:
On Sat, 2007-10-13 at 16:17 +0200, J. Mayer wrote:
On Sat, 2007-10-13 at 16:07 +0300, Blue Swirl wrote:
On 10/13/07, J. Mayer [EMAIL PROTECTED] wrote:
On Sat, 2007-10-13 at 13:47
On Sun, 2007-10-14 at 11:19 +0200, Oliver Falk wrote:
Hi list!
Hi you !
Just wanted to know how far the progress on alpha target is? I would be
happy if I have some 'virtual alpha' to test new isos.
If I can help some way (I have a few alphas around). Let me know.
I'm happy to see someone
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer j_mayer 07/10/14 10:21:20
Modified files:
target-ppc : cpu.h helper.c
Log message:
Properly implement non-execute bit on PowerPC segments and PTEs.
Fix page protection bits for PowerPC
Here's an updated version of the code fetch optimisation patch against
current CVS.
As a remainder, this patch avoid use of softmmu helpers to fetch the
code in most case. A new target define TARGET_HAS_VLE_INSNS has been
added which is used to handle the case of an instruction that span 2
pages,
Following the discussion initiated last week about Qemu build
dependencies, I do propose to include the included patch (or the one
that was previously proposed that was very close to this one).
Please tell about any objection or improvments suggestions.
--
J. Mayer [EMAIL PROTECTED]
Never
On 10/14/07, J. Mayer [EMAIL PROTECTED] wrote:
Here's an updated version of the patch against current CVS.
This patches provides reverse-endian, little-endian and big-endian
memory accessors, available with and without softmmu. It also provides
an IO_MEM_REVERSE TLB flag to allow future
J. Mayer wrote:
[snip]
Here's a new version. The only change is that, for consistency, I did
add the big-endian and little-endian accessors that were documented in
cpu-all.h as unimplemented. The implementation is quite trivial, having
native and reverse-endian accessors available, and
Blue Swirl wrote:
On 10/13/07, Robert Reif [EMAIL PROTECTED] wrote:
I'm trying to add SuperSparc II MXCC support and need some feedback.
Is there a better way to read and write physical memory in 64bit chunks?
I'm not sure what I'm doing is portable between 32/64 and big/little endian.
Some kvm users complained that the blue and red channels are flipped on
their displays. Reverting sdl.c rev 1.40 fixed that problem, so
apparently that commit made the problem larger than it was previously.
Attached a patch the removes the commit and fixes the problem. Please
apply.
--
On 10/14/07, Avi Kivity [EMAIL PROTECTED] wrote:
Some kvm users complained that the blue and red channels are flipped on
their displays. Reverting sdl.c rev 1.40 fixed that problem, so
apparently that commit made the problem larger than it was previously.
Attached a patch the removes the
Blue Swirl wrote:
On 10/14/07, Avi Kivity [EMAIL PROTECTED] wrote:
Some kvm users complained that the blue and red channels are flipped on
their displays. Reverting sdl.c rev 1.40 fixed that problem, so
apparently that commit made the problem larger than it was previously.
Attached a patch
Updated patch base of feedback.
This patch adds SuperSparc MXCC support.
DPRINTF_MMU and DPRINTF_MXCC added.
I decided not to use do_unassigned_access() at this time because I don't
know what real hardware does.
Index: hw/sun4m.c
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl blueswir1 07/10/14 16:27:31
Modified files:
. : Makefile.target configure thunk.c thunk.h
linux-user : elfload.c elfload32.c flat.h flatload.c
linuxload.c
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl blueswir1 07/10/14 16:29:21
Modified files:
hw : sun4m.c sun4u.c
linux-user : main.c
target-sparc : cpu.h op_helper.c translate.c
Log message:
SuperSparc MXCC
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl blueswir1 07/10/14 17:07:21
Modified files:
target-sparc : cpu.h op.c op_helper.c translate.c
Log message:
Sparc64 hypervisor mode
CVSWeb URLs:
Use stq_* for 64 bit stores.
This fixes one bug where T1 was used twice rather than T1 and T2.
Should the address be 64 bit alligned? i.e. T0 ~7 rather than T0 ~3?
Should these unaligned address cause traps?
Index: target-sparc/op_helper.c
On 10/14/07, Robert Reif [EMAIL PROTECTED] wrote:
Use stq_* for 64 bit stores.
This could be less optimal for 32 bit hosts, but hopefully the
compiler knows its business.
This fixes one bug where T1 was used twice rather than T1 and T2.
Great!
Should the address be 64 bit alligned? i.e. T0
Blue Swirl wrote:
On 10/14/07, Robert Reif [EMAIL PROTECTED] wrote:
Should the address be 64 bit alligned? i.e. T0 ~7 rather than T0 ~3?
Should these unaligned address cause traps?
Yes, but the checks are already generated from translate.c
(gen_op_check_align_T0_7).
De we to
On 10/14/07, Robert Reif [EMAIL PROTECTED] wrote:
Blue Swirl wrote:
On 10/14/07, Robert Reif [EMAIL PROTECTED] wrote:
Should the address be 64 bit alligned? i.e. T0 ~7 rather than T0 ~3?
Should these unaligned address cause traps?
Yes, but the checks are already generated from
On 10/14/07, Robert Reif [EMAIL PROTECTED] wrote:
Use stq_* for 64 bit stores.
I changed also uses of 64 bit loads to ldq. But it looks like this
makes OpenBIOS trigger alignment traps, this is the same reason why
the alignment checks aren't fully enabled. So I can't commit this yet
except for
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl blueswir1 07/10/14 20:27:01
Modified files:
target-sparc : op_helper.c
Log message:
Fix bug in Sparc32 sta op (Robert Reif)
CVSWeb URLs:
On Friday 12 October 2007, Felipe Contreras wrote:
Hi,
When I try to use codesourcery's toolchain arm-2006q3-27 in my Fedora
7 box I always have the following issue:
qemu: Unsupported syscall: 983045
I guess it's a problem of NPTL incompatibility. Anyway, the patch that
Paul Brook sent a
There seem to have specific problems when using dynticks in Qemu. What I
can see is that it makes the PowerPC emulation quite unusable, at least
on my PC, which is an amd64 (with a fix CPU frequency), no matter if I
run 32 or 64 bits mode.
I'd expect to see the same problems running a
Hi,
I recently tracked down a problem in the simulation of our software
on Qemu to two small problems in the ARM MMU code.
The first is that Qemu would not enable changing of the pid register
on processors with an MMU. This is a legal operation, and one that
several parts of our kernel
On Sunday 14 October 2007, J. Mayer wrote:
Here's an updated version of the code fetch optimisation patch against
current CVS.
As a remainder, this patch avoid use of softmmu helpers to fetch the
code in most case. A new target define TARGET_HAS_VLE_INSNS has been
added which is used to
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