Hello, I am trying to inject interrupt, in final phase of Live migration.
I use vmcs_write32 function to inject interrupt. This function is called
by qemu, with ioctl.
This is Code.
(KVM)
void vmcs_write32_provider(unsigned long field, u32 value)
{
vmcs_write32(field, value);
}
long kvm_arch
Hello, I am trying to inject interrupt, in final phase of Live migration.
I use vmcs_write32 function to inject interrupt. This function is called
by qemu, with ioctl.
This is Code.
(KVM)
void vmcs_write32_provider(unsigned long field, u32 value)
{
vmcs_write32(field, value);
}
long kvm_arch_
These are comparison and conditional move opcodes.
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov
---
target-xtensa/helper.h|8
target-xtensa/op_helper.c | 47 ++
target-xtensa/translate.c | 81 -
In case Coprocessor Context option is enabled CPENABLE SR bits control
whether access to coprocessors is allowed or would rise one of
CoprocessorXDisabled exceptions.
See ISA, 4.4.5 for more details.
FP is coprocessor 0.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |5 +
t
These are FP to integer and integer to FP conversion opcodes.
See ISA, 4.3.10 for more details.
Note that utrunc.s implementation follows ISS behaviour, not ISA.
Signed-off-by: Max Filippov
---
target-xtensa/helper.h|4 +++
target-xtensa/op_helper.c | 43 ++
These are FP arithmetic opcodes.
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov
---
target-xtensa/helper.h|7 +
target-xtensa/op_helper.c | 37 +++
target-xtensa/translate.c | 61 -
3 files changed
These are load/store instructions for FP registers with immediate or
register index and optional base post-update.
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 58 +---
1 files changed, 54 insertions(+), 4
There are 16 32-bit FP registers (f0 - f15), control and status user
registers (fcr, fsr).
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov
---
gdbstub.c |8 +++
target-xtensa/cpu.h |3 ++
target-xtensa/helper.h|2 +
target-xtensa/op_helper
NaN propagation rule: leftmost NaN in the expression gets propagated to
the result.
Signed-off-by: Max Filippov
---
fpu/softfloat-specialize.h |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 4902450..9
Signed-off-by: Max Filippov
---
target-xtensa/overlay_tool.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h
index a3a5650..e395053 100644
--- a/target-xtensa/overlay_tool.h
+++ b/target-xtensa/overlay_tool.h
@@
Flags passed into float{32,64}_muladd are treated as bits; assign
independent bits to float_muladd_negate_* to allow precise control over
what gets negated in float{32,64}_muladd.
Signed-off-by: Max Filippov
---
fpu/softfloat.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --
This series implements floating point coprocessor and coprocessor context
options for xtensa and fixes a couple of bugs to make it work.
Max Filippov (9):
softfloat: make float_muladd_negate_* flags independent
target-xtensa: handle boolean option in overlays
target-xtensa: specialize softfl
On 8 September 2012 22:12, Aurelien Jarno wrote:
> We can finally get rid of the ugly HANDLE_NAN{1,2,3} macros.
This is nice. I feel like it justifies my adding all that stuff
to fpu/ for ARM :-)
-- PMM
On Fri, Sep 07, 2012 at 06:00:50PM +0200, Paolo Bonzini wrote:
> Il 07/09/2012 08:48, Nicholas A. Bellinger ha scritto:
> > Cc: Stefan Hajnoczi
> > Cc: Zhi Yong Wu
> > Cc: Michael S. Tsirkin
> > Cc: Paolo Bonzini
> > Signed-off-by: Nicholas Bellinger
> > ---
> > hw/virtio-pci.c |2 ++
> >
On 8 September 2012 22:40, Max Filippov wrote:
> On Sun, Sep 9, 2012 at 1:12 AM, Aurelien Jarno wrote:
>> float{32,64}_muladd takes an enum as a parameter, and not flags. It
>> means the parameter should be checked with == test instead of &.
>
> I've also stumbled upon this bug, have a patch for
On Sun, Sep 9, 2012 at 1:12 AM, Aurelien Jarno wrote:
> float{32,64}_muladd takes an enum as a parameter, and not flags. It
> means the parameter should be checked with == test instead of &.
>
> Cc: Peter Maydell
> Signed-off-by: Aurelien Jarno
> ---
Hi Aurelien,
I've also stumbled upon this b
Commit e024e881bb1a8b5085026589360d26ed97acdd64 provided a pickNaN()
function for PowerPC, implementing the correct NaN propagation rules.
Therefore there is no need to test the operands manually, we can rely
on the softfloat code to do that.
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
float{32,64}_muladd takes an enum as a parameter, and not flags. It
means the parameter should be checked with == test instead of &.
Cc: Peter Maydell
Signed-off-by: Aurelien Jarno
---
fpu/softfloat.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/fpu/softflo
Use the new softfloat float32_min() and float32_max() to implement the
vminfp and vmaxfp instructions. As a bonus we can get rid of the call to
the HANDLE_NAN2 macro, as the NaN handling is directly done at the
softfloat level.
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-ppc/int
Use the new softfloat float32_muladd() function to implement the vmaddfp
and vnmsubfp instructions. As a bonus we can get rid of the call to the
HANDLE_NAN3 macro, as the NaN handling is directly done at the softfloat
level.
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-ppc/int_he
We can finally get rid of the ugly HANDLE_NAN{1,2,3} macros.
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-ppc/int_helper.c | 21 -
1 file changed, 21 deletions(-)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 51cb97c..6d8bf4d 100644
-
On Fri, Sep 7, 2012 at 9:26 PM, Stefan Weil wrote:
> Am 08.09.2012 02:48, schrieb Clemens Kolbitsch:
>>
>> Hi guys,
>>
>> I need to run Win7 64bit in Qemu without KVM support. I found a few
>> messages concerning the "unsupported architecture" problem (Windows
>> shows a BSOD with "STOP 0x005D
On 08.09.2012, at 17:00, Alexander Graf wrote:
>
>
> On 08.09.2012, at 16:57, Aurelien Jarno wrote:
>
>> On Sat, Sep 08, 2012 at 04:47:43PM +0200, Alexander Graf wrote:
>>>
>>>
>>> On 08.09.2012, at 13:26, Aurelien Jarno wrote:
>>>
This remove the fallback to std-vga in case, as av
On 08.09.2012, at 16:57, Aurelien Jarno wrote:
> On Sat, Sep 08, 2012 at 04:47:43PM +0200, Alexander Graf wrote:
>>
>>
>> On 08.09.2012, at 13:26, Aurelien Jarno wrote:
>>
>>> This remove the fallback to std-vga in case, as availability of the
>>> requested vga device is now tested in vl.c,
On 08.09.2012, at 14:30, Blue Swirl wrote:
> On Sat, Sep 8, 2012 at 12:13 PM, Alexander Graf wrote:
>>
>>
>> On 08.09.2012, at 12:16, Blue Swirl wrote:
>>
>>> On Sat, Sep 8, 2012 at 9:28 AM, Alexander Graf wrote:
On 08.09.2012, at 10:06, Blue Swirl wrote:
> On
On Sat, Sep 08, 2012 at 04:47:43PM +0200, Alexander Graf wrote:
>
>
> On 08.09.2012, at 13:26, Aurelien Jarno wrote:
>
> > This remove the fallback to std-vga in case, as availability of the
> > requested vga device is now tested in vl.c, and returns an error message
> > to the user.
> >
> > C
On 08.09.2012, at 13:26, Aurelien Jarno wrote:
> This patch series is technically a new version of the "add a video
> card only when requested" series I sent yesterday. It uses a different
> approach though.
>
> It creates a new pci_vga_init() function that takes care of initializing
> the req
On 08.09.2012, at 13:26, Aurelien Jarno wrote:
> This remove the fallback to std-vga in case, as availability of the
> requested vga device is now tested in vl.c, and returns an error message
> to the user.
>
> Cc: Richard Henderson
> Signed-off-by: Aurelien Jarno
> ---
> hw/alpha_dp264.c |
On Fri, Sep 07, 2012 at 05:11:33PM +0200, Paolo Bonzini wrote:
> This is a bug that has to be fixed anyway. There are provisions in
> aio.c, but they are broken apparently. Can you try this:
>
> diff --git a/aio.c b/aio.c
> index 0a9eb10..99b8b72 100644
> --- a/aio.c
> +++ b/aio.c
> @@ -119,7 +1
The operations for INDEX_op_deposit_i32 and INDEX_op_deposit_i64
are now supported and enabled by default.
Signed-off-by: Stefan Weil
---
tcg/tci/tcg-target.c | 24
tcg/tci/tcg-target.h |4 ++--
tci.c| 22 ++
3 files changed, 4
On Sat, Sep 08, 2012 at 11:50:04AM +, Blue Swirl wrote:
> Add an explicit CPUState parameter instead of relying on AREG0
> and switch to AREG0 free mode.
>
> Signed-off-by: Blue Swirl
> ---
> configure|2 +-
> target-sh4/Makefile.objs |2 -
> target-sh4/helper.h
The load/store slow path has been broken in e141ab52d:
- We need to move 4 registers for store functions and 3 registers for
load functions and not the reverse.
- According to the s390x calling convention the arguments of a function
should be zero extended. This means that the register shift sh
As a bonus it allows new vga card types (including none).
Cc: Blue Swirl
Signed-off-by: Aurelien Jarno
---
hw/sun4u.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/sun4u.c b/hw/sun4u.c
index cca090f..137a7c6 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -39,7 +39,6 @
Am 08.09.2012 13:26, schrieb Aurelien Jarno:
> As a bonus it allows new vga card types (including none).
>
> Cc: Andreas Färber
> Signed-off-by: Aurelien Jarno
Acked-by: Andreas Färber
/-F
From: Aurelien Jarno
Add an explicit CPUCRISState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
Signed-off-by: Aurelien Jarno
---
target-cris/helper.h| 37 +++-
target-cris/op_helper.c | 80 +++
target-
Signed-off-by: Aurelien Jarno
---
hw/mips_malta.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index c39dee5..632b466 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -33,7 +33,6 @@
#include "mips.h"
#include "mips_cpudev
Now that all machines call pci_vga_init(), some unused code can be
removed.
Cc: Anthony Liguori
Signed-off-by: Aurelien Jarno
---
hw/cirrus_vga.c |6 --
hw/vga-pci.c|6 --
hw/vga-pci.h| 12
hw/vmware_vga.c |1 -
hw/vmware_vga.h | 15 ---
From: Aurelien Jarno
Add an explicit CPUCRISState parameter instead of relying on AREG0, and
use cpu_ld* in translation and interrupt handling. Remove AREG0 swapping
in tlb_fill(). Switch to AREG0 free mode
Signed-off-by: Blue Swirl
Signed-off-by: Aurelien Jarno
---
configure
Am 08.09.2012 13:26, schrieb Aurelien Jarno:
> Check for qxl availability in vl.c. This will allow to remove #ifdef
> CONFIG_SPICE .. #endif later in this series
>
> Cc: Anthony Liguori
> Cc: Gerd Hoffmann
> Signed-off-by: Aurelien Jarno
> ---
> vl.c | 12 +++-
> 1 file changed, 11 i
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Tested-by: Guan Xuetao
Signed-off-by: Blue Swirl
---
configure |2 +-
target-unicore32/Makefile.objs |2 -
target-unicore32/helper.h | 26
target-un
Pass around CPUState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl
---
target-m68k/translate.c | 270 ---
1 files changed, 140 insertions(+), 130 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 10
Keep the case to prevent some vga card to be selected.
Cc: Alexander Graf
Cc: David Gibson
Signed-off-by: Aurelien Jarno
---
hw/spapr.c |7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index 80735d6..8b0c390 100644
--- a/hw/spapr.c
+++ b/hw/
On Sat, Sep 8, 2012 at 11:26 AM, Aurelien Jarno wrote:
> The CONFIG_SPICE is now tested in vl.c and thus not needed anymore. The
> various tests are still needed for the ISA cases.
>
> Cc: Anthony Liguori
> Signed-off-by: Aurelien Jarno
> ---
> hw/pc.c | 41 +++
Am 08.09.2012 13:26, schrieb Aurelien Jarno:
> This better explains what is this function about. Adjust all callers.
>
> Cc: Richard Henderson
> Cc: Alexander Graf
> Cc: Andreas Färber
> Cc: David Gibson
> Cc: Blue Swirl
> Cc: Anthony Liguori
> Signed-off-by: Aurelien Jarno
Looks fine,
Ac
On Sat, Sep 8, 2012 at 11:26 AM, Aurelien Jarno wrote:
> This better explains what is this function about. Adjust all callers.
>
> Cc: Richard Henderson
> Cc: Alexander Graf
> Cc: Andreas Färber
> Cc: David Gibson
> Cc: Blue Swirl
Acked-by: Blue Swirl
> Cc: Anthony Liguori
> Signed-off-by
On Sat, Sep 8, 2012 at 11:26 AM, Aurelien Jarno wrote:
> As a bonus it allows new vga card types (including none).
>
> Cc: Blue Swirl
Acked-by: Blue Swirl
> Signed-off-by: Aurelien Jarno
> ---
> hw/sun4u.c |3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/hw/sun4u
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl
---
configure |2 +-
target-m68k/Makefile.objs |2 -
target-m68k/helpers.h |2 +-
target-m68k/op_helper.c | 68 -
On Sat, Sep 8, 2012 at 12:13 PM, Alexander Graf wrote:
>
>
> On 08.09.2012, at 12:16, Blue Swirl wrote:
>
>> On Sat, Sep 8, 2012 at 9:28 AM, Alexander Graf wrote:
>>>
>>>
>>> On 08.09.2012, at 10:06, Blue Swirl wrote:
>>>
On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity wrote:
> On 09/05/20
Convert remaining helpers to AREG0 free mode: add an explicit
CPUState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
Reviewed-by: Peter Maydell
---
target-arm/helper.h| 52 +-
target-arm/op_helper.c | 64 +++---
target-arm/translate.c |
As a bonus it allows new vga card types (including none).
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
hw/ppc_newworld.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 84af948..b8d3c9c 100644
--- a/hw/ppc_newworld.c
+
Convert code load functions and switch to AREG0 free mode.
Signed-off-by: Blue Swirl
Reviewed-by: Peter Maydell
---
configure|2 +-
target-arm/Makefile.objs |2 --
target-arm/cpu.h | 10 ++
target-arm/helper.c |9 +
target-arm/op_helper
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl
---
configure|2 +-
target-sh4/Makefile.objs |2 -
target-sh4/helper.h | 84 +++---
target-sh4/op_helper.c | 182 +
This function create a PCI VGA device according to the value of
vga_interface_type. It returns a PCIDevice (and not a DeviceState).
Cc: Anthony Liguori
Signed-off-by: Aurelien Jarno
---
hw/pci.c | 18 ++
hw/pci.h |3 +++
2 files changed, 21 insertions(+)
diff --git a/hw/p
On 08.09.2012, at 12:16, Blue Swirl wrote:
> On Sat, Sep 8, 2012 at 9:28 AM, Alexander Graf wrote:
>>
>>
>> On 08.09.2012, at 10:06, Blue Swirl wrote:
>>
>>> On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity wrote:
On 09/05/2012 10:04 PM, Blue Swirl wrote:
>
> Reinventing a disasse
Add an explicit CPUState parameter instead of relying on AREG0.
For easier review, convert only op helpers which don't return any value.
Signed-off-by: Blue Swirl
Reviewed-by: Peter Maydell
---
target-arm/helper.h|8
target-arm/op_helper.c | 20 ++--
target-a
Check for qxl availability in vl.c. This will allow to remove #ifdef
CONFIG_SPICE .. #endif later in this series
Cc: Anthony Liguori
Cc: Gerd Hoffmann
Signed-off-by: Aurelien Jarno
---
vl.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/vl.c b/vl.c
index 7c5
On Sat, Sep 08, 2012 at 08:01:30PM +0800, Jia Liu wrote:
> Hi Aurelien,
>
> On Thu, Sep 6, 2012 at 5:11 PM, Aurelien Jarno wrote:
> > On Tue, Aug 28, 2012 at 02:36:23PM +0800, Jia Liu wrote:
> >> Add MIPS[32|64] ASE DSP[R1|R2] generic cpu model for test.
> >>
> >> Signed-off-by: Jia Liu
> >> ---
Hi Aurelien,
On Thu, Sep 6, 2012 at 5:11 PM, Aurelien Jarno wrote:
> On Tue, Aug 28, 2012 at 02:36:23PM +0800, Jia Liu wrote:
>> Add MIPS[32|64] ASE DSP[R1|R2] generic cpu model for test.
>>
>> Signed-off-by: Jia Liu
>> ---
>> target-mips/translate_init.c | 55
>>
As a bonus it allows new vga card types (including none).
Cc: Andreas Färber
Signed-off-by: Aurelien Jarno
---
hw/ppc_prep.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 1fa7609..1544430 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep
Pass around CPUState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl
---
target-s390x/translate.c | 356 --
1 files changed, 183 insertions(+), 173 deletions(-)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index
This better explains what is this function about. Adjust all callers.
Cc: Richard Henderson
Cc: Alexander Graf
Cc: Andreas Färber
Cc: David Gibson
Cc: Blue Swirl
Cc: Anthony Liguori
Signed-off-by: Aurelien Jarno
---
hw/alpha_pci.c|2 +-
hw/mips_malta.c |2 +-
hw/pc.c
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl
---
configure |2 +-
target-microblaze/Makefile.objs |2 -
target-microblaze/helper.h | 48
target-microblaze/op_helper.c
As a bonus it allows new vga card types (including none).
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
hw/ppc_oldworld.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 8267eb4..2c4a478 100644
--- a/hw/ppc_oldworld.c
+
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl
---
configure |2 +-
target-lm32/Makefile.objs |2 --
target-lm32/helper.h | 20 ++--
target-lm32/op_helper.c | 29 ++
Convert remaining targets to AREG0 free mode.
Avoid also cpu_single_env in translation code.
If there are no objections and the s390x queue gets pulled in,
I'll apply the series next weekend.
v2:
drop queued s390x patches
avoid also cpu_single_env
Aurelien Jarno (2):
target-cris: Avoid AR
This patch series is technically a new version of the "add a video
card only when requested" series I sent yesterday. It uses a different
approach though.
It creates a new pci_vga_init() function that takes care of initializing
the requested PCI video card. This way there is no need to duplicate
c
The CONFIG_SPICE is now tested in vl.c and thus not needed anymore. The
various tests are still needed for the ISA cases.
Cc: Anthony Liguori
Signed-off-by: Aurelien Jarno
---
hw/pc.c | 41 +++--
1 file changed, 15 insertions(+), 26 deletions(-)
diff --git
This remove the fallback to std-vga in case, as availability of the
requested vga device is now tested in vl.c, and returns an error message
to the user.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
hw/alpha_dp264.c |2 +-
hw/alpha_pci.c | 24
hw/alph
On 2012-09-07 18:09, Erik Lotspeich wrote:
> Hi,
>
> I apologize if this isn't the right venue for this message, but this
> mailing list seems a bit more active than qemu-discuss.
>
> Background:
> I am running OpenSUSE 12.1. I fixed audio issues in VM guests by setting
> the following in qemu.co
Il 08/09/2012 01:22, ronnie sahlberg ha scritto:
> Ping?
Both are already in scsi-next, thanks!
Paolo
> On Thu, Aug 30, 2012 at 4:56 PM, Ronnie Sahlberg
> wrote:
>> We no longer need to explicitely call qemu_notify_event() any more since
>> this is now done automatically any time the filehandl
Il 08/09/2012 09:15, Blue Swirl ha scritto:
>> Preferably some which don't
>> > break on 'qemu -nodefault -device isa-serial,chardev=foo'.
> Add a qdev property? The base address check can't be correct, the
> serial device could be the only one in the board and wired to wakeup
> but still use a dif
Thanks, applied.
On Sat, Sep 8, 2012 at 9:52 AM, Jan Kiszka wrote:
> The old arithmetic assumed 32 physical address bits which is no longer
> true for ARM since 3cc0cd61f4.
>
> Signed-off-by: Jan Kiszka
> ---
>
> Changes in v2a:
> - mark large constant ULL
>
> hw/musicpal.c |4 ++--
> 1 fil
On Sat, Sep 8, 2012 at 9:28 AM, Alexander Graf wrote:
>
>
> On 08.09.2012, at 10:06, Blue Swirl wrote:
>
>> On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity wrote:
>>> On 09/05/2012 10:04 PM, Blue Swirl wrote:
Reinventing a disassembler for ever growing x86 assembly is
no fun.
>>>
>>> W
The old arithmetic assumed 32 physical address bits which is no longer
true for ARM since 3cc0cd61f4.
Signed-off-by: Jan Kiszka
---
Changes in v2a:
- mark large constant ULL
hw/musicpal.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/musicpal.c b/hw/musicpal.c
On 2012-09-08 11:50, Peter Maydell wrote:
> On 8 September 2012 10:48, Jan Kiszka wrote:
>> The old arithmetic assumed 32 physical address bits which is no longer
>> true for ARM since 3cc0cd61f4.
>>
>> Signed-off-by: Jan Kiszka
>> ---
>>
>> Changes in v2:
>> - mark large constant ULL
>>
>> #ifd
On 8 September 2012 10:48, Jan Kiszka wrote:
> The old arithmetic assumed 32 physical address bits which is no longer
> true for ARM since 3cc0cd61f4.
>
> Signed-off-by: Jan Kiszka
> ---
>
> Changes in v2:
> - mark large constant ULL
>
> #ifdef TARGET_WORDS_BIGENDIAN
> -pflash_cfi02_regi
The old arithmetic assumed 32 physical address bits which is no longer
true for ARM since 3cc0cd61f4.
Signed-off-by: Jan Kiszka
---
Changes in v2:
- mark large constant ULL
hw/musicpal.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/musicpal.c b/hw/musicpal.c
i
On Sat, Sep 08, 2012 at 09:29:59AM +, Blue Swirl wrote:
> On Sat, Sep 8, 2012 at 9:12 AM, Aurelien Jarno wrote:
> > On Sat, Sep 08, 2012 at 09:06:52AM +, Blue Swirl wrote:
> >> On Sat, Sep 8, 2012 at 9:01 AM, Aurelien Jarno
> >> wrote:
> >> > On Sat, Sep 08, 2012 at 08:18:50AM +, Blu
On Sat, Sep 8, 2012 at 9:12 AM, Aurelien Jarno wrote:
> On Sat, Sep 08, 2012 at 09:06:52AM +, Blue Swirl wrote:
>> On Sat, Sep 8, 2012 at 9:01 AM, Aurelien Jarno wrote:
>> > On Sat, Sep 08, 2012 at 08:18:50AM +, Blue Swirl wrote:
>> >> On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno
>> >
On 08.09.2012, at 10:06, Blue Swirl wrote:
> On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity wrote:
>> On 09/05/2012 10:04 PM, Blue Swirl wrote:
>>>
>>> Reinventing a disassembler for ever growing x86 assembly is
>>> no fun.
>>
>> We can try linking to a disassembler library. I use udis86 to
>>
On Sat, Sep 08, 2012 at 09:06:52AM +, Blue Swirl wrote:
> On Sat, Sep 8, 2012 at 9:01 AM, Aurelien Jarno wrote:
> > On Sat, Sep 08, 2012 at 08:18:50AM +, Blue Swirl wrote:
> >> On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno
> >> wrote:
> >> > This patch series improves the TCG optimizer,
Thanks, applied.
On Tue, May 22, 2012 at 8:14 AM, Fabien Chouteau wrote:
>
> Signed-off-by: Fabien Chouteau
> ---
> MAINTAINERS |6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b45f075..3d773d3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @
Thanks, applied.
On Fri, Sep 7, 2012 at 3:13 PM, Aurelien Jarno wrote:
> fcmp{s,d,q} instructions are supposed to ignore quiet NaN (contrary to
> the fcmpe{s,d,q} instructions), but the current code is wrongly setting
> the NV exception in that case. Moreover the current code is duplicated:
> fir
Thanks, applied.
On Thu, Sep 6, 2012 at 12:36 AM, Max Filippov wrote:
> Put the following errno value mappings under #ifdef:
>
> xtensa-semi.c: In function 'errno_h2g':
> xtensa-semi.c:113: error: 'ENOTBLK' undeclared (first use in this function)
> xtensa-semi.c:113: error: (Each undeclared ident
On Sat, Sep 8, 2012 at 9:01 AM, Aurelien Jarno wrote:
> On Sat, Sep 08, 2012 at 08:18:50AM +, Blue Swirl wrote:
>> On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno wrote:
>> > This patch series improves the TCG optimizer, based on patterns found
>> > while executing various guest. The brcond ad
On Sat, Sep 08, 2012 at 08:35:18AM +, Blue Swirl wrote:
> On Fri, Sep 7, 2012 at 2:18 PM, Aurelien Jarno wrote:
> > On Sun, Sep 02, 2012 at 05:33:47PM +, Blue Swirl wrote:
> >> Add an explicit CPUState parameter instead of relying on AREG0
> >> and switch to AREG0 free mode.
> >>
> >> Sign
On Sat, Sep 08, 2012 at 08:18:50AM +, Blue Swirl wrote:
> On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno wrote:
> > This patch series improves the TCG optimizer, based on patterns found
> > while executing various guest. The brcond ad setcond constant folding
> > are useful especially useful w
On 2012-09-08 10:44, Blue Swirl wrote:
> On Fri, Sep 7, 2012 at 3:25 PM, Peter Maydell
> wrote:
>> On 7 September 2012 15:53, Jan Kiszka wrote:
>>> On 2012-09-07 16:41, Peter Maydell wrote:
On 7 September 2012 00:03, Jan Kiszka wrote:
> +pflash_cfi02_register(0x1-MP_FLA
On Fri, Sep 7, 2012 at 3:25 PM, Peter Maydell wrote:
> On 7 September 2012 15:53, Jan Kiszka wrote:
>> On 2012-09-07 16:41, Peter Maydell wrote:
>>> On 7 September 2012 00:03, Jan Kiszka wrote:
+pflash_cfi02_register(0x1-MP_FLASH_SIZE_MAX, NULL,
>>>
>>> I don't think this wi
On Fri, Sep 7, 2012 at 2:18 PM, Aurelien Jarno wrote:
> On Sun, Sep 02, 2012 at 05:33:47PM +, Blue Swirl wrote:
>> Add an explicit CPUState parameter instead of relying on AREG0
>> and switch to AREG0 free mode.
>>
>> Signed-off-by: Blue Swirl
>> ---
>> configure |2 +-
On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno wrote:
> This patch series improves the TCG optimizer, based on patterns found
> while executing various guest. The brcond ad setcond constant folding
> are useful especially useful when they are used to avoid some argument
> values (e.g. division by
On Thu, Sep 6, 2012 at 7:00 PM, Peter Maydell wrote:
> On 4 September 2012 21:48, Peter Maydell wrote:
>> On 4 September 2012 21:37, Blue Swirl wrote:
>>> Add an explicit CPUState parameter instead of relying on AREG0.
>>>
>>> For easier review, convert only op helpers which don't return any val
On Thu, Sep 6, 2012 at 6:33 PM, Alexander Graf wrote:
>
> On 02.09.2012, at 13:33, Blue Swirl wrote:
>
>> Before splitting op_helper.c and helper.c in the next patches,
>> fix style issues. No functional changes.
>>
>> Replace also GCC specific __FUNCTION__ with
>> standard __func__.
>>
>> Don't i
On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity wrote:
> On 09/05/2012 10:04 PM, Blue Swirl wrote:
>>
>> Reinventing a disassembler for ever growing x86 assembly is
>> no fun.
>
> We can try linking to a disassembler library. I use udis86 to
> disassemble instructions in kvm tracepoints
> (http://udis
On Thu, Sep 6, 2012 at 4:06 PM, Andreas Färber wrote:
> Am 06.09.2012 10:44, schrieb Jan Kiszka:
>> On 2012-08-30 20:30, Jan Kiszka wrote:
>>> This adds PCI device assignment for i386 targets using the classic KVM
>>> interfaces. This version is 100% identical to what is being maintained
>>> in qe
On Thu, Sep 6, 2012 at 3:42 AM, Alexander Graf wrote:
>
> On 05.09.2012, at 15:38, Blue Swirl wrote:
>
>> On Wed, Sep 5, 2012 at 7:22 PM, Anthony Liguori
>> wrote:
>>> Blue Swirl writes:
>>>
On Wed, Sep 5, 2012 at 3:41 PM, Anthony Liguori
wrote:
> Avi Kivity writes:
>
>
On Thu, Sep 6, 2012 at 3:38 PM, Aurelien Jarno wrote:
> On Sun, Sep 02, 2012 at 05:33:46PM +, Blue Swirl wrote:
>> Add an explicit CPUState parameter instead of relying on AREG0
>> and switch to AREG0 free mode.
>>
>> Signed-off-by: Blue Swirl
>> ---
>> configure |2
On Thu, Sep 6, 2012 at 3:32 PM, Avi Kivity wrote:
> On 09/02/2012 01:51 PM, Blue Swirl wrote:
>> I've used the following snippet to check what happens with the last 100
>> commits:
>> for i in '' 1 2 3 4 5 6 7 8 9; do for j in 0 1 2 3 4 5 6 7 8 9; do
>> echo $i$j; git show HEAD~$i$j >/tmp/a; clea
On Thu, Sep 6, 2012 at 10:47 AM, Gerd Hoffmann wrote:
> On 09/06/12 09:48, Peter Maydell wrote:
>> On 6 September 2012 08:42, Gerd Hoffmann wrote:
>>> @@ -789,6 +790,13 @@ static int serial_isa_initfn(ISADevice *dev)
>>> isa->isairq = isa_serial_irq[isa->index];
>>> index++;
>>>
>>>
On Thu, Sep 6, 2012 at 10:32 AM, Andreas Färber wrote:
> Am 05.09.2012 21:46, schrieb Blue Swirl:
>> Thanks, applied all.
>
> Question: Are additions to checkpatch.pl supposed to be in QEMU Coding
> Style as done here? Do you plan to convert it consistently then?
> checkpatch.pl uses tabs consiste
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