Re: [Qemu-devel] [PATCH V12 3/4] Use QemuOpts support in block layer
On Thu, Mar 21, 2013 at 11:31 PM, Markus Armbruster arm...@redhat.com wrote:
Dong Xu Wang wdon...@linux.vnet.ibm.com writes:
This patch will use QemuOpts related functions in block layer, add
a member bdrv_create_opts to BlockDriver struct, it will return
a QemuOptsList pointer, which includes the image format's create
options.
And create options's primary consumer is block creating related
functions, so modify them together.
Signed-off-by: Dong Xu Wang wdon...@linux.vnet.ibm.com
---
v11-v12:
1) create functions, such as qemu_opt_get_del and qemu_opt_replace_set.
These functions works like origin code.
2) use QEMU_OPT_SIZE, not QEMU_OPT_NUMBER.
3) in bdrv_create, if opts is NULL, will create an empty one, so can
discard if(opts) code safely.
v10-v11:
1) qed.h move QED_DEFAULT_CLUSTER_SIZE from enum to macro, or
qemu_opts_print produce un-expanded cluster_size.
2) In qcow2.c and qcow.c, bdrv_create_file(filename, NULL), NULL -
opts,
or while using protocol, there will be an error.
v8-v9:
1) add qemu_ prefix to gluster_create_opts.
2) fix bug: bdrv_gluster_unix and bdrv_gluster_rdma should also be
converted.
v7-v8:
1) rebase to upstream source tree.
2) add gluster.c, raw-win32.c, and rbd.c.
v6-v7:
1) use osdep.h:stringify(), not redefining new macro.
2) preserve TODO comment.
3) fix typo. BLOCK_OPT_ENCRYPT-BLOCK_OPT_STATIC.
4) initialize disk_type even when opts is NULL.
v5-v6:
1) judge if opts == NULL in block layer create functions.
2) use bdrv_create_file(filename, NULL) in qcow_create and cow_create
funtion.
3) made more readable while using qemu_opt_get_number.
block.c | 91
block/cow.c | 46 ++--
block/gluster.c | 37 +-
block/iscsi.c | 8 +--
block/qcow.c | 61
block/qcow2.c | 173
+++---
block/qed.c | 86 +++
block/qed.h | 2 +-
block/raw-posix.c | 59 +++-
block/raw-win32.c | 31 +
block/raw.c | 30
block/rbd.c | 62 -
block/sheepdog.c | 75 ++--
block/vdi.c | 70 +--
block/vmdk.c | 90
block/vpc.c | 57 +++
block/vvfat.c | 11 +--
include/block/block.h | 4 +-
include/block/block_int.h | 6 +-
include/qemu/option.h | 13 +++-
qemu-img.c| 61
util/qemu-option.c| 93 +++--
22 files changed, 613 insertions(+), 553 deletions(-)
*Ouch*
Any chance to split this patch up some? Its size makes it really hard
to review...
I will split this patch into some small patches in next version.
diff --git a/block.c b/block.c
index 4582961..975c3d8 100644
--- a/block.c
+++ b/block.c
@@ -357,7 +357,7 @@ BlockDriver *bdrv_find_whitelisted_format(const char
*format_name)
typedef struct CreateCo {
BlockDriver *drv;
char *filename;
-QEMUOptionParameter *options;
+QemuOpts *opts;
int ret;
} CreateCo;
@@ -366,11 +366,11 @@ static void coroutine_fn bdrv_create_co_entry(void
*opaque)
CreateCo *cco = opaque;
assert(cco-drv);
-cco-ret = cco-drv-bdrv_create(cco-filename, cco-options);
+cco-ret = cco-drv-bdrv_create(cco-filename, cco-opts);
}
int bdrv_create(BlockDriver *drv, const char* filename,
-QEMUOptionParameter *options)
+QemuOpts *opts)
Since you touch this anyway, consider unbreaking the line:
int bdrv_create(BlockDriver *drv, const char* filename, QemuOpts *opts)
Okay.
{
int ret;
@@ -378,7 +378,7 @@ int bdrv_create(BlockDriver *drv, const char* filename,
CreateCo cco = {
.drv = drv,
.filename = g_strdup(filename),
-.options = options,
+.opts = opts ?: qemu_opts_create_nofail(drv-bdrv_create_opts),
.ret = NOT_DONE,
};
As discussed during review of v11, this avoids passing null opts to the
bdrv_create() method. Good.
@@ -405,7 +405,7 @@ out:
out:
g_free(cco.filename);
return ret;
}
I suspect you need
if (!opts) {
qemu_opts_del(cco-opts);
}
to avoid leaking the empty cco-opts you create in the previous hunk.
Okay.
-int bdrv_create_file(const char* filename, QEMUOptionParameter *options)
+int bdrv_create_file(const char *filename, QemuOpts *opts)
{
BlockDriver *drv;
@@ -414,7 +414,7 @@ int bdrv_create_file(const char* filename,
QEMUOptionParameter *options)
return -ENOENT;
}
-return bdrv_create(drv, filename, options);
+return bdrv_create(drv, filename, opts);
}
/*
@@ -814,7 +814,7 @@ int bdrv_open(BlockDriverState *bs, const char
*filename, int flags,
Re: [Qemu-devel] [RFC qemu PATCH] only writing out the last byte of MAC makes it have effect
On Mon, Mar 25, 2013 at 10:23:57AM +0800, Amos Kong wrote:
On Fri, Mar 22, 2013 at 10:45:09AM +1030, Rusty Russell wrote:
Michael S. Tsirkin m...@redhat.com writes:
On Thu, Mar 21, 2013 at 02:44:50PM +0800, Amos Kong wrote:
The lengcy guests don't have mac programming command, we don't know when
it's safe to use MAC. This patch changed qemu to makes MAC change effect
when the last byte of MAC is written to config space.
MAC address takes first 6 bytes of config space of virtio-net, the addr
is 5 when the last byte is written in virtio_config_writeb().
MAC change will effect when n-mac is updated in virtio_net_set_config().
Signed-off-by: Amos Kong ak...@redhat.com
Let's see what Rusty says about the spec change.
Implementation notes like this belong as a footnote, eg:
For older systems, it is recommended and typical that the device
write byte 5 of the mac address last, so devices can use that as
a trigger to commit the mac address change.
Now, is this a real, or theoretical issue? Have we seen this problem in
practice, or should we continue to ignore it?
Hi Rusty, Michael
I didn't touch any problem. MST, and you?
In Linux guest, we should disable the interface before changing mac address.
ifconfig eth0 down
ifconfig eth0 hw ether 10:12:13:14:15:16
ifconfig eth0 up
In Windows 7 guest, after changing mac address in register table,
re-enabling interface to make it effect.
reg add HKLM
SYSTEM\CurrentControlSet\Control\Class\{4D36E972-E325-11CE-BFC1-08002BE10318}\0001]
/v NetworkAddress /d 0123456789AB
netsh interface set interface Local Area Connection DISABLED
netsh interface set interface Local Area Connection ENABLED
So when we change the mac address, guest os always disable interface
to receive all packages. It seems the theoretical issue doesn't exist?
Cheers,
Rusty.
--
Amos.
Nope. Looks like no spec change is necessary. We already say it's
not atomic and it looks like guests expect exactly that
and disable link to prevent strange issues.
--
MST
[Qemu-devel] [Bug 1159605] [NEW] run command hangs using -M none
Public bug reported: when i run following command, it just hangs there qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -machine none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile but blow command just fine qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none, -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile I installed qemu-git version on gentoo with kernel 3.8.4 is this a bug??? ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1159605 Title: run command hangs using -M none Status in QEMU: New Bug description: when i run following command, it just hangs there qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -machine none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile but blow command just fine qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none, -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile I installed qemu-git version on gentoo with kernel 3.8.4 is this a bug??? To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1159605/+subscriptions
Re: [Qemu-devel] [PATCH v3] gtk: Release modifier when graphic console loses keyboard focus
On Sun, Mar 24, 2013 at 07:10:02PM +0100, Jan Kiszka wrote: From: Jan Kiszka jan.kis...@siemens.com This solves, e.g., sticky ALT when selecting a GTK menu, switching to a different window or selecting a different virtual console. Signed-off-by: Jan Kiszka jan.kis...@siemens.com --- Changes in v3: - rebased ui/gtk.c | 53 +++-- 1 files changed, 51 insertions(+), 2 deletions(-) Doesn't apply with git-am(1) to qemu.git/master (fe6344a05fba26e16863fefcb823242e579b0991). patch(1) can merge it though. Tested-by: Stefan Hajnoczi stefa...@redhat.com
Re: [Qemu-devel] Abort in monitor_puts.
On 03/22/13 22:39, Luiz Capitulino wrote: On Fri, 22 Mar 2013 16:50:39 -0400 Luiz Capitulino lcapitul...@redhat.com wrote: On Fri, 22 Mar 2013 10:17:58 +0100 KONRAD Frédéric fred.kon...@greensocs.com wrote: Hi, Seems there is an issue with the current git (found by toddf on IRC). To reproduce: ./qemu-system-x86_64 --monitor stdio --nographic and put ? it should abort. Here is the backtrace: #0 0x7f77cd347935 in raise () from /lib64/libc.so.6 #1 0x7f77cd3490e8 in abort () from /lib64/libc.so.6 #2 0x7f77cd3406a2 in __assert_fail_base () from /lib64/libc.so.6 #3 0x7f77cd340752 in __assert_fail () from /lib64/libc.so.6 #4 0x7f77d1c1f226 in monitor_puts (mon=optimized out, str=optimized out) at Yes, it's easy to reproduce. Bisect says: f628926bb423fa8a7e0b114511400ea9df38b76a is the first bad commit commit f628926bb423fa8a7e0b114511400ea9df38b76a Author: Gerd Hoffmann kra...@redhat.com Date: Tue Mar 19 10:57:56 2013 +0100 fix monitor chardev flow control broke monitor, fix it by adding watch support. Signed-off-by: Anthony Liguori aligu...@us.ibm.com My impression is that monitor_puts() in being called in parallel. Not all. What's happening is that qemu_chr_fe_write() is returning 0, mon-outbuf_index is not reset and is full, this causes the assert in monitor_puts() to trig. The previous version of monitor_flush() ignores errors, and everything works, so doing the same thing here fixes the problem :) No, ignoring errors breaks qmp because the output isn't valid json any more when you cut off something ... For some reason I'm unable to see what the error code is. Gerd, do you think the patch below is reasonable? If it's not, how should we handle errors here? No, it's not. Ignoring the error for errno = EAGAIN breaks flow control. Ignoring the error for errno != EAGAIN (and maybe logging a debug message) would be ok, but I suspect it's actually EAGAIN you get here. Just go for a larger buffer? cheers, Gerd
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 2013-03-12 11:32, Gerd Hoffmann wrote: Use QemuConsole instead. Updates interfaces in console.[ch] and adapts gfx hardware emulation code. Breaks vmware-vga, the X server no longer starts up. I do not spot any obvious typo etc. in the conversion, so I suspect, some values returned by the surface API differ from those that the DisplayState used to provide. Jan signature.asc Description: OpenPGP digital signature
[Qemu-devel] qxl: qxl's event named QXL_INTERRUPT_DISPLAY
Hi, I'm learning about qxl device in KVM VM. I got a problem and asks
for help. Thanks.
The qemu's command is:
qemu-system-x86_64 -spice port=5900,disable-ticketing -vga qxl
--enable-kvm ...
The code in function 'interface_get_command' is followed:
SPICE_RING_POP(ring, notify);
if (notify) {
qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
}
What is the meaning about 'QXL_INTERRUPT_DISPLAY' ?
Does it means sending a 'QXL_INTERRUPT_DISPLAY' irq to vm?
If so, what's the irq's handler?
Thanks.
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 03/25/13 08:50, Jan Kiszka wrote: On 2013-03-12 11:32, Gerd Hoffmann wrote: Use QemuConsole instead. Updates interfaces in console.[ch] and adapts gfx hardware emulation code. Breaks vmware-vga, the X server no longer starts up. I do not spot any obvious typo etc. in the conversion, so I suspect, some values returned by the surface API differ from those that the DisplayState used to provide. Jan Known issue, fix is queued but not yet merged: http://patchwork.ozlabs.org/patch/229214/ cheers, Gerd
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 2013-03-25 08:55, Gerd Hoffmann wrote: On 03/25/13 08:50, Jan Kiszka wrote: On 2013-03-12 11:32, Gerd Hoffmann wrote: Use QemuConsole instead. Updates interfaces in console.[ch] and adapts gfx hardware emulation code. Breaks vmware-vga, the X server no longer starts up. I do not spot any obvious typo etc. in the conversion, so I suspect, some values returned by the surface API differ from those that the DisplayState used to provide. Jan Known issue, fix is queued but not yet merged: http://patchwork.ozlabs.org/patch/229214/ Nope, I seem to stress something else: No change here after applying that patch. Jan signature.asc Description: OpenPGP digital signature
[Qemu-devel] [Bug 1159605] Re: run command hangs using -M none
** Tags added: paramter passing -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1159605 Title: run command hangs using -M none Status in QEMU: New Bug description: when i run following command, it just hangs there qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -machine none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile but blow command just fine qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none, -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile I installed qemu-git version on gentoo with kernel 3.8.4 is this a bug??? To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1159605/+subscriptions
Re: [Qemu-devel] [RFC 10/12] Add qemu_put_buffer_no_copy
On 03/23/2013 06:27 PM, Michael R. Hines wrote:
Can you add a flag or something to indicate that the iov pointer belongs to
RAM and not to device state?
That way, I could re-use this code for RDMA - if I see this flag, I will know
to send to RDMA.
This function is called only for ram pages so no need for flag.
Orit
- Michael
On 03/21/2013 05:09 AM, Orit Wasserman wrote:
This allow us to add a buffer to the iovec to send without copying it
into the static buffer.
Signed-off-by: Orit Wasserman owass...@redhat.com
---
include/migration/qemu-file.h | 5 +
savevm.c | 42
--
2 files changed, 29 insertions(+), 18 deletions(-)
diff --git a/include/migration/qemu-file.h b/include/migration/qemu-file.h
index 8d3da9b..5168be2 100644
--- a/include/migration/qemu-file.h
+++ b/include/migration/qemu-file.h
@@ -75,6 +75,11 @@ int qemu_fclose(QEMUFile *f);
int64_t qemu_ftell(QEMUFile *f);
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
void qemu_put_byte(QEMUFile *f, int v);
+/*
+ * put_buffer without copying the buffer.
+ * The buffer should be available till it is sent.
+ */
+void qemu_put_buffer_no_copy(QEMUFile *f, const uint8_t *buf, int size);
static inline void qemu_put_ubyte(QEMUFile *f, unsigned int v)
{
diff --git a/savevm.c b/savevm.c
index 40d96f4..32a506e 100644
--- a/savevm.c
+++ b/savevm.c
@@ -629,6 +629,22 @@ void qemu_put_buffer(QEMUFile *f, const uint8_t *buf,
int size)
{
int l;
+while (size 0) {
+l = IO_BUF_SIZE - f-buf_index;
+if (l size) {
+l = size;
+}
+memcpy(f-buf + f-buf_index, buf, l);
+f-buf_index += l;
+f-is_write = 1;
+qemu_put_buffer_no_copy(f, f-buf + (f-buf_index - l), l);
+buf += l;
+size -= l;
+}
+}
+
+void qemu_put_buffer_no_copy(QEMUFile *f, const uint8_t *buf, int size)
+{
if (f-last_error) {
return;
}
@@ -639,24 +655,14 @@ void qemu_put_buffer(QEMUFile *f, const uint8_t *buf,
int size)
abort();
}
-while (size 0) {
-l = IO_BUF_SIZE - f-buf_index;
-if (l size)
-l = size;
-memcpy(f-buf + f-buf_index, buf, l);
-f-iov[f-iovcnt].iov_base = f-buf + f-buf_index;
-f-iov[f-iovcnt++].iov_len = l;
-f-is_write = 1;
-f-buf_index += l;
-f-bytes_xfer += l;
-buf += l;
-size -= l;
-if (f-buf_index = IO_BUF_SIZE || f-iovcnt = MAX_IOV_SIZE) {
-qemu_fflush(f);
-if (qemu_file_get_error(f)) {
-break;
-}
-}
+f-iov[f-iovcnt].iov_base = (uint8_t *)buf;
+f-iov[f-iovcnt++].iov_len = size;
+
+f-is_write = 1;
+f-bytes_xfer += size;
+
+if (f-buf_index = IO_BUF_SIZE || f-iovcnt = MAX_IOV_SIZE) {
+qemu_fflush(f);
}
}
[Qemu-devel] [PULL 0/2] ipxe: disable two second timeout
Hi, See $subject, minor tweak for the ipxe roms. please pull, Gerd The following changes since commit fe6344a05fba26e16863fefcb823242e579b0991: Remove device_tree.o from hw/moxie/Makefile.objs. (2013-03-24 11:30:04 +0100) are available in the git repository at: git://git.kraxel.org/qemu ipxe.3 for you to fetch changes up to 0099cd43ecf07710a608db5ca0945758514a14c2: ipxe: update binaries (2013-03-25 09:13:18 +0100) Gerd Hoffmann (2): ipxe: disable two second timeout ipxe: update binaries pc-bios/efi-e1000.rom | Bin 174080 - 173568 bytes pc-bios/efi-eepro100.rom | Bin 175104 - 174592 bytes pc-bios/efi-ne2k_pci.rom | Bin 173568 - 173056 bytes pc-bios/efi-pcnet.rom | Bin 173568 - 173056 bytes pc-bios/efi-rtl8139.rom| Bin 177152 - 176640 bytes pc-bios/efi-virtio.rom | Bin 171008 - 171008 bytes roms/Makefile |7 +-- roms/config.ipxe.general.h |2 ++ 8 files changed, 7 insertions(+), 2 deletions(-) create mode 100644 roms/config.ipxe.general.h
[Qemu-devel] [PATCH 2/2] ipxe: update binaries
Signed-off-by: Gerd Hoffmann kra...@redhat.com --- pc-bios/efi-e1000.rom| Bin 174080 - 173568 bytes pc-bios/efi-eepro100.rom | Bin 175104 - 174592 bytes pc-bios/efi-ne2k_pci.rom | Bin 173568 - 173056 bytes pc-bios/efi-pcnet.rom| Bin 173568 - 173056 bytes pc-bios/efi-rtl8139.rom | Bin 177152 - 176640 bytes pc-bios/efi-virtio.rom | Bin 171008 - 171008 bytes 6 files changed, 0 insertions(+), 0 deletions(-) diff --git a/pc-bios/efi-e1000.rom b/pc-bios/efi-e1000.rom index 7dfcea364a1c59a61b9581a3aa2bb64335b76037..21b880afc244548d097bf0ec4fe801417c7e74c8 100644 GIT binary patch [ ... snipped to not spam the list ... ]
[Qemu-devel] [PATCH 1/2] ipxe: disable two second timeout
Signed-off-by: Gerd Hoffmann kra...@redhat.com --- roms/Makefile |7 +-- roms/config.ipxe.general.h |2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) create mode 100644 roms/config.ipxe.general.h diff --git a/roms/Makefile b/roms/Makefile index 3dc5609..7a228ae 100644 --- a/roms/Makefile +++ b/roms/Makefile @@ -57,13 +57,13 @@ lgplvgabios-%: pxerom: $(patsubst %,pxe-rom-%,$(pxerom_variants)) -pxe-rom-%: +pxe-rom-%: ipxe/src/config/local/general.h make -C ipxe/src bin/$(VID)$(DID).rom cp ipxe/src/bin/$(VID)$(DID).rom ../pc-bios/pxe-$*.rom efirom: $(patsubst %,efi-rom-%,$(pxerom_variants)) -efi-rom-%: +efi-rom-%: ipxe/src/config/local/general.h make -C ipxe/src bin/$(VID)$(DID).rom make -C ipxe/src bin-i386-efi/$(VID)$(DID).efidrv make -C ipxe/src bin-x86_64-efi/$(VID)$(DID).efidrv @@ -72,3 +72,6 @@ efi-rom-%: -ec ipxe/src/bin-i386-efi/$(VID)$(DID).efidrv \ -ec ipxe/src/bin-x86_64-efi/$(VID)$(DID).efidrv \ -o ../pc-bios/efi-$*.rom + +ipxe/src/config/local/%: config.ipxe.% + cp $ $@ diff --git a/roms/config.ipxe.general.h b/roms/config.ipxe.general.h new file mode 100644 index 000..b3fce53 --- /dev/null +++ b/roms/config.ipxe.general.h @@ -0,0 +1,2 @@ +#undef BANNER_TIMEOUT +#define BANNER_TIMEOUT 0 -- 1.7.9.7
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 03/25/13 08:59, Jan Kiszka wrote: On 2013-03-25 08:55, Gerd Hoffmann wrote: On 03/25/13 08:50, Jan Kiszka wrote: On 2013-03-12 11:32, Gerd Hoffmann wrote: Use QemuConsole instead. Updates interfaces in console.[ch] and adapts gfx hardware emulation code. Breaks vmware-vga, the X server no longer starts up. I do not spot any obvious typo etc. in the conversion, so I suspect, some values returned by the surface API differ from those that the DisplayState used to provide. Jan Known issue, fix is queued but not yet merged: http://patchwork.ozlabs.org/patch/229214/ Nope, I seem to stress something else: No change here after applying that patch. Any hints in the X server log? What distro + x server version + vmware driver version is this? cheers, Gerd
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 2013-03-25 09:21, Gerd Hoffmann wrote: On 03/25/13 08:59, Jan Kiszka wrote: On 2013-03-25 08:55, Gerd Hoffmann wrote: On 03/25/13 08:50, Jan Kiszka wrote: On 2013-03-12 11:32, Gerd Hoffmann wrote: Use QemuConsole instead. Updates interfaces in console.[ch] and adapts gfx hardware emulation code. Breaks vmware-vga, the X server no longer starts up. I do not spot any obvious typo etc. in the conversion, so I suspect, some values returned by the surface API differ from those that the DisplayState used to provide. Jan Known issue, fix is queued but not yet merged: http://patchwork.ozlabs.org/patch/229214/ Nope, I seem to stress something else: No change here after applying that patch. Any hints in the X server log? vmwlegacy(0): Weight given (565) is inconsistent with the depth (24) What distro + x server version + vmware driver version is this? Oldish Opensuse 11.4 with server 1.9.3. Jan signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCHv4 1/9] move vector definitions to qemu-common.h
On 03/22/2013 02:46 PM, Peter Lieven wrote:
vector optimizations will now be used at various places
not just in is_dup_page() in arch_init.c
this patch also adds a zero splat vector.
Signed-off-by: Peter Lieven p...@kamp.de
Reviewed-by: Eric Blake ebl...@redhat.com
---
arch_init.c | 20
include/qemu-common.h | 24
2 files changed, 24 insertions(+), 20 deletions(-)
diff --git a/arch_init.c b/arch_init.c
index 98e2bc6..1b71912 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -114,26 +114,6 @@ const uint32_t arch_type = QEMU_ARCH;
#define RAM_SAVE_FLAG_CONTINUE 0x20
#define RAM_SAVE_FLAG_XBZRLE 0x40
-#ifdef __ALTIVEC__
-#include altivec.h
-#define VECTYPEvector unsigned char
-#define SPLAT(p) vec_splat(vec_ld(0, p), 0)
-#define ALL_EQ(v1, v2) vec_all_eq(v1, v2)
-/* altivec.h may redefine the bool macro as vector type.
- * Reset it to POSIX semantics. */
-#undef bool
-#define bool _Bool
-#elif defined __SSE2__
-#include emmintrin.h
-#define VECTYPE__m128i
-#define SPLAT(p) _mm_set1_epi8(*(p))
-#define ALL_EQ(v1, v2) (_mm_movemask_epi8(_mm_cmpeq_epi8(v1, v2)) == 0x)
-#else
-#define VECTYPEunsigned long
-#define SPLAT(p) (*(p) * (~0UL / 255))
-#define ALL_EQ(v1, v2) ((v1) == (v2))
-#endif
-
static struct defconfig_file {
const char *filename;
diff --git a/include/qemu-common.h b/include/qemu-common.h
index 7754ee2..e76ade3 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -448,4 +448,28 @@ int uleb128_decode_small(const uint8_t *in, uint32_t *n);
void hexdump(const char *buf, FILE *fp, const char *prefix, size_t size);
+/* vector definitions */
+#ifdef __ALTIVEC__
+#include altivec.h
+#define VECTYPEvector unsigned char
+#define SPLAT(p) vec_splat(vec_ld(0, p), 0)
+#define ZERO_SPLAT vec_splat(vec_ld(0, 0), 0)
This is new macro please move it to a separate patch
Orit
+#define ALL_EQ(v1, v2) vec_all_eq(v1, v2)
+/* altivec.h may redefine the bool macro as vector type.
+ * Reset it to POSIX semantics. */
+#undef bool
+#define bool _Bool
+#elif defined __SSE2__
+#include emmintrin.h
+#define VECTYPE__m128i
+#define SPLAT(p) _mm_set1_epi8(*(p))
+#define ZERO_SPLAT _mm_setzero_si128()
+#define ALL_EQ(v1, v2) (_mm_movemask_epi8(_mm_cmpeq_epi8(v1, v2)) == 0x)
+#else
+#define VECTYPEunsigned long
+#define SPLAT(p) (*(p) * (~0UL / 255))
+#define ZERO_SPLAT 0x0UL
+#define ALL_EQ(v1, v2) ((v1) == (v2))
+#endif
+
#endif
[Qemu-devel] [Bug 1159605] Re: run command hangs using -M none
Hi, Please see notes about all the commands that you are mentioning in the bug : 1. qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -machine none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile starts a dumb qemu monitor interface. You can see that by removing the -nographic option and using the command as follows: qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -machine none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile 2. qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile same as first. except that you are giving memory paramter as -M none. It defaults to 128 MB memory. 3. qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile This command will not work as kernel_irqchip and M are two different options: 1. kernel_irqchip is a -machine paramter (check qemu-system-x86_64 -help). 2. -M is the memory parameter, where you specify how much memory has to be used by your VM. Hence you should get the following warning like I get when I run your command: Supported machines are: none empty machine pc Standard PC (i440FX + PIIX, 1996) (alias of pc-i440fx-1.4) pc-i440fx-1.4Standard PC (i440FX + PIIX, 1996) (default) pc-1.3 Standard PC pc-1.2 Standard PC pc-1.1 Standard PC pc-1.0 Standard PC pc-0.15 Standard PC pc-0.14 Standard PC pc-0.13 Standard PC pc-0.12 Standard PC pc-0.11 Standard PC, qemu 0.11 pc-0.10 Standard PC, qemu 0.10 isapcISA-only PC q35 Standard PC (Q35 + ICH9, 2009) (alias of pc-q35-1.4) pc-q35-1.4 Standard PC (Q35 + ICH9, 2009) 4. the 4th command would also give you a error. Please see help to clearify where you should be using ',' and '-' as delimiters. Rest assured, the argument passing of qemu is done using optarg() which is a pretty stable function. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1159605 Title: run command hangs using -M none Status in QEMU: New Bug description: when i run following command, it just hangs there qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -machine none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile but blow command just fine qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none, -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile I installed qemu-git version on gentoo with kernel 3.8.4 is this a bug??? To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1159605/+subscriptions
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
Hi, Any hints in the X server log? vmwlegacy(0): Weight given (565) is inconsistent with the depth (24) Weight hints depth 16 indeed. What depth used the server to run at? 16 or 24? cheers, Gerd
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 2013-03-25 09:39, Gerd Hoffmann wrote: Hi, Any hints in the X server log? vmwlegacy(0): Weight given (565) is inconsistent with the depth (24) Weight hints depth 16 indeed. What depth used the server to run at? 16 or 24? 24 signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCHv4 2/9] cutils: add a function to find non-zero content in a buffer
On 03/22/2013 02:46 PM, Peter Lieven wrote:
this adds buffer_find_nonzero_offset() which is a SSE2/Altivec
optimized function that searches for non-zero content in a
buffer.
due to the optimizations used in the function there are restrictions
on buffer address and search length. the function
can_use_buffer_find_nonzero_content() can be used to check if
the function can be used safely.
Signed-off-by: Peter Lieven p...@kamp.de
---
include/qemu-common.h | 13 +
util/cutils.c | 45 +
2 files changed, 58 insertions(+)
diff --git a/include/qemu-common.h b/include/qemu-common.h
index e76ade3..078e535 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -472,4 +472,17 @@ void hexdump(const char *buf, FILE *fp, const char
*prefix, size_t size);
#define ALL_EQ(v1, v2) ((v1) == (v2))
#endif
+#define BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR 8
+static inline bool
+can_use_buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+if (len % (BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR
+* sizeof(VECTYPE)) == 0
+ ((uintptr_t) buf) % sizeof(VECTYPE) == 0) {
+return true;
+}
+return false;
+}
+size_t buffer_find_nonzero_offset(const void *buf, size_t len);
+
#endif
diff --git a/util/cutils.c b/util/cutils.c
index 1439da4..41c627e 100644
--- a/util/cutils.c
+++ b/util/cutils.c
@@ -143,6 +143,51 @@ int qemu_fdatasync(int fd)
}
/*
+ * Searches for an area with non-zero content in a buffer
+ *
+ * Attention! The len must be a multiple of
+ * BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR * sizeof(VECTYPE)
+ * and addr must be a multiple of sizeof(VECTYPE) due to
+ * restriction of optimizations in this function.
+ *
+ * can_use_buffer_find_nonzero_offset() can be used to check
+ * these requirements.
+ *
+ * The return value is the offset of the non-zero area rounded
+ * down to BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR * sizeof(VECTYPE).
+ * If the buffer is all zero the return value is equal to len.
+ */
+
+size_t buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+VECTYPE *p = (VECTYPE *)buf;
+VECTYPE zero = ZERO_SPLAT;
+size_t i;
+
+assert(len % (BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR
+* sizeof(VECTYPE)) == 0);
+assert(((uintptr_t) buf) % sizeof(VECTYPE) == 0);
+
+if (*((const long *) buf)) {
+return 0;
+}
+
+for (i = 0; i len / sizeof(VECTYPE);
Why not put len/sizeof(VECTYPE) in a variable?
Orit
+i += BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR) {
+VECTYPE tmp0 = p[i + 0] | p[i + 1];
+VECTYPE tmp1 = p[i + 2] | p[i + 3];
+VECTYPE tmp2 = p[i + 4] | p[i + 5];
+VECTYPE tmp3 = p[i + 6] | p[i + 7];
+VECTYPE tmp01 = tmp0 | tmp1;
+VECTYPE tmp23 = tmp2 | tmp3;
+if (!ALL_EQ(tmp01 | tmp23, zero)) {
+break;
+}
+}
+return i * sizeof(VECTYPE);
+}
+
+/*
* Checks if a buffer is all zeroes
*
* Attention! The len must be a multiple of 4 * sizeof(long) due to
Re: [Qemu-devel] [PATCHv4 3/9] buffer_is_zero: use vector optimizations if possible
On 03/22/2013 02:46 PM, Peter Lieven wrote:
performance gain on SSE2 is approx. 20-25%. altivec
is not tested. performance for unsigned long arithmetic
is unchanged.
Signed-off-by: Peter Lieven p...@kamp.de
Reviewed-by: Eric Blake ebl...@redhat.com
---
util/cutils.c |5 +
1 file changed, 5 insertions(+)
diff --git a/util/cutils.c b/util/cutils.c
index 41c627e..0f43c22 100644
--- a/util/cutils.c
+++ b/util/cutils.c
@@ -205,6 +205,11 @@ bool buffer_is_zero(const void *buf, size_t len)
long d0, d1, d2, d3;
const long * const data = buf;
+/* use vector optimized zero check if possible */
+if (can_use_buffer_find_nonzero_offset(buf, len)) {
+return buffer_find_nonzero_offset(buf, len) == len;
+}
+
assert(len % (4 * sizeof(long)) == 0);
len /= sizeof(long);
Reviewed-by: Orit Wasserman owass...@redhat.com
[Qemu-devel] [Bug 1159605] Re: run command hangs using -M none
** Changed in: qemu Status: New = Invalid -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1159605 Title: run command hangs using -M none Status in QEMU: Invalid Bug description: when i run following command, it just hangs there qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -machine none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile but blow command just fine qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none,kernel_irqchip=on -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile OR qemu-system-x86_64 -enable-kvm -S -no-user-config -nodefaults -nographic -M none, -monitor unix:/var/lib/libvirt/qemu/capabilities.monitor.sock,server,nowait -pidfile /var/lib/libvirt/qemu/capabilities.pidfile I installed qemu-git version on gentoo with kernel 3.8.4 is this a bug??? To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1159605/+subscriptions
Re: [Qemu-devel] [PATCH] block: Add options QDict to bdrv_file_open() prototypes (fix MinGW build)
On Sun, Mar 24, 2013 at 08:08:36AM +0100, Stefan Weil wrote: The new parameter is unused yet. This part was missing in commit 787e4a8500020695eb391e2f1cc4767ee071d441. Cc: Kevin Wolf kw...@redhat.com Cc: Eric Blake ebl...@redhat.com Signed-off-by: Stefan Weil s...@weilnetz.de --- block/raw-win32.c |6 -- 1 file changed, 4 insertions(+), 2 deletions(-) Thanks, applied to my block tree: https://github.com/stefanha/qemu/commits/block Stefan
Re: [Qemu-devel] [PATCH] rbd: fix compile error
On Sun, Mar 24, 2013 at 03:41:15PM +0800, Liu Yuan wrote: From: Liu Yuan tailai...@taobao.com Commit 787e4a85 [block: Add options QDict to bdrv_file_open() prototypes] didn't update rbd.c accordingly. Cc: Kevin Wolf kw...@redhat.com Cc: Stefan Hajnoczi stefa...@redhat.com Signed-off-by: Liu Yuan tailai...@taobao.com --- block/rbd.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Thanks, applied to my block tree: https://github.com/stefanha/qemu/commits/block Stefan
Re: [Qemu-devel] [PATCHv4 2/9] cutils: add a function to find non-zero content in a buffer
Am 25.03.2013 um 09:53 schrieb Orit Wasserman owass...@redhat.com:
On 03/22/2013 02:46 PM, Peter Lieven wrote:
this adds buffer_find_nonzero_offset() which is a SSE2/Altivec
optimized function that searches for non-zero content in a
buffer.
due to the optimizations used in the function there are restrictions
on buffer address and search length. the function
can_use_buffer_find_nonzero_content() can be used to check if
the function can be used safely.
Signed-off-by: Peter Lieven p...@kamp.de
---
include/qemu-common.h | 13 +
util/cutils.c | 45 +
2 files changed, 58 insertions(+)
diff --git a/include/qemu-common.h b/include/qemu-common.h
index e76ade3..078e535 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -472,4 +472,17 @@ void hexdump(const char *buf, FILE *fp, const char
*prefix, size_t size);
#define ALL_EQ(v1, v2) ((v1) == (v2))
#endif
+#define BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR 8
+static inline bool
+can_use_buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+if (len % (BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR
+* sizeof(VECTYPE)) == 0
+ ((uintptr_t) buf) % sizeof(VECTYPE) == 0) {
+return true;
+}
+return false;
+}
+size_t buffer_find_nonzero_offset(const void *buf, size_t len);
+
#endif
diff --git a/util/cutils.c b/util/cutils.c
index 1439da4..41c627e 100644
--- a/util/cutils.c
+++ b/util/cutils.c
@@ -143,6 +143,51 @@ int qemu_fdatasync(int fd)
}
/*
+ * Searches for an area with non-zero content in a buffer
+ *
+ * Attention! The len must be a multiple of
+ * BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR * sizeof(VECTYPE)
+ * and addr must be a multiple of sizeof(VECTYPE) due to
+ * restriction of optimizations in this function.
+ *
+ * can_use_buffer_find_nonzero_offset() can be used to check
+ * these requirements.
+ *
+ * The return value is the offset of the non-zero area rounded
+ * down to BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR * sizeof(VECTYPE).
+ * If the buffer is all zero the return value is equal to len.
+ */
+
+size_t buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+VECTYPE *p = (VECTYPE *)buf;
+VECTYPE zero = ZERO_SPLAT;
+size_t i;
+
+assert(len % (BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR
+* sizeof(VECTYPE)) == 0);
+assert(((uintptr_t) buf) % sizeof(VECTYPE) == 0);
+
+if (*((const long *) buf)) {
+return 0;
+}
+
+for (i = 0; i len / sizeof(VECTYPE);
Why not put len/sizeof(VECTYPE) in a variable?
are you afraid that there is a division at each iteration?
sizeof(VECTYPE) is a power of 2 so i think the compiler will optimize it
to a at compile time.
I would also be ok with writing len /= sizeof(VECTYPE) before the loop.
Peter
Orit
+i += BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR) {
+VECTYPE tmp0 = p[i + 0] | p[i + 1];
+VECTYPE tmp1 = p[i + 2] | p[i + 3];
+VECTYPE tmp2 = p[i + 4] | p[i + 5];
+VECTYPE tmp3 = p[i + 6] | p[i + 7];
+VECTYPE tmp01 = tmp0 | tmp1;
+VECTYPE tmp23 = tmp2 | tmp3;
+if (!ALL_EQ(tmp01 | tmp23, zero)) {
+break;
+}
+}
+return i * sizeof(VECTYPE);
+}
+
+/*
* Checks if a buffer is all zeroes
*
* Attention! The len must be a multiple of 4 * sizeof(long) due to
Re: [Qemu-devel] [PATCH] ifname=xxx for -netdev bridge
On Thu, Mar 21, 2013 at 07:05:09PM +0100, Alexandre Kandalintsev wrote: Hi! Here is the patch that allows us to specify the name of tap interface when -netdev bridge is used. It's like -netdev tap,ifname=xxx, but for bridges. ** Motivation ** We've got zillions of VMs and would like to see meaningful names of tap interfaces. This is really useful for for, e.g., system administrators in case they want to run tcpdump on it. ** How it works ** Just specify a ifname= parameter as it is done if --netdev tap is used. However, as it requires root privs, the interface renaming is actually done by qemu-bridge-helper. --netdev tap,ifname=xxx will fail if qemu is launched not from root. ** TODO ** 1. Update docs 2. I'm afraid that net_init_tap should not run helper with --br=DEFAULT_BRIDGE_INTERFACE . At least bridge name should be tunnable. But this is a future work. 3. May be we should call qemu-bridge-helper for tap interface renamings because it always has root privs? qemu-bridge-helper is a setuid root binary. It allows access to things an unprivileged user normally cannot do. We need to be very careful that new features cannot be abused. There needs to be a policy in qemu-bridge-helper to control network interface naming. Imagine an existing qemu-bridge-helper deployment. Now if your patch is merged and the new qemu-bridge-helper is installed, unprivileged users can create arbitrarily named network interfaces. It was previously not possible to create arbitrarily named network interfaces. This might pose a security problem given firewall configuration, monitoring software, etc which isn't configured to deal with these new interface names. By default, custom names should not be allowed. Perhaps the qemu-bridge-helper configuration file needs an option to specify a glob pattern, e.g. vm*. This way the host system administrator can restrict network interface names while still allowing humand-friendly names. Stefan
Re: [Qemu-devel] [PATCHv4 4/9] bitops: use vector algorithm to optimize find_next_bit()
On 03/22/2013 02:46 PM, Peter Lieven wrote:
this patch adds the usage of buffer_find_nonzero_offset()
to skip large areas of zeroes.
compared to loop unrolling presented in an earlier
patch this adds another 50% performance benefit for
skipping large areas of zeroes. loop unrolling alone
added close to 100% speedup.
Signed-off-by: Peter Lieven p...@kamp.de
Reviewed-by: Eric Blake ebl...@redhat.com
---
util/bitops.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/util/bitops.c b/util/bitops.c
index e72237a..9bb61ff 100644
--- a/util/bitops.c
+++ b/util/bitops.c
@@ -42,10 +42,28 @@ unsigned long find_next_bit(const unsigned long *addr,
unsigned long size,
size -= BITS_PER_LONG;
result += BITS_PER_LONG;
}
-while (size ~(BITS_PER_LONG-1)) {
-if ((tmp = *(p++))) {
-goto found_middle;
+while (size = BITS_PER_LONG) {
+tmp = *p;
+if (tmp) {
+ goto found_middle;
+}
+if (can_use_buffer_find_nonzero_offset(p, size / BITS_PER_BYTE)) {
+size_t tmp2 =
+buffer_find_nonzero_offset(p, size / BITS_PER_BYTE);
+result += tmp2 * BITS_PER_BYTE;
+size -= tmp2 * BITS_PER_BYTE;
+p += tmp2 / sizeof(unsigned long);
+if (!size) {
+return result;
+}
+if (tmp2) {
+tmp = *p;
+if (tmp) {
+goto found_middle;
+}
+}
}
+p++;
result += BITS_PER_LONG;
size -= BITS_PER_LONG;
}
Reviewed-by: Orit Wasserman owass...@redhat.com
Re: [Qemu-devel] [RFC PATCH 3/3] mc146818rtc: export the timezone information
Il 28/02/2013 03:12, H. Peter Anvin ha scritto:
From: H. Peter Anvin h...@zytor.com
There is no standard method for storing timezone information
associated with the classic PC/AT RTC, however, there are standard
methods in ACPI (Time and Alarm Device) and EFI (GetTime/SetTime) for
getting this information.
Since these are abstract methods, it is qreally firmware-specific how
it is stored, however, since Qemu initializes the RTC in the virtual
environment that information needs to come from Qemu in the first
place.
Non-PC platforms that use the MC146181 RTC may have their own
firmware-specific methods as well.
The most logical place to stash this information is in the RTC CMOS;
not only is it logically co-located with the relevant information, but
it is also very easy to access from ACPI bytecode. Thus, save the
timezone information in two bytes in CMOS that have no known standard
definition, but are yet within the 64 bytes that even the most basic
RTC CMOS implementations including the original MC146181 support.
Note: all timezones currently in use in the world are on 15-minutes
boundaries, which would allow this information to be stored in a
single signed byte. However, both EFI and ACPI use a minute-granular
interface (specified as -1440 to +1440 with 2047 used to mean
unknown, this requires a minimum of 12 bits to represent); this
follows that model.
Interesting, do you have SeaBIOS and/or OVMF patches for this?
Paolo
Signed-off-by: H. Peter Anvin h...@zytor.com
Cc: Kevin O'Connor ke...@koconnor.net
Cc: David Woodhouse dw...@infradead.org
---
hw/mc146818rtc.c | 6 ++
hw/mc146818rtc_regs.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index 2fb11f6..72541dd 100644
--- a/hw/mc146818rtc.c
+++ b/hw/mc146818rtc.c
@@ -681,6 +681,7 @@ static void rtc_set_date_from_host(ISADevice *dev)
{
RTCState *s = DO_UPCAST(RTCState, dev, dev);
struct tm tm;
+int minuteseast;
qemu_get_timedate(tm, 0);
@@ -690,6 +691,11 @@ static void rtc_set_date_from_host(ISADevice *dev)
/* set the CMOS date */
rtc_set_cmos(s, tm);
+
+/* Set the timezone information as a signed 16-bit number of minutes */
+minuteseast = ((int64_t)s-base_rtc - (int64_t)mktime(tm)) / 60;
+s-cmos_data[RTC_TIMEZONE_L] = (uint8_t)(minuteseast);
+s-cmos_data[RTC_TIMEZONE_H] = (uint8_t)(minuteseast 8);
}
static int rtc_post_load(void *opaque, int version_id)
diff --git a/hw/mc146818rtc_regs.h b/hw/mc146818rtc_regs.h
index ccdee42..7dd5e0d 100644
--- a/hw/mc146818rtc_regs.h
+++ b/hw/mc146818rtc_regs.h
@@ -47,6 +47,8 @@
/* PC cmos mappings */
#define RTC_CENTURY 0x32
#define RTC_IBM_PS2_CENTURY_BYTE 0x37
+#define RTC_TIMEZONE_L 0x3e
+#define RTC_TIMEZONE_H 0x3f
#define REG_A_UIP 0x80
Re: [Qemu-devel] [RFC PATCH 1/3] target-i386: Add 486sx, old486, and old486sx CPU models
Il 24/03/2013 06:06, H. Peter Anvin ha scritto: Low priority ping on this patchset...? -hpa I think it fell through the cracks due to the RFC tag. Patches 1 and 2 look good, but Anthony does not apply TCG patches. CCing Blue and Aurelien. Paolo
Re: [Qemu-devel] [PATCH 06/14] nbd: Keep hostname and port separate
Am 22.03.2013 um 23:46 hat Paolo Bonzini geschrieben:
Il 22/03/2013 18:41, Kevin Wolf ha scritto:
+QemuOpts *opts = qemu_opts_create_nofail(socket_optslist);
+
+qemu_opt_set(opts, host, s-inet_addr-host);
+qemu_opt_set(opts, port, s-inet_addr-port);
+if (s-inet_addr-has_to) {
+qemu_opt_set_number(opts, to, s-inet_addr-to);
+}
+if (s-inet_addr-has_ipv4) {
+qemu_opt_set_number(opts, ipv4, s-inet_addr-ipv4);
+}
+if (s-inet_addr-has_ipv6) {
+qemu_opt_set_number(opts, ipv6, s-inet_addr-ipv6);
+}
+
+sock = tcp_socket_outgoing_opts(opts);
Sorry for the late review... You're basically reinventing socket_connect
here. Would like to clean it up or shall I do it?
It's probably best if you change whatever you like to have changed.
FWIW, this specific code doesn't exist any more at the end of the
series.
Kevin
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 03/25/13 09:40, Jan Kiszka wrote:
On 2013-03-25 09:39, Gerd Hoffmann wrote:
Hi,
Any hints in the X server log?
vmwlegacy(0): Weight given (565) is inconsistent with the depth
(24)
Weight hints depth 16 indeed. What depth used the server to run at?
16 or 24?
24
As expected. Puzzling where the 565 weight comes from ...
Can you apply the attached patch, enable vmware_* + displaysurface_*
tracepoints + send a log?
thanks,
Gerd
From 40ced618a80d70f579aecb397d448a45fd499c63 Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann kra...@redhat.com
Date: Mon, 25 Mar 2013 09:53:35 +0100
Subject: [PATCH] vmware vga: trace value read+write
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hw/vmware_vga.c | 100 +--
trace-events|2 ++
2 files changed, 70 insertions(+), 32 deletions(-)
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index 4ebfe17..d317b4e 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -721,61 +721,79 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t
address)
uint32_t caps;
struct vmsvga_state_s *s = opaque;
DisplaySurface *surface = qemu_console_surface(s-vga.con);
+uint32_t ret;
switch (s-index) {
case SVGA_REG_ID:
-return s-svgaid;
+ret = s-svgaid;
+break;
case SVGA_REG_ENABLE:
-return s-enable;
+ret = s-enable;
+break;
case SVGA_REG_WIDTH:
-return surface_width(surface);
+ret = surface_width(surface);
+break;
case SVGA_REG_HEIGHT:
-return surface_height(surface);
+ret = surface_height(surface);
+break;
case SVGA_REG_MAX_WIDTH:
-return SVGA_MAX_WIDTH;
+ret = SVGA_MAX_WIDTH;
+break;
case SVGA_REG_MAX_HEIGHT:
-return SVGA_MAX_HEIGHT;
+ret = SVGA_MAX_HEIGHT;
+break;
case SVGA_REG_DEPTH:
-return s-depth;
+ret = s-depth;
+break;
case SVGA_REG_BITS_PER_PIXEL:
-return (s-depth + 7) ~7;
+ret = (s-depth + 7) ~7;
+break;
case SVGA_REG_PSEUDOCOLOR:
-return 0x0;
+ret = 0x0;
+break;
case SVGA_REG_RED_MASK:
-return surface-pf.rmask;
+ret = surface-pf.rmask;
+break;
case SVGA_REG_GREEN_MASK:
-return surface-pf.gmask;
+ret = surface-pf.gmask;
+break;
case SVGA_REG_BLUE_MASK:
-return surface-pf.bmask;
+ret = surface-pf.bmask;
+break;
case SVGA_REG_BYTES_PER_LINE:
-return s-bypp * s-new_width;
+ret = s-bypp * s-new_width;
+break;
case SVGA_REG_FB_START: {
struct pci_vmsvga_state_s *pci_vmsvga
= container_of(s, struct pci_vmsvga_state_s, chip);
-return pci_get_bar_addr(pci_vmsvga-card, 1);
+ret = pci_get_bar_addr(pci_vmsvga-card, 1);
+break;
}
case SVGA_REG_FB_OFFSET:
-return 0x0;
+ret = 0x0;
+break;
case SVGA_REG_VRAM_SIZE:
-return s-vga.vram_size; /* No physical VRAM besides the framebuffer */
+ret = s-vga.vram_size; /* No physical VRAM besides the framebuffer */
+break;
case SVGA_REG_FB_SIZE:
-return s-vga.vram_size;
+ret = s-vga.vram_size;
+break;
case SVGA_REG_CAPABILITIES:
caps = SVGA_CAP_NONE;
@@ -791,66 +809,84 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t
address)
SVGA_CAP_CURSOR_BYPASS;
}
#endif
-return caps;
+ret = caps;
+break;
case SVGA_REG_MEM_START: {
struct pci_vmsvga_state_s *pci_vmsvga
= container_of(s, struct pci_vmsvga_state_s, chip);
-return pci_get_bar_addr(pci_vmsvga-card, 2);
+ret = pci_get_bar_addr(pci_vmsvga-card, 2);
+break;
}
case SVGA_REG_MEM_SIZE:
-return s-fifo_size;
+ret = s-fifo_size;
+break;
case SVGA_REG_CONFIG_DONE:
-return s-config;
+ret = s-config;
+break;
case SVGA_REG_SYNC:
case SVGA_REG_BUSY:
-return s-syncing;
+ret = s-syncing;
+break;
case SVGA_REG_GUEST_ID:
-return s-guest;
+ret = s-guest;
+break;
case SVGA_REG_CURSOR_ID:
-return s-cursor.id;
+ret = s-cursor.id;
+break;
case SVGA_REG_CURSOR_X:
-return s-cursor.x;
+ret = s-cursor.x;
+break;
case SVGA_REG_CURSOR_Y:
-return s-cursor.x;
+ret = s-cursor.x;
+break;
case SVGA_REG_CURSOR_ON:
-return s-cursor.on;
+ret = s-cursor.on;
+break;
case SVGA_REG_HOST_BITS_PER_PIXEL:
-return (s-depth + 7) ~7;
+ret = (s-depth + 7) ~7;
+break;
case SVGA_REG_SCRATCH_SIZE:
-return s-scratch_size;
+ret = s-scratch_size;
+break;
Re: [Qemu-devel] [RFC PATCH 1/3] target-i386: Add 486sx, old486, and old486sx CPU models
Am 24.03.2013 06:06, schrieb H. Peter Anvin: Low priority ping on this patchset...? You forgot to CC me on the CPU models... Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCHv4 2/9] cutils: add a function to find non-zero content in a buffer
On 03/25/2013 10:56 AM, Peter Lieven wrote:
Am 25.03.2013 um 09:53 schrieb Orit Wasserman owass...@redhat.com:
On 03/22/2013 02:46 PM, Peter Lieven wrote:
this adds buffer_find_nonzero_offset() which is a SSE2/Altivec
optimized function that searches for non-zero content in a
buffer.
due to the optimizations used in the function there are restrictions
on buffer address and search length. the function
can_use_buffer_find_nonzero_content() can be used to check if
the function can be used safely.
Signed-off-by: Peter Lieven p...@kamp.de
---
include/qemu-common.h | 13 +
util/cutils.c | 45 +
2 files changed, 58 insertions(+)
diff --git a/include/qemu-common.h b/include/qemu-common.h
index e76ade3..078e535 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -472,4 +472,17 @@ void hexdump(const char *buf, FILE *fp, const char
*prefix, size_t size);
#define ALL_EQ(v1, v2) ((v1) == (v2))
#endif
+#define BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR 8
+static inline bool
+can_use_buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+if (len % (BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR
+* sizeof(VECTYPE)) == 0
+ ((uintptr_t) buf) % sizeof(VECTYPE) == 0) {
+return true;
+}
+return false;
+}
+size_t buffer_find_nonzero_offset(const void *buf, size_t len);
+
#endif
diff --git a/util/cutils.c b/util/cutils.c
index 1439da4..41c627e 100644
--- a/util/cutils.c
+++ b/util/cutils.c
@@ -143,6 +143,51 @@ int qemu_fdatasync(int fd)
}
/*
+ * Searches for an area with non-zero content in a buffer
+ *
+ * Attention! The len must be a multiple of
+ * BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR * sizeof(VECTYPE)
+ * and addr must be a multiple of sizeof(VECTYPE) due to
+ * restriction of optimizations in this function.
+ *
+ * can_use_buffer_find_nonzero_offset() can be used to check
+ * these requirements.
+ *
+ * The return value is the offset of the non-zero area rounded
+ * down to BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR * sizeof(VECTYPE).
+ * If the buffer is all zero the return value is equal to len.
+ */
+
+size_t buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+VECTYPE *p = (VECTYPE *)buf;
+VECTYPE zero = ZERO_SPLAT;
+size_t i;
+
+assert(len % (BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR
+* sizeof(VECTYPE)) == 0);
+assert(((uintptr_t) buf) % sizeof(VECTYPE) == 0);
+
+if (*((const long *) buf)) {
+return 0;
+}
+
+for (i = 0; i len / sizeof(VECTYPE);
Why not put len/sizeof(VECTYPE) in a variable?
are you afraid that there is a division at each iteration?
sizeof(VECTYPE) is a power of 2 so i think the compiler will optimize it
to a at compile time.
true, but it still is done every iteration.
I would also be ok with writing len /= sizeof(VECTYPE) before the loop.
I would prefer it :)
Orit
Peter
Orit
+i += BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR) {
+VECTYPE tmp0 = p[i + 0] | p[i + 1];
+VECTYPE tmp1 = p[i + 2] | p[i + 3];
+VECTYPE tmp2 = p[i + 4] | p[i + 5];
+VECTYPE tmp3 = p[i + 6] | p[i + 7];
+VECTYPE tmp01 = tmp0 | tmp1;
+VECTYPE tmp23 = tmp2 | tmp3;
+if (!ALL_EQ(tmp01 | tmp23, zero)) {
+break;
+}
+}
+return i * sizeof(VECTYPE);
+}
+
+/*
* Checks if a buffer is all zeroes
*
* Attention! The len must be a multiple of 4 * sizeof(long) due to
Re: [Qemu-devel] [PATCHv4 5/9] migration: search for zero instead of dup pages
On 03/22/2013 02:46 PM, Peter Lieven wrote:
virtually all dup pages are zero pages. remove
the special is_dup_page() function and use the
optimized buffer_find_nonzero_offset() function
instead.
here buffer_find_nonzero_offset() is used directly
to avoid the unnecssary additional checks in
buffer_is_zero().
raw performace gain checking zeroed memory
over is_dup_page() is approx. 15-20% with SSE2.
Signed-off-by: Peter Lieven p...@kamp.de
---
arch_init.c | 21 ++---
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/arch_init.c b/arch_init.c
index 1b71912..9ebca83 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -144,19 +144,10 @@ int qemu_read_default_config_files(bool userconfig)
return 0;
}
-static int is_dup_page(uint8_t *page)
+static inline bool is_zero_page(uint8_t *p)
{
-VECTYPE *p = (VECTYPE *)page;
-VECTYPE val = SPLAT(page);
-int i;
-
-for (i = 0; i TARGET_PAGE_SIZE / sizeof(VECTYPE); i++) {
-if (!ALL_EQ(val, p[i])) {
-return 0;
-}
-}
-
-return 1;
+return buffer_find_nonzero_offset(p, TARGET_PAGE_SIZE) ==
+TARGET_PAGE_SIZE;
}
/* struct contains XBZRLE cache and a static page
@@ -443,12 +434,12 @@ static int ram_save_block(QEMUFile *f, bool last_stage)
/* In doubt sent page as normal */
bytes_sent = -1;
-if (is_dup_page(p)) {
+if (is_zero_page(p)) {
acct_info.dup_pages++;
bytes_sent = save_block_hdr(f, block, offset, cont,
RAM_SAVE_FLAG_COMPRESS);
-qemu_put_byte(f, *p);
-bytes_sent += 1;
+qemu_put_byte(f, 0);
+bytes_sent++;
} else if (migrate_use_xbzrle()) {
current_addr = block-offset + offset;
bytes_sent = save_xbzrle_page(f, p, current_addr, block,
Reviewed-by: Orit Wasserman owass...@redhat.com
Re: [Qemu-devel] [PATCHv4 6/9] migration: add an indicator for bulk state of ram migration
On 03/22/2013 02:46 PM, Peter Lieven wrote:
the first round of ram transfer is special since all pages
are dirty and thus all memory pages are transferred to
the target. this patch adds a boolean variable to track
this stage.
Signed-off-by: Peter Lieven p...@kamp.de
Reviewed-by: Eric Blake ebl...@redhat.com
---
arch_init.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch_init.c b/arch_init.c
index 9ebca83..4c4caf4 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -317,6 +317,7 @@ static ram_addr_t last_offset;
static unsigned long *migration_bitmap;
static uint64_t migration_dirty_pages;
static uint32_t last_version;
+static bool ram_bulk_stage;
static inline
ram_addr_t migration_bitmap_find_and_reset_dirty(MemoryRegion *mr,
@@ -424,6 +425,7 @@ static int ram_save_block(QEMUFile *f, bool last_stage)
if (!block) {
block = QTAILQ_FIRST(ram_list.blocks);
complete_round = true;
+ram_bulk_stage = false;
}
} else {
uint8_t *p;
@@ -527,6 +529,7 @@ static void reset_ram_globals(void)
last_sent_block = NULL;
last_offset = 0;
last_version = ram_list.version;
+ram_bulk_stage = true;
}
#define MAX_WAIT 50 /* ms, half buffered_file limit */
Reviewed-by: Orit Wasserman owass...@redhat.com
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 2013-03-25 10:10, Gerd Hoffmann wrote: On 03/25/13 09:40, Jan Kiszka wrote: On 2013-03-25 09:39, Gerd Hoffmann wrote: Hi, Any hints in the X server log? vmwlegacy(0): Weight given (565) is inconsistent with the depth (24) Weight hints depth 16 indeed. What depth used the server to run at? 16 or 24? 24 As expected. Puzzling where the 565 weight comes from ... Can you apply the attached patch, enable vmware_* + displaysurface_* tracepoints + send a log? [shrinking CC list at this chance] read: index 1, value 0x0 read: index 2, value 0x320 read: index 3, value 0x258 read: index 7, value 0x20 read: index 0, value 0x9002 read: index 20, value 0x0 write: index 0, value 0x9002 read: index 0, value 0x9002 read: index 17, value 0x3 read: index 28, value 0x20 read: index 6, value 0x20 read: index 15, value 0x100 read: index 13, value 0xfd00 read: index 4, value 0x938 read: index 5, value 0x6ea read: index 9, value 0xf800 read: index 10, value 0x7e0 read: index 11, value 0x1f read: index 8, value 0x0 read: index 1, value 0x0 read: index 2, value 0x320 read: index 3, value 0x258 read: index 7, value 0x20 read: index 0, value 0x9002 read: index 20, value 0x0 write: index 0, value 0x9002 read: index 0, value 0x9002 read: index 17, value 0x3 read: index 28, value 0x20 read: index 6, value 0x20 read: index 15, value 0x100 read: index 13, value 0xfd00 read: index 4, value 0x938 read: index 5, value 0x6ea read: index 9, value 0xf800 read: index 10, value 0x7e0 read: index 11, value 0x1f read: index 8, value 0x0 Jan signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH 11/20] qemu-char: use a glib timeout instead of qemu-timer
On Fri, Mar 15, 2013 at 4:44 PM, Anthony Liguori aligu...@us.ibm.com wrote:
Laurent Desnogues laurent.desnog...@gmail.com writes:
Hello,
On Tue, Mar 5, 2013 at 6:51 PM, Amit Shah amit.s...@redhat.com wrote:
From: Anthony Liguori aligu...@us.ibm.com
Signed-off-by: Anthony Liguori aligu...@us.ibm.com
Signed-off-by: Amit Shah amit.s...@redhat.com
---
qemu-char.c | 68
-
1 file changed, 45 insertions(+), 23 deletions(-)
diff --git a/qemu-char.c b/qemu-char.c
index eb0ac81..6dba943 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -990,12 +990,50 @@ typedef struct {
int connected;
int polling;
int read_bytes;
-QEMUTimer *timer;
+guint timer_tag;
} PtyCharDriver;
static void pty_chr_update_read_handler(CharDriverState *chr);
static void pty_chr_state(CharDriverState *chr, int connected);
+static gboolean pty_chr_timer(gpointer opaque)
+{
+struct CharDriverState *chr = opaque;
+PtyCharDriver *s = chr-opaque;
+
+if (s-connected) {
+goto out;
+}
+if (s-polling) {
+/* If we arrive here without polling being cleared due
+ * read returning -EIO, then we are (re-)connected */
+pty_chr_state(chr, 1);
+goto out;
+}
+
+/* Next poll ... */
+pty_chr_update_read_handler(chr);
+
+out:
+return FALSE;
+}
+
+static void pty_chr_rearm_timer(CharDriverState *chr, int ms)
+{
+PtyCharDriver *s = chr-opaque;
+
+if (s-timer_tag) {
+g_source_remove(s-timer_tag);
+s-timer_tag = 0;
+}
+
+if (ms == 1000) {
+s-timer_tag = g_timeout_add_seconds(1, pty_chr_timer, chr);
It looks like g_timeout_add_seconds isn't available for
poor people using some old distros (glib 2.12.3 here).
Can you test adding:
#if !GLIB_CHECK_VERSION(2, 14, 0)
static guint g_timeout_add_seconds(guint interval, GSourceFunc function,
gpointer data)
{
return g_timeout_add(interval * 1000, function, data);
}
#endif
We probably should introduce a glib-compat to centralize work arounds
for older versions of glib...
Hi Anthony,
Are you sending a patch for g_timeout_add_seconds() compatibility?
The RHEL5 builds are failing because their glib is old:
http://buildbot.b1-systems.de/qemu/builders/default_x86_64_rhel5/builds/551/steps/compile/logs/stdio
Stefan
Re: [Qemu-devel] [RFC PATCH 1/3] target-i386: Add 486sx, old486, and old486sx CPU models
Am 28.02.2013 03:12, schrieb H. Peter Anvin:
From: H. Peter Anvin h...@zytor.com
Add models for 486SX, and pre-CPUID versions of the 486 (DX SX).
Change the model number for the standard 486DX to a model which
actually had CPUID.
Note: these models are fairly vestigial, for example most of the FPU
operations still work; only F*ST[CS]W have been modified to appear as
through there is no FPU.
This also changes the classic 486 model number to 8 (DX4) which
matches the feature set presented.
Signed-off-by: H. Peter Anvin h...@zytor.com
---
target-i386/cpu.c | 39 ++---
target-i386/fpu_helper.c | 12 +++--
target-i386/misc_helper.c | 15
target-i386/translate.c | 62
+++
4 files changed, 75 insertions(+), 53 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index aab35c7..a5aad19 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -365,8 +365,11 @@ typedef struct x86_def_t {
uint32_t cpuid_7_0_ebx_features;
} x86_def_t;
-#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
-#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
+#define OLD_I486SX_FEATURES 0
+#define OLD_I486_FEATURES CPUID_FP87
+#define I486SX_FEATURES CPUID_VME /* SX2+ */
+#define I486_FEATURES (CPUID_FP87 | CPUID_VME) /* DX4 and some DX2 */
+#define PENTIUM_FEATURES (I486_FEATURES | CPUID_PSE | CPUID_DE | CPUID_TSC |
\
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
@@ -535,16 +538,46 @@ static x86_def_t builtin_x86_defs[] = {
.model_id = Genuine Intel(R) CPU T2600 @ 2.16GHz,
},
{
+.name = old486,
+.level = 0,
+.vendor = CPUID_VENDOR_INTEL,
+.family = 4,
+.model = 1,
+.stepping = 0,
+.features = OLD_I486_FEATURES,
+.xlevel = 0,
+},
+{
+.name = old486sx,
+.level = 0,
+.vendor = CPUID_VENDOR_INTEL,
+.family = 4,
+.model = 2,
+.stepping = 0,
+.features = OLD_I486SX_FEATURES,
+.xlevel = 0,
+},
+{
.name = 486,
.level = 1,
.vendor = CPUID_VENDOR_INTEL,
.family = 4,
-.model = 0,
+.model = 8,
Such changes have been rejected in the past (e.g., n270 Atom).
I personally wouldn't object to 486 changes, but I guess it should
rather be handled via Igor's CPU static properties that I have in my
review queue: The .model value would be set to 8 but the PC machine
would be changed alongside to set model = 0 for pc-1.4 and earlier.
.stepping = 0,
.features = I486_FEATURES,
.xlevel = 0,
},
{
+.name = 486sx,
+.level = 1,
+.vendor = CPUID_VENDOR_INTEL,
+.family = 4,
+.model = 5,
+.stepping = 0,
+.features = I486SX_FEATURES,
+.xlevel = 0,
+},
+{
.name = pentium,
.level = 1,
.vendor = CPUID_VENDOR_INTEL,
[...]
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 112c310..6d8abff 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
[...]
@@ -7926,6 +7900,8 @@ static inline void
gen_intermediate_code_internal(CPUX86State *env,
if (flags HF_SOFTMMU_MASK) {
dc-mem_index = (cpu_mmu_index(env) + 1) 2;
}
+dc-cpuid_family = (env-cpuid_version 8) 0x0f;
+dc-cpuid_level = env-cpuid_level;
dc-cpuid_features = env-cpuid_features;
dc-cpuid_ext_features = env-cpuid_ext_features;
dc-cpuid_ext2_features = env-cpuid_ext2_features;
Would be better to reuse the family QOM property that also reads the
upper two nibbles, to avoid surprises.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCHv4 2/9] cutils: add a function to find non-zero content in a buffer
+size_t buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+VECTYPE *p = (VECTYPE *)buf;
+VECTYPE zero = ZERO_SPLAT;
+size_t i;
+
+assert(len % (BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR
+* sizeof(VECTYPE)) == 0);
+assert(((uintptr_t) buf) % sizeof(VECTYPE) == 0);
+
+if (*((const long *) buf)) {
+return 0;
+}
+
+for (i = 0; i len / sizeof(VECTYPE);
Why not put len/sizeof(VECTYPE) in a variable?
are you afraid that there is a division at each iteration?
sizeof(VECTYPE) is a power of 2 so i think the compiler will
optimize it
to a at compile time.
true, but it still is done every iteration.
len is an invariant, the compiler will move it out of the loop
automatically. Write readable code unless you have good clues
that it is also slow.
Paolo
Re: [Qemu-devel] [PATCHv4 7/9] migration: do not sent zero pages in bulk stage
On 03/22/2013 02:46 PM, Peter Lieven wrote:
during bulk stage of ram migration if a page is a
zero page do not send it at all.
the memory at the destination reads as zero anyway.
even if there is an madvise with QEMU_MADV_DONTNEED
at the target upon receipt of a zero page I have observed
that the target starts swapping if the memory is overcommitted.
it seems that the pages are dropped asynchronously.
Signed-off-by: Peter Lieven p...@kamp.de
---
arch_init.c | 24
hmp.c |2 ++
include/migration/migration.h |2 ++
migration.c |3 ++-
qapi-schema.json |6 --
qmp-commands.hx |3 ++-
6 files changed, 32 insertions(+), 8 deletions(-)
diff --git a/arch_init.c b/arch_init.c
index 4c4caf4..c34a4af 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -181,6 +181,7 @@ int64_t xbzrle_cache_resize(int64_t new_size)
/* accounting for migration statistics */
typedef struct AccountingInfo {
uint64_t dup_pages;
+uint64_t skipped_pages;
uint64_t norm_pages;
uint64_t iterations;
uint64_t xbzrle_bytes;
@@ -206,6 +207,16 @@ uint64_t dup_mig_pages_transferred(void)
return acct_info.dup_pages;
}
+uint64_t skipped_mig_bytes_transferred(void)
+{
+return acct_info.skipped_pages * TARGET_PAGE_SIZE;
+}
+
+uint64_t skipped_mig_pages_transferred(void)
+{
+return acct_info.skipped_pages;
+}
+
uint64_t norm_mig_bytes_transferred(void)
{
return acct_info.norm_pages * TARGET_PAGE_SIZE;
@@ -438,10 +449,15 @@ static int ram_save_block(QEMUFile *f, bool last_stage)
bytes_sent = -1;
if (is_zero_page(p)) {
acct_info.dup_pages++;
-bytes_sent = save_block_hdr(f, block, offset, cont,
-RAM_SAVE_FLAG_COMPRESS);
-qemu_put_byte(f, 0);
-bytes_sent++;
+if (!ram_bulk_stage) {
+bytes_sent = save_block_hdr(f, block, offset, cont,
+RAM_SAVE_FLAG_COMPRESS);
+qemu_put_byte(f, 0);
+bytes_sent++;
+} else {
+acct_info.skipped_pages++;
+bytes_sent = 0;
+}
} else if (migrate_use_xbzrle()) {
current_addr = block-offset + offset;
bytes_sent = save_xbzrle_page(f, p, current_addr, block,
diff --git a/hmp.c b/hmp.c
index b0a861c..e3e833e 100644
--- a/hmp.c
+++ b/hmp.c
@@ -173,6 +173,8 @@ void hmp_info_migrate(Monitor *mon, const QDict *qdict)
info-ram-total 10);
monitor_printf(mon, duplicate: % PRIu64 pages\n,
info-ram-duplicate);
+monitor_printf(mon, skipped: % PRIu64 pages\n,
+ info-ram-skipped);
monitor_printf(mon, normal: % PRIu64 pages\n,
info-ram-normal);
monitor_printf(mon, normal bytes: % PRIu64 kbytes\n,
diff --git a/include/migration/migration.h b/include/migration/migration.h
index bb617fd..e2acec6 100644
--- a/include/migration/migration.h
+++ b/include/migration/migration.h
@@ -96,6 +96,8 @@ extern SaveVMHandlers savevm_ram_handlers;
uint64_t dup_mig_bytes_transferred(void);
uint64_t dup_mig_pages_transferred(void);
+uint64_t skipped_mig_bytes_transferred(void);
+uint64_t skipped_mig_pages_transferred(void);
uint64_t norm_mig_bytes_transferred(void);
uint64_t norm_mig_pages_transferred(void);
uint64_t xbzrle_mig_bytes_transferred(void);
diff --git a/migration.c b/migration.c
index 185d112..7fb2147 100644
--- a/migration.c
+++ b/migration.c
@@ -197,11 +197,11 @@ MigrationInfo *qmp_query_migrate(Error **errp)
info-ram-remaining = ram_bytes_remaining();
info-ram-total = ram_bytes_total();
info-ram-duplicate = dup_mig_pages_transferred();
+info-ram-skipped = skipped_mig_pages_transferred();
info-ram-normal = norm_mig_pages_transferred();
info-ram-normal_bytes = norm_mig_bytes_transferred();
info-ram-dirty_pages_rate = s-dirty_pages_rate;
-
if (blk_mig_active()) {
info-has_disk = true;
info-disk = g_malloc0(sizeof(*info-disk));
@@ -227,6 +227,7 @@ MigrationInfo *qmp_query_migrate(Error **errp)
info-ram-remaining = 0;
info-ram-total = ram_bytes_total();
info-ram-duplicate = dup_mig_pages_transferred();
+info-ram-skipped = skipped_mig_pages_transferred();
info-ram-normal = norm_mig_pages_transferred();
info-ram-normal_bytes = norm_mig_bytes_transferred();
break;
diff --git a/qapi-schema.json b/qapi-schema.json
index fdaa9da..b737460 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@
Re: [Qemu-devel] [PATCH 14/42] migration: prepare to access s-state outside critical sections
On Fri, Feb 22, 2013 at 5:36 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Accessing s-state outside the big QEMU lock will simplify a bit the
locking/unlocking of the iothread lock.
We need to keep the lock in migrate_fd_error and migrate_fd_completed,
however, because they call migrate_fd_cleanup.
Reviewed-by: Orit Wasserman owass...@redhat.com
Reviewed-by: Juan Quintela quint...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
migration.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/migration.c b/migration.c
index b091532..b40755f 100644
--- a/migration.c
+++ b/migration.c
@@ -279,19 +279,25 @@ static void migrate_fd_cleanup(MigrationState *s)
notifier_list_notify(migration_state_notifiers, s);
}
+static void migrate_finish_set_state(MigrationState *s, int new_state)
+{
+if (__sync_val_compare_and_swap(s-state, MIG_STATE_ACTIVE,
kraxel_rhel61's mingw build fails:
LINK i386-softmmu/qemu-system-i386.exe
../migration.o:migration.c:(.text+0x408): undefined reference to
`__sync_val_compare_and_swap_4'
../migration.o:migration.c:(.text+0x7af): undefined reference to
`__sync_val_compare_and_swap_4'
../migration.o:migration.c:(.text+0x827): undefined reference to
`__sync_val_compare_and_swap_4'
http://buildbot.b1-systems.de/qemu/builders/default_mingw32/builds/566/steps/compile/logs/stdio
The latest RHEL6 mingw gcc is version 4.4 but this buildslave is
RHEL6.1 so perhaps it's an older version that is missing the atomics
builtins?
Stefan
Re: [Qemu-devel] qxl: qxl's event named QXL_INTERRUPT_DISPLAY
Hi, I'm learning about qxl device in KVM VM. I got a problem and asks
for help. Thanks.
The qemu's command is:
qemu-system-x86_64 -spice port=5900,disable-ticketing -vga
qxl
--enable-kvm ...
The code in function 'interface_get_command' is followed:
SPICE_RING_POP(ring, notify);
if (notify) {
qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
}
What is the meaning about 'QXL_INTERRUPT_DISPLAY' ?
Does it means sending a 'QXL_INTERRUPT_DISPLAY' irq to vm?
Yes.
If so, what's the irq's handler?
It's in the driver code:
http://cgit.freedesktop.org/~airlied/linux/tree/drivers/gpu/drm/qxl/qxl_irq.c?h=qxl-upstreamid=1a401a749cb1f06e637ef0e91fb8c120963aa356#n28
Thanks.
Re: [Qemu-devel] [PATCH 02/10] versatile_pci: Expose PCI I/O region on Versatile PB
On 25 March 2013 01:01, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
On Sun, Mar 24, 2013 at 9:32 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
Comments in the QEMU source code claim that the version of the PCI
controller on the VersatilePB board doesn't support the PCI I/O
region, but this is incorrect; expose that region, map it in the
correct location, and drop the misleading comments.
This change removes the only currently implemented difference
between the realview-pci and versatile-pci models; however there
are other differences in not-yet-implemented functionality, so we
retain the distinction between the two device types.
@@ -85,10 +85,8 @@ static int pci_vpb_init(SysBusDevice *dev)
memory_region_init_io(s-mem_config2, pci_vpb_config_ops, bus,
pci-vpb-config, 0x100);
sysbus_init_mmio(dev, s-mem_config2);
-if (s-realview) {
This is the one and only usage of -realview. I wonder if this
argument is flawed - in real hardware is there any functional
difference between realview and versatile PCI requiring the level of
heirachy defined here?
Please read the commit message and the later patches in the series :-)
thanks
-- PMM
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 03/25/13 10:32, Jan Kiszka wrote: On 2013-03-25 10:10, Gerd Hoffmann wrote: On 03/25/13 09:40, Jan Kiszka wrote: On 2013-03-25 09:39, Gerd Hoffmann wrote: Hi, Any hints in the X server log? vmwlegacy(0): Weight given (565) is inconsistent with the depth (24) Weight hints depth 16 indeed. What depth used the server to run at? 16 or 24? 24 As expected. Puzzling where the 565 weight comes from ... Can you apply the attached patch, enable vmware_* + displaysurface_* tracepoints + send a log? [shrinking CC list at this chance] Hmm, no displaysurface_* tracepoints? read: index 1, value 0x0 read: index 2, value 0x320 read: index 3, value 0x258 800x600 read: index 7, value 0x20 4 bytes per pixel read: index 9, value 0xf800 read: index 10, value 0x7e0 read: index 11, value 0x1f 16bpp r/g/b masks. Hmm. No attempt to initialize the display (set res etc). Maybe because the x11 server driver errors out early. The 800x600 video mode was probably set from vgabios. That doesn't explain the inconsistency though. Do you boot with vesafb enabled? Which video mode? Probably 800x600? What depth? cheers, Gerd
Re: [Qemu-devel] [PATCH 14/42] migration: prepare to access s-state outside critical sections
Hi, http://buildbot.b1-systems.de/qemu/builders/default_mingw32/builds/566/steps/compile/logs/stdio The latest RHEL6 mingw gcc is version 4.4 but this buildslave is RHEL6.1 so perhaps it's an older version that is missing the atomics builtins? No, it's RHEL-6.4 actually, even though the name suggests otherwise (was a bad idea to include the minor rev in the buildslave name ...). There is a detailed slave info page btw: http://buildbot.b1-systems.de/qemu/buildslaves/kraxel_rhel61 cheers, Gerd
Re: [Qemu-devel] [PATCH 1/8] RFC: chardev frontend open handling cleanup
This patch-series is the result of the [PATCH 1/2] char: add qemu_chr_be_is_fe_connected discussion thread. This patch series (tries to) make(s) the frontend open concept both more explicit and generic, and significantly cleans up the surrounding code. The whole patch series looks good to me. Regards, Hans
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 2013-03-25 10:48, Gerd Hoffmann wrote: On 03/25/13 10:32, Jan Kiszka wrote: On 2013-03-25 10:10, Gerd Hoffmann wrote: On 03/25/13 09:40, Jan Kiszka wrote: On 2013-03-25 09:39, Gerd Hoffmann wrote: Hi, Any hints in the X server log? vmwlegacy(0): Weight given (565) is inconsistent with the depth (24) Weight hints depth 16 indeed. What depth used the server to run at? 16 or 24? 24 As expected. Puzzling where the 565 weight comes from ... Can you apply the attached patch, enable vmware_* + displaysurface_* tracepoints + send a log? [shrinking CC list at this chance] Hmm, no displaysurface_* tracepoints? Setting up a full trace was a bit too unhandy (it still lacks some ad-hoc configuration). If you need it, I'll redo. read: index 1, value 0x0 read: index 2, value 0x320 read: index 3, value 0x258 800x600 read: index 7, value 0x20 4 bytes per pixel read: index 9, value 0xf800 read: index 10, value 0x7e0 read: index 11, value 0x1f 16bpp r/g/b masks. Hmm. No attempt to initialize the display (set res etc). Maybe because the x11 server driver errors out early. The 800x600 video mode was probably set from vgabios. That doesn't explain the inconsistency though. Do you boot with vesafb enabled? Which video mode? Probably 800x600? What depth? I'm booting with vga=0x314. Jan signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCHv4 2/9] cutils: add a function to find non-zero content in a buffer
On 03/25/2013 11:42 AM, Paolo Bonzini wrote:
+size_t buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+VECTYPE *p = (VECTYPE *)buf;
+VECTYPE zero = ZERO_SPLAT;
+size_t i;
+
+assert(len % (BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR
+* sizeof(VECTYPE)) == 0);
+assert(((uintptr_t) buf) % sizeof(VECTYPE) == 0);
+
+if (*((const long *) buf)) {
+return 0;
+}
+
+for (i = 0; i len / sizeof(VECTYPE);
Why not put len/sizeof(VECTYPE) in a variable?
are you afraid that there is a division at each iteration?
sizeof(VECTYPE) is a power of 2 so i think the compiler will
optimize it
to a at compile time.
true, but it still is done every iteration.
len is an invariant, the compiler will move it out of the loop
automatically. Write readable code unless you have good clues
that it is also slow.
I know it does for x86 but I wasn't sure for other platforms.
I'm fine with as is.
Orit
Paolo
Re: [Qemu-devel] [PATCHv4 8/9] migration: do not search dirty pages in bulk stage
On 03/22/2013 02:46 PM, Peter Lieven wrote:
avoid searching for dirty pages just increment the
page offset. all pages are dirty anyway.
Signed-off-by: Peter Lieven p...@kamp.de
Reviewed-by: Eric Blake ebl...@redhat.com
---
arch_init.c |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch_init.c b/arch_init.c
index c34a4af..b2b932a 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -338,7 +338,13 @@ ram_addr_t
migration_bitmap_find_and_reset_dirty(MemoryRegion *mr,
unsigned long nr = base + (start TARGET_PAGE_BITS);
unsigned long size = base + (int128_get64(mr-size) TARGET_PAGE_BITS);
-unsigned long next = find_next_bit(migration_bitmap, size, nr);
+unsigned long next;
+
+if (ram_bulk_stage nr base) {
+next = nr + 1;
+} else {
+next = find_next_bit(migration_bitmap, size, nr);
+}
if (next size) {
clear_bit(next, migration_bitmap);
Reviewed-by: Orit Wasserman owass...@redhat.com
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
On 2013-03-25 10:55, Jan Kiszka wrote: On 2013-03-25 10:48, Gerd Hoffmann wrote: On 03/25/13 10:32, Jan Kiszka wrote: On 2013-03-25 10:10, Gerd Hoffmann wrote: On 03/25/13 09:40, Jan Kiszka wrote: On 2013-03-25 09:39, Gerd Hoffmann wrote: Hi, Any hints in the X server log? vmwlegacy(0): Weight given (565) is inconsistent with the depth (24) Weight hints depth 16 indeed. What depth used the server to run at? 16 or 24? 24 As expected. Puzzling where the 565 weight comes from ... Can you apply the attached patch, enable vmware_* + displaysurface_* tracepoints + send a log? [shrinking CC list at this chance] Hmm, no displaysurface_* tracepoints? Setting up a full trace was a bit too unhandy (it still lacks some ad-hoc configuration). If you need it, I'll redo. Ah, just found one, though I'm unsure if it is intended to work like this: -trace events=., then trace-event vmware*/display* on from the monitor. [5424.260045] displaysurface_create surface=0x7ff3158c33b0, 720x400 [5424.260332] displaysurface_free surface=0x7ff3158f6250 [5425.580115] displaysurface_create_from surface=0x7ff315d3df40, 800x600, bpp 16, bswap 0 [5425.580257] displaysurface_free surface=0x7ff3158c33b0 [5431.993087] vmware_value_read index 1, value 0x0 [5431.993147] vmware_value_read index 2, value 0x320 [5431.993165] vmware_value_read index 3, value 0x258 [5431.993180] vmware_value_read index 7, value 0x20 [5431.993196] vmware_value_read index 0, value 0x9002 [5431.993211] vmware_value_read index 20, value 0x0 [5431.993226] vmware_value_write index 0, value 0x9002 [5431.993240] vmware_value_read index 0, value 0x9002 [5431.993256] vmware_value_read index 17, value 0x3 [5431.993272] vmware_value_read index 28, value 0x20 [5431.993287] vmware_value_read index 6, value 0x20 [5431.993301] vmware_value_read index 15, value 0x100 [5431.993317] vmware_value_read index 13, value 0xfd00 [5431.99] vmware_value_read index 4, value 0x938 [5431.993348] vmware_value_read index 5, value 0x6ea [5431.993465] vmware_value_read index 9, value 0xf800 [5431.993486] vmware_value_read index 10, value 0x7e0 [5431.993502] vmware_value_read index 11, value 0x1f [5431.993517] vmware_value_read index 8, value 0x0 [5432.270084] displaysurface_create_from surface=0x7ff3158f6250, 800x600, bpp 16, bswap 0 [5432.270156] displaysurface_free surface=0x7ff315d3df40 [5433.467540] vmware_value_read index 1, value 0x0 [5433.467584] vmware_value_read index 2, value 0x320 [5433.467621] vmware_value_read index 3, value 0x258 [5433.467637] vmware_value_read index 7, value 0x20 [5433.467652] vmware_value_read index 0, value 0x9002 [5433.467667] vmware_value_read index 20, value 0x0 [5433.467681] vmware_value_write index 0, value 0x9002 [5433.467695] vmware_value_read index 0, value 0x9002 [5433.467713] vmware_value_read index 17, value 0x3 [5433.467727] vmware_value_read index 28, value 0x20 [5433.467742] vmware_value_read index 6, value 0x20 [5433.467757] vmware_value_read index 15, value 0x100 [5433.467772] vmware_value_read index 13, value 0xfd00 [5433.467786] vmware_value_read index 4, value 0x938 [5433.467801] vmware_value_read index 5, value 0x6ea [5433.467934] vmware_value_read index 9, value 0xf800 [5433.467957] vmware_value_read index 10, value 0x7e0 [5433.467977] vmware_value_read index 11, value 0x1f [5433.467993] vmware_value_read index 8, value 0x0 [5433.470111] displaysurface_create_from surface=0x7ff315d3df40, 800x600, bpp 16, bswap 0 [5433.470171] displaysurface_free surface=0x7ff3158f6250 [5433.650177] displaysurface_create_from surface=0x7ff315c41750, 800x600, bpp 16, bswap 0 [5433.650231] displaysurface_free surface=0x7ff315d3df40 [5434.710649] vmware_value_read index 1, value 0x0 [5434.710690] vmware_value_read index 2, value 0x320 [5434.710713] vmware_value_read index 3, value 0x258 [5434.710735] vmware_value_read index 7, value 0x20 ... Jan signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH v2] net: increase buffer size to accommodate Jumbo frame pkts
On Mon, Mar 18, 2013 at 11:43:44AM -0700, sfel...@cumulusnetworks.com wrote: From: Scott Feldman sfel...@cumulusnetworks.com Socket buffer sizes were hard-coded to 4K for VDE and socket netdevs. Bump this up to 68K (ala tap netdev) to handle maximum GSO packet size (64k) plus plenty of room for the ethernet and virtio_net headers. Originally, ran into this limitation when using -netdev UDP sockets to connect VM-to-VM, where VM interface is configure with MTU=9000. (Using virtio_net NIC model). Test is simple: ping -M do -s 8500 target. This test will attempt to ping with unfragmented packet of given size. Without patch, size is limited to 4K (minus protocol hdrs). With patch, ping test works with pkt size up to 9000 (again, minus protocol hdrs). v2: per Stefan, increase buf size to (4096+65536) as done in tap and apply to vde and socket netdevs. v1: increase buf size to 12K just for -netdev UDP sockets Signed-off-by: Scott Feldman sfel...@cumulusnetworks.com --- include/net/net.h |5 + net/net.c |2 +- net/socket.c |4 ++-- net/tap.c |7 +-- net/vde.c |2 +- 5 files changed, 10 insertions(+), 10 deletions(-) Thanks, applied to my net tree: https://github.com/stefanha/qemu/commits/net Stefan
Re: [Qemu-devel] [PATCHv4 9/9] migration: use XBZRLE only after bulk stage
On 03/22/2013 02:46 PM, Peter Lieven wrote:
at the beginning of migration all pages are marked dirty and
in the first round a bulk migration of all pages is performed.
currently all these pages are copied to the page cache regardless
of whether they are frequently updated or not. this doesn't make sense
since most of these pages are never transferred again.
this patch changes the XBZRLE transfer to only be used after
the bulk stage has been completed. that means a page is added
to the page cache the second time it is transferred and XBZRLE
can benefit from the third time of transfer.
since the page cache is likely smaller than the number of pages
it's also likely that in the second round the page is missing in the
cache due to collisions in the bulk phase.
on the other hand a lot of unnecessary mallocs, memdups and frees
are saved.
the following results have been taken earlier while executing
the test program from docs/xbzrle.txt. (+) with the patch and (-)
without. (thanks to Eric Blake for reformatting and comments)
+ total time: 22185 milliseconds
- total time: 22410 milliseconds
Shaved 0.3 seconds, better than 1%!
+ downtime: 29 milliseconds
- downtime: 21 milliseconds
Not sure why downtime seemed worse, but probably not the end of the world.
+ transferred ram: 706034 kbytes
- transferred ram: 721318 kbytes
Fewer bytes sent - good.
+ remaining ram: 0 kbytes
- remaining ram: 0 kbytes
+ total ram: 1057216 kbytes
- total ram: 1057216 kbytes
+ duplicate: 108556 pages
- duplicate: 105553 pages
+ normal: 175146 pages
- normal: 179589 pages
+ normal bytes: 700584 kbytes
- normal bytes: 718356 kbytes
Fewer normal bytes...
+ cache size: 67108864 bytes
- cache size: 67108864 bytes
+ xbzrle transferred: 3127 kbytes
- xbzrle transferred: 630 kbytes
...and more compressed pages sent - good.
+ xbzrle pages: 117811 pages
- xbzrle pages: 21527 pages
+ xbzrle cache miss: 18750
- xbzrle cache miss: 179589
And very good improvement on the cache miss rate.
+ xbzrle overflow : 0
- xbzrle overflow : 0
Signed-off-by: Peter Lieven p...@kamp.de
Reviewed-by: Eric Blake ebl...@redhat.com
---
arch_init.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch_init.c b/arch_init.c
index b2b932a..86f7e28 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -464,7 +464,7 @@ static int ram_save_block(QEMUFile *f, bool last_stage)
acct_info.skipped_pages++;
bytes_sent = 0;
}
-} else if (migrate_use_xbzrle()) {
+} else if (!ram_bulk_stage migrate_use_xbzrle()) {
current_addr = block-offset + offset;
bytes_sent = save_xbzrle_page(f, p, current_addr, block,
offset, cont, last_stage);
Reviewed-by: Orit Wasserman owass...@redhat.com
Re: [Qemu-devel] [PATCH 02/10] versatile_pci: Expose PCI I/O region on Versatile PB
On 25 March 2013 09:47, Peter Maydell peter.mayd...@linaro.org wrote: On 25 March 2013 01:01, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote: This is the one and only usage of -realview. I wonder if this argument is flawed - in real hardware is there any functional difference between realview and versatile PCI requiring the level of heirachy defined here? Please read the commit message and the later patches in the series :-) Er, and to be slightly more helpful, the following things differ between versatilepb and realview: * behaviour of IMAP registers * memory window sizes * IRQ mapping and some things we don't yet implement: * SMAP register behaviour * PCI_FLAGS register bits seem to be a little different -- PMM
Re: [Qemu-devel] [PATCHv4 0/9] buffer_is_zero / migration optimizations
On 22.03.2013 22:24, Paolo Bonzini wrote:
Il 22/03/2013 20:20, Peter Lieven ha scritto:
I think patch 4 is a bit overengineered. I would prefer the simple
patch you had using three/four non-vectorized accesses. The setup cost
of the vectorized buffer_is_zero is quite high, and 64 bits are just
256k RAM; if the host doesn't touch 256k RAM, it will incur the overhead.
I think you are right. I was a little to eager to utilize
buffer_find_nonzero_offset()
as much as possible. The performance gain by unrolling was impressive enough.
The gain by the vector functions is not that big that it would justify a
possible
slow down by the high setup costs. My testings revealed that in most cases
buffer_find_nonzero_offset()
returns 0 or a big offset. All the 0 return values would have increased setup
costs with
the vectorized version of patch 4.
I would prefer some more benchmarking for patch 5, but it looks ok.
What would you like to see? Statistics how many pages of a real system
are not zero, but zero in the first sizeof(long) bytes?
Yeah, more or less. Running the system for a while, migrating, and
plotting a histogram of the return values of buffer_find_nonzero_offset
(hmm, perhaps using a nonvectorized version is better for this experiment).
It seems that Paolos concern regarding only checking the first 64-bit where
right. What I would propose is
to check the first BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR * sizeof(VECTYPE)
bytes in
sizeof(VECTYPE) chunks and use the unrolled version afterwards.
basically this would result in sth like this:
size_t buffer_find_nonzero_offset(const void *buf, size_t len)
{
VECTYPE *p = (VECTYPE *)buf;
VECTYPE zero = ZERO_SPLAT;
size_t i;
assert(can_use_buffer_find_nonzero_offset(buf, len));
if (!len) {
return 0;
}
for (i = 0; i BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR; i++) {
if (!ALL_EQ(p[i], zero)) {
return 0;
}
}
for (i = BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR;
i len / sizeof(VECTYPE);
i += BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR) {
VECTYPE tmp0 = p[i + 0] | p[i + 1];
VECTYPE tmp1 = p[i + 2] | p[i + 3];
VECTYPE tmp2 = p[i + 4] | p[i + 5];
VECTYPE tmp3 = p[i + 6] | p[i + 7];
VECTYPE tmp01 = tmp0 | tmp1;
VECTYPE tmp23 = tmp2 | tmp3;
if (!ALL_EQ(tmp01 | tmp23, zero)) {
break;
}
}
return i * sizeof(VECTYPE);
}
this version is approx. 1-2% slower than the first one, but still 15% faster
than old is_dup_page() for zero pages.
BUT, if the first 8 bytes are zero and afterwards non-zero, the first version
is approx. 200% slower due to
the high setup costs.
Paolo, with this one maybe you would also be fine witht he vectorized version
of patch 4?
Peter
---
here are the results of the tests with the return values of
buffer_find_nonzero_offset (64-bit chunks):
ubuntu 12.04 LTS 64-bit desktop with 1G memory shortly after boot:
return values: 83905 3281 1169 448 412 212 284 180 146 93 54 77 64 44 48 50 68 46 28 62 40 81 34 69 52 47 31 21 35 29 39 24 83 43 22 17 10 37 30 10 17 23 12 12 12 17 9 23 12 20 2 9 22 16 16 64 15 39 8 9 7 12 8 10 10 13 8 12 58 10 7 8 18 18 10 12 11 6 9 16
9 60 5 6 7 7 5 12 98 32 7 9 4 11 7 6 11 4 11 45 7 19 4 6 6 13 5 8 5 14 7 5 11 6 3 8 12 8 3 12 10 23 11 5 9 3 10 13 46 6 2 14 7 7 4 11 9 4 1 9 5 10 4 6 14 62 5 10 106 6 7 7 6 26 3 34 80 8 12 12 8 5 2 6 7 14 5 8 8 8 7 3 6 16 4 13 16 9 4 14 6 22 14 15 6 25 4
12 6 6 3 7 13 11 5 11 3 11 8 5 16 12 2 5 3 8 4 3 11 62 147 9 54 20 14 3 5 28 12 3 6 5 7 2 9 9 10 8 11 4 4 6 10 7 20 5 4 1 6 9 6 7 9 2 2 6 5 10 3 23 5 13 6 7 20 11 12 15 17 2 4 2 3 25 2 6 3 15 4 6 5 30 15 9 4 28 3 4 6 5 6 18 7 2 9 2 2 9 8 11 8 1 4 5 4 4 2
4 6 75 9 8 6 5 3 6 3 6 15 5 5 5 6 20 6 10 7 9 6 4 9 5 6 6 9 7 5 5 5 4 4 1 46 6 10 10 92 4 7 3 3 32 6 7 34 30 2 8 2 7 8 5 9 8 4 21 9 9 12 5 12 5 3 5 5 5 65 4 4 67 7 7 5 8 7 1 3 3 5 7 4 7 7 7 15 15 8 11 5 6 2 7 12 6 5 9 13 2 19 6 2 8 3 11 8 9 38 1 7 1 20 11
5 7 1 4 6 5 4 2 2 7 5 5 2 51 5 4 9 7 4 16 3 67 7 45 9 8 9 12 38 11 6 14 2 2 10 10 6 10 4 9 9 5 4 7 2 8 7 4 5 1 2 2 6 3 5 4 7 0 2 6 5 13 5 5 4 11 4 4 9 4 2 8 10 5 6 10 6 4 2 2 6 4 6 3 4 7 5 7 0 6 4 5 4 1 8 11 15 15 14 20 168432
histogram: 31.7% 32.9% 33.3% 33.5% 33.7% 33.7% 33.9% 33.9% 34.0% 34.0% 34.0% 34.1% 34.1% 34.1% 34.1% 34.1% 34.2% 34.2% 34.2% 34.2% 34.2% 34.3% 34.3% 34.3% 34.3% 34.3% 34.3% 34.4% 34.4% 34.4% 34.4% 34.4% 34.4% 34.5% 34.5% 34.5% 34.5% 34.5% 34.5% 34.5%
34.5% 34.5% 34.5% 34.5% 34.5% 34.5% 34.5% 34.5% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.6% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.7% 34.8%
34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.8% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9% 34.9%
[Qemu-devel] virsh resume/qemu loadvm (from disk) latency
Dear all, why does the resume time depend on the maximum amount of memory the instance is configured with? For a dump size of 500 MB resuming the instance takes 2/3/5 seconds for a virtual machine configured with 1/2/4 GB of RAM. I measure the time it takes for the 'virsh restore file' command to return. The numbers were collected on a Ubuntu 12.04 machine with kvm 1.0 and libvirt 0.9.8. I would be interested in ways to cut the baseline overhead, i.e., the resume time should depend on the dump size and not on the maximum configured RAM size. At least not in the extend it does now (1 second increase in resume time per GB). Thanks, Thomas.
Re: [Qemu-devel] [PATCH 16/18] console: stop using DisplayState in gfx hardware emulation
Hi, [5425.580115] displaysurface_create_from surface=0x7ff315d3df40, 800x600, bpp 16, bswap 0 [5425.580257] displaysurface_free surface=0x7ff3158c33b0 This is vga=0x314 Looks like we have some funky interaction between vga and vmware. I'll go dig. Meanwhile you can try vga=0x315 (800x600x24) or vga=normal (textmode), that has a high chance to workaround this. cheers, Gerd
Re: [Qemu-devel] [PATCHv4 0/9] buffer_is_zero / migration optimizations
ubuntu 12.04 LTS 64-bit desktop with 1G memory shortly after boot: histogram: 31.7% 32.9% [...] 36.4% 100.0% --- opensuse 11.1 64-bit with 24GB ram (busy server) histogram: 97.5% 97.9% [...] 99.5% 100.0% --- windows server 2008 R2 with 8G ram running for 3 days: histogram: 20.9% 21.3% [...] 22.5% 100.0% --- windows XP guest with 1G Ram running for approx. 1 hours histogram: 25.6% [...] 35.8% 100.0% Doesn't this suggest checking the first _and the last_ word, and using the vectorized loop if none is zero? Paolo
[Qemu-devel] [PATCH 2/2] block: Add options QDict to bdrv_file_open() prototypes (fix MinGW build)
From: Stefan Weil s...@weilnetz.de
The new parameter is unused yet.
This part was missing in commit 787e4a8500020695eb391e2f1cc4767ee071d441.
Cc: Kevin Wolf kw...@redhat.com
Cc: Eric Blake ebl...@redhat.com
Signed-off-by: Stefan Weil s...@weilnetz.de
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
block/raw-win32.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/block/raw-win32.c b/block/raw-win32.c
index 18e0068..ece2f1a 100644
--- a/block/raw-win32.c
+++ b/block/raw-win32.c
@@ -221,7 +221,8 @@ static void raw_parse_flags(int flags, int *access_flags,
DWORD *overlapped)
}
}
-static int raw_open(BlockDriverState *bs, const char *filename, int flags)
+static int raw_open(BlockDriverState *bs, const char *filename,
+QDict *options, int flags)
{
BDRVRawState *s = bs-opaque;
int access_flags;
@@ -494,7 +495,8 @@ static int hdev_probe_device(const char *filename)
return 0;
}
-static int hdev_open(BlockDriverState *bs, const char *filename, int flags)
+static int hdev_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRawState *s = bs-opaque;
int access_flags, create_flags;
--
1.8.1.4
Re: [Qemu-devel] [PATCH 14/42] migration: prepare to access s-state outside critical sections
- Messaggio originale - Da: Gerd Hoffmann kra...@redhat.com A: Stefan Hajnoczi stefa...@gmail.com Cc: Paolo Bonzini pbonz...@redhat.com, qemu-devel qemu-devel@nongnu.org, Orit Wasserman owass...@redhat.com, Juan Quintela quint...@redhat.com Inviato: Lunedì, 25 marzo 2013 10:52:36 Oggetto: Re: [Qemu-devel] [PATCH 14/42] migration: prepare to access s-state outside critical sections Hi, http://buildbot.b1-systems.de/qemu/builders/default_mingw32/builds/566/steps/compile/logs/stdio The latest RHEL6 mingw gcc is version 4.4 but this buildslave is RHEL6.1 so perhaps it's an older version that is missing the atomics builtins? No, it's RHEL-6.4 actually, even though the name suggests otherwise (was a bad idea to include the minor rev in the buildslave name ...). Can you check if this fixes it? diff --git a/configure b/configure index 46a7594..a324ca5 100755 --- a/configure +++ b/configure @@ -931,9 +931,9 @@ case $cpu in LDFLAGS=-m64 $LDFLAGS ;; i386) - QEMU_CFLAGS=-m32 $QEMU_CFLAGS - LDFLAGS=-m32 $LDFLAGS - cc_i386='$(CC) -m32' + QEMU_CFLAGS=-m32 -mcpu=i486 $QEMU_CFLAGS + LDFLAGS=-m32 -mcpu=i486 $LDFLAGS + cc_i386='$(CC) -m32 -mcpu=i486' ;; x86_64) QEMU_CFLAGS=-m64 $QEMU_CFLAGS Paolo
[Qemu-devel] [PULL 0/2] Block patches
This tiny pull request contains build fixes for a regression introduced in the last pull request. Kevin and I investigated to find out why these build failures were missed. Both my buildslave and Kevin's workstation did not have the rbd libraries installed so block/rbd.c was not built. The buildslave now has the missing libraries and will warn us if block/rbd.c breaks again. Kevin has also installed the package so his local builds exercise the code. The mingw build is already failing in buildbot due to an unrelated issue. The bdrv_file_open() prototype warning was not spotted amongst all the other warnings. The following changes since commit fe6344a05fba26e16863fefcb823242e579b0991: Remove device_tree.o from hw/moxie/Makefile.objs. (2013-03-24 11:30:04 +0100) are available in the git repository at: git://github.com/stefanha/qemu.git block for you to fetch changes up to ea804cadf867a0521b9069193db339d041a40689: block: Add options QDict to bdrv_file_open() prototypes (fix MinGW build) (2013-03-25 09:53:04 +0100) Liu Yuan (1): rbd: fix compile error Stefan Weil (1): block: Add options QDict to bdrv_file_open() prototypes (fix MinGW build) block/raw-win32.c | 6 -- block/rbd.c | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) -- 1.8.1.4
[Qemu-devel] [PATCH 1/2] rbd: fix compile error
From: Liu Yuan tailai...@taobao.com
Commit 787e4a85 [block: Add options QDict to bdrv_file_open() prototypes] didn't
update rbd.c accordingly.
Cc: Kevin Wolf kw...@redhat.com
Cc: Stefan Hajnoczi stefa...@redhat.com
Signed-off-by: Liu Yuan tailai...@taobao.com
Reviewed-by: Stefan Weil s...@weilnetz.de
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
block/rbd.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/block/rbd.c b/block/rbd.c
index 8cd10a7..1a8ea6d 100644
--- a/block/rbd.c
+++ b/block/rbd.c
@@ -441,7 +441,8 @@ static int qemu_rbd_aio_flush_cb(void *opaque)
return (s-qemu_aio_count 0);
}
-static int qemu_rbd_open(BlockDriverState *bs, const char *filename, int flags)
+static int qemu_rbd_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRBDState *s = bs-opaque;
char pool[RBD_MAX_POOL_NAME_SIZE];
--
1.8.1.4
Re: [Qemu-devel] [PATCHv4 0/9] buffer_is_zero / migration optimizations
Am 25.03.2013 um 11:53 schrieb Paolo Bonzini pbonz...@redhat.com: ubuntu 12.04 LTS 64-bit desktop with 1G memory shortly after boot: histogram: 31.7% 32.9% [...] 36.4% 100.0% --- opensuse 11.1 64-bit with 24GB ram (busy server) histogram: 97.5% 97.9% [...] 99.5% 100.0% --- windows server 2008 R2 with 8G ram running for 3 days: histogram: 20.9% 21.3% [...] 22.5% 100.0% --- windows XP guest with 1G Ram running for approx. 1 hours histogram: 25.6% [...] 35.8% 100.0% Doesn't this suggest checking the first _and the last_ word, and using the vectorized loop if none is zero? Maybe I should have explained the output more detailed. The percentages are added. 35.8% in the second last column means that 35.8% have a return value that is less than TARGET_PAGE_SIZE. This was meant to illustrate at how many 64-bit chunks you have to look to grab a certain percentage of non-zero pages. 25.6% 26.1% 34.0% 34.1% 34.2% 34.3% 34.3% 34.4% 34.4% 34.4% 34.5% 34.5% 34.5% [...] 35.8% 100% Looking e.g. at the third value it means that looking at the first three 64-bit chunks it will catch 34.0% of all pages. It turns out that the non-zeroness of a page can be detected looking at the first 256 or so bits and only a low percentage turns out to be non-zero at a later position. So after having checked the first chunks one by one there is no big penalty looking at the remaining chunks with the vectorized loop. Here is the distribution of return values for the Windows XP example: 25.62% 0.49% 7.86% 0.12% 0.15% 0.05% 0.05% 0.04% 0.05% 0.02% 0.03% 0.02% 0.03% 0.02% 0.02% 0.01% 0.03% 0.02% 0.01% 0.02% 0.02% 0.01% 0.02% 0.01% 0.01% 0.01% 0.01% 0.01% 0.02% 0.00% 0.01% 0.02% 0.03% 0.01% 0.01% 0.01% 0.01% 0.01% 0.01% 0.00% 0.00% 0.01% 0.07% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.01% 0.02% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.02% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.03% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.02% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.02% 0.00% 0.00% 0.02% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.01% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 64.23% The last value is the percentage of return value of TARGET_PAGE_SIZE meaning the page is all zero. Peter
Re: [Qemu-devel] [PATCHv2 0/6] ARM dump-guest-memory support
Hi, Am 24.03.2013 18:27, schrieb Rabin Vincent: A second patchset to add dump-guest-memory support for ARM. This version of the patchset addresses the following comments from the previous posting, and also adds some more patches to the core dump code (patch #4 and #6): - memset prstatus to 0 in x86_64_write_elf64_note() - handle big endian in dump_write_elf_note() - Save CPSR in ARM prstatus - set correct ELF endianness for ARM BE This still does not address the architectural issue that I brought up. That would affect the equivalent s390x patch as well. Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PULL 0/2] Block patches
On Mon, Mar 25, 2013 at 12:00:47PM +0100, Stefan Hajnoczi wrote: This tiny pull request contains build fixes for a regression introduced in the last pull request. Kevin and I investigated to find out why these build failures were missed. Both my buildslave and Kevin's workstation did not have the rbd libraries installed so block/rbd.c was not built. The buildslave now has the missing libraries and will warn us if block/rbd.c breaks again. Kevin has also installed the package so his local builds exercise the code. The mingw build is already failing in buildbot due to an unrelated issue. The bdrv_file_open() prototype warning was not spotted amongst all the other warnings. The following changes since commit fe6344a05fba26e16863fefcb823242e579b0991: Remove device_tree.o from hw/moxie/Makefile.objs. (2013-03-24 11:30:04 +0100) are available in the git repository at: git://github.com/stefanha/qemu.git block for you to fetch changes up to ea804cadf867a0521b9069193db339d041a40689: block: Add options QDict to bdrv_file_open() prototypes (fix MinGW build) (2013-03-25 09:53:04 +0100) Tested, and this fixes the build failure of rbd for me. Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones virt-top is 'top' for virtual machines. Tiny program with many powerful monitoring features, net stats, disk stats, logging, etc. http://people.redhat.com/~rjones/virt-top
Re: [Qemu-devel] [PATCH] Introduce query-cpu-max QMP command and cpu_max HMP counterpart
On 03/21/2013 01:51 PM, Luiz Capitulino wrote: On Tue, 12 Mar 2013 17:03:31 +0100 Michal Novotny minov...@redhat.com wrote: This is the patch to introduce the query-cpu-max QMP command to get the maximum number of CPUs supported by the currently running emulator instance. This may differ machine from machine as defined by -machine settings and max_cpus member of QEMUMachine structure. It's been tested both using QMP/qmp utility and telnet session on the QEMU session. Patch looks good, but it doesn't build. See below. Thanks! I've rebased but I don't know why it didn't apply before. I sent v2 to the list about a minute ago with Markus' comments taken in account (thanks Markus!). Everything compiled fine for all archs and it's been tested for x86_64 and ARM architectures (Raspbian ARM image is the only one for non-x86 arch I have on my laptop). Thanks, Michal -- Michal Novotny minov...@redhat.com, RHCE, Red Hat Virtualization | libvirt-php bindings | php-virt-control.org
Re: [Qemu-devel] Abort in monitor_puts.
On Mon, 25 Mar 2013 08:42:57 +0100 Gerd Hoffmann kra...@redhat.com wrote: On 03/22/13 22:39, Luiz Capitulino wrote: On Fri, 22 Mar 2013 16:50:39 -0400 Luiz Capitulino lcapitul...@redhat.com wrote: On Fri, 22 Mar 2013 10:17:58 +0100 KONRAD Frédéric fred.kon...@greensocs.com wrote: Hi, Seems there is an issue with the current git (found by toddf on IRC). To reproduce: ./qemu-system-x86_64 --monitor stdio --nographic and put ? it should abort. Here is the backtrace: #0 0x7f77cd347935 in raise () from /lib64/libc.so.6 #1 0x7f77cd3490e8 in abort () from /lib64/libc.so.6 #2 0x7f77cd3406a2 in __assert_fail_base () from /lib64/libc.so.6 #3 0x7f77cd340752 in __assert_fail () from /lib64/libc.so.6 #4 0x7f77d1c1f226 in monitor_puts (mon=optimized out, str=optimized out) at Yes, it's easy to reproduce. Bisect says: f628926bb423fa8a7e0b114511400ea9df38b76a is the first bad commit commit f628926bb423fa8a7e0b114511400ea9df38b76a Author: Gerd Hoffmann kra...@redhat.com Date: Tue Mar 19 10:57:56 2013 +0100 fix monitor chardev flow control broke monitor, fix it by adding watch support. Signed-off-by: Anthony Liguori aligu...@us.ibm.com My impression is that monitor_puts() in being called in parallel. Not all. What's happening is that qemu_chr_fe_write() is returning 0, mon-outbuf_index is not reset and is full, this causes the assert in monitor_puts() to trig. The previous version of monitor_flush() ignores errors, and everything works, so doing the same thing here fixes the problem :) No, ignoring errors breaks qmp because the output isn't valid json any more when you cut off something ... What you mean when you cut off? When the other side disconnects? Do we care? For some reason I'm unable to see what the error code is. Gerd, do you think the patch below is reasonable? If it's not, how should we handle errors here? No, it's not. Ignoring the error for errno = EAGAIN breaks flow control. Ignoring the error for errno != EAGAIN (and maybe logging a debug message) would be ok, but I suspect it's actually EAGAIN you get here. Just go for a larger buffer? That's simple, but it's not a real fix. We hit that problem because the help output is a large one. I'd guess that this is easily reproduced with something like QIDL, which (iirc) generates long json output on QMP. Looks like we need a dynamic buffer there. Other ideas?
[Qemu-devel] [PATCH v9 01/24] target-arm: add Faraday ARMv5TE processors support
From: Kuo-Jung Su dant...@faraday-tech.com
This patch includes the single core support to FA606TE, FA626TE,
FA616TE and FA726TE with CP15 Faraday extensions (AUX and I/D-Scratchpad).
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
target-arm/cpu.c | 52 +++
target-arm/cpu.h |6 +++-
target-arm/helper.c | 84 ++
target-arm/machine.c |4 +++
4 files changed, 145 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index a1e9093..aed97b0 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -244,6 +244,54 @@ static void arm926_initfn(Object *obj)
cpu-reset_sctlr = 0x00090078;
}
+static void fa606te_initfn(Object *obj)
+{
+ARMCPU *cpu = ARM_CPU(obj);
+set_feature(cpu-env, ARM_FEATURE_V5);
+set_feature(cpu-env, ARM_FEATURE_DUMMY_C15_REGS);
+set_feature(cpu-env, ARM_FEATURE_MPU_FARADAY);
+cpu-midr = 0x66056061; /* CR0-0 Identification Code Register (ID) */
+cpu-ctr = 0x; /* CR0-1 Cache Type Register (CTR) */
+cpu-reset_sctlr = 0x0078; /* CR1-0 Configuration Register (CFG) */
+}
+
+static void fa616te_initfn(Object *obj)
+{
+ARMCPU *cpu = ARM_CPU(obj);
+set_feature(cpu-env, ARM_FEATURE_V5);
+set_feature(cpu-env, ARM_FEATURE_DUMMY_C15_REGS);
+set_feature(cpu-env, ARM_FEATURE_CACHE_TEST_CLEAN);
+set_feature(cpu-env, ARM_FEATURE_TCM_FARADAY);
+cpu-midr = 0x66056161; /* CR0-0 Identification Code Register (ID) */
+cpu-ctr = 0x1d152152; /* CR0-1 Cache Type Register (CTR) */
+cpu-reset_sctlr = 0x00050078; /* CR1-0 Configuration Register (CFG) */
+}
+
+static void fa626te_initfn(Object *obj)
+{
+ARMCPU *cpu = ARM_CPU(obj);
+set_feature(cpu-env, ARM_FEATURE_V5);
+set_feature(cpu-env, ARM_FEATURE_DUMMY_C15_REGS);
+set_feature(cpu-env, ARM_FEATURE_CACHE_TEST_CLEAN);
+set_feature(cpu-env, ARM_FEATURE_TCM_FARADAY);
+set_feature(cpu-env, ARM_FEATURE_AUXCR);
+cpu-midr = 0x66056261; /* CR0-0 Identification Code Register (ID) */
+cpu-ctr = 0x0f192192; /* CR0-1 Cache Type Register (CTR) */
+cpu-reset_sctlr = 0x0078; /* CR1-0 Configuration Register (CFG) */
+}
+
+static void fa726te_initfn(Object *obj)
+{
+ARMCPU *cpu = ARM_CPU(obj);
+set_feature(cpu-env, ARM_FEATURE_V5);
+set_feature(cpu-env, ARM_FEATURE_DUMMY_C15_REGS);
+set_feature(cpu-env, ARM_FEATURE_CACHE_TEST_CLEAN);
+set_feature(cpu-env, ARM_FEATURE_TCM_FARADAY);
+cpu-midr = 0x66057261; /* CR0-0 Identification Code Register (ID) */
+cpu-ctr = 0x1d192192; /* CR0-1 Cache Type Register (CTR) */
+cpu-reset_sctlr = 0x00050078; /* CR1-0 Configuration Register (CFG) */
+}
+
static void arm946_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -766,6 +814,10 @@ typedef struct ARMCPUInfo {
static const ARMCPUInfo arm_cpus[] = {
{ .name = arm926, .initfn = arm926_initfn },
+{ .name = fa606te, .initfn = fa606te_initfn },
+{ .name = fa616te, .initfn = fa616te_initfn },
+{ .name = fa626te, .initfn = fa626te_initfn },
+{ .name = fa726te, .initfn = fa726te_initfn },
{ .name = arm946, .initfn = arm946_initfn },
{ .name = arm1026, .initfn = arm1026_initfn },
/* What QEMU calls arm1136-r2 is actually the 1136 r0p2, i.e. an
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2b97221..dd27e80 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -152,6 +152,8 @@ typedef struct CPUARMState {
uint32_t c15_diagnostic; /* diagnostic register */
uint32_t c15_power_diagnostic;
uint32_t c15_power_control; /* power control */
+uint32_t c15_tcm_data; /* Data TCM region register */
+uint32_t c15_tcm_inst; /* Instruction TCM region register */
} cp15;
struct {
@@ -392,6 +394,8 @@ enum arm_features {
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
+ARM_FEATURE_TCM_FARADAY, /* Faraday Scratchpad(TCM) */
+ARM_FEATURE_MPU_FARADAY, /* Faraday MPU */
};
static inline int arm_feature(CPUARMState *env, int feature)
@@ -640,7 +644,7 @@ static inline CPUARMState *cpu_init(const char *cpu_model)
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
-#define CPU_SAVE_VERSION 9
+#define CPU_SAVE_VERSION 10
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
diff --git a/target-arm/helper.c b/target-arm/helper.c
index fd055e8..337d8b8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1015,6 +1015,84 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static int faraday_pmsav5_ircfg_read(CPUARMState *env,
+ const ARMCPRegInfo *ri,
+ uint64_t *value)
+{
+if (ri-crm = 4) {
+return
[Qemu-devel] [PATCH v9 03/24] hw/arm: add FTINTC020 interrupt controller support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTINTC020 interrupt controller supports both FIQ and IRQ signals
to the microprocessor.
It can handle up to 64 configurable IRQ sources and 64 FIQ sources.
The output signals to the microprocessor can be configured as
level-high/low active or edge-rising/falling triggered.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|1 +
hw/arm/ftplat_a369soc.c | 11 ++
hw/ftintc020.c | 307 +++
hw/ftintc020.h | 55 +
4 files changed, 374 insertions(+)
create mode 100644 hw/ftintc020.c
create mode 100644 hw/ftintc020.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 09217c6..7cdd831 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -24,6 +24,7 @@ obj-y += framebuffer.o
obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
+obj-y += ftintc020.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 624b549..331ec2a 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -51,6 +51,8 @@ static void a369soc_reset(DeviceState *ds)
static void a369soc_chip_init(FaradaySoCState *s)
{
+int i;
+DeviceState *ds;
DriveInfo *dinfo;
/* Remappable Memory Region Init */
@@ -84,6 +86,15 @@ static void a369soc_chip_init(FaradaySoCState *s)
memory_region_add_subregion(s-rmr, s-rom_base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(s-rom), 0));
+/* Interrupt Controller */
+ds = sysbus_create_varargs(ftintc020, 0x9010,
+ s-cpu_pic[ARM_PIC_CPU_IRQ],
+ s-cpu_pic[ARM_PIC_CPU_FIQ], NULL);
+s-pic = g_new0(qemu_irq, 64);
+for (i = 0; i 64; ++i) {
+s-pic[i] = qdev_get_gpio_in(ds, i);
+}
+
/* Serial (FTUART010 which is 16550A compatible) */
if (serial_hds[0]) {
serial_mm_init(s-as,
diff --git a/hw/ftintc020.c b/hw/ftintc020.c
new file mode 100644
index 000..9aaff1d
--- /dev/null
+++ b/hw/ftintc020.c
@@ -0,0 +1,307 @@
+/*
+ * Faraday FTINTC020 Programmable Interrupt Controller.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This code is licensed under GNU GPL v2+.
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+
+#include qemu/bitops.h
+#include hw/ftintc020.h
+
+#define TYPE_FTINTC020 ftintc020
+
+#define CFG_REGSIZE (0x100 / 4)
+
+typedef struct Ftintc020State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+
+qemu_irq irq;
+qemu_irq fiq;
+
+uint32_t irq_ps[2]; /* IRQ pin state */
+uint32_t fiq_ps[2]; /* FIQ pin state */
+
+/* HW register caches */
+uint32_t regs[CFG_REGSIZE];
+} Ftintc020State;
+
+#define FTINTC020(obj) \
+OBJECT_CHECK(Ftintc020State, obj, TYPE_FTINTC020)
+
+#define PIC_REG32(s, off) \
+((s)-regs[(off) / 4])
+
+#define IRQ_REG32(s, n, off) \
+((s)-regs[(REG_IRQ(n) + ((off) REG_MASK)) / 4])
+
+#define FIQ_REG32(s, n, off) \
+((s)-regs[(REG_FIQ(n) + ((off) REG_MASK)) / 4])
+
+static void
+ftintc020_update_irq(Ftintc020State *s)
+{
+uint32_t mask[2];
+
+/* FIQ */
+mask[0] = PIC_REG32(s, REG_FIQ32SRC) PIC_REG32(s, REG_FIQ32ENA);
+mask[1] = PIC_REG32(s, REG_FIQ64SRC) PIC_REG32(s, REG_FIQ64ENA);
+qemu_set_irq(s-fiq, !!(mask[0] || mask[1]));
+
+/* IRQ */
+mask[0] = PIC_REG32(s, REG_IRQ32SRC) PIC_REG32(s, REG_IRQ32ENA);
+mask[1] = PIC_REG32(s, REG_IRQ64SRC) PIC_REG32(s, REG_IRQ64ENA);
+qemu_set_irq(s-irq, !!(mask[0] || mask[1]));
+}
+
+/* Note: Here level means state of the signal on a pin */
+static void
+ftintc020_set_irq(void *opaque, int irq, int level)
+{
+Ftintc020State *s = FTINTC020(opaque);
+uint32_t i = irq / 32;
+uint32_t mask = BIT(irq 0x1f);
+
+switch (irq) {
+case 0 ... 63:
+/* IRQ */
+if (IRQ_REG32(s, irq, REG_MDR) mask) {
+/* Edge Triggered */
+if (IRQ_REG32(s, irq, REG_LVR) mask) {
+/* Falling Active */
+if ((s-irq_ps[i] mask) !level) {
+IRQ_REG32(s, irq, REG_SRC) |= mask;
+}
+} else {
+/* Rising Active */
+if (!(s-irq_ps[i] mask) level) {
+IRQ_REG32(s, irq, REG_SRC) |= mask;
+}
+}
+} else {
+/* Level Triggered */
+if (IRQ_REG32(s, irq, REG_LVR) mask) {
+/* Low Active */
+if (level) {
+IRQ_REG32(s, irq, REG_SRC) = ~mask;
+} else {
+IRQ_REG32(s, irq, REG_SRC) |= mask;
+}
+} else {
+/* High Active */
+if (level) {
+IRQ_REG32(s, irq, REG_SRC) |=
[Qemu-devel] [PATCH v9 00/24] hw/arm: add Faraday A369 SoC platform support
From: Kuo-Jung Su dant...@faraday-tech.com These patches introduce Faraday A369 SoC platform support. Here are some public documents for your reference. http://www.faraday-tech.com/html/documentation/index.html The partial version of faraday cpu datasheet with only the CP15 and MPU description are available at my Google Drive: https://docs.google.com/folder/d/0BwfiewvSmUgAalh5TkxyZWtlWEE/edit?usp=sharing The pre-built A369 images are also available at my Google Drive: https://docs.google.com/folder/d/0BwfiewvSmUgAX2pTTmtUMGFCZW8/edit Here is the image file list: 1. android-4.0.4/zImage: A369 linux-3.0.31 2. android-4.0.4/romfs-4.0.4.tar.bz2: android-4.0.4 3. nand.img.bz2: A369 nand flash image 4. rom.img.bz2: A369 embedded ROM image 5. u-boot: A369 u-boot-2012.10 ELF file 6. zImage: A369 linux-3.4.12 + initramfs 7. README If you want to re-build the image from scratch, try my Faraday Linux BSP/SDK: falinux. 1. Download the falinux $ git clone https://github.com/dantesu1218/falinux.git 2. Download all the required software packages: $ cd falinux $ make setup 3. Launch the menuconfig of falinux, and enable 'QEMU Support' $ make menuconfig 4. Re-build the packages $ make 5. Laungh the qemu-1.3.0 with the generated falinux images. $ make qemu Changes for v8 - v9: 1. hw/arm: Update the file directory structure (Addressed by Peter.M) hw/arm: top level board models and things directly reference the CPU only hw: otherwise 2. hw/arm: Rename SoC platform specific files: hw/arm/faraday_a369.c - hw/arm/ftplat_a369.c hw/arm/faraday_a369_soc.c - hw/arm/ftplat_a369soc.c hw/arm/faraday_a369_scu.c - hw/arm/ftplat_a369scu.c hw/arm/faraday_a369_kpd.c - hw/arm/ftplat_a369kpd.c 3. hw: audio_codec.[ch] - audio.[ch] 4. hw/fti2c010: Drop .addr from Fti2c010State. (Addressed by Peter.C) 5. hw/fti2c010: Add qemu_log_mask(LOG_UNIMP, ) to slave mode. (Addressed by Peter.C) 6. hw/fti2c010: Update data type of Fti2c010State.recv from 'uint8_t' into 'bool'. 7. hw/*.c: QOM Coding Conventions (Addressed by Peter.C) 8. hw/*.h: Inlcudes bitops only if they need it. (Addressed by Peter.C) 9. hw/ftplat_a369soc: Add a container memory region for remappable devices. (i.e. ROM, RAM) (Addressed by Peter.C and Peter.M) 10. hw/faraday.h: Drop cpu, cpu_model, ahb_remapped, ddr_inited, rom_size, ram_size scu, ahbc, ddrc from FaradaySoCState. 11. hw/faraday.h: Replace FaradaySoCState.bi with FaradaySoCState.ram_boot 12. hw/arm/ftplat_a369soc: Move customized system reset to ftplat_a369.c 13. hw/faraday.h: Add faraday_soc_ahb_remap() and faraday_soc_ram_setup() for ftddrii030, ftahbc020, ftplat_a369soc and ftplat_a369. 14. hw/ftahbc020, ftapbbrg020, ftddrii030, ftnandc021, ftssp010.c: Move object_property_add_link() to object::instance_init() Changes for v7 - v8: 1. [hw/arm/ftintc020.c] (Addressed by Peter) 'uint32_t mask = BIT(irq % 32);' - 'uint32_t mask = BIT(irq 0x1f);' 2. [hw/arm/*.c] (Addressed by Peter) Drop '#include faraday.h', and define DPRINTF() at per-file basis exit(1) - abort() SysBusDeviceClass::init() - Device::realize() Changes for v6 - v7: 1. hw/arm/ftwdt010: (Addressed by Paolo) Replace 'qemu_system_reset_request()' with 'watchdog_perform_action()'. 2. hw/arm/ftrtc011: (Addressed by Paolo) Replace 'get_clock_realtime()' with 'qemu_get_clock_ns(rtc_clock)'. Replace 'qemu_new_timer_ms(rt_clock...)' with 'qemu_new_timer_ms(rtc_clock...)' Rename 'ftrtc011_timer_resync' - 'ftrtc011_timer_rebase' Add ftrtc011_timer_resche() Add QTest support 3. hw/arm/faraday_a369_soc: (Addressed by Paolo) Remove redundant device reset from a369soc_system_reset(...) 4. include/qemu/bitops.h: (Addressed by Paolo) Update bitrev8() to use a kind of divide and conquer algorithm. 5. hw/arm/ftahb020,ftddrii030,ftapbbrg020,faraday_a369_soc: Drop FARADAY_SOC_GET_CORE(), replaced with device to device QOM link. 6. hw/wm8731,wm8750,marvell_88w8618_audio,spitz,z2: Add AudioCodecClass for wm87xx audio class abstration. 7. hw/arm/ftnandc021: Drop nand_init(), replaced with device to device QOM link. 8. hw/arm/ftsdc010: Bug fixed to write operation: remove sd_data_ready() in write path. 9. hw/arm/ftgmac100,ftmac110,ftwdt010: rt-clock - vm_clock 10. hw/nand.c: Drop [hw/nand.c: correct the sense of the BUSY/READY], since it's already applied. Drop [hw/nand.c: bug fix to erase operation], since Peter has a better solution. Changes for v5 - v6: 1. hw/arm/Makefile.objs: Shift to the next line only after current line length is 80 characters. 2. hw/arm/faraday.h: Update debug macro format per discussions at the link bellow:
[Qemu-devel] [PATCH v9 20/24] hw/arm: add FTTSC010 touchscreen controller support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTTSC010 provides two operation modes to sample
the analog input voltage.
1. The manual operation mode needs to program
and control the panel drivers by software
step-by-step for the x-y position measurement.
2. The auto-scan mode provides a periodic sampling
method to convert the analog input.
This patch only implements the auto-scan mode.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |3 +
hw/fttsc010.c | 264 +++
hw/fttsc010.h | 39 +++
4 files changed, 307 insertions(+), 1 deletion(-)
create mode 100644 hw/fttsc010.c
create mode 100644 hw/fttsc010.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index f6b947e..d163239 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -26,7 +26,7 @@ obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o fti2c010.o \
-ftssp010.o ftgmac100.o ftlcdc200.o
+ftssp010.o ftgmac100.o ftlcdc200.o fttsc010.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index cdc6d4a..231ea1e 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -238,6 +238,9 @@ static void a369soc_chip_init(FaradaySoCState *s)
s-pic[23], /* FIFO Under-Run */
s-pic[22], /* AHB Bus Error */
NULL);
+
+/* fttsc010 */
+sysbus_create_simple(fttsc010, 0x9240, s-pic[19]);
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/fttsc010.c b/hw/fttsc010.c
new file mode 100644
index 000..02b7ec2
--- /dev/null
+++ b/hw/fttsc010.c
@@ -0,0 +1,264 @@
+/*
+ * Faraday FTTSC010 emulator.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This code is licensed under GNU GPL v2+.
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include hw/devices.h
+#include ui/console.h
+#include qemu/timer.h
+#include sysemu/sysemu.h
+
+#include hw/fttsc010.h
+
+#define X_AXIS_DMAX 3470
+#define X_AXIS_MIN 290
+#define Y_AXIS_DMAX 3450
+#define Y_AXIS_MIN 200
+
+#define ADS_XPOS(x, y) \
+(X_AXIS_MIN + ((X_AXIS_DMAX * (x)) 15))
+#define ADS_YPOS(x, y) \
+(Y_AXIS_MIN + ((Y_AXIS_DMAX * (y)) 15))
+#define ADS_Z1POS(x, y) \
+(8)
+#define ADS_Z2POS(x, y) \
+((1600 + ADS_XPOS(x, y)) * ADS_Z1POS(x, y) / ADS_XPOS(x, y))
+
+#define TYPE_FTTSC010 fttsc010
+
+#define CFG_REGSIZE (0x3c / 4)
+
+typedef struct Fttsc010State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+qemu_irq irq;
+
+uint64_t interval;
+QEMUTimer *qtimer;
+
+int x, y;
+int z1, z2;
+uint32_t freq;
+
+/* HW registers */
+uint32_t regs[CFG_REGSIZE];
+} Fttsc010State;
+
+#define FTTSC010(obj) \
+OBJECT_CHECK(Fttsc010State, obj, TYPE_FTTSC010)
+
+#define TSC_REG32(s, off) \
+((s)-regs[(off) / 4])
+
+static void fttsc010_update_irq(Fttsc010State *s)
+{
+qemu_set_irq(s-irq, !!(TSC_REG32(s, REG_IMR) TSC_REG32(s, REG_ISR)));
+}
+
+static uint64_t
+fttsc010_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+uint32_t ret = 0;
+Fttsc010State *s = FTTSC010(opaque);
+
+switch (addr) {
+case REG_CR ... REG_DCR:
+ret = s-regs[addr / 4];
+break;
+case REG_XYR:
+ret = deposit32(ret, 0, 12, s-x);
+ret = deposit32(ret, 16, 12, s-y);
+break;
+case REG_ZR:
+ret = deposit32(ret, 0, 12, s-z1);
+ret = deposit32(ret, 16, 12, s-z2);
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+fttsc010: undefined memory access@%# HWADDR_PRIx \n, addr);
+break;
+}
+
+return ret;
+}
+
+static void
+fttsc010_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+uint32_t dly, sdiv, mdiv;
+Fttsc010State *s = FTTSC010(opaque);
+
+switch (addr) {
+case REG_CR:
+TSC_REG32(s, REG_CR) = (uint32_t)val;
+if (TSC_REG32(s, REG_CR) (CR_AS | CR_RD1)) {
+/* ADC conversion delay with frame number */
+dly = extract32(TSC_REG32(s, REG_DCR), 0, 16);
+/* ADC sample clock divider */
+sdiv = extract32(TSC_REG32(s, REG_CSR), 8, 8);
+/* ADC main clock divider */
+mdiv = extract32(TSC_REG32(s, REG_CSR), 0, 8);
+/* Calculate sample rate/timer interval */
+s-interval = s-freq / ((mdiv + 1) * (sdiv + 1) * (dly + 1) * 64);
+s-interval = MAX(1ULL, s-interval);
+qemu_mod_timer(s-qtimer,
+s-interval + qemu_get_clock_ms(vm_clock));
[Qemu-devel] [PATCH v9 07/24] hw/arm: add FTWDT010 watchdog timer support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTWDT010 is used to prevent system from infinite loop
while software gets trapped in the deadlock.
Under the normal operation, users should restart FTWDT010
at the regular intervals before counter counts down to 0.
If the counter does reach 0, FTWDT010 will try to reset
the system by generating one or a combination of signals,
system reset, system interrupt, and external interrupt.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369.c|8 ++
hw/arm/ftplat_a369soc.c |3 +
hw/ftwdt010.c | 213 +++
hw/ftwdt010.h | 35
5 files changed, 260 insertions(+), 1 deletion(-)
create mode 100644 hw/ftwdt010.c
create mode 100644 hw/ftwdt010.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 4fe0222..22f0c64 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -24,7 +24,7 @@ obj-y += framebuffer.o
obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
-obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o
+obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369.c b/hw/arm/ftplat_a369.c
index 6f00c82..45f0846 100644
--- a/hw/arm/ftplat_a369.c
+++ b/hw/arm/ftplat_a369.c
@@ -19,6 +19,11 @@
#include hw/faraday.h
+static void a369_system_reset(void *opaque)
+{
+cpu_reset(CPU(opaque));
+}
+
/* Board init. */
static void a369_board_init(QEMUMachineInitArgs *args)
@@ -57,6 +62,9 @@ static void a369_board_init(QEMUMachineInitArgs *args)
vmstate_register_ram_global(s-ram);
qdev_init_nofail(ds);
+/* Customized system reset */
+qemu_register_reset(a369_system_reset, cpu);
+
/* System start-up */
if (args-kernel_filename) {
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 6e2ea65..56f0920 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -147,6 +147,9 @@ static void a369soc_chip_init(FaradaySoCState *s)
sysbus_connect_irq(SYS_BUS_DEVICE(ds), 1, s-pic[9]);
sysbus_connect_irq(SYS_BUS_DEVICE(ds), 2, s-pic[10]);
sysbus_connect_irq(SYS_BUS_DEVICE(ds), 3, s-pic[11]);
+
+/* ftwdt010 */
+sysbus_create_simple(ftwdt010, 0x9220, s-pic[46]);
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftwdt010.c b/hw/ftwdt010.c
new file mode 100644
index 000..cdbe2f3
--- /dev/null
+++ b/hw/ftwdt010.c
@@ -0,0 +1,213 @@
+/*
+ * QEMU model of the FTWDT010 WatchDog Timer
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ */
+
+#include hw/sysbus.h
+#include hw/watchdog.h
+#include sysemu/sysemu.h
+#include qemu/timer.h
+
+#include hw/ftwdt010.h
+
+#define TYPE_FTWDT010 ftwdt010
+
+typedef struct Ftwdt010State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion mmio;
+
+qemu_irq irq;
+
+QEMUTimer *qtimer;
+
+uint64_t timeout;
+uint64_t freq;/* desired source clock */
+uint64_t step;/* get_ticks_per_sec() / freq */
+bool running;
+
+/* HW register cache */
+uint32_t load;
+uint32_t cr;
+uint32_t sr;
+} Ftwdt010State;
+
+#define FTWDT010(obj) \
+OBJECT_CHECK(Ftwdt010State, obj, TYPE_FTWDT010)
+
+static uint64_t
+ftwdt010_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+Ftwdt010State *s = FTWDT010(opaque);
+uint32_t ret = 0;
+
+switch (addr) {
+case REG_COUNTER:
+if (s-cr CR_EN) {
+ret = s-timeout - qemu_get_clock_ms(rt_clock);
+ret = MIN(s-load, ret * 100ULL / s-step);
+} else {
+ret = s-load;
+}
+break;
+case REG_LOAD:
+return s-load;
+case REG_CR:
+return s-cr;
+case REG_SR:
+return s-sr;
+case REG_REVR:
+return 0x00010601; /* rev. 1.6.1 */
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ftwdt010: undefined memory access@%# HWADDR_PRIx \n, addr);
+break;
+}
+
+return ret;
+}
+
+static void
+ftwdt010_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+Ftwdt010State *s = FTWDT010(opaque);
+
+switch (addr) {
+case REG_LOAD:
+s-load = (uint32_t)val;
+break;
+case REG_RESTART:
+if ((s-cr CR_EN) (val == WDT_MAGIC)) {
+s-timeout = (s-step * (uint64_t)s-load) / 100ULL;
+s-timeout = qemu_get_clock_ms(rt_clock) + MAX(s-timeout, 1);
+qemu_mod_timer(s-qtimer, s-timeout);
+}
+break;
+case REG_CR:
+s-cr = (uint32_t)val;
+if (s-cr CR_EN) {
+if (s-running) {
+break;
+}
+s-running = true;
+s-timeout =
[Qemu-devel] [PATCH v9 06/24] hw/arm: add FTPWMTMR010 timer support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTPWMTMR010 is an APB device which provides up to 8 independent timers.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c | 10 ++
hw/ftpwmtmr010.c| 261 +++
hw/ftpwmtmr010.h| 31 ++
4 files changed, 303 insertions(+), 1 deletion(-)
create mode 100644 hw/ftpwmtmr010.c
create mode 100644 hw/ftpwmtmr010.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index e774962..4fe0222 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -24,7 +24,7 @@ obj-y += framebuffer.o
obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
-obj-y += ftintc020.o ftahbc020.o ftddrii030.o
+obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index b2da582..6e2ea65 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -137,6 +137,16 @@ static void a369soc_chip_init(FaradaySoCState *s)
fprintf(stderr, a369soc: Unable to set soc link for FTDDRII030\n);
abort();
}
+
+/* Timer */
+ds = qdev_create(NULL, ftpwmtmr010);
+qdev_prop_set_uint32(ds, freq, 66 * 100);
+qdev_init_nofail(ds);
+sysbus_mmio_map(SYS_BUS_DEVICE(ds), 0, 0x9230);
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 0, s-pic[8]);
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 1, s-pic[9]);
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 2, s-pic[10]);
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 3, s-pic[11]);
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftpwmtmr010.c b/hw/ftpwmtmr010.c
new file mode 100644
index 000..d08eaa6
--- /dev/null
+++ b/hw/ftpwmtmr010.c
@@ -0,0 +1,261 @@
+/*
+ * Faraday FTPWMTMR010 Timer.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This code is licensed under GNU GPL v2+.
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include qemu/timer.h
+#include sysemu/sysemu.h
+
+#include hw/ftpwmtmr010.h
+
+#define TYPE_FTPWMTMR010ftpwmtmr010
+#define TYPE_FTPWMTMR010_TIMER ftpwmtmr010_timer
+
+typedef struct Ftpwmtmr010State Ftpwmtmr010State;
+
+typedef struct Ftpwmtmr010Timer {
+uint32_t ctrl;
+uint32_t cntb;
+int id;
+uint64_t timeout;
+uint64_t countdown;
+qemu_irq irq;
+QEMUTimer *qtimer;
+Ftpwmtmr010State *chip;
+} Ftpwmtmr010Timer;
+
+struct Ftpwmtmr010State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+Ftpwmtmr010Timer timer[8];
+uint32_t freq;/* desired source clock */
+uint64_t step;/* get_ticks_per_sec() / freq */
+uint32_t stat;
+};
+
+#define FTPWMTMR010(obj) \
+OBJECT_CHECK(Ftpwmtmr010State, obj, TYPE_FTPWMTMR010)
+
+static uint64_t
+ftpwmtmr010_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+Ftpwmtmr010State *s = FTPWMTMR010(opaque);
+Ftpwmtmr010Timer *t;
+uint64_t now = qemu_get_clock_ns(vm_clock);
+uint64_t ret = 0;
+
+switch (addr) {
+case REG_SR:
+ret = s-stat;
+break;
+case REG_REVR:
+ret = 0x; /* Rev. 0.0.0 (no rev. id) */
+break;
+case REG_TIMER_BASE(1) ... REG_TIMER_BASE(8) + 0x0C:
+t = s-timer + (addr 4) - 1;
+switch (addr 0x0f) {
+case REG_TIMER_CTRL:
+return t-ctrl;
+case REG_TIMER_CNTB:
+return t-cntb;
+case REG_TIMER_CNTO:
+if ((t-ctrl TIMER_CTRL_START) (t-timeout now)) {
+ret = (t-timeout - now) / s-step;
+}
+break;
+}
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ftpwmtmr010: undefined memory access@%# HWADDR_PRIx \n, addr);
+break;
+}
+
+return ret;
+}
+
+static void
+ftpwmtmr010_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+Ftpwmtmr010State *s = FTPWMTMR010(opaque);
+Ftpwmtmr010Timer *t;
+int i;
+
+switch (addr) {
+case REG_SR:
+s-stat = ~((uint32_t)val);
+for (i = 0; i 8; ++i) {
+if (val BIT(i)) {
+qemu_irq_lower(s-timer[i].irq);
+}
+}
+break;
+case REG_TIMER_BASE(1) ... REG_TIMER_BASE(8) + 0x0C:
+t = s-timer + (addr 4) - 1;
+switch (addr 0x0f) {
+case REG_TIMER_CTRL:
+t-ctrl = (uint32_t)val;
+if (t-ctrl TIMER_CTRL_UPDATE) {
+t-countdown = (uint64_t)t-cntb * s-step;
+}
+if (t-ctrl TIMER_CTRL_START) {
+t-timeout = t-countdown + qemu_get_clock_ns(vm_clock);
+qemu_mod_timer(t-qtimer, t-timeout);
+}
+break;
+case REG_TIMER_CNTB:
+t-cntb =
[Qemu-devel] [PATCH v9 04/24] hw/arm: add FTAHBC020 AHB controller support
From: Kuo-Jung Su dant...@faraday-tech.com
It's used to manage AHB slave devices
and also the AHB remap function for slave4 slave6.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |9 ++
hw/ftahbc020.c | 216 +++
3 files changed, 226 insertions(+), 1 deletion(-)
create mode 100644 hw/ftahbc020.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 7cdd831..b2fa20f 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -24,7 +24,7 @@ obj-y += framebuffer.o
obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
-obj-y += ftintc020.o
+obj-y += ftintc020.o ftahbc020.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 331ec2a..7f222cb 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -54,6 +54,7 @@ static void a369soc_chip_init(FaradaySoCState *s)
int i;
DeviceState *ds;
DriveInfo *dinfo;
+Error *local_errp = NULL;
/* Remappable Memory Region Init */
s-rmr = g_new0(MemoryRegion, 1);
@@ -120,6 +121,14 @@ static void a369soc_chip_init(FaradaySoCState *s)
/* ftkbc010 */
sysbus_create_simple(a369-kpd, 0x92f0, s-pic[21]);
+
+/* ftahbc020 */
+ds = sysbus_create_simple(ftahbc020, 0x9400, NULL);
+object_property_set_link(OBJECT(ds), OBJECT(s), soc, local_errp);
+if (local_errp) {
+fprintf(stderr, a369soc: Unable to set soc link for FTAHBC020\n);
+abort();
+}
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftahbc020.c b/hw/ftahbc020.c
new file mode 100644
index 000..76e8b75
--- /dev/null
+++ b/hw/ftahbc020.c
@@ -0,0 +1,216 @@
+/*
+ * Faraday AHB controller
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This code is licensed under GNU GPL v2+
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include hw/devices.h
+#include sysemu/sysemu.h
+
+#include hw/faraday.h
+
+#define REG_SLAVE(n)((n) * 4) /* Slave config (base size) */
+#define REG_PRIR0x80/* Priority register */
+#define REG_IDLECR 0x84/* IDLE count register */
+#define REG_CR 0x88/* Control register */
+#define REG_REVR0x8c/* Revision register */
+
+#define CR_REMAP0x01/* Enable AHB remap for slave 4 6 */
+
+#define TYPE_FTAHBC020 ftahbc020
+
+typedef struct Ftahbc020State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+
+FaradaySoCState *soc;
+
+/* HW register cache */
+uint32_t prir; /* Priority register */
+uint32_t cr;/* Control register */
+} Ftahbc020State;
+
+#define FTAHBC020(obj) \
+OBJECT_CHECK(Ftahbc020State, obj, TYPE_FTAHBC020)
+
+static uint64_t
+ftahbc020_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+Ftahbc020State *s = FTAHBC020(opaque);
+FaradaySoCState *soc = s-soc;
+bool remapped = (soc-ram_base != (soc-ahb_slave[6] 0xfff0));
+uint64_t ret = 0;
+
+switch (addr) {
+/* slave address window configuration */
+case REG_SLAVE(0) ... REG_SLAVE(3):
+/* fall-through - skip slave4 */
+case REG_SLAVE(5):
+/* fall-through - skip slave6 */
+case REG_SLAVE(7) ... REG_SLAVE(31):
+ret = soc-ahb_slave[addr / 4];
+break;
+case REG_SLAVE(4):
+ret = soc-rom_base | (soc-ahb_slave[4] 0x000f);
+break;
+case REG_SLAVE(6):
+ret = soc-ram_base | (soc-ahb_slave[6] 0x000f);
+break;
+/* priority register */
+case REG_PRIR:
+ret = s-prir;
+break;
+/* idle counter register */
+case REG_IDLECR:
+break;
+/* control register */
+case REG_CR:
+if (remapped) {
+s-cr |= CR_REMAP;
+}
+ret = s-cr;
+break;
+/* revision register */
+case REG_REVR:
+ret = 0x00010301; /* rev. 1.3.1 */
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ftahbc020: undefined memory access@%# HWADDR_PRIx \n, addr);
+break;
+}
+
+return ret;
+}
+
+static void
+ftahbc020_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+Ftahbc020State *s = FTAHBC020(opaque);
+FaradaySoCState *soc = s-soc;
+bool remapped = (soc-ram_base != (soc-ahb_slave[6] 0xfff0));
+
+switch (addr) {
+case REG_CR:/* control register */
+s-cr = (uint32_t)val;
+if (remapped !(s-cr CR_REMAP)) {
+fprintf(stderr,
+ftahbc020:
+AHB remap could only be disabled via system reset!\n);
+abort();
+}
+if (!remapped (s-cr CR_REMAP)) {
+faraday_soc_ahb_remap(soc, true);
+}
+break;
+case
[Qemu-devel] [PATCH v9 19/24] hw/arm: add FTLCDC200 LCD controller support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray or color value
2. an address to a 256 x 16 bit wide palette RAM gray or color value.
The FTLCDC200 generates 4 individual interrupts for:
1. DMA FIFO underflow
2. base address update
3. vertical status
4. bus error.
There is also a single combined interrupt that is raised when any of
the individual interrupts become active.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c | 10 +
hw/ftlcdc200.c | 516 +++
hw/ftlcdc200.h | 110 ++
hw/ftlcdc200_template.h | 439
5 files changed, 1076 insertions(+), 1 deletion(-)
create mode 100644 hw/ftlcdc200.c
create mode 100644 hw/ftlcdc200.h
create mode 100644 hw/ftlcdc200_template.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 62c823d..f6b947e 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -26,7 +26,7 @@ obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o fti2c010.o \
-ftssp010.o ftgmac100.o
+ftssp010.o ftgmac100.o ftlcdc200.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 622b1db..cdc6d4a 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -228,6 +228,16 @@ static void a369soc_chip_init(FaradaySoCState *s)
if (nb_nics 0) {
ftgmac100_init(nd_table[0], 0x90c0, s-pic[32]);
}
+
+/* ftlcdc200 */
+sysbus_create_varargs(ftlcdc200,
+ 0x94a0,
+ s-pic[0], /* ALL (NC in A369) */
+ s-pic[25], /* VSTATUS */
+ s-pic[24], /* Base Address Update */
+ s-pic[23], /* FIFO Under-Run */
+ s-pic[22], /* AHB Bus Error */
+ NULL);
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftlcdc200.c b/hw/ftlcdc200.c
new file mode 100644
index 000..2e25372
--- /dev/null
+++ b/hw/ftlcdc200.c
@@ -0,0 +1,516 @@
+/*
+ * Faraday FTLCDC200 Color LCD Controller
+ *
+ * base is pl110.c
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This code is licensed under the GNU LGPL
+ */
+
+#include hw/sysbus.h
+#include hw/framebuffer.h
+#include ui/console.h
+#include ui/pixel_ops.h
+
+#include qemu/bitops.h
+#include hw/ftlcdc200.h
+
+enum ftlcdc200_irqpin {
+IRQ_ALL = 0,
+IRQ_VSTATUS,
+IRQ_BASEUPT,
+IRQ_FIFOUR,
+IRQ_BUSERR,
+};
+
+enum ftlcdc200_bppmode {
+BPP_1 = 0,
+BPP_2,
+BPP_4,
+BPP_8,
+BPP_16,
+BPP_32,
+BPP_16_565,
+BPP_12,
+};
+
+#define TYPE_FTLCDC200 ftlcdc200
+
+typedef struct Ftlcdc200State {
+SysBusDevice busdev;
+MemoryRegion iomem;
+QemuConsole *con;
+
+qemu_irq irq[5];
+int cols;
+int rows;
+enum ftlcdc200_bppmode bpp;
+int invalidate;
+uint32_t palette[256];
+uint32_t raw_palette[128];
+
+/* hw register caches */
+uint32_t fer; /* function enable register */
+uint32_t ppr; /* panel pixel register */
+uint32_t ier; /* interrupt enable register */
+uint32_t isr; /* interrupt status register */
+uint32_t sppr; /* serail panel pixel register */
+
+uint32_t fb[4]; /* frame buffer base address register */
+uint32_t ht;/* horizontal timing control register */
+uint32_t vt0; /* vertital timing control register 0 */
+uint32_t vt1; /* vertital timing control register 1 */
+uint32_t pol; /* polarity */
+
+} Ftlcdc200State;
+
+#define FTLCDC200(obj) \
+OBJECT_CHECK(Ftlcdc200State, obj, TYPE_FTLCDC200)
+
+static const VMStateDescription vmstate_ftlcdc200 = {
+.name = TYPE_FTLCDC200,
+.version_id = 2,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_INT32(cols, Ftlcdc200State),
+VMSTATE_INT32(rows, Ftlcdc200State),
+VMSTATE_UINT32(bpp, Ftlcdc200State),
+VMSTATE_INT32(invalidate, Ftlcdc200State),
+VMSTATE_UINT32_ARRAY(palette, Ftlcdc200State, 256),
+VMSTATE_UINT32_ARRAY(raw_palette, Ftlcdc200State, 128),
+VMSTATE_UINT32(fer, Ftlcdc200State),
+VMSTATE_UINT32(ppr, Ftlcdc200State),
+VMSTATE_UINT32(ier, Ftlcdc200State),
+VMSTATE_UINT32(isr, Ftlcdc200State),
+VMSTATE_UINT32(sppr, Ftlcdc200State),
+
[Qemu-devel] [PATCH v9 18/24] hw/arm: add FTGMAC100 1Gbps ethernet support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTGMAC100 Ethernet controller has a DMA engine which handles
all data transfers between the system memory and on-chip memories.
Its DMA engine supports both 16-bits and 32-bits alignment,
and thus make it possible to support zero-copy transfer at both
Linux and WINCE.
It also has 802.1Q VLAN tagging support for both insertion and removal.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |5 +
hw/faraday.h|3 +
hw/ftgmac100.c | 712 +++
hw/ftgmac100.h | 237
5 files changed, 958 insertions(+), 1 deletion(-)
create mode 100644 hw/ftgmac100.c
create mode 100644 hw/ftgmac100.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 42c8472..62c823d 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -26,7 +26,7 @@ obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o fti2c010.o \
-ftssp010.o
+ftssp010.o ftgmac100.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 9391764..622b1db 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -223,6 +223,11 @@ static void a369soc_chip_init(FaradaySoCState *s)
req = qdev_get_gpio_in(s-pdma[0], 8);
qdev_connect_gpio_out(s-pdma[0], 8, ack);
qdev_connect_gpio_out(ds, 1, req);
+
+/* ftgmac100 */
+if (nb_nics 0) {
+ftgmac100_init(nd_table[0], 0x90c0, s-pic[32]);
+}
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/faraday.h b/hw/faraday.h
index 39a608c..068b799 100644
--- a/hw/faraday.h
+++ b/hw/faraday.h
@@ -124,4 +124,7 @@ static inline void faraday_soc_ahb_remap(FaradaySoCState
*s, bool active)
/* ftssp010.c */
void ftssp010_i2s_data_req(void *opaque, int tx, int rx);
+/* ftgmac100.c */
+void ftgmac100_init(NICInfo *nd, uint32_t base, qemu_irq irq);
+
#endif
diff --git a/hw/ftgmac100.c b/hw/ftgmac100.c
new file mode 100644
index 000..45f8a5b
--- /dev/null
+++ b/hw/ftgmac100.c
@@ -0,0 +1,712 @@
+/*
+ * QEMU model of the FTGMAC100 Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ */
+
+#include hw/sysbus.h
+#include qemu/timer.h
+#include sysemu/sysemu.h
+#include sysemu/dma.h
+#include net/net.h
+
+#include hw/faraday.h
+#include hw/ftgmac100.h
+
+#ifndef DEBUG
+#define DEBUG 0
+#endif
+
+#define DPRINTF(fmt, ...) \
+do { \
+if (DEBUG) { \
+fprintf(stderr, fmt , ## __VA_ARGS__); \
+} \
+} while (0)
+
+#define TYPE_FTGMAC100 ftgmac100
+
+#define CFG_MAXFRMLEN 9220/* Max. frame length */
+#define CFG_REGSIZE (0x100 / 4)
+
+typedef struct Ftgmac100State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion mmio;
+
+QEMUBH *bh;
+qemu_irq irq;
+NICState *nic;
+NICConf conf;
+DMAContext *dma;
+QEMUTimer *qtimer;
+
+bool phycr_rd;
+
+struct {
+uint8_t buf[CFG_MAXFRMLEN];
+uint32_t len;
+} txbuff;
+
+uint32_t hptx_idx;
+uint32_t tx_idx;
+uint32_t rx_idx;
+
+/* HW register cache */
+uint32_t regs[CFG_REGSIZE];
+} Ftgmac100State;
+
+#define FTGMAC100(obj) \
+OBJECT_CHECK(Ftgmac100State, obj, TYPE_FTGMAC100)
+
+#define MAC_REG32(s, off) \
+((s)-regs[(off) / 4])
+
+static int ftgmac100_mcast_hash(Ftgmac100State *s, const uint8_t *data)
+{
+#define CRCPOLY_BE0x04c11db7
+int i, len;
+uint32_t crc = 0x;
+
+len = (MAC_REG32(s, REG_MACCR) MACCR_GMODE) ? 5 : 6;
+
+while (len--) {
+uint32_t c = *(data++);
+for (i = 0; i 8; ++i) {
+crc = (crc 1) ^ crc 31) ^ c) 0x01) ? CRCPOLY_BE : 0);
+c = 1;
+}
+}
+crc = ~crc;
+
+/* Reverse CRC32 and return MSB 6 bits only */
+return bitrev8(crc 24) 2;
+}
+
+static void
+ftgmac100_read_txdesc(Ftgmac100State *s, hwaddr addr, Ftgmac100TXD *desc)
+{
+int i;
+uint32_t *p = (uint32_t *)desc;
+
+if (addr 0x0f) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ ftgmac100: Tx desc is not 16-byte aligned!\n
+ It's fine in QEMU but the real HW would panic.\n);
+}
+
+dma_memory_read(s-dma, addr, desc, sizeof(*desc));
+
+for (i = 0; i sizeof(*desc); i += 4) {
+*p = le32_to_cpu(*p);
+}
+
+if (desc-buf 0x01) {
+qemu_log_mask(LOG_GUEST_ERROR,
+ ftgmac100: tx buffer is not 16-bit aligned!\n);
+}
+}
+
+static void
+ftgmac100_write_txdesc(Ftgmac100State *s, hwaddr addr, Ftgmac100TXD *desc)
+{
+int i;
+uint32_t *p
[Qemu-devel] [PATCH v9 05/24] hw/arm: add FTDDRII030 DDRII controller support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTDDRII030 is a DDRII SDRAM controller which is responsible for
SDRAM initialization.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |8 ++
hw/ftddrii030.c | 192 +++
3 files changed, 201 insertions(+), 1 deletion(-)
create mode 100644 hw/ftddrii030.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index b2fa20f..e774962 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -24,7 +24,7 @@ obj-y += framebuffer.o
obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
-obj-y += ftintc020.o ftahbc020.o
+obj-y += ftintc020.o ftahbc020.o ftddrii030.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 7f222cb..b2da582 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -129,6 +129,14 @@ static void a369soc_chip_init(FaradaySoCState *s)
fprintf(stderr, a369soc: Unable to set soc link for FTAHBC020\n);
abort();
}
+
+/* ftddrii030 */
+ds = sysbus_create_simple(ftddrii030, 0x9310, NULL);
+object_property_set_link(OBJECT(ds), OBJECT(s), soc, local_errp);
+if (local_errp) {
+fprintf(stderr, a369soc: Unable to set soc link for FTDDRII030\n);
+abort();
+}
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftddrii030.c b/hw/ftddrii030.c
new file mode 100644
index 000..158db1f
--- /dev/null
+++ b/hw/ftddrii030.c
@@ -0,0 +1,192 @@
+/*
+ * Faraday DDRII controller
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This code is licensed under GNU GPL v2+
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include hw/devices.h
+#include sysemu/sysemu.h
+
+#include hw/faraday.h
+
+#define REG_MCR 0x00/* memory configuration register */
+#define REG_MSR 0x04/* memory status register */
+#define REG_REVR0x50/* revision register */
+
+#define MSR_INIT_OK BIT(8) /* initialization finished */
+#define MSR_CMD_MRS BIT(0) /* start MRS command (init. seq.) */
+
+#define CFG_REGSIZE (REG_REVR / 4)
+
+#define TYPE_FTDDRII030 ftddrii030
+
+typedef struct Ftddrii030State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+
+FaradaySoCState *soc;
+
+/* HW register cache */
+uint32_t regs[CFG_REGSIZE];
+} Ftddrii030State;
+
+#define FTDDRII030(obj) \
+OBJECT_CHECK(Ftddrii030State, obj, TYPE_FTDDRII030)
+
+#define DDR_REG32(s, off) \
+((s)-regs[(off) / 4])
+
+static uint64_t
+ftddrii030_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+Ftddrii030State *s = FTDDRII030(opaque);
+FaradaySoCState *soc = s-soc;
+uint64_t ret = 0;
+
+if (soc-ram_visible) {
+DDR_REG32(s, REG_MSR) |= MSR_INIT_OK;
+} else {
+DDR_REG32(s, REG_MSR) = ~MSR_INIT_OK;
+}
+
+switch (addr) {
+case REG_MCR ... REG_REVR - 4:
+ret = DDR_REG32(s, addr);
+break;
+case REG_REVR:
+ret = 0x100;/* rev. = 0.1.0 */
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ftddrii030: undefined memory access@%# HWADDR_PRIx \n, addr);
+break;
+}
+
+return ret;
+}
+
+static void
+ftddrii030_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+Ftddrii030State *s = FTDDRII030(opaque);
+FaradaySoCState *soc = s-soc;
+
+switch (addr) {
+case REG_MCR:
+DDR_REG32(s, addr) = (uint32_t)val 0x;
+break;
+case REG_MSR:
+if (!soc-ram_visible (val MSR_CMD_MRS)) {
+val = ~MSR_CMD_MRS;
+faraday_soc_ram_setup(soc, true);
+}
+DDR_REG32(s, addr) = (uint32_t)val;
+break;
+/* SDRAM Timing, ECC ...etc. */
+case REG_MSR + 4 ... REG_REVR - 4:
+DDR_REG32(s, addr) = (uint32_t)val;
+break;
+case REG_REVR:
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ftddrii030: undefined memory access@%# HWADDR_PRIx \n, addr);
+break;
+}
+}
+
+static const MemoryRegionOps mmio_ops = {
+.read = ftddrii030_mem_read,
+.write = ftddrii030_mem_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+.valid = {
+.min_access_size = 4,
+.max_access_size = 4,
+}
+};
+
+static void ftddrii030_reset(DeviceState *ds)
+{
+Ftddrii030State *s = FTDDRII030(SYS_BUS_DEVICE(ds));
+Error *local_errp = NULL;
+
+s-soc = FARADAY_SOC(object_property_get_link(OBJECT(s),
+ soc,
+ local_errp));
+if (local_errp) {
+fprintf(stderr, ftahbc020: Unable to get soc link\n);
+abort();
+}
+
[Qemu-devel] [PATCH v9 23/24] hw/arm: add FTTMR010 timer support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTTMR010 provides three independent sets of sub-timers.
Two match registers are provided for each sub-timer, whenever
the value of the match registers equals any one value of the
sub-timers, the timer interrupt will be immediately triggered.
And it would also issue an interrupt when an overflow occurs.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |2 +-
hw/arm/ftplat_a369.c |8 +
hw/fttmr010.c| 449 ++
hw/fttmr010.h| 39 +
4 files changed, 497 insertions(+), 1 deletion(-)
create mode 100644 hw/fttmr010.c
create mode 100644 hw/fttmr010.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 4697a76..bcfb70a 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -27,7 +27,7 @@ obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o fti2c010.o \
ftssp010.o ftgmac100.o ftlcdc200.o fttsc010.o ftsdc010.o \
-ftmac110.o
+ftmac110.o fttmr010.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369.c b/hw/arm/ftplat_a369.c
index 1b3e3cd..f22e2ca 100644
--- a/hw/arm/ftplat_a369.c
+++ b/hw/arm/ftplat_a369.c
@@ -117,6 +117,14 @@ static void a369_board_init(QEMUMachineInitArgs *args)
ftmac110_init(nd_table[1], 0xC010, s-pic[5]);
}
+/* Timer: FTTMR010 */
+ds = qdev_create(NULL, fttmr010);
+qdev_prop_set_uint32(ds, freq, 33 * 100);
+qdev_init_nofail(ds);
+sysbus_mmio_map(SYS_BUS_DEVICE(ds), 0, 0xC020);
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 1, s-pic[6]);
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 2, s-pic[7]);
+
/* System start-up */
if (args-kernel_filename) {
diff --git a/hw/fttmr010.c b/hw/fttmr010.c
new file mode 100644
index 000..ccb0c6a
--- /dev/null
+++ b/hw/fttmr010.c
@@ -0,0 +1,449 @@
+/*
+ * Faraday FTTMR010 Timer.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This code is licensed under GNU GPL v2+.
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include qemu/timer.h
+#include sysemu/sysemu.h
+
+#include hw/fttmr010.h
+
+#define TYPE_FTTMR010 fttmr010
+#define TYPE_FTTMR010_TIMER fttmr010_timer
+
+typedef struct Fttmr010State Fttmr010State;
+
+typedef struct Fttmr010Timer {
+int id;
+int up;
+Fttmr010State *chip;
+qemu_irq irq;
+QEMUTimer *qtimer;
+uint64_t start;
+uint32_t intr_match1:1;
+uint32_t intr_match2:1;
+
+/* HW register caches */
+uint64_t counter;
+uint64_t reload;
+uint32_t match1;
+uint32_t match2;
+
+} Fttmr010Timer;
+
+struct Fttmr010State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+qemu_irq irq;
+Fttmr010Timer timer[3];
+uint32_t freq;/* desired source clock */
+uint64_t step;/* get_ticks_per_sec() / freq */
+
+/* HW register caches */
+uint32_t cr;
+uint32_t isr;
+uint32_t imr;
+};
+
+#define FTTMR010(obj) \
+OBJECT_CHECK(Fttmr010State, obj, TYPE_FTTMR010)
+
+static void fttmr010_timer_restart(Fttmr010Timer *t)
+{
+Fttmr010State *s = t-chip;
+uint64_t interval;
+int pending = 0;
+
+t-intr_match1 = 0;
+t-intr_match2 = 0;
+
+/* check match1 */
+if (t-up t-match1 = t-counter) {
+t-intr_match1 = 1;
+}
+if (!t-up t-match1 = t-counter) {
+t-intr_match1 = 1;
+}
+if (t-match1 == t-counter) {
+s-isr |= ISR_MATCH1(t-id);
+++pending;
+}
+
+/* check match2 */
+if (t-up t-match2 = t-counter) {
+t-intr_match2 = 1;
+}
+if (!t-up t-match2 = t-counter) {
+t-intr_match2 = 1;
+}
+if (t-match2 == t-counter) {
+s-isr |= ISR_MATCH2(t-id);
+++pending;
+}
+
+/* determine delay interval */
+if (t-up) {
+if ((t-match1 t-counter) (t-match2 t-counter)) {
+interval = MIN(t-match1, t-match2) - t-counter;
+} else if (t-match1 t-counter) {
+interval = t-match1 - t-counter;
+} else if (t-match2 t-reload) {
+interval = t-match2 - t-counter;
+} else {
+interval = 0xULL - t-counter;
+}
+} else {
+if ((t-match1 t-counter) (t-match2 t-counter)) {
+interval = t-counter - MAX(t-match1, t-match2);
+} else if (t-match1 t-reload) {
+interval = t-counter - t-match1;
+} else if (t-match2 t-reload) {
+interval = t-counter - t-match2;
+} else {
+interval = t-counter;
+}
+}
+
+if (pending) {
+qemu_irq_pulse(s-irq);
+qemu_irq_pulse(t-irq);
+}
+t-start = qemu_get_clock_ns(vm_clock);
+qemu_mod_timer(t-qtimer, t-start +
[Qemu-devel] [PATCH v9 24/24] hw/arm: add FTSPI020 SPI flash controller support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSPI020 is an integrated SPI Flash controller
which supports up to 4 flash chips.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |2 +-
hw/arm/ftplat_a369.c | 16 +++
hw/ftspi020.c| 341 ++
hw/ftspi020.h| 81
4 files changed, 439 insertions(+), 1 deletion(-)
create mode 100644 hw/ftspi020.c
create mode 100644 hw/ftspi020.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index bcfb70a..a34ca41 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -27,7 +27,7 @@ obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o fti2c010.o \
ftssp010.o ftgmac100.o ftlcdc200.o fttsc010.o ftsdc010.o \
-ftmac110.o fttmr010.o
+ftmac110.o fttmr010.o ftspi020.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369.c b/hw/arm/ftplat_a369.c
index f22e2ca..77cd44d 100644
--- a/hw/arm/ftplat_a369.c
+++ b/hw/arm/ftplat_a369.c
@@ -125,6 +125,22 @@ static void a369_board_init(QEMUMachineInitArgs *args)
sysbus_connect_irq(SYS_BUS_DEVICE(ds), 1, s-pic[6]);
sysbus_connect_irq(SYS_BUS_DEVICE(ds), 2, s-pic[7]);
+/* SPI: FTSPI020 */
+ds = sysbus_create_simple(ftspi020, 0xC000, s-pic[4]);
+s-spi_fl[0] = ds;
+
+/* Attach the spi flash to ftspi020.0 */
+nr_flash = 1;
+for (i = 0; i nr_flash; i++) {
+SSIBus *ssi = (SSIBus *)qdev_get_child_bus(s-spi_fl[0], spi);
+DeviceState *fl = ssi_create_slave_no_init(ssi, w25q64);
+qemu_irq cs_line;
+
+qdev_init_nofail(fl);
+cs_line = qdev_get_gpio_in(fl, 0);
+sysbus_connect_irq(SYS_BUS_DEVICE(s-spi_fl[0]), i + 1, cs_line);
+}
+
/* System start-up */
if (args-kernel_filename) {
diff --git a/hw/ftspi020.c b/hw/ftspi020.c
new file mode 100644
index 000..a7253bd
--- /dev/null
+++ b/hw/ftspi020.c
@@ -0,0 +1,341 @@
+/*
+ * Faraday FTSPI020 Flash Controller
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This code is licensed under GNU GPL v2+.
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include hw/ssi.h
+#include sysemu/sysemu.h
+
+#include hw/ftspi020.h
+
+#define TYPE_FTSPI020 ftspi020
+
+typedef struct Ftspi020State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+qemu_irq irq;
+
+/* DMA hardware handshake */
+qemu_irq req;
+
+SSIBus *spi;
+qemu_irq *cs_lines;
+
+int wip;/* SPI Flash Status: Write In Progress BIT shift */
+
+/* HW register caches */
+uint32_t cmd[4];
+uint32_t ctrl;
+uint32_t timing;
+uint32_t icr;
+uint32_t isr;
+uint32_t rdsr;
+} Ftspi020State;
+
+#define FTSPI020(obj) \
+OBJECT_CHECK(Ftspi020State, obj, TYPE_FTSPI020)
+
+static void ftspi020_update_irq(Ftspi020State *s)
+{
+qemu_set_irq(s-irq, s-isr ? 1 : 0);
+}
+
+static void ftspi020_handle_ack(void *opaque, int line, int level)
+{
+Ftspi020State *s = FTSPI020(opaque);
+
+if (!(s-icr ICR_DMA)) {
+return;
+}
+
+if (level) {
+qemu_set_irq(s-req, 0);
+} else if (s-cmd[2]) {
+qemu_set_irq(s-req, 1);
+}
+}
+
+static int ftspi020_do_command(Ftspi020State *s)
+{
+uint32_t cs = extract32(s-cmd[3], 8, 2);
+uint32_t cmd = extract32(s-cmd[3], 24, 8);
+uint32_t ilen = extract32(s-cmd[1], 24, 2);
+uint32_t alen = extract32(s-cmd[1], 0, 3);
+uint32_t dcyc = extract32(s-cmd[1], 16, 8);
+
+if (dcyc % 8) {
+fprintf(stderr, ftspi020: bad dummy clock (%u) to QEMU\n, dcyc);
+abort();
+}
+
+/* activate the spi flash */
+qemu_set_irq(s-cs_lines[cs], 0);
+
+/* if it's a SPI flash READ_STATUS command */
+if ((s-cmd[3] (CMD3_RDSR | CMD3_WRITE)) == CMD3_RDSR) {
+uint32_t rdsr;
+
+ssi_transfer(s-spi, cmd);
+do {
+rdsr = ssi_transfer(s-spi, 0x00);
+if (s-cmd[3] CMD3_RDSR_SW) {
+break;
+}
+} while (rdsr (1 s-wip));
+s-rdsr = rdsr;
+} else {
+/* otherwise */
+int i;
+
+ilen = MIN(ilen, 2);
+alen = MIN(alen, 4);
+
+/* command cycles */
+for (i = 0; i ilen; ++i) {
+ssi_transfer(s-spi, cmd);
+}
+/* address cycles */
+for (i = alen - 1; i = 0; --i) {
+ssi_transfer(s-spi, extract32(s-cmd[0], i * 8, 8));
+}
+/* dummy cycles */
+for (i = 0; i (dcyc 3); ++i) {
+ssi_transfer(s-spi, 0x00);
+}
+}
+
+if (!s-cmd[2]) {
+qemu_set_irq(s-cs_lines[cs], 1);
+} else if (s-icr ICR_DMA) {
+qemu_set_irq(s-req, 1);
+}
+
+if (s-cmd[3] CMD3_INTR) {
+s-isr
[Qemu-devel] [PATCH v9 21/24] hw/arm: add FTSDC010 MMC/SD controller support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSDC010 is a simple MMC/SD host controller and
many of its registers are similar to Arm PrimeCell PL181.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |7 +
hw/ftsdc010.c | 359 +++
hw/ftsdc010.h | 88
4 files changed, 455 insertions(+), 1 deletion(-)
create mode 100644 hw/ftsdc010.c
create mode 100644 hw/ftsdc010.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index d163239..93e94db 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -26,7 +26,7 @@ obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o fti2c010.o \
-ftssp010.o ftgmac100.o ftlcdc200.o fttsc010.o
+ftssp010.o ftgmac100.o ftlcdc200.o fttsc010.o ftsdc010.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 231ea1e..21387df 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -241,6 +241,13 @@ static void a369soc_chip_init(FaradaySoCState *s)
/* fttsc010 */
sysbus_create_simple(fttsc010, 0x9240, s-pic[19]);
+
+/* ftsdc010 */
+ds = sysbus_create_simple(ftsdc010, 0x9060, s-pic[39]);
+ack = qdev_get_gpio_in(ds, 0);
+req = qdev_get_gpio_in(s-hdma[0], 13);
+qdev_connect_gpio_out(s-hdma[0], 13, ack);
+qdev_connect_gpio_out(ds, 0, req);
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftsdc010.c b/hw/ftsdc010.c
new file mode 100644
index 000..8b93fa6
--- /dev/null
+++ b/hw/ftsdc010.c
@@ -0,0 +1,359 @@
+/*
+ * QEMU model of the FTSDC010 MMC/SD Host Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ */
+
+#include hw/sysbus.h
+#include hw/sd.h
+#include sysemu/sysemu.h
+#include sysemu/blockdev.h
+
+#include qemu/bitops.h
+#include hw/ftsdc010.h
+
+#define TYPE_FTSDC010 ftsdc010
+
+typedef struct Ftsdc010State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+SDState *card;
+qemu_irq irq;
+
+/* DMA hardware handshake */
+qemu_irq req;
+
+uint32_t datacnt;
+
+/* HW register cache */
+uint32_t cmd;
+uint32_t arg;
+uint32_t rsp[4];
+uint32_t rspcmd;
+uint32_t dcr;
+uint32_t dtr;
+uint32_t dlr;
+uint32_t status;
+uint32_t ier;
+uint32_t pwr;
+uint32_t clk;
+} Ftsdc010State;
+
+#define FTSDC010(obj) \
+OBJECT_CHECK(Ftsdc010State, obj, TYPE_FTSDC010)
+
+static void ftsdc010_update_irq(Ftsdc010State *s)
+{
+qemu_set_irq(s-irq, !!(s-ier s-status));
+}
+
+static void ftsdc010_handle_ack(void *opaque, int line, int level)
+{
+Ftsdc010State *s = FTSDC010(opaque);
+
+if (!(s-dcr DCR_DMA)) {
+return;
+}
+
+if (level) {
+qemu_set_irq(s-req, 0);
+} else if (s-datacnt) {
+qemu_set_irq(s-req, 1);
+}
+}
+
+static void ftsdc010_send_command(Ftsdc010State *s)
+{
+SDRequest request;
+uint8_t response[16];
+int rlen;
+
+request.cmd = s-cmd CMD_IDX;
+request.arg = s-arg;
+
+rlen = sd_do_command(s-card, request, response);
+if (rlen 0) {
+goto error;
+}
+if (s-cmd CMD_WAIT_RSP) {
+#define RWORD(n) ((response[n] 24) | (response[n + 1] 16) \
+ | (response[n + 2] 8) | response[n + 3])
+if (rlen == 0 || (rlen == 4 (s-cmd CMD_LONG_RSP))) {
+goto error;
+}
+if (rlen != 4 rlen != 16) {
+goto error;
+}
+if (rlen == 4) {
+s-rsp[0] = RWORD(0);
+s-rsp[1] = s-rsp[2] = s-rsp[3] = 0;
+} else {
+s-rsp[3] = RWORD(0);
+s-rsp[2] = RWORD(4);
+s-rsp[1] = RWORD(8);
+s-rsp[0] = RWORD(12) ~1;
+}
+s-rspcmd = (s-cmd CMD_IDX);
+s-rspcmd |= (s-cmd CMD_APP) ? RSP_CMDAPP : 0;
+s-status |= SR_RSP;
+#undef RWORD
+} else {
+s-status |= SR_CMD;
+}
+
+if ((s-dcr DCR_DMA) s-datacnt) {
+qemu_set_irq(s-req, 1);
+}
+
+return;
+
+error:
+s-status |= SR_RSP_TIMEOUT;
+}
+
+static void ftsdc010_chip_reset(Ftsdc010State *s)
+{
+s-cmd = 0;
+s-arg = 0;
+s-rsp[0] = 0;
+s-rsp[1] = 0;
+s-rsp[2] = 0;
+s-rsp[3] = 0;
+s-rspcmd = 0;
+s-dcr = 0;
+s-dtr = 0;
+s-dlr = 0;
+s-datacnt = 0;
+s-status = ~(SR_CARD_REMOVED | SR_WPROT);
+s-status |= SR_TXRDY | SR_RXRDY;
+s-ier = 0;
+s-pwr = 0;
+s-clk = 0;
+}
+
+static uint64_t ftsdc010_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+Ftsdc010State *s = FTSDC010(opaque);
+
[Qemu-devel] [PATCH v9 02/24] hw/arm: add Faraday a369 SoC platform support
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday A369 EVB is a Faraday SoC platform evalution board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +
hw/arm/ftplat_a369.c| 96 +++
hw/arm/ftplat_a369kpd.c | 235 +++
hw/arm/ftplat_a369scu.c | 186 +
hw/arm/ftplat_a369soc.c | 155 +++
hw/faraday.h| 124 +
hw/ftkbc010.h | 44 +
7 files changed, 842 insertions(+)
create mode 100644 hw/arm/ftplat_a369.c
create mode 100644 hw/arm/ftplat_a369kpd.c
create mode 100644 hw/arm/ftplat_a369scu.c
create mode 100644 hw/arm/ftplat_a369soc.c
create mode 100644 hw/faraday.h
create mode 100644 hw/ftkbc010.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index f5f7d0e..09217c6 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -34,3 +34,5 @@ obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-y += omap1.o omap2.o
+
+obj-y += ftplat_a369.o ftplat_a369soc.o ftplat_a369scu.o ftplat_a369kpd.o
diff --git a/hw/arm/ftplat_a369.c b/hw/arm/ftplat_a369.c
new file mode 100644
index 000..6f00c82
--- /dev/null
+++ b/hw/arm/ftplat_a369.c
@@ -0,0 +1,96 @@
+/*
+ * Faraday A369 Evalution Board
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This code is licensed under GNU GPL v2+.
+ */
+
+#include hw/sysbus.h
+#include hw/arm-misc.h
+#include hw/devices.h
+#include hw/i2c.h
+#include hw/boards.h
+#include hw/ssi.h
+#include net/net.h
+#include sysemu/sysemu.h
+#include exec/address-spaces.h
+
+#include hw/faraday.h
+
+/* Board init. */
+
+static void a369_board_init(QEMUMachineInitArgs *args)
+{
+ARMCPU *cpu;
+DeviceState *ds;
+FaradaySoCState *s;
+
+if (!args-cpu_model) {
+args-cpu_model = fa626te;
+}
+
+if (!args-ram_size) {
+args-ram_size = 512 20;
+}
+
+/* CPU */
+cpu = cpu_arm_init(args-cpu_model);
+if (!cpu) {
+fprintf(stderr, a369: Unable to find CPU definition\n);
+abort();
+}
+
+/* SoC */
+ds = qdev_create(NULL, TYPE_FARADAY_SOC);
+s = FARADAY_SOC(ds);
+/* Setup QOM path for the SoC object (i.e. /machine/faraday.soc) */
+object_property_add_child(qdev_get_machine(),
+ TYPE_FARADAY_SOC,
+ OBJECT(ds),
+ NULL);
+s-cpu_pic = arm_pic_init_cpu(cpu);
+s-as = get_system_memory();
+s-ram = g_new0(MemoryRegion, 1);
+memory_region_init_ram(s-ram, TYPE_FARADAY_SOC .ram, args-ram_size);
+vmstate_register_ram_global(s-ram);
+qdev_init_nofail(ds);
+
+/* System start-up */
+
+if (args-kernel_filename) {
+struct arm_boot_info *bi = g_new0(struct arm_boot_info, 1);
+
+s-ram_boot = true;
+
+faraday_soc_ram_setup(s, true);
+
+faraday_soc_ahb_remap(s, true);
+
+/* Boot Info */
+bi-ram_size = args-ram_size;
+bi-kernel_filename = args-kernel_filename;
+bi-kernel_cmdline = args-kernel_cmdline;
+bi-initrd_filename = args-initrd_filename;
+bi-board_id = 0x3369;
+arm_load_kernel(cpu, bi);
+} else if (!drive_get(IF_PFLASH, 0, 0)) {
+fprintf(stderr, a369: Unable to load ROM image!\n);
+abort();
+}
+}
+
+static QEMUMachine a369_machine = {
+.name = a369,
+.desc = Faraday A369 (fa626te),
+.init = a369_board_init,
+DEFAULT_MACHINE_OPTIONS,
+};
+
+static void a369_machine_init(void)
+{
+qemu_register_machine(a369_machine);
+}
+
+machine_init(a369_machine_init);
diff --git a/hw/arm/ftplat_a369kpd.c b/hw/arm/ftplat_a369kpd.c
new file mode 100644
index 000..6d42dfa
--- /dev/null
+++ b/hw/arm/ftplat_a369kpd.c
@@ -0,0 +1,235 @@
+/*
+ * Faraday FTKBC010 emulator for A369.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * In A369 EVB, the FTKBC010 is configured as a keypad controller.
+ * It acts like a group of hard wired buttons on the board, each of them
+ * is monitored by the FTKBC010, and coordinated as (x, y).
+ * However there is a pinmux issue in A369 EVB, the Y-axis usually
+ * malfunctioned, so there are only 3 button emulated here.
+ *
+ * This code is licensed under GNU GPL v2+
+ */
+
+#include hw/hw.h
+#include hw/sysbus.h
+#include hw/devices.h
+#include ui/console.h
+#include sysemu/sysemu.h
+
+#include hw/ftkbc010.h
+
+#define CFG_REGSIZE (0x3c / 4)
+
+/* Key codes */
+#define KEYCODE_ESC 1
+#define KEYCODE_BACKSPACE 14
+#define KEYCODE_ENTER 28
+#define KEYCODE_SPACE 57
+#define KEYCODE_MENU139/* Menu
Re: [Qemu-devel] [PULL 0/2] Block patches
On 03/25/2013 05:00 AM, Stefan Hajnoczi wrote: This tiny pull request contains build fixes for a regression introduced in the last pull request. Kevin and I investigated to find out why these build failures were missed. Both my buildslave and Kevin's workstation did not have the rbd libraries installed so block/rbd.c was not built. The buildslave now has the missing libraries and will warn us if block/rbd.c breaks again. Kevin has also installed the package so his local builds exercise the code. The mingw build is already failing in buildbot due to an unrelated issue. The bdrv_file_open() prototype warning was not spotted amongst all the other warnings. Series: Reviewed-by: Eric Blake ebl...@redhat.com -- Eric Blake eblake redhat com+1-919-301-3266 Libvirt virtualization library http://libvirt.org signature.asc Description: OpenPGP digital signature
[Qemu-devel] [PATCH v9 22/24] hw/arm: add FTMAC110 10/100Mbps ethernet support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps specifications.
Its DMA controller handles all data transfers between system memory
and on-chip memories.
It supports half-word data transfer for Linux. However it has a weird DMA
alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: Invalid (It means 0x0, 0x4, 0x8, 0xC are invalid)
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |3 +-
hw/arm/ftplat_a369.c |7 +
hw/faraday.h |3 +
hw/ftmac110.c| 665 ++
hw/ftmac110.h| 166 +
5 files changed, 843 insertions(+), 1 deletion(-)
create mode 100644 hw/ftmac110.c
create mode 100644 hw/ftmac110.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 93e94db..4697a76 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -26,7 +26,8 @@ obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o fti2c010.o \
-ftssp010.o ftgmac100.o ftlcdc200.o fttsc010.o ftsdc010.o
+ftssp010.o ftgmac100.o ftlcdc200.o fttsc010.o ftsdc010.o \
+ftmac110.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369.c b/hw/arm/ftplat_a369.c
index 922fb55..1b3e3cd 100644
--- a/hw/arm/ftplat_a369.c
+++ b/hw/arm/ftplat_a369.c
@@ -110,6 +110,13 @@ static void a369_board_init(QEMUMachineInitArgs *args)
s-i2s[0]);
}
+/* External AHB devices */
+
+/* Ethernet: FTMAC110 */
+if (nb_nics 1) {
+ftmac110_init(nd_table[1], 0xC010, s-pic[5]);
+}
+
/* System start-up */
if (args-kernel_filename) {
diff --git a/hw/faraday.h b/hw/faraday.h
index 068b799..ba7ea0e 100644
--- a/hw/faraday.h
+++ b/hw/faraday.h
@@ -127,4 +127,7 @@ void ftssp010_i2s_data_req(void *opaque, int tx, int rx);
/* ftgmac100.c */
void ftgmac100_init(NICInfo *nd, uint32_t base, qemu_irq irq);
+/* ftmac110.c */
+void ftmac110_init(NICInfo *nd, uint32_t base, qemu_irq irq);
+
#endif
diff --git a/hw/ftmac110.c b/hw/ftmac110.c
new file mode 100644
index 000..de1164d
--- /dev/null
+++ b/hw/ftmac110.c
@@ -0,0 +1,665 @@
+/*
+ * QEMU model of the FTMAC110 Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ */
+
+/***/
+/* FTMAC110 DMA design issue */
+/* Dante Su 2010.02.03 */
+/* */
+/* The DMA engine has a weird restriction that its Rx DMA engine */
+/* accepts only 16-bits aligned address, 32-bits aligned is still */
+/* invalid. However this restriction does not apply to Tx DMA. */
+/* Conclusion: */
+/* (1) Tx DMA Buffer Address: */
+/* 1 bytes aligned: Invalid*/
+/* 2 bytes aligned: O.K*/
+/* 4 bytes aligned: O.K (- u-boot ZeroCopy is possible) */
+/* (2) Rx DMA Buffer Address: */
+/* 1 bytes aligned: Invalid*/
+/* 2 bytes aligned: O.K*/
+/* 4 bytes aligned: Invalid*/
+/***/
+
+#include hw/sysbus.h
+#include qemu/timer.h
+#include sysemu/sysemu.h
+#include sysemu/dma.h
+#include net/net.h
+
+#include hw/faraday.h
+#include hw/ftmac110.h
+
+#ifndef DEBUG
+#define DEBUG 0
+#endif
+
+#define DPRINTF(fmt, ...) \
+do { \
+if (DEBUG) { \
+fprintf(stderr, fmt , ## __VA_ARGS__); \
+} \
+} while (0)
+
+#define TYPE_FTMAC110 ftmac110
+
+#define CFG_MAXFRMLEN 1536/* Max. frame length */
+#define CFG_REGSIZE (0x100 / 4)
+
+typedef struct Ftmac110State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion mmio;
+
+QEMUBH *bh;
+qemu_irq irq;
+NICState *nic;
+NICConf conf;
+DMAContext *dma;
+QEMUTimer *qtimer;
+
+bool phycr_rd;
+
+struct {
+uint8_t buf[CFG_MAXFRMLEN];
+uint32_t len;
+} txbuff;
+
+uint32_t tx_idx;
+uint32_t rx_idx;
+
+/* HW register cache */
+uint32_t
Re: [Qemu-devel] [PATCH 07/10] versatile_pci: Implement the correct PCI IRQ mapping
On 25 March 2013 12:12, Michael S. Tsirkin m...@redhat.com wrote: On Sun, Mar 24, 2013 at 11:32:37AM +, Peter Maydell wrote: +return (PCI_SLOT(d-devfn) + irq_num - 2) % PCI_NUM_PINS; It seems this can be a bit shorter: pci_swizzle_map_irq_fn(d, irq_num - 2) and below irq_num - 1 ? Yes (though does pci_swizzle_map_irq_fn() accept negative pin values deliberately or by fluke? it might be better to use irq_num + 2 / + 3 , maybe.) -- PMM
[Qemu-devel] [PATCH v9 17/24] qemu/bitops.h: add the bit ordering reversal functions
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
include/qemu/bitops.h | 59 -
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index affcc96..64cbb04 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -3,7 +3,8 @@
*
* Copyright (C) 2010 Corentin Chary corentin.ch...@gmail.com
*
- * Mostly inspired by (stolen from) linux/bitmap.h and linux/bitops.h
+ * Mostly inspired by (stolen from) linux/bitmap.h, linux/bitops.h
+ * and linux/bitrev.h
*
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
* See the COPYING.LIB file in the top-level directory.
@@ -273,4 +274,60 @@ static inline uint64_t deposit64(uint64_t value, int
start, int length,
return (value ~mask) | ((fieldval start) mask);
}
+/**
+ * bitrev8:
+ * @value: the value to reverse bit ordering from
+ *
+ * Reverse the 8 bit input @value
+ *
+ * Returns: the input @value with reversed bit ordering
+ */
+static inline uint8_t bitrev8(uint8_t value)
+{
+value = (value 0xF0) 4 | (value 0x0F) 4;
+value = (value 0xCC) 2 | (value 0x33) 2;
+value = (value 0xAA) 1 | (value 0x55) 1;
+return value;
+}
+
+/**
+ * bitrev16:
+ * @value: the value to reverse bit ordering from
+ *
+ * Reverse the 16 bit input @value
+ *
+ * Returns: the input @value with reversed bit ordering
+ */
+static inline uint16_t bitrev16(uint16_t value)
+{
+return (bitrev8(value 0xff) 8) | bitrev8(value 8);
+}
+
+/**
+ * bitrev32:
+ * @value: the value to reverse bit ordering from
+ *
+ * Reverse the 32 bit input @value
+ *
+ * Returns: the input @value with reversed bit ordering
+ */
+static inline uint32_t bitrev32(uint32_t value)
+{
+return (bitrev16(value 0x) 16) | bitrev16(value 16);
+}
+
+/**
+ * bitrev64:
+ * @value: the value to reverse bit ordering from
+ *
+ * Reverse the 64 bit input @value
+ *
+ * Returns: the input @value with reversed bit ordering
+ */
+static inline uint64_t bitrev64(uint64_t value)
+{
+return ((uint64_t)bitrev32(value 0xULL) 32)
+| (uint64_t)bitrev32(value 32);
+}
+
#endif
--
1.7.9.5
[Qemu-devel] [PATCH v9 10/24] hw/arm: add FTDMAC020 AHB DMA support
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTDMAC020 provides eight configurable
channels for the memory-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and peripheral-to-memory transfers.
Each DMA channel supports chain transfer and can be programmed
to one of the 16 handshaking channels in the hardware handshake mode.
The main function of the hardware handshake mode is to provide an
indication of the device status. Users can also disable the hardware
handshake mode by programming the register when a DMA transfer is not
necessary of referring to the handshaking channels.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c | 14 ++
hw/ftdmac020.c | 599 +++
hw/ftdmac020.h | 107 +
4 files changed, 721 insertions(+), 1 deletion(-)
create mode 100644 hw/ftdmac020.c
create mode 100644 hw/ftdmac020.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 6a41b21..6510c51 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -25,7 +25,7 @@ obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
-ftrtc011.o
+ftrtc011.o ftdmac020.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index bd696c4..59e2c61 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -168,6 +168,20 @@ static void a369soc_chip_init(FaradaySoCState *s)
sysbus_connect_irq(SYS_BUS_DEVICE(ds), 3, s-pic[44]);
/* Hour (Edge) */
sysbus_connect_irq(SYS_BUS_DEVICE(ds), 4, s-pic[45]);
+
+/* ftdmac020 */
+s-hdma[0] = sysbus_create_varargs(ftdmac020,
+ 0x9030,
+ s-pic[0], /* ALL (NC in A369) */
+ s-pic[15], /* TC */
+ s-pic[16], /* ERR */
+ NULL);
+s-hdma[1] = sysbus_create_varargs(ftdmac020,
+ 0x9610,
+ s-pic[0], /* ALL (NC in A369) */
+ s-pic[17], /* TC */
+ s-pic[18], /* ERR */
+ NULL);
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftdmac020.c b/hw/ftdmac020.c
new file mode 100644
index 000..81b49b2
--- /dev/null
+++ b/hw/ftdmac020.c
@@ -0,0 +1,599 @@
+/*
+ * QEMU model of the FTDMAC020 DMA Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ *
+ * Note: The FTDMAC020 descending address mode is not implemented.
+ */
+
+#include hw/sysbus.h
+#include sysemu/dma.h
+#include sysemu/sysemu.h
+#include sysemu/blockdev.h
+
+#include hw/ftdmac020.h
+
+#define TYPE_FTDMAC020ftdmac020
+
+enum ftdmac020_irqpin {
+IRQ_ALL = 0,
+IRQ_TC,
+IRQ_ERR,
+};
+
+typedef struct Ftdmac020State Ftdmac020State;
+
+/**
+ * struct Ftdmac020LLD - hardware link list descriptor.
+ * @src: source physical address
+ * @dst: destination physical addr
+ * @next: phsical address to the next link list descriptor
+ * @ctrl: control field
+ * @size: transfer size
+ *
+ * should be word aligned
+ */
+typedef struct Ftdmac020LLD {
+uint32_t src;
+uint32_t dst;
+uint32_t next;
+uint32_t ctrl;
+uint32_t size;
+} Ftdmac020LLD;
+
+typedef struct Ftdmac020Chan {
+Ftdmac020State *chip;
+
+int id;
+int burst;
+int llp_cnt;
+int src_bw;
+int src_stride;
+int dst_bw;
+int dst_stride;
+
+/* HW register cache */
+uint32_t ccr;
+uint32_t cfg;
+uint32_t src;
+uint32_t dst;
+uint32_t llp;
+uint32_t len;
+} Ftdmac020Chan;
+
+typedef struct Ftdmac020State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+qemu_irq irq[3];
+
+Ftdmac020Chan chan[8];
+qemu_irq ack[16];
+uint32_t req;
+
+int busy;/* Busy Channel ID */
+int bh_owner;
+QEMUBH *bh;
+DMAContext *dma;
+
+/* HW register cache */
+uint32_t tcisr;
+uint32_t eaisr;
+uint32_t tcsr;
+uint32_t easr;
+uint32_t cesr;
+uint32_t cbsr;
+uint32_t csr;
+uint32_t sync;
+} Ftdmac020State;
+
+#define FTDMAC020(obj) \
+OBJECT_CHECK(Ftdmac020State, obj, TYPE_FTDMAC020)
+
+static void ftdmac020_update_irq(Ftdmac020State *s)
+{
+uint32_t tc, err;
+
+/* 1. Checking TC interrupts */
+tc = s-tcisr 0xff;
+qemu_set_irq(s-irq[IRQ_TC], tc ? 1 : 0);
+
+/* 2. Checking Error/Abort interrupts */
+err = s-eaisr 0x00ff00ff;
+qemu_set_irq(s-irq[IRQ_ERR], err ? 1 : 0);
+
+
[Qemu-devel] [PATCH v9 08/24] hw/arm: add FTRTC011 RTC timer support
From: Kuo-Jung Su dant...@faraday-tech.com
It provides separate second, minute, hour, and day counters. The second
counter is toggled each second, the minute counter is toggled each minute,
the hour counter is toggled each hour, and the day counter is toggled each day.
The FTRTC011 provides a programmable auto-alarm function. When the second
auto-alarm function is turned on, the RTC will automatically trigger an
interrupt each second. The automatic minute and hour alarms can be turned on
as well.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|3 +-
hw/arm/ftplat_a369soc.c | 18 +++
hw/ftrtc011.c | 387 +++
hw/ftrtc011.h | 53 +++
4 files changed, 460 insertions(+), 1 deletion(-)
create mode 100644 hw/ftrtc011.c
create mode 100644 hw/ftrtc011.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 22f0c64..6a41b21 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -24,7 +24,8 @@ obj-y += framebuffer.o
obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
-obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o
+obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
+ftrtc011.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 56f0920..bd696c4 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -150,6 +150,24 @@ static void a369soc_chip_init(FaradaySoCState *s)
/* ftwdt010 */
sysbus_create_simple(ftwdt010, 0x9220, s-pic[46]);
+
+/* ftrtc011 */
+ds = qdev_create(NULL, ftrtc011);
+/* Setup QOM path for QTest */
+object_property_add_child(OBJECT(s),
+ ftrtc011,
+ OBJECT(ds),
+ NULL);
+qdev_init_nofail(ds);
+sysbus_mmio_map(SYS_BUS_DEVICE(ds), 0, 0x9210);
+/* Alarm (Edge) */
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 1, s-pic[42]);
+/* Second (Edge) */
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 2, s-pic[43]);
+/* Minute (Edge) */
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 3, s-pic[44]);
+/* Hour (Edge) */
+sysbus_connect_irq(SYS_BUS_DEVICE(ds), 4, s-pic[45]);
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftrtc011.c b/hw/ftrtc011.c
new file mode 100644
index 000..79b9021
--- /dev/null
+++ b/hw/ftrtc011.c
@@ -0,0 +1,387 @@
+/*
+ * QEMU model of the FTRTC011 RTC Timer
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ */
+
+#include hw/sysbus.h
+#include qemu/timer.h
+#include sysemu/sysemu.h
+
+#include hw/ftrtc011.h
+
+enum ftrtc011_irqpin {
+IRQ_ALARM_LEVEL = 0,
+IRQ_ALARM_EDGE,
+IRQ_SEC,
+IRQ_MIN,
+IRQ_HOUR,
+IRQ_DAY,
+};
+
+#define TYPE_FTRTC011 ftrtc011
+
+#define CFG_REGSIZE (0x3c / 4)
+
+typedef struct Ftrtc011State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion mmio;
+
+qemu_irq irq[6];
+
+QEMUTimer *qtimer;
+int64_t rtc_base;
+int64_t rtc_start;
+
+/* HW register caches */
+uint32_t regs[CFG_REGSIZE];
+} Ftrtc011State;
+
+#define FTRTC011(obj) \
+OBJECT_CHECK(Ftrtc011State, obj, TYPE_FTRTC011)
+
+#define RTC_REG32(s, off) \
+((s)-regs[(off) / 4])
+
+/* Update interrupts. */
+static void ftrtc011_update_irq(Ftrtc011State *s)
+{
+uint32_t mask = extract32(RTC_REG32(s, REG_CR), 1, 5)
+ RTC_REG32(s, REG_ISR);
+
+qemu_set_irq(s-irq[IRQ_ALARM_LEVEL], !!(mask ISR_ALARM));
+
+if (mask) {
+if (mask ISR_SEC) {
+qemu_irq_pulse(s-irq[IRQ_SEC]);
+}
+if (mask ISR_MIN) {
+qemu_irq_pulse(s-irq[IRQ_MIN]);
+}
+if (mask ISR_HOUR) {
+qemu_irq_pulse(s-irq[IRQ_HOUR]);
+}
+if (mask ISR_DAY) {
+qemu_irq_pulse(s-irq[IRQ_DAY]);
+}
+if (mask ISR_ALARM) {
+qemu_irq_pulse(s-irq[IRQ_ALARM_EDGE]);
+}
+}
+}
+
+static void ftrtc011_timer_rebase(Ftrtc011State *s)
+{
+int64_t ticks = get_ticks_per_sec();
+int64_t elapsed = RTC_REG32(s, REG_SEC)
++ (60LL * RTC_REG32(s, REG_MIN))
++ (3600LL * RTC_REG32(s, REG_HOUR))
++ (86400LL * RTC_REG32(s, REG_DAY));
+
+s-rtc_base = elapsed;
+s-rtc_start = qemu_get_clock_ns(rtc_clock);
+/* adjust to the beginning of the current second */
+s-rtc_start = s-rtc_start - (s-rtc_start % ticks);
+}
+
+static void ftrtc011_timer_update(Ftrtc011State *s)
+{
+int64_t elapsed;
+uint8_t sec, min, hr;
+uint32_t day;
+
+/* check if RTC is enabled */
+if (!(RTC_REG32(s, REG_CR) CR_EN)) {
+return;
+}
+
+/*
+ *
Re: [Qemu-devel] [PATCH 07/10] versatile_pci: Implement the correct PCI IRQ mapping
On Sun, Mar 24, 2013 at 11:32:37AM +, Peter Maydell wrote:
Implement the correct IRQ mapping for the Versatile PCI controller; it
differs between realview and versatile boards, but the previous QEMU
implementation was correct only for the first PCI card on a versatile
board, since we weren't swizzling IRQs based on the slot number.
Note that this change will break any uses of PCI on Linux kernels which
have an equivalent bug (since they have effectively only been tested
against QEMU, not real hardware). Unfortunately this currently means
all Linux kernels and all uses of versatilepb with a hard disk
since we default to a PCI SCSI controller.
We therefore provide a property for enabling the old broken IRQ mapping;
this can be enabled with the command line option:
-global versatile_pci.broken-irq-mapping=1
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/versatile_pci.c | 61
++--
1 file changed, 59 insertions(+), 2 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 576e619..7739f4c 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -26,6 +26,7 @@ typedef struct {
/* Constant for life of device: */
int realview;
+uint8_t broken_irq_mapping;
} PCIVPBState;
#define TYPE_VERSATILE_PCI versatile_pci
@@ -61,11 +62,52 @@ static const MemoryRegionOps pci_vpb_config_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
+static int pci_vpb_broken_map_irq(PCIDevice *d, int irq_num)
{
+/* Map IRQs as old and buggy versions of QEMU have done in the past;
+ * this is not how hardware behaves, and it will not work with guests
+ * which drive the hardware correctly, but it allows us to work with
+ * buggy Linux kernels which were written against the buggy QEMU.
+ */
return irq_num;
}
+static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
+{
+/* Slot to IRQ mapping for RealView Platform Baseboard 926 backplane
+ * nameslotIntAIntBIntCIntD
+ * A 31 IRQ28 IRQ29 IRQ30 IRQ27
+ * B 30 IRQ27 IRQ28 IRQ29 IRQ30
+ * C 29 IRQ30 IRQ27 IRQ28 IRQ29
+ * Slot C is for the host bridge; A and B the peripherals.
+ * Our output irqs 0..3 correspond to the baseboard's 27..30.
+ *
+ * This mapping function takes account of an oddity in the PB926
+ * board wiring, where the FPGA's P_nINTA input is connected to
+ * the INTB connection on the board PCI edge connector, P_nINTB
+ * is connected to INTC, and so on, so everything is one number
+ * further round from where you might expect.
+ */
+return (PCI_SLOT(d-devfn) + irq_num - 2) % PCI_NUM_PINS;
It seems this can be a bit shorter:
pci_swizzle_map_irq_fn(d, irq_num - 2)
and below irq_num - 1 ?
+}
+
+static int pci_vpb_rv_map_irq(PCIDevice *d, int irq_num)
+{
+/* Slot to IRQ mapping for RealView EB and PB1176 backplane
+ * nameslotIntAIntBIntCIntD
+ * A 31 IRQ50 IRQ51 IRQ48 IRQ49
+ * B 30 IRQ49 IRQ50 IRQ51 IRQ48
+ * C 29 IRQ48 IRQ49 IRQ50 IRQ51
+ * Slot C is for the host bridge; A and B the peripherals.
+ * Our output irqs 0..3 correspond to the baseboard's 48..51.
+ *
+ * The PB1176 and EB boards don't have the PB926 wiring oddity
+ * described above; P_nINTA connects to INTA, P_nINTB to INTB
+ * and so on, which is why this mapping function is different.
+ */
+return (PCI_SLOT(d-devfn) + irq_num - 1) % PCI_NUM_PINS;
+}
+
static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
{
qemu_irq *pic = opaque;
@@ -95,13 +137,22 @@ static void pci_vpb_realize(DeviceState *dev, Error
**errp)
{
PCIVPBState *s = PCI_VPB(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+pci_map_irq_fn mapfn;
int i;
for (i = 0; i 4; i++) {
sysbus_init_irq(sbd, s-irq[i]);
}
-pci_bus_irqs(s-pci_bus, pci_vpb_set_irq, pci_vpb_map_irq, s-irq, 4);
+if (s-broken_irq_mapping) {
+mapfn = pci_vpb_broken_map_irq;
+} else if (s-realview) {
+mapfn = pci_vpb_rv_map_irq;
+} else {
+mapfn = pci_vpb_map_irq;
+}
+
+pci_bus_irqs(s-pci_bus, pci_vpb_set_irq, mapfn, s-irq, 4);
/* ??? Register memory space. */
@@ -154,11 +205,17 @@ static const TypeInfo versatile_pci_host_info = {
.class_init= versatile_pci_host_class_init,
};
+static Property pci_vpb_properties[] = {
+DEFINE_PROP_UINT8(broken-irq-mapping, PCIVPBState, broken_irq_mapping,
0),
+DEFINE_PROP_END_OF_LIST()
+};
+
static void pci_vpb_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
Re: [Qemu-devel] [PATCH 00/10] Fix versatile_pci (and break versatilepb linux guests!)
On 24 March 2013 21:37, Michael S. Tsirkin m...@redhat.com wrote: On Sun, Mar 24, 2013 at 09:16:28PM +, Arnd Bergmann wrote: I think it actually does on versatile and other platforms on which the kernel probes the PCI bus itself, rather than relying on firmware to have resources assigned in advance. IIRC, the PCI_INTERRUPT_LINE pci config space byte (0x3c) is purely informational and used as a way to communicate the interrupt number from the bus scan code (assumed to be a PC BIOS in the PCI spec, but drivers/pci/setup-irq.c in case of versatile+linux) to a device driver. So the kernel should actually write the proper interrupt number in there. In future kernels, this may not necessarily be the hardware number, but today it is. OK, so I've now tested, and the kernel writes the interrupt number (27..30) into PCI_INTERRUPT_LINE, so we can successfully use this to detect broken kernels and switch to the old irq mapping. (Broken kernels write 27 regardless of slot number, good ones write 27..30 depending on slot number.) [patches in progress, will send later.] For future kernels, let's build in some hook that let qemu detect a non broken guest. How about writing some magic value into revision ID or some other readonly field? So do we still need the non-broken-guest detection hook too? We could maybe steal a bit in PCI_FLAGS for this, but somebody would need to check the behaviour of the hardware if you try to write to the reserved bits on real hardware. (Usually it's RAZ/WI or reads-as-written, either of which would be OK here.) thanks -- PMM
[Qemu-devel] [PATCH v9 11/24] hw/arm: add FTAPBBRG020 APB DMA support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTAPBBRG020 supports the DMA functions for the AHB-to-AHB,
AHB-to-APB, APB-to-AHB, and APB-to-APB transactions.
The DMA engine can support up to 4 DMA channels (A, B, C, and D)
and 15 handshaking channels. A DMA channel granted by the arbiter
block is the only channel starts transfers. Each DMA channel can
be programmed to one of the 15 handshaking channels in the hardware
handshake mode to act as the source device or act as the destination
device.
The main function of the hardware handshake mode is to provide an
indication of the device status. Users can also disable the hardware
handshake mode by programming the register when a DMA transfer is not
necessary of referring to the handshaking channels.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |9 +
hw/ftapbbrg020.c| 478 +++
hw/ftapbbrg020.h| 44 +
4 files changed, 532 insertions(+), 1 deletion(-)
create mode 100644 hw/ftapbbrg020.c
create mode 100644 hw/ftapbbrg020.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 6510c51..34e2939 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -25,7 +25,7 @@ obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
-ftrtc011.o ftdmac020.o
+ftrtc011.o ftdmac020.o ftapbbrg020.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 59e2c61..99eb428 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -182,6 +182,15 @@ static void a369soc_chip_init(FaradaySoCState *s)
s-pic[17], /* TC */
s-pic[18], /* ERR */
NULL);
+
+/* ftapbbrg020 */
+ds = sysbus_create_simple(ftapbbrg020, 0x90f0, s-pic[14]);
+s-pdma[0] = ds;
+object_property_set_link(OBJECT(ds), OBJECT(s), soc, local_errp);
+if (local_errp) {
+fprintf(stderr, a369soc: Unable to set soc link for FTAPBBRG020\n);
+abort();
+}
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftapbbrg020.c b/hw/ftapbbrg020.c
new file mode 100644
index 000..efc8376
--- /dev/null
+++ b/hw/ftapbbrg020.c
@@ -0,0 +1,478 @@
+/*
+ * QEMU model of the FTAPBBRG020 DMA Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ *
+ * Note: The FTAPBBRG020 DMA descending address mode is not implemented.
+ */
+
+#include hw/sysbus.h
+#include sysemu/dma.h
+#include sysemu/sysemu.h
+#include sysemu/blockdev.h
+
+#include hw/faraday.h
+#include hw/ftapbbrg020.h
+
+#define TYPE_FTAPBBRG020ftapbbrg020
+
+typedef struct Ftapbbrg020State Ftapbbrg020State;
+
+typedef struct Ftapbbrg020Chan {
+Ftapbbrg020State *chip;
+
+int id;
+int burst;
+int src_bw;
+int src_stride;
+int dst_bw;
+int dst_stride;
+
+/* HW register caches */
+uint32_t src;
+uint32_t dst;
+uint32_t len;
+uint32_t cmd;
+} Ftapbbrg020Chan;
+
+typedef struct Ftapbbrg020State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion iomem;
+qemu_irq irq;
+
+FaradaySoCState *soc;
+Ftapbbrg020Chan chan[4];
+qemu_irq ack[16];
+uint32_t req;
+
+int busy;/* Busy Channel ID */
+int bh_owner;
+QEMUBH *bh;
+DMAContext *dma;
+} Ftapbbrg020State;
+
+#define FTAPBBRG020(obj) \
+OBJECT_CHECK(Ftapbbrg020State, obj, TYPE_FTAPBBRG020)
+
+static uint32_t ftapbbrg020_get_isr(Ftapbbrg020State *s)
+{
+int i;
+uint32_t isr = 0;
+Ftapbbrg020Chan *chan;
+
+for (i = 0; i 4; ++i) {
+chan = s-chan + i;
+isr |= (chan-cmd CMD_INTR_STATUS);
+}
+
+return isr;
+}
+
+static void ftapbbrg020_update_irq(Ftapbbrg020State *s)
+{
+uint32_t isr = ftapbbrg020_get_isr(s);
+
+qemu_set_irq(s-irq, isr ? 1 : 0);
+}
+
+static void ftapbbrg020_chan_cmd_decode(Ftapbbrg020Chan *c)
+{
+uint32_t tmp;
+
+/* 1. decode burst size */
+c-burst = (c-cmd CMD_BURST4) ? 4 : 1;
+
+/* 2. decode source/destination width */
+tmp = extract32(c-cmd, 20, 2);
+if (tmp 2) {
+tmp = 2;
+}
+c-src_bw = c-dst_bw = 8 (2 - tmp);
+
+/* 3. decode source address stride */
+switch (extract32(c-cmd, 8, 2)) {
+case 0:
+c-src_stride = 0;
+break;
+case 1:
+c-src_stride = c-src_bw 3;
+break;
+case 2:
+c-src_stride = 2 * (c-src_bw 3);
+break;
+case 3:
+c-src_stride = 4 * (c-src_bw 3);
+break;
+}
+
+/* 4. decode destination address stride */
+switch (extract32(c-cmd, 12, 2))
[Qemu-devel] [PATCH v9 14/24] hw: Add AudioCodecClass for wm87xx audio class abstration.
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/Makefile.objs |1 +
hw/arm/spitz.c |9 +++--
hw/arm/z2.c|9 +++--
hw/audio.c | 81 +++
hw/audio.h | 56 +++
hw/i2c.h |9 -
hw/marvell_88w8618_audio.c | 23 +++
hw/wm8750.c| 91 ++--
8 files changed, 211 insertions(+), 68 deletions(-)
create mode 100644 hw/audio.c
create mode 100644 hw/audio.h
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 11812c6..808e2d0 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -168,6 +168,7 @@ common-obj-$(CONFIG_REALLY_VIRTFS) += 9pfs/
common-obj-y += usb/
common-obj-$(CONFIG_PTIMER) += ptimer.o
common-obj-$(CONFIG_MAX7310) += max7310.o
+common-obj-y += audio.o
common-obj-$(CONFIG_WM8750) += wm8750.o
common-obj-$(CONFIG_TWL92230) += twl92230.o
common-obj-$(CONFIG_TSC2005) += tsc2005.o
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index f5832be..a07dfe3 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -24,6 +24,7 @@
#include ui/console.h
#include block/block.h
#include audio/audio.h
+#include hw/audio.h
#include hw/boards.h
#include sysemu/blockdev.h
#include hw/sysbus.h
@@ -739,9 +740,11 @@ static void spitz_i2c_setup(PXA2xxState *cpu)
qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
/* .. and to the sound interface. */
cpu-i2s-opaque = wm;
-cpu-i2s-codec_out = wm8750_dac_dat;
-cpu-i2s-codec_in = wm8750_adc_dat;
-wm8750_data_req_set(wm, cpu-i2s-data_req, cpu-i2s);
+cpu-i2s-codec_out = audio_codec_dac_dat;
+cpu-i2s-codec_in = audio_codec_adc_dat;
+audio_codec_data_req_set(DEVICE(wm),
+ cpu-i2s-data_req,
+ cpu-i2s);
}
static void spitz_akita_i2c_setup(PXA2xxState *cpu)
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index cbb6d80..1fecdc5 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -23,6 +23,7 @@
#include sysemu/blockdev.h
#include ui/console.h
#include audio/audio.h
+#include hw/audio.h
#include exec/address-spaces.h
#ifdef DEBUG_Z2
@@ -353,9 +354,11 @@ static void z2_init(QEMUMachineInitArgs *args)
i2c_create_slave(bus, aer915, 0x55);
wm = i2c_create_slave(bus, wm8750, 0x1b);
mpu-i2s-opaque = wm;
-mpu-i2s-codec_out = wm8750_dac_dat;
-mpu-i2s-codec_in = wm8750_adc_dat;
-wm8750_data_req_set(wm, mpu-i2s-data_req, mpu-i2s);
+mpu-i2s-codec_out = audio_codec_dac_dat;
+mpu-i2s-codec_in = audio_codec_adc_dat;
+audio_codec_data_req_set(DEVICE(wm),
+ mpu-i2s-data_req,
+ mpu-i2s);
qdev_connect_gpio_out(mpu-gpio, Z2_GPIO_LCD_CS,
qemu_allocate_irqs(z2_lcd_cs, z2_lcd, 1)[0]);
diff --git a/hw/audio.c b/hw/audio.c
new file mode 100644
index 000..35f99b9
--- /dev/null
+++ b/hw/audio.c
@@ -0,0 +1,81 @@
+/*
+ * Audio Codec Class
+ *
+ * Copyright (c) 2013 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ */
+
+#include hw/qdev.h
+#include hw/i2c.h
+#include hw/audio.h
+
+void audio_codec_data_req_set(DeviceState *dev,
+ void (*data_req)(void *, int, int),
+ void *opaque)
+{
+AudioCodecClass *k = AUDIO_CODEC_GET_CLASS(dev);
+if (k-data_req_set) {
+k-data_req_set(dev, data_req, opaque);
+}
+}
+
+void audio_codec_dac_dat(void *opaque, uint32_t sample)
+{
+AudioCodecClass *k = AUDIO_CODEC_GET_CLASS(opaque);
+if (k-dac_dat) {
+k-dac_dat(opaque, sample);
+}
+}
+
+uint32_t audio_codec_adc_dat(void *opaque)
+{
+AudioCodecClass *k = AUDIO_CODEC_GET_CLASS(opaque);
+uint32_t ret = 0;
+if (k-adc_dat) {
+ret = k-adc_dat(opaque);
+}
+return ret;
+}
+
+void *audio_codec_dac_buffer(void *opaque, int samples)
+{
+AudioCodecClass *k = AUDIO_CODEC_GET_CLASS(opaque);
+void *ret = NULL;
+if (k-dac_buffer) {
+ret = k-dac_buffer(opaque, samples);
+}
+return ret;
+}
+
+void audio_codec_dac_commit(void *opaque)
+{
+AudioCodecClass *k = AUDIO_CODEC_GET_CLASS(opaque);
+if (k-dac_commit) {
+k-dac_commit(opaque);
+}
+}
+
+void audio_codec_set_bclk_in(void *opaque, int new_hz)
+{
+AudioCodecClass *k = AUDIO_CODEC_GET_CLASS(opaque);
+if (k-set_bclk_in) {
+k-set_bclk_in(opaque, new_hz);
+}
+}
+
+static const TypeInfo audio_codec_info = {
+.name = TYPE_AUDIO_CODEC,
+.parent= TYPE_I2C_SLAVE,
+.instance_size = sizeof(AudioCodecState),
+.abstract = true,
+.class_size= sizeof(AudioCodecClass),
+};
+
+static void audio_codec_register_types(void)
+{
+type_register_static(audio_codec_info);
+}
+
[Qemu-devel] [PATCH v9 12/24] hw/arm: add FTNANDC021 nand flash controller support
From: Kuo-Jung Su dant...@faraday-tech.com
The FTNANDC021 is an integrated NAND flash controller which
re-pack the NAND flash command set with a shorter built-in opcode.
It also provides a register base interface for user to easily
access the underlying NAND flash chips, and also supports HW ECC.
However the optional hardware ECC function is not implemented.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369.c| 14 ++
hw/arm/ftplat_a369soc.c |9 +
hw/ftnandc021.c | 526 +++
hw/ftnandc021.h | 84
5 files changed, 634 insertions(+), 1 deletion(-)
create mode 100644 hw/ftnandc021.c
create mode 100644 hw/ftnandc021.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 34e2939..8fe0f67 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -25,7 +25,7 @@ obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
-ftrtc011.o ftdmac020.o ftapbbrg020.o
+ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369.c b/hw/arm/ftplat_a369.c
index 45f0846..827c58a 100644
--- a/hw/arm/ftplat_a369.c
+++ b/hw/arm/ftplat_a369.c
@@ -31,6 +31,8 @@ static void a369_board_init(QEMUMachineInitArgs *args)
ARMCPU *cpu;
DeviceState *ds;
FaradaySoCState *s;
+DriveInfo *dinfo;
+Error *local_errp = NULL;
if (!args-cpu_model) {
args-cpu_model = fa626te;
@@ -65,6 +67,18 @@ static void a369_board_init(QEMUMachineInitArgs *args)
/* Customized system reset */
qemu_register_reset(a369_system_reset, cpu);
+/* Attach the nand flash to ftnandc021 */
+dinfo = drive_get_next(IF_MTD);
+ds = nand_init(dinfo ? dinfo-bdrv : NULL, NAND_MFR_SAMSUNG, 0xda);
+object_property_set_link(OBJECT(s-nandc[0]),
+ OBJECT(ds),
+ flash,
+ local_errp);
+if (local_errp) {
+fprintf(stderr, a369: Unable to set flash link for FTNANDC021\n);
+abort();
+}
+
/* System start-up */
if (args-kernel_filename) {
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index 99eb428..e057629 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -54,6 +54,7 @@ static void a369soc_chip_init(FaradaySoCState *s)
int i;
DeviceState *ds;
DriveInfo *dinfo;
+qemu_irq ack, req;
Error *local_errp = NULL;
/* Remappable Memory Region Init */
@@ -191,6 +192,14 @@ static void a369soc_chip_init(FaradaySoCState *s)
fprintf(stderr, a369soc: Unable to set soc link for FTAPBBRG020\n);
abort();
}
+
+/* ftnandc021 */
+ds = sysbus_create_simple(ftnandc021, 0x9020, s-pic[30]);
+s-nandc[0] = ds;
+ack = qdev_get_gpio_in(ds, 0);
+req = qdev_get_gpio_in(s-hdma[0], 15);
+qdev_connect_gpio_out(s-hdma[0], 15, ack);
+qdev_connect_gpio_out(ds, 0, req);
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ftnandc021.c b/hw/ftnandc021.c
new file mode 100644
index 000..fef92aa
--- /dev/null
+++ b/hw/ftnandc021.c
@@ -0,0 +1,526 @@
+/*
+ * QEMU model of the FTNANDC021 NAND Flash Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ */
+
+#include hw/sysbus.h
+#include hw/devices.h
+#include hw/flash.h
+#include sysemu/blockdev.h
+
+#include hw/ftnandc021.h
+
+#define TYPE_FTNANDC021 ftnandc021
+
+typedef struct Ftnandc021State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion mmio;
+
+qemu_irq irq;
+DeviceState *flash;
+
+/* DMA hardware handshake */
+qemu_irq req;
+
+uint8_t manf_id, chip_id;
+
+int cmd;
+int len;/* buffer length for page read/write */
+int pi;/* page index */
+int bw;/* bus width (8-bits, 16-bits) */
+
+uint64_t size;/* flash size (maximum access range) */
+uint32_t pgsz;/* page size (Bytes) */
+uint32_t bksz;/* block size (Bytes) */
+uint32_t alen;/* address length (cycle) */
+
+uint32_t id[2];
+uint8_t oob[8];/* 5 bytes for 512/2048 page; 7 bytes for 4096 page */
+
+/* HW register caches */
+uint32_t sr;
+uint32_t fcr;
+uint32_t mcr;
+uint32_t ier;
+uint32_t bcr;
+} Ftnandc021State;
+
+#define FTNANDC021(obj) \
+OBJECT_CHECK(Ftnandc021State, obj, TYPE_FTNANDC021)
+
+static void ftnandc021_update_irq(Ftnandc021State *s)
+{
+if (s-ier IER_ENA) {
+if ((s-ier 0x0f) (s-sr 2)) {
+qemu_set_irq(s-irq, 1);
+} else {
+qemu_set_irq(s-irq, 0);
+}
+}
+}
+
+static void
[Qemu-devel] [PATCH v9 09/24] tests: add QTest for FTRTC011
From: Kuo-Jung Su dant...@faraday-tech.com
The FTRTC011 QEMU model is implemented without calender functions.
It acts in counter mode only, all the time timezone conversion
relies on the c runtime library. (i.e. mktime(), localtime() ...etc)
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
tests/Makefile|3 +
tests/ftrtc011-test.c | 410 +
2 files changed, 413 insertions(+)
create mode 100644 tests/ftrtc011-test.c
diff --git a/tests/Makefile b/tests/Makefile
index 567e36e..bc75f2b 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -75,6 +75,8 @@ gcov-files-sparc-y += hw/m48t59.c
gcov-files-sparc64-y += hw/m48t59.c
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
gcov-files-arm-y += hw/tmp105.c
+check-qtest-arm-y = tests/ftrtc011-test$(EXESUF)
+gcov-files-arm-y += hw/ftrtc011.c
GENERATED_HEADERS += tests/test-qapi-types.h tests/test-qapi-visit.h
tests/test-qmp-commands.h
@@ -133,6 +135,7 @@ tests/m48t59-test$(EXESUF): tests/m48t59-test.o
tests/fdc-test$(EXESUF): tests/fdc-test.o
tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
tests/tmp105-test$(EXESUF): tests/tmp105-test.o
+tests/ftrtc011-test$(EXESUF): tests/ftrtc011-test.o
# QTest rules
diff --git a/tests/ftrtc011-test.c b/tests/ftrtc011-test.c
new file mode 100644
index 000..15b4f0d
--- /dev/null
+++ b/tests/ftrtc011-test.c
@@ -0,0 +1,410 @@
+/*
+ * QTest testcase for the FTRTC011 real-time clock
+ *
+ * Copyright (c) 2013 Kuo-Jung Su
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include libqtest.h
+#include hw/ftrtc011.h
+
+#include glib.h
+#include stdio.h
+#include string.h
+#include stdlib.h
+#include unistd.h
+
+#define A369_FTRTC011_BASE 0x9210
+#define A369_FTRTC011_IRQ_ALARM 42 /* edge triggered */
+#define A369_FTRTC011_IRQ_SEC 43 /* edge triggered */
+#define A369_FTRTC011_IRQ_MIN 44 /* edge triggered */
+#define A369_FTRTC011_IRQ_HOUR 45 /* edge triggered */
+
+#define CFG_BASEYEAR2010
+
+static time_t ts_base;
+
+static uint32_t rtc_read(uint32_t reg)
+{
+return readl(A369_FTRTC011_BASE + reg);
+}
+
+static void rtc_write(uint32_t reg, uint32_t val)
+{
+writel(A369_FTRTC011_BASE + reg, val);
+}
+
+static int rtc_get_irq(int irq)
+{
+#if 0 /* It looks to me that get_irq() doesn't work well
+ * with edge interrupts.
+ */
+return get_irq(irq);
+#else
+switch (irq) {
+case A369_FTRTC011_IRQ_ALARM:
+return !!(rtc_read(REG_ISR) ISR_ALARM);
+case A369_FTRTC011_IRQ_SEC:
+return !!(rtc_read(REG_ISR) ISR_SEC);
+case A369_FTRTC011_IRQ_MIN:
+return !!(rtc_read(REG_ISR) ISR_MIN);
+case A369_FTRTC011_IRQ_HOUR:
+return !!(rtc_read(REG_ISR) ISR_HOUR);
+default:
+return 0;
+}
+#endif
+}
+
+static int tm_cmp(struct tm *lhs, struct tm *rhs)
+{
+time_t a, b;
+struct tm d1, d2;
+
+memcpy(d1, lhs, sizeof(d1));
+memcpy(d2, rhs, sizeof(d2));
+
+a = mktime(d1);
+b = mktime(d2);
+
+if (a b) {
+return -1;
+} else if (a b) {
+return 1;
+}
+
+return 0;
+}
+
+static void rtc_start(void)
+{
+time_t ts;
+struct tm base;
+
+if (!ts_base) {
+base.tm_isdst = -1;
+base.tm_year = CFG_BASEYEAR - 1900;
+base.tm_mon = 0;
+base.tm_mday = 1;
+base.tm_hour = 0;
+base.tm_min = 0;
+base.tm_sec = 0;
+ts_base = mktime(base);
+}
+
+ts = time(NULL) - ts_base;
+rtc_write(REG_WDAY, ts / 86400LL);
+ts %= 86400LL;
+rtc_write(REG_WHOUR, ts / 3600LL);
+ts %= 3600LL;
+rtc_write(REG_WMIN, ts / 60LL);
+ts %= 60LL;
+rtc_write(REG_WSEC, ts);
+
+rtc_write(REG_ISR, ISR_MASK);
+rtc_write(REG_CR, CR_EN | CR_LOAD | CR_INTR_MASK);
+}
+
+static void rtc_get_datetime(struct tm *date)
+{
+time_t ts;
+int64_t sec, min, hour, day;
+
+if (!ts_base) {
+fprintf(stderr, ts_base is not yet initialized!\n);
+exit(1);
+}
+
+sec = rtc_read(REG_SEC);
+min = rtc_read(REG_MIN);
+hour = rtc_read(REG_HOUR);
+day = rtc_read(REG_DAY);
+ts = ts_base + (86400LL * day) + (hour * 3600LL) + (min * 60LL) + sec;
+
+localtime_r(ts, date);
+}
+
+static void rtc_test_check_time(int wiggle)
+{
+struct tm start, date[4], end;
+struct tm *datep;
+time_t ts;
+
+rtc_start();
+
+/*
+ * This check assumes a few things.
+ * First, we cannot guarantee that we get a consistent reading
+ * from the wall clock because we may hit an edge of the clock
+ * while reading.
+ * To work around this, we read four clock readings such that
+ * at least two of them should match. We need to assume that one
+ * reading is corrupt so we need four readings to ensure that we have at
+ * least two consecutive identical readings
+ *
+ * It's also
[Qemu-devel] [PATCH v9 15/24] hw: add WM8731 audio codec support
From: Kuo-Jung Su dant...@faraday-tech.com
Wolfson WM8731 is a simple audio codec for embedded systems.
It has 2 input and 1 output ports:
** Input **
1. Linue-In
2. Microphone
** Output **
1. Headphone out
BTW it's based on hw/wm8750.c with 16-bit I2S support by default.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
default-configs/arm-softmmu.mak |1 +
hw/Makefile.objs|1 +
hw/wm8731.c | 505 +++
3 files changed, 507 insertions(+)
create mode 100644 hw/wm8731.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index ab87035..b682c24 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -11,6 +11,7 @@ CONFIG_SERIAL=y
CONFIG_PTIMER=y
CONFIG_SD=y
CONFIG_MAX7310=y
+CONFIG_WM8731=y
CONFIG_WM8750=y
CONFIG_TWL92230=y
CONFIG_TSC2005=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 808e2d0..5b4bf20 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -169,6 +169,7 @@ common-obj-y += usb/
common-obj-$(CONFIG_PTIMER) += ptimer.o
common-obj-$(CONFIG_MAX7310) += max7310.o
common-obj-y += audio.o
+common-obj-$(CONFIG_WM8731) += wm8731.o
common-obj-$(CONFIG_WM8750) += wm8750.o
common-obj-$(CONFIG_TWL92230) += twl92230.o
common-obj-$(CONFIG_TSC2005) += tsc2005.o
diff --git a/hw/wm8731.c b/hw/wm8731.c
new file mode 100644
index 000..820341f
--- /dev/null
+++ b/hw/wm8731.c
@@ -0,0 +1,505 @@
+/*
+ * WM8731 audio codec.
+ *
+ * base is wm8750.c
+ *
+ * Copyright (c) 2013 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ */
+
+#include hw/hw.h
+#include hw/i2c.h
+#include hw/audio.h
+#include audio/audio.h
+
+#define IN_PORT_N 2
+#define OUT_PORT_N 1
+
+#define TYPE_WM8731 wm8731
+
+typedef struct WMRate {
+int adc;
+int adc_hz;
+int dac;
+int dac_hz;
+} WMRate;
+
+typedef struct WM8731State {
+AudioCodecState parent;
+
+uint8_t i2c_data[2];
+int i2c_len;
+QEMUSoundCard card;
+SWVoiceIn *adc_voice[IN_PORT_N];
+SWVoiceOut *dac_voice[OUT_PORT_N];
+void (*data_req)(void *, int, int);
+void *opaque;
+uint8_t data_in[4096];
+uint8_t data_out[4096];
+int idx_in, req_in;
+int idx_out, req_out;
+
+SWVoiceOut **out[2];
+uint8_t outvol[2];
+SWVoiceIn **in[2];
+uint8_t invol[2], inmute[2], mutemic;
+
+uint8_t mute;
+uint8_t power, format, active;
+const WMRate *rate;
+uint8_t rate_vmstate;
+int adc_hz, dac_hz, ext_adc_hz, ext_dac_hz, master;
+} WM8731State;
+
+#define WM8731(obj) \
+OBJECT_CHECK(WM8731State, obj, TYPE_WM8731)
+
+#define WM8731_OUTVOL_TRANSFORM(x) (x 1)
+#define WM8731_INVOL_TRANSFORM(x) (x 3)
+
+static inline void wm8731_in_load(WM8731State *s)
+{
+if (s-idx_in + s-req_in = sizeof(s-data_in)) {
+return;
+}
+s-idx_in = audio_MAX(0, (int) sizeof(s-data_in) - s-req_in);
+AUD_read(*s-in[0], s-data_in + s-idx_in,
+ sizeof(s-data_in) - s-idx_in);
+}
+
+static inline void wm8731_out_flush(WM8731State *s)
+{
+int sent = 0;
+while (sent s-idx_out) {
+sent += AUD_write(*s-out[0], s-data_out + sent, s-idx_out - sent)
+? 0 : s-idx_out;
+}
+s-idx_out = 0;
+}
+
+static void wm8731_audio_in_cb(void *opaque, int avail_b)
+{
+WM8731State *s = WM8731(opaque);
+s-req_in = avail_b;
+/* 16 bit samples */
+s-data_req(s-opaque, s-req_out 1, avail_b 1);
+}
+
+static void wm8731_audio_out_cb(void *opaque, int free_b)
+{
+WM8731State *s = WM8731(opaque);
+
+if (s-idx_out = free_b) {
+s-idx_out = free_b;
+s-req_out = 0;
+wm8731_out_flush(s);
+} else {
+s-req_out = free_b - s-idx_out;
+}
+/* 16 bit samples */
+s-data_req(s-opaque, s-req_out 1, s-req_in 1);
+}
+
+static const WMRate wm_rate_table[] = {
+{ 256, 48000, 256, 48000 },/* SR: , BOSR: 0 */
+{ 384, 48000, 384, 48000 },/* SR: , BOSR: 1 */
+{ 256, 48000, 256, 8000 },/* SR: 0001, BOSR: 0 */
+{ 384, 48000, 384, 8000 },/* SR: 0001, BOSR: 1 */
+{ 256, 8000, 256, 48000 },/* SR: 0010, BOSR: 0 */
+{ 384, 8000, 384, 48000 },/* SR: 0010, BOSR: 1 */
+{ 256, 8000, 256, 8000 },/* SR: 0011, BOSR: 0 */
+{ 384, 8000, 384, 8000 },/* SR: 0011, BOSR: 1 */
+{ 256, 32000, 256, 32000 },/* SR: 0110, BOSR: 0 */
+{ 384, 32000, 384, 32000 },/* SR: 0110, BOSR: 1 */
+{ 128, 96000, 128, 96000 },/* SR: 0111, BOSR: 0 */
+{ 192, 96000, 192, 96000 },/* SR: 0111, BOSR: 1 */
+{ 256, 44100, 256, 44100 },/* SR: 1000, BOSR: 0 */
+{ 384, 44100, 384, 44100 },/* SR: 1000, BOSR: 1 */
+{ 256, 44100, 256, 8000 },/* SR: 1001, BOSR: 0 */
+{ 384, 44100, 384, 8000 },/* SR: 1001, BOSR: 1 */
+{ 256, 8000, 256, 44100 },/* SR:
[Qemu-devel] [PATCH v9 16/24] The FTSSP010 is a multi-function synchronous serial port interface controller which supports SSP, SPI, I2S, AC97 and SPDIF.
From: Kuo-Jung Su dant...@faraday-tech.com
Only I2S and SPI protocol have been implemented in this patch.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs|3 +-
hw/arm/ftplat_a369.c| 31 +++
hw/arm/ftplat_a369soc.c | 17 ++
hw/faraday.h|3 +
hw/ftssp010.c | 504 +++
hw/ftssp010.h | 96 +
6 files changed, 653 insertions(+), 1 deletion(-)
create mode 100644 hw/ftssp010.c
create mode 100644 hw/ftssp010.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 2bb67f7..42c8472 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -25,7 +25,8 @@ obj-y += strongarm.o
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
obj-$(CONFIG_KVM) += kvm/arm_gic.o
obj-y += ftintc020.o ftahbc020.o ftddrii030.o ftpwmtmr010.o ftwdt010.o \
-ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o fti2c010.o
+ftrtc011.o ftdmac020.o ftapbbrg020.o ftnandc021.o fti2c010.o \
+ftssp010.o
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/arm/ftplat_a369.c b/hw/arm/ftplat_a369.c
index 827c58a..922fb55 100644
--- a/hw/arm/ftplat_a369.c
+++ b/hw/arm/ftplat_a369.c
@@ -11,6 +11,7 @@
#include hw/arm-misc.h
#include hw/devices.h
#include hw/i2c.h
+#include hw/audio.h
#include hw/boards.h
#include hw/ssi.h
#include net/net.h
@@ -28,6 +29,7 @@ static void a369_system_reset(void *opaque)
static void a369_board_init(QEMUMachineInitArgs *args)
{
+int i, nr_flash;
ARMCPU *cpu;
DeviceState *ds;
FaradaySoCState *s;
@@ -79,6 +81,35 @@ static void a369_board_init(QEMUMachineInitArgs *args)
abort();
}
+/* Attach the spi flash to ftssp010.0 */
+nr_flash = 1;
+for (i = 0; i nr_flash; i++) {
+SSIBus *ssi = (SSIBus *)qdev_get_child_bus(s-spi[0], spi);
+DeviceState *fl = ssi_create_slave_no_init(ssi, w25q64);
+qemu_irq cs_line;
+
+qdev_init_nofail(fl);
+cs_line = qdev_get_gpio_in(fl, 0);
+sysbus_connect_irq(SYS_BUS_DEVICE(s-spi[0]), i + 1, cs_line);
+}
+
+/* Attach the wm8731 to fti2c010.0 ftssp010.0 */
+for (i = 0; i 1; ++i) {
+i2c_bus *i2c = (i2c_bus *)qdev_get_child_bus(s-i2c[0], i2c);
+ds = i2c_create_slave(i2c, wm8731, 0x1B);
+object_property_set_link(OBJECT(s-i2s[0]),
+ OBJECT(ds),
+ codec,
+ local_errp);
+if (local_errp) {
+fprintf(stderr, a369: Unable to set codec link for FTSSP010\n);
+abort();
+}
+audio_codec_data_req_set(ds,
+ ftssp010_i2s_data_req,
+ s-i2s[0]);
+}
+
/* System start-up */
if (args-kernel_filename) {
diff --git a/hw/arm/ftplat_a369soc.c b/hw/arm/ftplat_a369soc.c
index b6e82ad..9391764 100644
--- a/hw/arm/ftplat_a369soc.c
+++ b/hw/arm/ftplat_a369soc.c
@@ -206,6 +206,23 @@ static void a369soc_chip_init(FaradaySoCState *s)
s-i2c[0] = ds;
ds = sysbus_create_simple(fti2c010, 0x92A0, s-pic[52]);
s-i2c[1] = ds;
+
+/* ftssp010 */
+ds = sysbus_create_simple(ftssp010, 0x9270, s-pic[49]);
+s-spi[0] = ds;
+s-i2s[0] = ds;
+
+/* ftssp010 - DMA (Tx) */
+ack = qdev_get_gpio_in(ds, 0);
+req = qdev_get_gpio_in(s-pdma[0], 7);
+qdev_connect_gpio_out(s-pdma[0], 7, ack);
+qdev_connect_gpio_out(ds, 0, req);
+
+/* ftssp010 - DMA (Rx) */
+ack = qdev_get_gpio_in(ds, 1);
+req = qdev_get_gpio_in(s-pdma[0], 8);
+qdev_connect_gpio_out(s-pdma[0], 8, ack);
+qdev_connect_gpio_out(ds, 1, req);
}
static void a369soc_realize(DeviceState *dev, Error **errp)
diff --git a/hw/faraday.h b/hw/faraday.h
index 7373ba0..39a608c 100644
--- a/hw/faraday.h
+++ b/hw/faraday.h
@@ -121,4 +121,7 @@ static inline void faraday_soc_ahb_remap(FaradaySoCState
*s, bool active)
}
}
+/* ftssp010.c */
+void ftssp010_i2s_data_req(void *opaque, int tx, int rx);
+
#endif
diff --git a/hw/ftssp010.c b/hw/ftssp010.c
new file mode 100644
index 000..fe1ddbb
--- /dev/null
+++ b/hw/ftssp010.c
@@ -0,0 +1,504 @@
+/*
+ * QEMU model of the FTSSP010 Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Written by Dante Su dant...@faraday-tech.com
+ *
+ * This file is licensed under GNU GPL v2+.
+ */
+
+#include hw/sysbus.h
+#include hw/i2c.h
+#include hw/ssi.h
+#include hw/audio.h
+#include sysemu/sysemu.h
+#include qemu/fifo8.h
+
+#include hw/faraday.h
+#include hw/ftssp010.h
+
+#define CFG_FIFO_DEPTH 16
+
+#define TYPE_FTSSP010 ftssp010
+
+typedef struct Ftssp010State {
+/* private */
+SysBusDevice parent;
+
+/* public */
+MemoryRegion mmio;
+
+qemu_irq irq;
+SSIBus *spi;
+AudioCodecState *codec;
+
+uint8_t num_cs;
+qemu_irq *cs_lines;
+
+Fifo8 rx_fifo;
+Fifo8 tx_fifo;
+
+uint8_t
[Qemu-devel] [PATCH 3/7] net: iovec checksum calculator
From: Dmitry Fleytman dmi...@daynix.com
Signed-off-by: Dmitry Fleytman dmi...@daynix.com
Signed-off-by: Yan Vugenfirer y...@daynix.com
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
include/net/checksum.h | 12
net/checksum.c | 29 +
2 files changed, 41 insertions(+)
diff --git a/include/net/checksum.h b/include/net/checksum.h
index 3e7b93d..80203fb 100644
--- a/include/net/checksum.h
+++ b/include/net/checksum.h
@@ -38,4 +38,16 @@ net_raw_checksum(uint8_t *data, int length)
return net_checksum_finish(net_checksum_add(length, data));
}
+/**
+ * net_checksum_add_iov: scatter-gather vector checksumming
+ *
+ * @iov: input scatter-gather array
+ * @iov_cnt: number of array elements
+ * @iov_off: starting iov offset for checksumming
+ * @size: length of data to be checksummed
+ */
+uint32_t net_checksum_add_iov(const struct iovec *iov,
+ const unsigned int iov_cnt,
+ uint32_t iov_off, uint32_t size);
+
#endif /* QEMU_NET_CHECKSUM_H */
diff --git a/net/checksum.c b/net/checksum.c
index 4fa5563..14c0855 100644
--- a/net/checksum.c
+++ b/net/checksum.c
@@ -15,6 +15,7 @@
* along with this program; if not, see http://www.gnu.org/licenses/.
*/
+#include qemu-common.h
#include net/checksum.h
#define PROTO_TCP 6
@@ -84,3 +85,31 @@ void net_checksum_calculate(uint8_t *data, int length)
data[14+hlen+csum_offset] = csum 8;
data[14+hlen+csum_offset+1] = csum 0xff;
}
+
+uint32_t
+net_checksum_add_iov(const struct iovec *iov, const unsigned int iov_cnt,
+ uint32_t iov_off, uint32_t size)
+{
+size_t iovec_off, buf_off;
+unsigned int i;
+uint32_t res = 0;
+uint32_t seq = 0;
+
+iovec_off = 0;
+buf_off = 0;
+for (i = 0; i iov_cnt size; i++) {
+if (iov_off (iovec_off + iov[i].iov_len)) {
+size_t len = MIN((iovec_off + iov[i].iov_len) - iov_off , size);
+void *chunk_buf = iov[i].iov_base + (iov_off - iovec_off);
+
+res += net_checksum_add_cont(len, chunk_buf, seq);
+seq += len;
+
+buf_off += len;
+iov_off += len;
+size -= len;
+}
+iovec_off += iov[i].iov_len;
+}
+return res;
+}
--
1.8.1.4
[Qemu-devel] [PATCH 2/7] Checksum-related utility functions
From: Dmitry Fleytman dmi...@daynix.com
net_checksum_add_cont()
checksum calculation for scattered data with odd chunk sizes
net_raw_checksum()
checksum calculation for a buffer
Signed-off-by: Dmitry Fleytman dmi...@daynix.com
Signed-off-by: Yan Vugenfirer y...@daynix.com
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
include/net/checksum.h | 14 +-
net/checksum.c | 13 +++--
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/include/net/checksum.h b/include/net/checksum.h
index 1f05298..3e7b93d 100644
--- a/include/net/checksum.h
+++ b/include/net/checksum.h
@@ -20,10 +20,22 @@
#include stdint.h
-uint32_t net_checksum_add(int len, uint8_t *buf);
+uint32_t net_checksum_add_cont(int len, uint8_t *buf, int seq);
uint16_t net_checksum_finish(uint32_t sum);
uint16_t net_checksum_tcpudp(uint16_t length, uint16_t proto,
uint8_t *addrs, uint8_t *buf);
void net_checksum_calculate(uint8_t *data, int length);
+static inline uint32_t
+net_checksum_add(int len, uint8_t *buf)
+{
+return net_checksum_add_cont(len, buf, 0);
+}
+
+static inline uint16_t
+net_raw_checksum(uint8_t *data, int length)
+{
+return net_checksum_finish(net_checksum_add(length, data));
+}
+
#endif /* QEMU_NET_CHECKSUM_H */
diff --git a/net/checksum.c b/net/checksum.c
index 9919b2e..4fa5563 100644
--- a/net/checksum.c
+++ b/net/checksum.c
@@ -20,16 +20,17 @@
#define PROTO_TCP 6
#define PROTO_UDP 17
-uint32_t net_checksum_add(int len, uint8_t *buf)
+uint32_t net_checksum_add_cont(int len, uint8_t *buf, int seq)
{
uint32_t sum = 0;
int i;
-for (i = 0; i len; i++) {
- if (i 1)
- sum += (uint32_t)buf[i];
- else
- sum += (uint32_t)buf[i] 8;
+for (i = seq; i seq + len; i++) {
+if (i 1) {
+sum += (uint32_t)buf[i - seq];
+} else {
+sum += (uint32_t)buf[i - seq] 8;
+}
}
return sum;
}
--
1.8.1.4
[Qemu-devel] [PULL 0/7] Net patches
The big change here is the new vmxnet3 emulated NIC. The following changes since commit fe6344a05fba26e16863fefcb823242e579b0991: Remove device_tree.o from hw/moxie/Makefile.objs. (2013-03-24 11:30:04 +0100) are available in the git repository at: git://github.com/stefanha/qemu.git net for you to fetch changes up to d32fcad366e5f45d33dab2ee4de0e5729439680b: net: increase buffer size to accommodate Jumbo frame pkts (2013-03-25 11:14:07 +0100) Dmitry Fleytman (5): Checksum-related utility functions net: iovec checksum calculator Common definitions for VMWARE devices Packet abstraction for VMWARE network devices VMXNET3 device implementation Scott Feldman (1): net: increase buffer size to accommodate Jumbo frame pkts Stefan Hajnoczi (1): net: use socket_set_nodelay() for -netdev socket default-configs/pci.mak |1 + hw/Makefile.objs|2 + hw/pci/pci.h|1 + hw/vmware_utils.h | 143 +++ hw/vmxnet3.c| 2461 +++ hw/vmxnet3.h| 760 +++ hw/vmxnet_debug.h | 115 +++ hw/vmxnet_rx_pkt.c | 187 hw/vmxnet_rx_pkt.h | 174 hw/vmxnet_tx_pkt.c | 567 +++ hw/vmxnet_tx_pkt.h | 148 +++ include/net/checksum.h | 26 +- include/net/eth.h | 347 +++ include/net/net.h |5 + net/Makefile.objs |1 + net/checksum.c | 42 +- net/eth.c | 217 + net/net.c |2 +- net/socket.c|7 +- net/tap.c |7 +- net/vde.c |2 +- 21 files changed, 5198 insertions(+), 17 deletions(-) create mode 100644 hw/vmware_utils.h create mode 100644 hw/vmxnet3.c create mode 100644 hw/vmxnet3.h create mode 100644 hw/vmxnet_debug.h create mode 100644 hw/vmxnet_rx_pkt.c create mode 100644 hw/vmxnet_rx_pkt.h create mode 100644 hw/vmxnet_tx_pkt.c create mode 100644 hw/vmxnet_tx_pkt.h create mode 100644 include/net/eth.h create mode 100644 net/eth.c -- 1.8.1.4
[Qemu-devel] [PATCH 4/7] Common definitions for VMWARE devices
From: Dmitry Fleytman dmi...@daynix.com
Signed-off-by: Dmitry Fleytman dmi...@daynix.com
Signed-off-by: Yan Vugenfirer y...@daynix.com
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/vmware_utils.h | 143 ++
hw/vmxnet_debug.h | 115 ++
include/net/eth.h | 347 ++
net/Makefile.objs | 1 +
net/eth.c | 217 ++
5 files changed, 823 insertions(+)
create mode 100644 hw/vmware_utils.h
create mode 100644 hw/vmxnet_debug.h
create mode 100644 include/net/eth.h
create mode 100644 net/eth.c
diff --git a/hw/vmware_utils.h b/hw/vmware_utils.h
new file mode 100644
index 000..5307e2c
--- /dev/null
+++ b/hw/vmware_utils.h
@@ -0,0 +1,143 @@
+/*
+ * QEMU VMWARE paravirtual devices - auxiliary code
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman dmi...@daynix.com
+ * Yan Vugenfirer y...@daynix.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef VMWARE_UTILS_H
+#define VMWARE_UTILS_H
+
+#include qemu/range.h
+
+#ifndef VMW_SHPRN
+#define VMW_SHPRN(fmt, ...) do {} while (0)
+#endif
+
+/*
+ * Shared memory access functions with byte swap support
+ * Each function contains printout for reverse-engineering needs
+ *
+ */
+static inline void
+vmw_shmem_read(hwaddr addr, void *buf, int len)
+{
+VMW_SHPRN(SHMEM r: % PRIx64 , len: %d to %p, addr, len, buf);
+cpu_physical_memory_read(addr, buf, len);
+}
+
+static inline void
+vmw_shmem_write(hwaddr addr, void *buf, int len)
+{
+VMW_SHPRN(SHMEM w: % PRIx64 , len: %d to %p, addr, len, buf);
+cpu_physical_memory_write(addr, buf, len);
+}
+
+static inline void
+vmw_shmem_rw(hwaddr addr, void *buf, int len, int is_write)
+{
+VMW_SHPRN(SHMEM r/w: % PRIx64 , len: %d (to %p), is write: %d,
+ addr, len, buf, is_write);
+
+cpu_physical_memory_rw(addr, buf, len, is_write);
+}
+
+static inline void
+vmw_shmem_set(hwaddr addr, uint8 val, int len)
+{
+int i;
+VMW_SHPRN(SHMEM set: % PRIx64 , len: %d (value 0x%X), addr, len, val);
+
+for (i = 0; i len; i++) {
+cpu_physical_memory_write(addr + i, val, 1);
+}
+}
+
+static inline uint32_t
+vmw_shmem_ld8(hwaddr addr)
+{
+uint8_t res = ldub_phys(addr);
+VMW_SHPRN(SHMEM load8: % PRIx64 (value 0x%X), addr, res);
+return res;
+}
+
+static inline void
+vmw_shmem_st8(hwaddr addr, uint8_t value)
+{
+VMW_SHPRN(SHMEM store8: % PRIx64 (value 0x%X), addr, value);
+stb_phys(addr, value);
+}
+
+static inline uint32_t
+vmw_shmem_ld16(hwaddr addr)
+{
+uint16_t res = lduw_le_phys(addr);
+VMW_SHPRN(SHMEM load16: % PRIx64 (value 0x%X), addr, res);
+return res;
+}
+
+static inline void
+vmw_shmem_st16(hwaddr addr, uint16_t value)
+{
+VMW_SHPRN(SHMEM store16: % PRIx64 (value 0x%X), addr, value);
+stw_le_phys(addr, value);
+}
+
+static inline uint32_t
+vmw_shmem_ld32(hwaddr addr)
+{
+uint32_t res = ldl_le_phys(addr);
+VMW_SHPRN(SHMEM load32: % PRIx64 (value 0x%X), addr, res);
+return res;
+}
+
+static inline void
+vmw_shmem_st32(hwaddr addr, uint32_t value)
+{
+VMW_SHPRN(SHMEM store32: % PRIx64 (value 0x%X), addr, value);
+stl_le_phys(addr, value);
+}
+
+static inline uint64_t
+vmw_shmem_ld64(hwaddr addr)
+{
+uint64_t res = ldq_le_phys(addr);
+VMW_SHPRN(SHMEM load64: % PRIx64 (value % PRIx64 ), addr, res);
+return res;
+}
+
+static inline void
+vmw_shmem_st64(hwaddr addr, uint64_t value)
+{
+VMW_SHPRN(SHMEM store64: % PRIx64 (value % PRIx64 ), addr, value);
+stq_le_phys(addr, value);
+}
+
+/* Macros for simplification of operations on array-style registers */
+
+/*
+ * Whether addr lies inside of array-style register defined by base,
+ * number of elements (cnt) and element size (regsize)
+ *
+*/
+#define VMW_IS_MULTIREG_ADDR(addr, base, cnt, regsize) \
+range_covers_byte(base, cnt * regsize, addr)
+
+/*
+ * Returns index of given register (addr) in array-style register defined by
+ * base and element size (regsize)
+ *
+*/
+#define VMW_MULTIREG_IDX_BY_ADDR(addr, base, regsize) \
+(((addr) - (base)) / (regsize))
+
+#endif
diff --git a/hw/vmxnet_debug.h b/hw/vmxnet_debug.h
new file mode 100644
index 000..96dae0f
--- /dev/null
+++ b/hw/vmxnet_debug.h
@@ -0,0 +1,115 @@
+/*
+ * QEMU VMWARE VMXNET* paravirtual NICs - debugging facilities
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman dmi...@daynix.com
+ * Tamir Shomer tam...@daynix.com
+ * Yan Vugenfirer y...@daynix.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in
[Qemu-devel] [PATCH 1/7] net: use socket_set_nodelay() for -netdev socket
Reduce -netdev socket latency by disabling the Nagle algorithm on
SOCK_STREAM sockets in net/socket.c. Since we are tunelling Ethernet
over TCP we shouldn't artificially delay outgoing packets, let the guest
decide packet scheduling.
I already get sub-millisecond -netdev socket ping times on localhost, so
there was no measurable difference in my testing. This won't hurt
though and may improve remote socket performance.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
Reviewed-by: Benoit Canet ben...@irqsave.net
Reviewed-by: Daniel P. Berrange berra...@redhat.com
---
net/socket.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/net/socket.c b/net/socket.c
index d8b35a2..b0c83e0 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -438,6 +438,9 @@ static NetSocketState
*net_socket_fd_init_stream(NetClientState *peer,
s-fd = fd;
s-listen_fd = -1;
+/* Disable Nagle algorithm on TCP sockets to reduce latency */
+socket_set_nodelay(fd);
+
if (is_connected) {
net_socket_connect(s);
} else {
--
1.8.1.4
