Re: [Qemu-devel] [PATCH 2/5] machine: introduce get_fw_dev_path() callback
On 12/11/2013 06:47 PM, Paolo Bonzini wrote: Il 11/12/2013 06:20, Alexey Kardashevskiy ha scritto: Any progress on this? I am asking since the patchset about bootindex you gave me yesterday prints (process:38896): GLib-CRITICAL **: g_hash_table_foreach: assertion `version == hash_table-version' failed which I fixed by moving the machine object creation chunk before kvm_init() in vl.c. btw what do I do with that patchset now? I works for me (except the issue above), do I have to repost it again? Thanks. Please do, but we need to sort out the get_fw_dev_path suffixes first. I'll be on IRC in ~1 hour. And this is not it, make check on x86 fails: GTESTER tests/test-bitops LINK tests/test-qdev-global-props hw/core/qdev.o: In function `qdev_get_fw_dev_path_from_handler': /home/alexey/p/qemu/hw/core/qdev.c:514: undefined reference to `fw_path_provider_try_get_dev_path' collect2: error: ld returned 1 exit status -- Alexey
Re: [Qemu-devel] [PATCH rebased for-1.8] i386: pc: align gpa-hpa on 1GB boundary (v6)
Hi, I'd like to merge Gerd's patch, and a similar patch for q35. For q35 we need to get rid of MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT. Missing q35 patch is no reason to delay the i440fx fix though. However, I think we have to limit this change to pc-2.0 and newer: qemu 1.8 still has the pci hole concept, so guest can't put devices outside the specific ranges. --verbose please. I fail to see the problem here. cheers, Gerd
[Qemu-devel] [PATCH v11 0/5] add allwinner A10 SoC support
lay a foundation for allwinner A10 SoC with a cortex-a8 processor, and will add more devices later. v2: split timer and interrupt controller emulation into their corresponding files. v3: 1. change loader_start address 2. add 64-bit counter 3. fixup fail to clear interrup status issue v4: 1. add VMSD 2. use defines of magic number for readability 3. code cleanup v5: 1. add VMSTATE_PTIMER_ARRAY 2. code cleanup v6: 1. fix a fiq lost issue pointed out by Peter Crosthwaite 2. code cleanup v7: model allwinner A10 as a SoC device, and add cubieboard. v8: 1. A10 be QOMified as a device 2. add AW as prefix of A10 v9: code cleanup for PATCH 4/5 A10 SoC support v10: code cleanup for PATCH 2/5 v11: code cleanup for PATCH 2/5, 3/5 TODO: 1. add BROM support 2. add more devices test: can boot-up officially released linux kernel build with PLL disabled. can find test zImage at: http://dl.dbank.com/c0jaibr54s reference: http://linux-sunxi.org/Main_Page Li Guang (5) vmstate: add VMSTATE_PTIMER_ARRAY hw/timer: add allwinner a10 timer hw/intc: add allwinner A10 interrupt controller hw/arm: add allwinner a10 SoC support hw/arm: add cubieboard support default-configs/arm-softmmu.mak | 2 + hw/arm/Makefile.objs | 4 +- hw/arm/allwinner-a10.c | 39 +++ hw/arm/cubieboard.c | 33 + hw/intc/Makefile.objs| 1 + hw/intc/allwinner-a10_pic.c | 218 +++ hw/timer/Makefile.objs | 2 + hw/timer/allwinner-a10_pit.c | 253 ++ include/hw/arm/allwinner-a10.h | 27 +++ include/hw/intc/allwinner-a10_pic.h | 40 +++ include/hw/timer/allwinner-a10_pit.h | 57 include/migration/vmstate.h | 4 savevm.c | 31 +++ 13 files changed, 709 insertions(+), 2 deletions(-) create mode 100644 hw/timer/allwinner-a10_pit.c create mode 100644 include/hw/timer/allwinner-a10_pit.h create mode 100644 hw/intc/allwinner-a10_pic.c create mode 100644 include/hw/intc/allwinner-a10_pic.h create mode 100644 hw/arm/allwinner-a10.c create mode 100644 include/hw/arm/allwinner-a10.h create mode 100644 hw/arm/cubieboard.c
[Qemu-devel] [PATCH v11 1/5] vmstate: add VMSTATE_PTIMER_ARRAY
Signed-off-by: liguang lig.f...@cn.fujitsu.com
---
include/migration/vmstate.h |4
savevm.c| 31 +++
2 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 9d09e60..f5d6e81 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -165,6 +165,7 @@ extern const VMStateInfo vmstate_info_timer;
extern const VMStateInfo vmstate_info_buffer;
extern const VMStateInfo vmstate_info_unused_buffer;
extern const VMStateInfo vmstate_info_bitmap;
+extern const VMStateInfo vmstate_info_ptimer;
#define type_check_2darray(t1,t2,n,m) ((t1(*)[n][m])0 - (t2*)0)
#define type_check_array(t1,t2,n) ((t1(*)[n])0 - (t2*)0)
@@ -613,6 +614,9 @@ extern const VMStateInfo vmstate_info_bitmap;
#define VMSTATE_TIMER_ARRAY(_f, _s, _n) \
VMSTATE_ARRAY_OF_POINTER(_f, _s, _n, 0, vmstate_info_timer, QEMUTimer *)
+#define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
+VMSTATE_ARRAY_OF_POINTER(_f, _s, _n, 0, vmstate_info_ptimer, ptimer_state*)
+
#define VMSTATE_BOOL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_bool, bool)
diff --git a/savevm.c b/savevm.c
index 2f631d4..54dbb33 100644
--- a/savevm.c
+++ b/savevm.c
@@ -30,6 +30,7 @@
#include monitor/monitor.h
#include sysemu/sysemu.h
#include qemu/timer.h
+#include hw/ptimer.h
#include audio/audio.h
#include migration/migration.h
#include qemu/sockets.h
@@ -1362,6 +1363,36 @@ const VMStateInfo vmstate_info_timer = {
.put = put_timer,
};
+static int get_ptimer(QEMUFile *f, void *pv, size_t size)
+{
+ptimer_state *v = pv;
+uint64_t count;
+
+count = qemu_get_be64(f);
+if (count != -1) {
+ptimer_set_count(v, count);
+} else {
+ptimer_stop(v);
+}
+
+return 0;
+}
+
+static void put_ptimer(QEMUFile *f, void *pv, size_t size)
+{
+ptimer_state *v = pv;
+uint64_t count;
+
+count = ptimer_get_count(v);
+qemu_put_be64(f, count);
+}
+
+const VMStateInfo vmstate_info_ptimer = {
+.name = ptimer,
+.get = get_ptimer,
+.put = put_ptimer,
+};
+
/* uint8_t buffers */
static int get_buffer(QEMUFile *f, void *pv, size_t size)
--
1.7.2.5
[Qemu-devel] [PATCH v11 3/5] hw/intc: add allwinner A10 interrupt controller
Signed-off-by: liguang lig.f...@cn.fujitsu.com
---
default-configs/arm-softmmu.mak |1 +
hw/intc/Makefile.objs |1 +
hw/intc/allwinner-a10-pic.c | 200 +++
include/hw/intc/allwinner-a10-pic.h | 40 +++
4 files changed, 242 insertions(+), 0 deletions(-)
create mode 100644 hw/intc/allwinner-a10-pic.c
create mode 100644 include/hw/intc/allwinner-a10-pic.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 7858abf..e965068 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -83,3 +83,4 @@ CONFIG_SDHCI=y
CONFIG_INTEGRATOR_DEBUG=y
CONFIG_ALLWINNER_A10_PIT=y
+CONFIG_ALLWINNER_A10_PIC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..60eb936 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -24,3 +24,4 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
obj-$(CONFIG_SH4) += sh_intc.o
obj-$(CONFIG_XICS) += xics.o
obj-$(CONFIG_XICS_KVM) += xics_kvm.o
+obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
new file mode 100644
index 000..f39051a
--- /dev/null
+++ b/hw/intc/allwinner-a10-pic.c
@@ -0,0 +1,200 @@
+/*
+ * Allwinner A10 interrupt controller device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang lig.f...@cn.fujitsu.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include hw/sysbus.h
+#include hw/devices.h
+#include sysemu/sysemu.h
+#include hw/intc/allwinner-a10-pic.h
+
+static void aw_a10_pic_update(AwA10PICState *s)
+{
+uint8_t i;
+int irq = 0, fiq = 0;
+
+for (i = 0; i AW_A10_PIC_REG_NUM; i++) {
+irq |= s-irq_pending[i] ~s-mask[i];
+fiq |= s-select[i] s-irq_pending[i] ~s-mask[i];
+}
+
+qemu_set_irq(s-parent_irq, irq);
+qemu_set_irq(s-parent_fiq, fiq);
+}
+
+static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
+{
+AwA10PICState *s = opaque;
+
+if (level) {
+set_bit(irq%32, (void *)s-irq_pending[irq/32]);
+}
+aw_a10_pic_update(s);
+}
+
+static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size)
+{
+AwA10PICState *s = opaque;
+uint8_t index = (offset 0xc)/4;
+
+switch (offset) {
+case AW_A10_PIC_VECTOR:
+return s-vector;
+case AW_A10_PIC_BASE_ADDR:
+return s-base_addr;
+case AW_A10_PIC_PROTECT:
+return s-protect;
+case AW_A10_PIC_NMI:
+return s-nmi;
+case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
+return s-irq_pending[index];
+case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
+return s-fiq_pending[index];
+case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
+return s-select[index];
+case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
+return s-enable[index];
+case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
+return s-mask[index];
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ %s: Bad offset 0x%x\n, __func__, (int)offset);
+break;
+}
+
+return 0;
+}
+
+static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+AwA10PICState *s = opaque;
+uint8_t index = (offset 0xc)/4;
+
+switch (offset) {
+case AW_A10_PIC_VECTOR:
+s-vector = value ~0x3;
+break;
+case AW_A10_PIC_BASE_ADDR:
+s-base_addr = value ~0x3;
+case AW_A10_PIC_PROTECT:
+s-protect = value;
+break;
+case AW_A10_PIC_NMI:
+s-nmi = value;
+break;
+case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
+s-irq_pending[index] = ~value;
+break;
+case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
+s-fiq_pending[index] = ~value;
+break;
+case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
+s-select[index] = value;
+break;
+case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
+s-enable[index] = value;
+break;
+case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
+s-mask[index] = value;
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ %s: Bad offset 0x%x\n, __func__, (int)offset);
+break;
+}
+
+aw_a10_pic_update(s);
+}
+
+static const MemoryRegionOps aw_a10_pic_ops = {
+.read = aw_a10_pic_read,
+.write = aw_a10_pic_write,
+
[Qemu-devel] [PATCH v11 2/5] hw/timer: add allwinner a10 timer
Signed-off-by: liguang lig.f...@cn.fujitsu.com
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
default-configs/arm-softmmu.mak |2 +
hw/timer/Makefile.objs |2 +
hw/timer/allwinner-a10-pit.c | 254 ++
include/hw/timer/allwinner-a10-pit.h | 59
4 files changed, 317 insertions(+), 0 deletions(-)
create mode 100644 hw/timer/allwinner-a10-pit.c
create mode 100644 include/hw/timer/allwinner-a10-pit.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..7858abf 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y
CONFIG_SDHCI=y
CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_ALLWINNER_A10_PIT=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..f6ace47 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,5 @@ obj-$(CONFIG_SH4) += sh_timer.o
obj-$(CONFIG_TUSB6010) += tusb6010.o
obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+
+obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
new file mode 100644
index 000..8bba5e2
--- /dev/null
+++ b/hw/timer/allwinner-a10-pit.c
@@ -0,0 +1,254 @@
+/*
+ * Allwinner A10 timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang lig.f...@cn.fujitsu.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include hw/sysbus.h
+#include sysemu/sysemu.h
+#include hw/timer/allwinner-a10-pit.h
+
+static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+AwA10PITState *s = AW_A10_PIT(opaque);
+uint8_t index;
+
+switch (offset) {
+case AW_A10_PIT_TIMER_IRQ_EN:
+return s-irq_enable;
+case AW_A10_PIT_TIMER_IRQ_ST:
+return s-irq_status;
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
+index = offset 0xf0;
+index = 4;
+index -= 1;
+switch (offset 0x0f) {
+case AW_A10_PIT_TIMER_CONTROL:
+return s-control[index];
+case AW_A10_PIT_TIMER_INTERVAL:
+return s-interval[index];
+case AW_A10_PIT_TIMER_COUNT:
+s-count[index] = ptimer_get_count(s-timer[index]);
+return s-count[index];
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ %s: Bad offset 0x%x\n, __func__, (int)offset);
+break;
+}
+case AW_A10_PIT_WDOG_CONTROL:
+break;
+case AW_A10_PIT_WDOG_MODE:
+break;
+case AW_A10_PIT_COUNT_LO:
+return s-count_lo;
+case AW_A10_PIT_COUNT_HI:
+return s-count_hi;
+case AW_A10_PIT_COUNT_CTL:
+return s-count_ctl;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ %s: Bad offset 0x%x\n, __func__, (int)offset);
+break;
+}
+
+return 0;
+}
+
+static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
+unsigned size)
+{
+ AwA10PITState *s = AW_A10_PIT(opaque);
+ uint8_t index;
+
+switch (offset) {
+case AW_A10_PIT_TIMER_IRQ_EN:
+s-irq_enable = value;
+break;
+case AW_A10_PIT_TIMER_IRQ_ST:
+s-irq_status = ~value;
+break;
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
+index = offset 0xf0;
+index = 4;
+index -= 1;
+switch (offset 0x0f) {
+case AW_A10_PIT_TIMER_CONTROL:
+s-control[index] = value;
+if (s-control[index] AW_A10_PIT_TIMER_RELOAD) {
+ptimer_set_count(s-timer[index], s-interval[index]);
+}
+if (s-control[index] AW_A10_PIT_TIMER_EN) {
+int oneshot = 0;
+if (s-control[index] AW_A10_PIT_TIMER_MODE) {
+oneshot = 1;
+}
+ptimer_run(s-timer[index], oneshot);
+} else {
+ptimer_stop(s-timer[index]);
+}
+break;
+case AW_A10_PIT_TIMER_INTERVAL:
+s-interval[index] = value;
+ptimer_set_limit(s-timer[index], s-interval[index], 1);
+break;
+case AW_A10_PIT_TIMER_COUNT:
+s-count[index] = value;
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ %s: Bad offset 0x%x\n, __func__, (int)offset);
+}
+
Re: [Qemu-devel] [PATCH v11 3/5] hw/intc: add allwinner A10 interrupt controller
On Wed, Dec 11, 2013 at 6:08 PM, liguang lig.f...@cn.fujitsu.com wrote:
Signed-off-by: liguang lig.f...@cn.fujitsu.com
---
default-configs/arm-softmmu.mak |1 +
hw/intc/Makefile.objs |1 +
hw/intc/allwinner-a10-pic.c | 200
+++
include/hw/intc/allwinner-a10-pic.h | 40 +++
4 files changed, 242 insertions(+), 0 deletions(-)
create mode 100644 hw/intc/allwinner-a10-pic.c
create mode 100644 include/hw/intc/allwinner-a10-pic.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 7858abf..e965068 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -83,3 +83,4 @@ CONFIG_SDHCI=y
CONFIG_INTEGRATOR_DEBUG=y
CONFIG_ALLWINNER_A10_PIT=y
+CONFIG_ALLWINNER_A10_PIC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..60eb936 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -24,3 +24,4 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
obj-$(CONFIG_SH4) += sh_intc.o
obj-$(CONFIG_XICS) += xics.o
obj-$(CONFIG_XICS_KVM) += xics_kvm.o
+obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
new file mode 100644
index 000..f39051a
--- /dev/null
+++ b/hw/intc/allwinner-a10-pic.c
@@ -0,0 +1,200 @@
+/*
+ * Allwinner A10 interrupt controller device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang lig.f...@cn.fujitsu.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include hw/sysbus.h
+#include hw/devices.h
+#include sysemu/sysemu.h
+#include hw/intc/allwinner-a10-pic.h
+
+static void aw_a10_pic_update(AwA10PICState *s)
+{
+uint8_t i;
+int irq = 0, fiq = 0;
+
+for (i = 0; i AW_A10_PIC_REG_NUM; i++) {
+irq |= s-irq_pending[i] ~s-mask[i];
+fiq |= s-select[i] s-irq_pending[i] ~s-mask[i];
+}
+
+qemu_set_irq(s-parent_irq, irq);
+qemu_set_irq(s-parent_fiq, fiq);
!!irq or irq ? 1 : 0 to pass either 0 or 1 to qemu_set_irq, rather
than a random value. Reduces reliance on qemu_set_irq implementation
(ideally someone converts that API to accept bool).
otherwise,
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Please leave it a day or two to allow other reviewers a chance before respin.
Regards,
Peter
+}
+
+static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
+{
+AwA10PICState *s = opaque;
+
+if (level) {
+set_bit(irq%32, (void *)s-irq_pending[irq/32]);
+}
+aw_a10_pic_update(s);
+}
+
+static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size)
+{
+AwA10PICState *s = opaque;
+uint8_t index = (offset 0xc)/4;
+
+switch (offset) {
+case AW_A10_PIC_VECTOR:
+return s-vector;
+case AW_A10_PIC_BASE_ADDR:
+return s-base_addr;
+case AW_A10_PIC_PROTECT:
+return s-protect;
+case AW_A10_PIC_NMI:
+return s-nmi;
+case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
+return s-irq_pending[index];
+case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
+return s-fiq_pending[index];
+case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
+return s-select[index];
+case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
+return s-enable[index];
+case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
+return s-mask[index];
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+ %s: Bad offset 0x%x\n, __func__, (int)offset);
+break;
+}
+
+return 0;
+}
+
+static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+AwA10PICState *s = opaque;
+uint8_t index = (offset 0xc)/4;
+
+switch (offset) {
+case AW_A10_PIC_VECTOR:
+s-vector = value ~0x3;
+break;
+case AW_A10_PIC_BASE_ADDR:
+s-base_addr = value ~0x3;
+case AW_A10_PIC_PROTECT:
+s-protect = value;
+break;
+case AW_A10_PIC_NMI:
+s-nmi = value;
+break;
+case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
+s-irq_pending[index] = ~value;
+break;
+case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
+s-fiq_pending[index] = ~value;
+break;
+case AW_A10_PIC_SELECT ...
Re: [Qemu-devel] [PATCH] qemu-img: set nocow flag to new file
On Tue, Dec 10, 2013 at 10:23:41PM +, Alex Bennée wrote: stefa...@redhat.com writes: On Mon, Nov 18, 2013 at 12:54:59PM +0800, Chunyan Liu wrote: 2013/11/15 Stefan Hajnoczi stefa...@gmail.com On Thu, Nov 14, 2013 at 04:15:28PM +0800, Chunyan Liu wrote: Set NOCOW flag to newly created images to solve performance issues on btrfs. snip This should be optional and I'm not sure it should be the default. Rationale: If you're on btrfs you probably expect the copy-on-write and snapshot features of the file system. We shouldn't silently disable that unless the user asks for it. snip When the NOCOW attribute is set on a file, reflink copying (aka file-level snapshots) do not work: $ cp --reflink test.img test-snapshot.img This produces EINVAL. It is a regression if qemu-img create suddenly starts breaking this standard btrfs feature for existing users. Please make it a .bdrv_create() option which is off by default to avoid breaking existing users' workflows/scripts. The result should be something like: $ qemu-img create test.img 8G # file has NOCOW cleared $ qemu-img create -o nocow=on test.img 8G # file has NOCOW set I agree we shouldn't break existing work flows. I wonder if it would OK for qemu-img to issue a warning (when not --quiet) when it detects creation of an image on a partition where performance may not be as expected due to COW behaviour. A warning could help or at least prompt users to consider switching to nocow. Stefan
[Qemu-devel] [PATCH v11 5/5] hw/arm: add cubieboard support
Signed-off-by: liguang lig.f...@cn.fujitsu.com
Acked-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/arm/Makefile.objs |2 +-
hw/arm/cubieboard.c | 69 ++
2 files changed, 70 insertions(+), 1 deletions(-)
create mode 100644 hw/arm/cubieboard.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 012bd2c..1dd94de 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,4 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-y += omap1.o omap2.o strongarm.o
-obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o
+obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
new file mode 100644
index 000..3fcb6d2
--- /dev/null
+++ b/hw/arm/cubieboard.c
@@ -0,0 +1,69 @@
+/*
+ * cubieboard emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang lig.f...@cn.fujitsu.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include hw/sysbus.h
+#include hw/devices.h
+#include hw/boards.h
+#include hw/arm/allwinner-a10.h
+
+static struct arm_boot_info cubieboard_binfo = {
+.loader_start = AW_A10_SDRAM_BASE,
+.board_id = 0x1008,
+};
+
+typedef struct CubieBoardState {
+AwA10State *a10;
+MemoryRegion sdram;
+} CubieBoardState;
+
+static void cubieboard_init(QEMUMachineInitArgs *args)
+{
+CubieBoardState *s = g_new(CubieBoardState, 1);
+Error *err = NULL;
+
+s-a10 = AW_A10(object_new(TYPE_AW_A10));
+object_property_set_bool(OBJECT(s-a10), true, realized, err);
+if (err != NULL) {
+error_report(Couldn't realize Allwinner A10: %s\n,
+error_get_pretty(err));
+exit(1);
+}
+
+memory_region_init_ram(s-sdram, NULL, cubieboard.ram, args-ram_size);
+vmstate_register_ram_global(s-sdram);
+memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
+s-sdram);
+
+cubieboard_binfo.ram_size = args-ram_size;
+cubieboard_binfo.kernel_filename = args-kernel_filename;
+cubieboard_binfo.kernel_cmdline = args-kernel_cmdline;
+arm_load_kernel(s-a10-cpu, cubieboard_binfo);
+}
+
+static QEMUMachine cubieboard_machine = {
+.name = cubieboard,
+.desc = cubietech cubieboard,
+.init = cubieboard_init,
+};
+
+
+static void cubieboard_machine_init(void)
+{
+qemu_register_machine(cubieboard_machine);
+}
+
+machine_init(cubieboard_machine_init)
--
1.7.2.5
Re: [Qemu-devel] [PATCH v2 0/4] X86/KVM: enable Intel MPX for KVM
Paolo, comments for version 2? Thanks, Jinsong Liu, Jinsong wrote: These patches are version 2 to enalbe Intel MPX for KVM. Version 1: * Add some Intel MPX definiation * Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features enable/disable * vmx and msr handle for MPX support at KVM * enalbe MPX feature for guest Version 2: * remove generic MPX definiation, kernel side has add the definiation * add MSR_IA32_BNDCFGS to msrs_to_save Thanks, Jinsong Liu Jinsong (4): KVM/X86: Fix xsave cpuid exposing bug KVM/X86: Intel MPX vmx and msr handle KVM/X86: add MSR_IA32_BNDCFGS to msrs_to_save KVM/X86: Enable Intel MPX for guest. arch/x86/include/asm/vmx.h|4 arch/x86/include/asm/xsave.h |2 ++ arch/x86/include/uapi/asm/msr-index.h |1 + arch/x86/kvm/cpuid.c |8 arch/x86/kvm/vmx.c| 18 -- arch/x86/kvm/x86.c| 12 +--- arch/x86/kvm/x86.h|3 ++- 7 files changed, 38 insertions(+), 10 deletions(-)
Re: [Qemu-devel] [PATCH 2/5] machine: introduce get_fw_dev_path() callback
On 12/11/2013 06:59 PM, Alexey Kardashevskiy wrote: On 12/11/2013 06:47 PM, Paolo Bonzini wrote: Il 11/12/2013 06:20, Alexey Kardashevskiy ha scritto: Any progress on this? I am asking since the patchset about bootindex you gave me yesterday prints (process:38896): GLib-CRITICAL **: g_hash_table_foreach: assertion `version == hash_table-version' failed which I fixed by moving the machine object creation chunk before kvm_init() in vl.c. btw what do I do with that patchset now? I works for me (except the issue above), do I have to repost it again? Thanks. Please do, but we need to sort out the get_fw_dev_path suffixes first. I'll be on IRC in ~1 hour. And this is not it, make check on x86 fails: GTESTER tests/test-bitops LINK tests/test-qdev-global-props hw/core/qdev.o: In function `qdev_get_fw_dev_path_from_handler': /home/alexey/p/qemu/hw/core/qdev.c:514: undefined reference to `fw_path_provider_try_get_dev_path' collect2: error: ld returned 1 exit status And make check on ppc64 fails: GTESTER check-qtest-ppc64 (process:34077): GLib-CRITICAL **: g_hash_table_foreach: assertion `version == hash_table-version' failed Unable to find PowerPC CPU definition Broken pipe GTester: last random seed: R02S285a6f9556504cf9918b792d3bbff9f3 (process:34081): GLib-CRITICAL **: g_hash_table_foreach: assertion `version == hash_table-version' failed Unable to find PowerPC CPU definition Broken pipe GTester: last random seed: R02S4b1c4b660fcbbbf3907b024c4dd96e69 Oh :) -- Alexey
Re: [Qemu-devel] [PULL 1/4] net: Adding netmap network backend
On Tue, Dec 10, 2013 at 10:49:00AM -0700, Eric Blake wrote: On 12/09/2013 06:11 AM, Stefan Hajnoczi wrote: +++ b/qapi-schema.json @@ -3009,6 +3009,27 @@ 'hubid': 'int32' } } ## +# @NetdevNetmapOptions +# +# Connect a client to a netmap-enabled NIC or to a VALE switch port +# +# @ifname: Either the name of an existing network interface supported by +# netmap, or the name of a VALE port (created on the fly). +# A VALE port name is in the form 'valeXXX:YYY', where XXX and +# YYY are non-negative integers. XXX identifies a switch and +# YYY identifies a port of the switch. VALE ports having the +# same XXX are therefore connected to the same switch. +# +# @devname: #optional path of the netmap device (default: '/dev/netmap'). +# +# Since 1.8 s/1.8/2.0/ Thank you for spotting this. Sending a separate patch to fix this since the pull request has been merged. Stefan
Re: [Qemu-devel] [PATCH v2 0/4] dataplane: use more of the generic virtio data structures, drop hostmem
On Tue, Dec 10, 2013 at 01:26:57PM +0100, Paolo Bonzini wrote:
Now that the memory API is thread-safe, we can use it in
virtio-blk-dataplane and replace hostmem.[ch]. This series does this,
and also changes the vring API to use VirtQueueElement (with an eye
towards migration). With this change, virtio-blk-dataplane is also safe
against memory hot-unplug.
The next step would be to replace memory_region_find with
address_space_{map,unmap}, which handle dirtying of memory correctly.
However these APIs are not thread-safe yet, and neither is the handling
of dirty memory (Juan's patches may be a start here).
Also, the usage of iov_discard_{front,back} may cause some complication
when we use address_space_{map,unmap}. We may have to change a bit the
logic in virtio-blk-dataplane to switch to address_space_{map,unmap}.
v1-v2: introduce vring_free_element
Paolo Bonzini (4):
vring: create a common function to parse descriptors
vring: factor common code for error exits
dataplane: change vring API to use VirtQueueElement
dataplane: replace hostmem with memory_region_find
hw/block/dataplane/virtio-blk.c | 86 +---
hw/virtio/dataplane/Makefile.objs | 2 +-
hw/virtio/dataplane/hostmem.c | 183
hw/virtio/dataplane/vring.c | 253
++
include/hw/virtio/dataplane/hostmem.h | 58
include/hw/virtio/dataplane/vring.h | 10 +-
6 files changed, 203 insertions(+), 389 deletions(-)
delete mode 100644 hw/virtio/dataplane/hostmem.c
delete mode 100644 include/hw/virtio/dataplane/hostmem.h
Reviewed-by: Stefan Hajnoczi stefa...@redhat.com
[Qemu-devel] [RfC PATCH] x86: gigabyte alignment for ram
Map 3G (i440fx) or 2G (q35) of memory below 4G, so the RAM pieces
are nicely aligned to gigabyte borders.
Keep old memory layout for (a) old machine types and (b) in case all
memory fits below 4G and thus we don't have to split RAM into pieces
in the first place. The later makes sure this change doesn't take
away memory from 32bit guests.
So, with i440fx and up to 3.5 GB of memory, all of it will be mapped
below 4G. With more than 3.5 GB of memory 3 GB will be mapped below
4G and the remaining amount will be mapped above 4G.
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hw/i386/pc_piix.c | 20 +---
hw/i386/pc_q35.c | 20 +---
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index ab56285..60635a5 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -59,6 +59,7 @@ static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
static bool has_pci_info;
static bool has_acpi_build = true;
+static bool gigabyte_align = true;
/* PC hardware initialisation */
static void pc_init1(QEMUMachineInitArgs *args,
@@ -105,8 +106,9 @@ static void pc_init1(QEMUMachineInitArgs *args,
}
if (args-ram_size = 0xe000) {
-above_4g_mem_size = args-ram_size - 0xe000;
-below_4g_mem_size = 0xe000;
+ram_addr_t lowmem = gigabyte_align ? 0xc000 : 0xe000;
+above_4g_mem_size = args-ram_size - lowmem;
+below_4g_mem_size = lowmem;
} else {
above_4g_mem_size = 0;
below_4g_mem_size = args-ram_size;
@@ -235,11 +237,17 @@ static void pc_init_pci(QEMUMachineInitArgs *args)
pc_init1(args, 1, 1);
}
+static void pc_compat_1_7(QEMUMachineInitArgs *args)
+{
+gigabyle_align = false;
+}
+
static void pc_compat_1_6(QEMUMachineInitArgs *args)
{
has_pci_info = false;
rom_file_in_ram = false;
has_acpi_build = false;
+pc_compat_1_7(args);
}
static void pc_compat_1_5(QEMUMachineInitArgs *args)
@@ -267,6 +275,12 @@ static void pc_compat_1_2(QEMUMachineInitArgs *args)
disable_kvm_pv_eoi();
}
+static void pc_init_pci_1_7(QEMUMachineInitArgs *args)
+{
+pc_compat_1_7(args);
+pc_init_pci(args);
+}
+
static void pc_init_pci_1_6(QEMUMachineInitArgs *args)
{
pc_compat_1_6(args);
@@ -356,7 +370,7 @@ static QEMUMachine pc_i440fx_machine_v2_0 = {
static QEMUMachine pc_i440fx_machine_v1_7 = {
PC_I440FX_1_7_MACHINE_OPTIONS,
.name = pc-i440fx-1.7,
-.init = pc_init_pci,
+.init = pc_init_pci_1_7,
};
#define PC_I440FX_1_6_MACHINE_OPTIONS PC_I440FX_MACHINE_OPTIONS
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 97aa842..3d4a32c 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -49,6 +49,7 @@
static bool has_pci_info;
static bool has_acpi_build = true;
+static bool gigabyte_align = true;
/* PC hardware initialisation */
static void pc_q35_init(QEMUMachineInitArgs *args)
@@ -91,8 +92,9 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
kvmclock_create();
if (args-ram_size = 0xb000) {
-above_4g_mem_size = args-ram_size - 0xb000;
-below_4g_mem_size = 0xb000;
+ram_addr_t lowmem = gigabyte_align ? 0x8000 : 0xb000;
+above_4g_mem_size = args-ram_size - lowmem;
+below_4g_mem_size = lowmem;
} else {
above_4g_mem_size = 0;
below_4g_mem_size = args-ram_size;
@@ -217,11 +219,17 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
}
}
+static void pc_compat_1_7(QEMUMachineInitArgs *args)
+{
+gigabyte_align = false;
+}
+
static void pc_compat_1_6(QEMUMachineInitArgs *args)
{
has_pci_info = false;
rom_file_in_ram = false;
has_acpi_build = false;
+pc_compat_1_7(args);
}
static void pc_compat_1_5(QEMUMachineInitArgs *args)
@@ -236,6 +244,12 @@ static void pc_compat_1_4(QEMUMachineInitArgs *args)
x86_cpu_compat_set_features(Westmere, FEAT_1_ECX, 0,
CPUID_EXT_PCLMULQDQ);
}
+static void pc_q35_init_1_7(QEMUMachineInitArgs *args)
+{
+pc_compat_1_7(args);
+pc_q35_init(args);
+}
+
static void pc_q35_init_1_6(QEMUMachineInitArgs *args)
{
pc_compat_1_6(args);
@@ -275,7 +289,7 @@ static QEMUMachine pc_q35_machine_v2_0 = {
static QEMUMachine pc_q35_machine_v1_7 = {
PC_Q35_1_7_MACHINE_OPTIONS,
.name = pc-q35-1.7,
-.init = pc_q35_init,
+.init = pc_q35_init_1_7,
};
#define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
--
1.8.3.1
[Qemu-devel] [PATCH] qapi-schema: fix QEMU 1.8 references
We are moving boldly on to QEMU 2.0 in the next release. Some patches
written at a time where we assumed 1.8 would be the next version number
managed to sneak in.
s/1.8/2.0/ in qapi-schema.json
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
qapi-schema.json | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qapi-schema.json b/qapi-schema.json
index d6f8615..5aa4581 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -949,7 +949,7 @@
# (only present if removable is true)
#
# @dirty-bitmaps: #optional dirty bitmaps information (only present if the
-# driver has one or more dirty bitmaps) (Since 1.8)
+# driver has one or more dirty bitmaps) (Since 2.0)
#
# @io-status: #optional @BlockDeviceIoStatus. Only present if the device
# supports it and the VM is configured to stop on errors
@@ -3022,7 +3022,7 @@
#
# @devname: #optional path of the netmap device (default: '/dev/netmap').
#
-# Since 1.8
+# Since 2.0
##
{ 'type': 'NetdevNetmapOptions',
'data': {
--
1.8.4.2
Re: [Qemu-devel] [PULL 1/4] net: Adding netmap network backend
Do you want me to send the patch? Thanks, Vincenzo 2013/12/11 Stefan Hajnoczi stefa...@redhat.com On Tue, Dec 10, 2013 at 10:49:00AM -0700, Eric Blake wrote: On 12/09/2013 06:11 AM, Stefan Hajnoczi wrote: +++ b/qapi-schema.json @@ -3009,6 +3009,27 @@ 'hubid': 'int32' } } ## +# @NetdevNetmapOptions +# +# Connect a client to a netmap-enabled NIC or to a VALE switch port +# +# @ifname: Either the name of an existing network interface supported by +# netmap, or the name of a VALE port (created on the fly). +# A VALE port name is in the form 'valeXXX:YYY', where XXX and +# YYY are non-negative integers. XXX identifies a switch and +# YYY identifies a port of the switch. VALE ports having the +# same XXX are therefore connected to the same switch. +# +# @devname: #optional path of the netmap device (default: '/dev/netmap'). +# +# Since 1.8 s/1.8/2.0/ Thank you for spotting this. Sending a separate patch to fix this since the pull request has been merged. Stefan -- Vincenzo Maffione
Re: [Qemu-devel] [PULL 1/4] net: Adding netmap network backend
On Wed, Dec 11, 2013 at 10:04 AM, Vincenzo Maffione v.maffi...@gmail.com wrote: Do you want me to send the patch? Don't worry about it, I sent a patch this morning. Stefan
Re: [Qemu-devel] [PATCH] exec: separate sections and nodes per address space
On Tue, 2013-12-10 at 18:48 +0200, Michael S. Tsirkin wrote: On Tue, Dec 10, 2013 at 02:50:32PM +0200, Marcel Apfelbaum wrote: On Tue, 2013-12-10 at 13:38 +0100, Paolo Bonzini wrote: Il 10/12/2013 13:37, Marcel Apfelbaum ha scritto: Beside this it looks OK, the branch does not compile and I couldn't look into it more... Can you please also merge my other patch memory.c: bugfix - ref counting mismatch in memory_region_find ? Regarding the compilation issue, I suggest rebasing on top of Stefan's pull request (commit ac9524d, qemu-iotests: filter QEMU monitor \r\n, 2013-11-14). Sure, thanks, but Michael specifically asked for his pci branch, probably because it conflicts with his patch: exec: memory radix tree page level compression which is long (~50 patches) after qemu-iotests: filter QEMU monitor \r\n Exactly. Pls take a look, I think I fixed the issues with the rebase. I checked the patch and the rebase is OK, thanks! Marcel Rebasing on top of the later resulted in 0 conflicts/patch unchanged... Thanks, Marcel Paolo
[Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset.
Fix a bug that was introduced in commit c046e8c4. QEMU fails to
resume from suspend mode (S3).
Signed-off-by: Gal Hammer gham...@redhat.com
---
hw/acpi/piix4.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 93849c8..5c736a4 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -376,7 +376,6 @@ static void piix4_reset(void *opaque)
pci_conf[0x5b] = 0;
pci_conf[0x40] = 0x01; /* PM io base read only bit */
-pci_conf[0x80] = 0;
if (s-kvm_enabled) {
/* Mark SMM as already inited (until KVM supports SMM). */
--
1.8.1.4
[Qemu-devel] [PATCH v2] char: restore read callback on a reattached (hotplug) chardev
Fix a bug that was introduced in commit 386a5a1e. A removal of a device
set the chr handlers to NULL. However when the device is plugged back,
its read callback is not restored so data can't be transfter from the
host to the guest via the virtio-serial port.
https://bugzilla.redhat.com/show_bug.cgi?id=1027181
V2: - do not call chr_update_read_handler on device removal.
- add asserts to verify chr_update_read_handler is not called
with an assigned fd_in_tag to prevent fd leaks.
- update fd and udp backends' chr_update_read_handler function
so it won't remove fd_in to prevent a double release.
Signed-off-by: Gal Hammer gham...@redhat.com
---
qemu-char.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/qemu-char.c b/qemu-char.c
index e00f84c..69649f0 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -213,7 +213,7 @@ void qemu_chr_add_handlers(CharDriverState *s,
s-chr_read = fd_read;
s-chr_event = fd_event;
s-handler_opaque = opaque;
-if (s-chr_update_read_handler)
+if (fe_open s-chr_update_read_handler)
s-chr_update_read_handler(s);
if (!s-explicit_fe_open) {
@@ -870,6 +870,7 @@ static void fd_chr_update_read_handler(CharDriverState *chr)
{
FDCharDriver *s = chr-opaque;
+assert(!chr-fd_in_tag);
remove_fd_in_watch(chr);
if (s-fd_in) {
chr-fd_in_tag = io_add_watch_poll(s-fd_in, fd_chr_read_poll,
@@ -2228,7 +2229,7 @@ static void udp_chr_update_read_handler(CharDriverState
*chr)
{
NetCharDriver *s = chr-opaque;
-remove_fd_in_watch(chr);
+assert(!chr-fd_in_tag);
if (s-chan) {
chr-fd_in_tag = io_add_watch_poll(s-chan, udp_chr_read_poll,
udp_chr_read, chr);
@@ -2510,6 +2511,17 @@ static void tcp_chr_connect(void *opaque)
qemu_chr_be_generic_open(chr);
}
+static void tcp_chr_update_read_handler(CharDriverState *chr)
+{
+TCPCharDriver *s = chr-opaque;
+
+assert(!chr-fd_in_tag);
+if (s-chan !chr-fd_in_tag) {
+chr-fd_in_tag = io_add_watch_poll(s-chan, tcp_chr_read_poll,
+ tcp_chr_read, chr);
+}
+}
+
#define IACSET(x,a,b,c) x[0] = a; x[1] = b; x[2] = c;
static void tcp_chr_telnet_init(int fd)
{
@@ -2665,6 +2677,7 @@ static CharDriverState *qemu_chr_open_socket_fd(int fd,
bool do_nodelay,
chr-get_msgfd = tcp_get_msgfd;
chr-chr_add_client = tcp_chr_add_client;
chr-chr_add_watch = tcp_chr_add_watch;
+chr-chr_update_read_handler = tcp_chr_update_read_handler;
/* be isn't opened until we get a connection */
chr-explicit_be_open = true;
--
1.8.1.4
Re: [Qemu-devel] [PATCH] qapi-schema: fix QEMU 1.8 references
On 2013年12月11日 16:49, Stefan Hajnoczi wrote:
We are moving boldly on to QEMU 2.0 in the next release. Some patches
written at a time where we assumed 1.8 would be the next version number
managed to sneak in.
s/1.8/2.0/ in qapi-schema.json
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
qapi-schema.json | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qapi-schema.json b/qapi-schema.json
index d6f8615..5aa4581 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -949,7 +949,7 @@
# (only present if removable is true)
#
# @dirty-bitmaps: #optional dirty bitmaps information (only present if the
-# driver has one or more dirty bitmaps) (Since 1.8)
+# driver has one or more dirty bitmaps) (Since 2.0)
#
# @io-status: #optional @BlockDeviceIoStatus. Only present if the device
# supports it and the VM is configured to stop on errors
@@ -3022,7 +3022,7 @@
#
# @devname: #optional path of the netmap device (default: '/dev/netmap').
#
-# Since 1.8
+# Since 2.0
##
{ 'type': 'NetdevNetmapOptions',
'data': {
Reviewed-by: Fam Zheng f...@redhat.com
Re: [Qemu-devel] [PATCH v2 0/4] X86/KVM: enable Intel MPX for KVM
Il 11/12/2013 09:31, Liu, Jinsong ha scritto: Paolo, comments for version 2? I think I commented that it's fine, I'm just waiting for a rebase on top of the generic patches. Paolo Thanks, Jinsong Liu, Jinsong wrote: These patches are version 2 to enalbe Intel MPX for KVM. Version 1: * Add some Intel MPX definiation * Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features enable/disable * vmx and msr handle for MPX support at KVM * enalbe MPX feature for guest Version 2: * remove generic MPX definiation, kernel side has add the definiation * add MSR_IA32_BNDCFGS to msrs_to_save Thanks, Jinsong Liu Jinsong (4): KVM/X86: Fix xsave cpuid exposing bug KVM/X86: Intel MPX vmx and msr handle KVM/X86: add MSR_IA32_BNDCFGS to msrs_to_save KVM/X86: Enable Intel MPX for guest. arch/x86/include/asm/vmx.h|4 arch/x86/include/asm/xsave.h |2 ++ arch/x86/include/uapi/asm/msr-index.h |1 + arch/x86/kvm/cpuid.c |8 arch/x86/kvm/vmx.c| 18 -- arch/x86/kvm/x86.c| 12 +--- arch/x86/kvm/x86.h|3 ++- 7 files changed, 38 insertions(+), 10 deletions(-)
Re: [Qemu-devel] [PATCH v10 5/5] hw/arm: add cubieboard support
On 11 December 2013 05:59, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote: On Mon, Dec 9, 2013 at 10:10 AM, liguang lig.f...@cn.fujitsu.com wrote: Signed-off-by: liguang lig.f...@cn.fujitsu.com Acked-by: Peter Crosthwaite peter.crosthwa...@xilinx.com Why Acked-by rather than Reviewed-by ? thanks -- PMM
[Qemu-devel] [PATCH v4 4/8] spapr-llan: add to boot device list
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru --- hw/net/spapr_llan.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c index 1bd6f50..229de00 100644 --- a/hw/net/spapr_llan.c +++ b/hw/net/spapr_llan.c @@ -29,6 +29,7 @@ #include hw/qdev.h #include hw/ppc/spapr.h #include hw/ppc/spapr_vio.h +#include sysemu/sysemu.h #include libfdt.h @@ -213,6 +214,8 @@ static int spapr_vlan_init(VIOsPAPRDevice *sdev) object_get_typename(OBJECT(sdev)), sdev-qdev.id, dev); qemu_format_nic_info_str(qemu_get_queue(dev-nic), dev-nicconf.macaddr.a); +add_boot_device_path(dev-nicconf.bootindex, DEVICE(dev), ); + return 0; } -- 1.8.4.rc4
[Qemu-devel] [PATCH v4 1/8] qom: do not register interface types in the type table
From: Paolo Bonzini pbonz...@redhat.com
There should be no need to look them up nor enumerate the interface
types, whose classes are really just vtables. Just create the
types and add them to the interface list of the parent type.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
qom/object.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/qom/object.c b/qom/object.c
index fc19cf6..3a43186 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -88,7 +88,7 @@ static TypeImpl *type_table_lookup(const char *name)
return g_hash_table_lookup(type_table_get(), name);
}
-static TypeImpl *type_register_internal(const TypeInfo *info)
+static TypeImpl *type_new(const TypeInfo *info)
{
TypeImpl *ti = g_malloc0(sizeof(*ti));
int i;
@@ -122,8 +122,15 @@ static TypeImpl *type_register_internal(const TypeInfo
*info)
}
ti-num_interfaces = i;
+return ti;
+}
+
+static TypeImpl *type_register_internal(const TypeInfo *info)
+{
+TypeImpl *ti;
+ti = type_new(info);
+
type_table_add(ti);
-
return ti;
}
@@ -216,7 +223,7 @@ static void type_initialize_interface(TypeImpl *ti, const
char *parent)
info.name = g_strdup_printf(%s::%s, ti-name, info.parent);
info.abstract = true;
-iface_impl = type_register(info);
+iface_impl = type_new(info);
type_initialize(iface_impl);
g_free((char *)info.name);
--
1.8.4.rc4
[Qemu-devel] [PATCH v4 8/8] spapr: define interface to fix device pathname
This defines an object with the interface to fix firmware pathnames
for devices which have @bootindex property.
This fixes SCSI disks device node names (which are wildcard nodes in
the device-tree).
This fixes PHB name from pci to pci@ where is a BUID as
there is no bus on top of sPAPRPHBState where PHB firmware name could
be fixed using the BusClass::get_fw_dev_path mechanism.
This stores the boot list in the /chosen/qemu,boot-list property of
the device tree. \n are replaced by spaces to support OF1275.
SLOF needs an update in order to support the boot list.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/ppc/spapr.c | 80 +-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 38b43c9..2cac1ef 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -26,6 +26,7 @@
*/
#include sysemu/sysemu.h
#include hw/hw.h
+#include hw/fw-path-provider.h
#include elf.h
#include net/net.h
#include sysemu/blockdev.h
@@ -45,6 +46,7 @@
#include hw/pci/msi.h
#include hw/pci/pci.h
+#include hw/scsi/scsi.h
#include exec/address-spaces.h
#include hw/usb.h
@@ -80,6 +82,8 @@
#define HTAB_SIZE(spapr)(1ULL ((spapr)-htab_shift))
+#define TYPE_SPAPR_MACHINE machine-spapr
+
sPAPREnvironment *spapr;
int spapr_allocate_irq(int hint, bool lsi)
@@ -587,7 +591,9 @@ static void spapr_finalize_fdt(sPAPREnvironment *spapr,
hwaddr rtas_addr,
hwaddr rtas_size)
{
-int ret;
+int ret, i;
+size_t cb = 0;
+char *bootlist;
void *fdt;
sPAPRPHBState *phb;
@@ -629,6 +635,21 @@ static void spapr_finalize_fdt(sPAPREnvironment *spapr,
fprintf(stderr, Couldn't finalize CPU device tree properties\n);
}
+bootlist = get_boot_devices_list(cb, true);
+if (cb bootlist) {
+int offset = fdt_path_offset(fdt, /chosen);
+if (offset 0) {
+exit(1);
+}
+for (i = 0; i cb; i++) {
+if (bootlist[i] == '\n') {
+bootlist[i] = ' ';
+}
+
+}
+ret = fdt_setprop_string(fdt, offset, qemu,boot-list, bootlist);
+}
+
if (!spapr-has_graphics) {
spapr_populate_chosen_stdout(fdt, spapr-vio_bus);
}
@@ -1352,6 +1373,7 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
static QEMUMachine spapr_machine = {
.name = pseries,
.desc = pSeries Logical Partition (PAPR compliant),
+.class_name = TYPE_SPAPR_MACHINE,
.is_default = 1,
.init = ppc_spapr_init,
.reset = ppc_spapr_reset,
@@ -1367,3 +1389,59 @@ static void spapr_machine_init(void)
}
machine_init(spapr_machine_init);
+
+/*
+ * Implementation of an interface to adjust firmware patch
+ * for the bootindex property handling.
+ */
+static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
+ DeviceState *dev)
+{
+#define CAST(type, obj, name) \
+((type *)object_dynamic_cast(OBJECT(obj), (name)))
+SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
+sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
+
+if (d) {
+/*
+ * Replace channel@0/disk@0,0 with disk@8000:
+ * We use SRP luns of the form 8000 | (bus 8) | (id 5) | lun
+ * in the top 16 bits of the 64-bit LUN
+ */
+unsigned id = 0x8000 | (d-channel 8) | (d-id 5) | d-lun;
+
+return g_strdup_printf(%s@%PRIX64, qdev_fw_name(dev),
+ (uint64_t)id 48);
+}
+
+if (phb) {
+/* Replace pci with pci@8002000 */
+return g_strdup_printf(pci@%PRIX64, phb-buid);
+}
+
+return NULL;
+}
+
+static void spapr_machine_class_init(ObjectClass *oc, void *data)
+{
+FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
+
+fwc-get_dev_path = spapr_get_fw_dev_path;
+}
+
+static const TypeInfo spapr_machine_info = {
+.name = TYPE_SPAPR_MACHINE,
+.parent= TYPE_OBJECT,
+.class_init= spapr_machine_class_init,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_FW_PATH_PROVIDER },
+{ }
+}
+};
+
+static void spapr_machine_register_types(void)
+{
+type_register_static(spapr_machine_info);
+}
+
+type_init(spapr_machine_register_types)
--
1.8.4.rc4
[Qemu-devel] [PATCH v4 6/8] qdev: introduce FWPathProvider interface
QEMU supports firmware names for all devices in the QEMU tree but
some architectures expect some parts of firmware path names in different
format.
This introduces a firmware-pathname-change interface definition.
If some machines needs to redefine the firmware path format, it has
to add the TYPE_FW_PATH_PROVIDER interface to an object that is above
the device on the QOM tree (typically /machine).
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
Changes:
v4:
* added fw-path-provider.o into tests/Makefile
* fixed 80chars warning from checkpatch.pl
---
hw/core/Makefile.objs | 1 +
hw/core/fw-path-provider.c| 36
hw/core/qdev.c| 18 +-
include/hw/fw-path-provider.h | 32
tests/Makefile| 1 +
5 files changed, 87 insertions(+), 1 deletion(-)
create mode 100644 hw/core/fw-path-provider.c
create mode 100644 include/hw/fw-path-provider.h
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index 950146c..d829479 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -1,5 +1,6 @@
# core qdev-related obj files, also used by *-user:
common-obj-y += qdev.o qdev-properties.o
+common-obj-y += fw-path-provider.o
# irq.o needed for qdev GPIO handling:
common-obj-y += irq.o
diff --git a/hw/core/fw-path-provider.c b/hw/core/fw-path-provider.c
new file mode 100644
index 000..0187568
--- /dev/null
+++ b/hw/core/fw-path-provider.c
@@ -0,0 +1,36 @@
+#include hw/fw-path-provider.h
+
+char *fw_path_provider_get_dev_path(FWPathProvider *p, BusState *bus,
+DeviceState *dev)
+{
+FWPathProviderClass *k = FW_PATH_PROVIDER_GET_CLASS(p);
+
+return k-get_dev_path(p, bus, dev);
+}
+
+char *fw_path_provider_try_get_dev_path(Object *o, BusState *bus,
+DeviceState *dev)
+{
+FWPathProvider *p = (FWPathProvider *)
+object_dynamic_cast(o, TYPE_FW_PATH_PROVIDER);
+
+if (p) {
+return fw_path_provider_get_dev_path(p, bus, dev);
+}
+
+return NULL;
+}
+
+static const TypeInfo fw_path_provider_info = {
+.name = TYPE_FW_PATH_PROVIDER,
+.parent= TYPE_INTERFACE,
+.class_size = sizeof(FWPathProviderClass),
+};
+
+
+static void fw_path_provider_register_types(void)
+{
+type_register_static(fw_path_provider_info);
+}
+
+type_init(fw_path_provider_register_types)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 959130c..81a0e75 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -26,6 +26,7 @@
this API directly. */
#include hw/qdev.h
+#include hw/fw-path-provider.h
#include sysemu/sysemu.h
#include qapi/error.h
#include qapi/qmp/qerror.h
@@ -503,6 +504,18 @@ static char *bus_get_fw_dev_path(BusState *bus,
DeviceState *dev)
return NULL;
}
+static char *qdev_get_fw_dev_path_from_handler(BusState *bus, DeviceState *dev)
+{
+Object *obj = OBJECT(dev);
+char *d = NULL;
+
+while (!d obj-parent) {
+obj = obj-parent;
+d = fw_path_provider_try_get_dev_path(obj, bus, dev);
+}
+return d;
+}
+
static int qdev_get_fw_dev_path_helper(DeviceState *dev, char *p, int size)
{
int l = 0;
@@ -510,7 +523,10 @@ static int qdev_get_fw_dev_path_helper(DeviceState *dev,
char *p, int size)
if (dev dev-parent_bus) {
char *d;
l = qdev_get_fw_dev_path_helper(dev-parent_bus-parent, p, size);
-d = bus_get_fw_dev_path(dev-parent_bus, dev);
+d = qdev_get_fw_dev_path_from_handler(dev-parent_bus, dev);
+if (!d) {
+d = bus_get_fw_dev_path(dev-parent_bus, dev);
+}
if (d) {
l += snprintf(p + l, size - l, %s, d);
g_free(d);
diff --git a/include/hw/fw-path-provider.h b/include/hw/fw-path-provider.h
new file mode 100644
index 000..765170b
--- /dev/null
+++ b/include/hw/fw-path-provider.h
@@ -0,0 +1,32 @@
+#ifndef FW_PATH_PROVIDER_H
+#define FW_PATH_PROVIDER_H 1
+
+#include qemu-common.h
+#include qom/object.h
+
+#define TYPE_FW_PATH_PROVIDER fw-path-provider
+
+#define FW_PATH_PROVIDER_CLASS(klass) \
+ OBJECT_CLASS_CHECK(FWPathProviderClass, (klass), TYPE_FW_PATH_PROVIDER)
+#define FW_PATH_PROVIDER_GET_CLASS(obj) \
+OBJECT_GET_CLASS(FWPathProviderClass, (obj), TYPE_FW_PATH_PROVIDER)
+#define FW_PATH_PROVIDER(obj) \
+ INTERFACE_CHECK(FWPathProvider, (obj), TYPE_FW_PATH_PROVIDER)
+
+typedef struct FWPathProvider {
+Object Parent;
+} FWPathProvider;
+
+typedef void (*StreamCanPushNotifyFn)(void *opaque);
+
+typedef struct FWPathProviderClass {
+InterfaceClass parent;
+char *(*get_dev_path)(FWPathProvider *p, BusState *bus, DeviceState *dev);
+} FWPathProviderClass;
+
+char *fw_path_provider_get_dev_path(FWPathProvider *p, BusState *bus,
+DeviceState *dev);
+char *fw_path_provider_try_get_dev_path(Object *o,
[Qemu-devel] [PATCH v4 7/8] vl: allow customizing the class of /machine
From: Paolo Bonzini pbonz...@redhat.com
This is a first step towards QOMifying /machine.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
include/hw/boards.h | 1 +
vl.c| 5 +
2 files changed, 6 insertions(+)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 5a7ae9f..431d016 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -25,6 +25,7 @@ typedef struct QEMUMachine {
const char *name;
const char *alias;
const char *desc;
+const char *class_name;
QEMUMachineInitFunc *init;
QEMUMachineResetFunc *reset;
QEMUMachineHotAddCPUFunc *hot_add_cpu;
diff --git a/vl.c b/vl.c
index 2cde6a1..442b190 100644
--- a/vl.c
+++ b/vl.c
@@ -4047,6 +4047,11 @@ int main(int argc, char **argv, char **envp)
qtest_init();
}
+if (machine-class_name) {
+Object *m = object_new(machine-class_name);
+object_property_add_child(object_get_root(), machine, m, NULL);
+}
+
machine_opts = qemu_get_machine_opts();
kernel_filename = qemu_opt_get(machine_opts, kernel);
initrd_filename = qemu_opt_get(machine_opts, initrd);
--
1.8.4.rc4
[Qemu-devel] [PATCH v4 2/8] qom: detect bad reentrance during object_class_foreach
From: Hervé Poussineau hpous...@reactos.org
We should not modify the type hash table while it is being iterated on.
Assert that it does not happen.
Signed-off-by: Hervé Poussineau hpous...@reactos.org
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
v4:
* rename: @enumerating - @enumerating_types
* @enumerating_types is static and does not require initialization to false
---
qom/object.c | 4
1 file changed, 4 insertions(+)
diff --git a/qom/object.c b/qom/object.c
index 3a43186..937af00 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -78,8 +78,10 @@ static GHashTable *type_table_get(void)
return type_table;
}
+static bool enumerating_types;
static void type_table_add(TypeImpl *ti)
{
+assert(!enumerating_types);
g_hash_table_insert(type_table_get(), (void *)ti-name, ti);
}
@@ -666,7 +668,9 @@ void object_class_foreach(void (*fn)(ObjectClass *klass,
void *opaque),
{
OCFData data = { fn, implements_type, include_abstract, opaque };
+enumerating_types = true;
g_hash_table_foreach(type_table_get(), object_class_foreach_tramp, data);
+enumerating_types = false;
}
int object_child_foreach(Object *obj, int (*fn)(Object *child, void *opaque),
--
1.8.4.rc4
[Qemu-devel] [PATCH v4 3/8] boot: extend get_boot_devices_list() to ignore suffixes
As suffixes do not make sense for sPAPR's device tree and
there is no way to filter them out on the BusState::get_fw_dev_path
level, let's add an ability for the external caller to specify
whether to apply suffixes or not.
We could handle suffixes in SLOF (ignore for now) but this would require
serious rework in the node opening code in SLOF which has no obvious
benefit for the currently emulated sPAPR machine.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
v4:
* changed commit message about not having plans in SLOF rework as it is scary :)
---
hw/nvram/fw_cfg.c | 2 +-
include/sysemu/sysemu.h | 2 +-
vl.c| 6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index f5dc3ea..4d0c76f 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -504,7 +504,7 @@ static void fw_cfg_machine_ready(struct Notifier *n, void
*data)
{
size_t len;
FWCfgState *s = container_of(n, FWCfgState, machine_ready);
-char *bootindex = get_boot_devices_list(len);
+char *bootindex = get_boot_devices_list(len, false);
fw_cfg_add_file(s, bootorder, (uint8_t*)bootindex, len);
}
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 495dae8..2b71a4a 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -185,7 +185,7 @@ void rtc_change_mon_event(struct tm *tm);
void add_boot_device_path(int32_t bootindex, DeviceState *dev,
const char *suffix);
-char *get_boot_devices_list(size_t *size);
+char *get_boot_devices_list(size_t *size, bool ignore_suffixes);
DeviceState *get_boot_device(uint32_t position);
diff --git a/vl.c b/vl.c
index b0399de..2cde6a1 100644
--- a/vl.c
+++ b/vl.c
@@ -1213,7 +1213,7 @@ DeviceState *get_boot_device(uint32_t position)
* memory pointed by size is assigned total length of the array in bytes
*
*/
-char *get_boot_devices_list(size_t *size)
+char *get_boot_devices_list(size_t *size, bool ignore_suffixes)
{
FWBootEntry *i;
size_t total = 0;
@@ -1228,7 +1228,7 @@ char *get_boot_devices_list(size_t *size)
assert(devpath);
}
-if (i-suffix devpath) {
+if (i-suffix !ignore_suffixes devpath) {
size_t bootpathlen = strlen(devpath) + strlen(i-suffix) + 1;
bootpath = g_malloc(bootpathlen);
@@ -1236,7 +1236,7 @@ char *get_boot_devices_list(size_t *size)
g_free(devpath);
} else if (devpath) {
bootpath = devpath;
-} else {
+} else if (!ignore_suffixes) {
assert(i-suffix);
bootpath = g_strdup(i-suffix);
}
--
1.8.4.rc4
[Qemu-devel] [PATCH v4 5/8] spapr-vio: fix firmware names
This changes VIO bridge fw name from spapr-vio-bridge to vdevice and
vscsi/veth node names from QEMU object names to VIO specific device tree
names.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/ppc/spapr_vio.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index fee6195..42b8416 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -68,6 +68,7 @@ static void spapr_vio_bus_class_init(ObjectClass *klass, void
*data)
BusClass *k = BUS_CLASS(klass);
k-get_dev_path = spapr_vio_get_dev_name;
+k-get_fw_dev_path = spapr_vio_get_dev_name;
}
static const TypeInfo spapr_vio_bus_info = {
@@ -531,6 +532,7 @@ static void spapr_vio_bridge_class_init(ObjectClass *klass,
void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+dc-fw_name = vdevice;
k-init = spapr_vio_bridge_init;
dc-no_user = 1;
}
--
1.8.4.rc4
[Qemu-devel] [PATCH v4 0/8] spapr: bootindex support
With the great help from Paolo, I am presenting yet another try of bootindex support on sPAPR, this time with some QOM fixes. Details are in the commit messages. Please, comment. Thanks. Alexey Kardashevskiy (5): boot: extend get_boot_devices_list() to ignore suffixes spapr-llan: add to boot device list spapr-vio: fix firmware names qdev: introduce FWPathProvider interface spapr: define interface to fix device pathname Hervé Poussineau (1): qom: detect bad reentrance during object_class_foreach Paolo Bonzini (2): qom: do not register interface types in the type table vl: allow customizing the class of /machine hw/core/Makefile.objs | 1 + hw/core/fw-path-provider.c| 34 ++ hw/core/qdev.c| 18 +- hw/net/spapr_llan.c | 3 ++ hw/nvram/fw_cfg.c | 2 +- hw/ppc/spapr.c| 80 ++- hw/ppc/spapr_vio.c| 2 ++ include/hw/boards.h | 1 + include/hw/fw-path-provider.h | 31 + include/sysemu/sysemu.h | 2 +- qom/object.c | 17 +++-- tests/Makefile| 1 + vl.c | 11 -- 13 files changed, 193 insertions(+), 10 deletions(-) create mode 100644 hw/core/fw-path-provider.c create mode 100644 include/hw/fw-path-provider.h -- 1.8.4.rc4
Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset.
Il 11/12/2013 10:21, Gal Hammer ha scritto:
Fix a bug that was introduced in commit c046e8c4. QEMU fails to
resume from suspend mode (S3).
Signed-off-by: Gal Hammer gham...@redhat.com
---
hw/acpi/piix4.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 93849c8..5c736a4 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -376,7 +376,6 @@ static void piix4_reset(void *opaque)
pci_conf[0x5b] = 0;
pci_conf[0x40] = 0x01; /* PM io base read only bit */
-pci_conf[0x80] = 0;
if (s-kvm_enabled) {
/* Mark SMM as already inited (until KVM supports SMM). */
Cc: qemu-sta...@nongnu.org
Re: [Qemu-devel] [PATCH v10 5/5] hw/arm: add cubieboard support
On Wed, Dec 11, 2013 at 7:56 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 11 December 2013 05:59, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote: On Mon, Dec 9, 2013 at 10:10 AM, liguang lig.f...@cn.fujitsu.com wrote: Signed-off-by: liguang lig.f...@cn.fujitsu.com Acked-by: Peter Crosthwaite peter.crosthwa...@xilinx.com Why Acked-by rather than Reviewed-by ? Not 100% myself on the new QOM styles and standards around boards and SoC. But it is reviewed by me to the best of my knowledge. If that is enough, please feel free to promote to Reviewed-by. thanks -- PMM
Re: [Qemu-devel] [PATCH v10 5/5] hw/arm: add cubieboard support
On 11 December 2013 10:24, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote: On Wed, Dec 11, 2013 at 7:56 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 11 December 2013 05:59, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote: On Mon, Dec 9, 2013 at 10:10 AM, liguang lig.f...@cn.fujitsu.com wrote: Signed-off-by: liguang lig.f...@cn.fujitsu.com Acked-by: Peter Crosthwaite peter.crosthwa...@xilinx.com Why Acked-by rather than Reviewed-by ? Not 100% myself on the new QOM styles and standards around boards and SoC. But it is reviewed by me to the best of my knowledge. If that is enough, please feel free to promote to Reviewed-by. I'd call that Reviewed-by, yes. Acked-by is just I don't object to this which is a sufficiently weak statement that it's not often used... thanks -- PMM
Re: [Qemu-devel] [PATCH v10 5/5] hw/arm: add cubieboard support
On Wed, Dec 11, 2013 at 8:31 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 11 December 2013 10:24, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote: On Wed, Dec 11, 2013 at 7:56 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 11 December 2013 05:59, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote: On Mon, Dec 9, 2013 at 10:10 AM, liguang lig.f...@cn.fujitsu.com wrote: Signed-off-by: liguang lig.f...@cn.fujitsu.com Acked-by: Peter Crosthwaite peter.crosthwa...@xilinx.com Why Acked-by rather than Reviewed-by ? Not 100% myself on the new QOM styles and standards around boards and SoC. But it is reviewed by me to the best of my knowledge. If that is enough, please feel free to promote to Reviewed-by. I'd call that Reviewed-by, yes. Acked-by is just I don't object to this which is a sufficiently weak statement that it's not often used... Ok, Liguang, please drop the acks on p4 and p5 and replace by Reviewed-by on next spin. Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com Regards, Peter thanks -- PMM
Re: [Qemu-devel] [PATCH v4 0/8] spapr: bootindex support
Il 11/12/2013 11:22, Alexey Kardashevskiy ha scritto: With the great help from Paolo, I am presenting yet another try of bootindex support on sPAPR, this time with some QOM fixes. Details are in the commit messages. Please, comment. Thanks. Alexey Kardashevskiy (5): boot: extend get_boot_devices_list() to ignore suffixes spapr-llan: add to boot device list spapr-vio: fix firmware names qdev: introduce FWPathProvider interface spapr: define interface to fix device pathname Hervé Poussineau (1): qom: detect bad reentrance during object_class_foreach Paolo Bonzini (2): qom: do not register interface types in the type table vl: allow customizing the class of /machine hw/core/Makefile.objs | 1 + hw/core/fw-path-provider.c| 34 ++ hw/core/qdev.c| 18 +- hw/net/spapr_llan.c | 3 ++ hw/nvram/fw_cfg.c | 2 +- hw/ppc/spapr.c| 80 ++- hw/ppc/spapr_vio.c| 2 ++ include/hw/boards.h | 1 + include/hw/fw-path-provider.h | 31 + include/sysemu/sysemu.h | 2 +- qom/object.c | 17 +++-- tests/Makefile| 1 + vl.c | 11 -- 13 files changed, 193 insertions(+), 10 deletions(-) create mode 100644 hw/core/fw-path-provider.c create mode 100644 include/hw/fw-path-provider.h Acked-by: Paolo Bonzini pbonz...@redhat.com
Re: [Qemu-devel] [PATCH v2] char: restore read callback on a reattached (hotplug) chardev
Il 11/12/2013 10:47, Gal Hammer ha scritto:
Fix a bug that was introduced in commit 386a5a1e. A removal of a device
set the chr handlers to NULL. However when the device is plugged back,
its read callback is not restored so data can't be transfter from the
host to the guest via the virtio-serial port.
https://bugzilla.redhat.com/show_bug.cgi?id=1027181
V2: - do not call chr_update_read_handler on device removal.
- add asserts to verify chr_update_read_handler is not called
with an assigned fd_in_tag to prevent fd leaks.
- update fd and udp backends' chr_update_read_handler function
so it won't remove fd_in to prevent a double release.
Signed-off-by: Gal Hammer gham...@redhat.com
---
qemu-char.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/qemu-char.c b/qemu-char.c
index e00f84c..69649f0 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -213,7 +213,7 @@ void qemu_chr_add_handlers(CharDriverState *s,
s-chr_read = fd_read;
s-chr_event = fd_event;
s-handler_opaque = opaque;
-if (s-chr_update_read_handler)
+if (fe_open s-chr_update_read_handler)
s-chr_update_read_handler(s);
if (!s-explicit_fe_open) {
@@ -870,6 +870,7 @@ static void fd_chr_update_read_handler(CharDriverState
*chr)
{
FDCharDriver *s = chr-opaque;
+assert(!chr-fd_in_tag);
remove_fd_in_watch(chr);
if (s-fd_in) {
chr-fd_in_tag = io_add_watch_poll(s-fd_in, fd_chr_read_poll,
@@ -2228,7 +2229,7 @@ static void udp_chr_update_read_handler(CharDriverState
*chr)
{
NetCharDriver *s = chr-opaque;
-remove_fd_in_watch(chr);
+assert(!chr-fd_in_tag);
if (s-chan) {
chr-fd_in_tag = io_add_watch_poll(s-chan, udp_chr_read_poll,
udp_chr_read, chr);
@@ -2510,6 +2511,17 @@ static void tcp_chr_connect(void *opaque)
qemu_chr_be_generic_open(chr);
}
+static void tcp_chr_update_read_handler(CharDriverState *chr)
+{
+TCPCharDriver *s = chr-opaque;
+
+assert(!chr-fd_in_tag);
+if (s-chan !chr-fd_in_tag) {
+chr-fd_in_tag = io_add_watch_poll(s-chan, tcp_chr_read_poll,
+ tcp_chr_read, chr);
+}
+}
+
#define IACSET(x,a,b,c) x[0] = a; x[1] = b; x[2] = c;
static void tcp_chr_telnet_init(int fd)
{
@@ -2665,6 +2677,7 @@ static CharDriverState *qemu_chr_open_socket_fd(int fd,
bool do_nodelay,
chr-get_msgfd = tcp_get_msgfd;
chr-chr_add_client = tcp_chr_add_client;
chr-chr_add_watch = tcp_chr_add_watch;
+chr-chr_update_read_handler = tcp_chr_update_read_handler;
/* be isn't opened until we get a connection */
chr-explicit_be_open = true;
Cc: qemu-sta...@nongnu.org
Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset.
On Wed, Dec 11, 2013 at 11:23:27AM +0100, Paolo Bonzini wrote:
Il 11/12/2013 10:21, Gal Hammer ha scritto:
Fix a bug that was introduced in commit c046e8c4. QEMU fails to
resume from suspend mode (S3).
Signed-off-by: Gal Hammer gham...@redhat.com
---
hw/acpi/piix4.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 93849c8..5c736a4 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -376,7 +376,6 @@ static void piix4_reset(void *opaque)
pci_conf[0x5b] = 0;
pci_conf[0x40] = 0x01; /* PM io base read only bit */
-pci_conf[0x80] = 0;
if (s-kvm_enabled) {
/* Mark SMM as already inited (until KVM supports SMM). */
Cc: qemu-sta...@nongnu.org
It's good to know this helps but I don't think we can apply
it as is without figuring out why,
otherwise it might break something else.
--
MST
Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset.
Michael,
True, I haven't figure it out yet, but the current status is that recover from
sleep doesn't work.
As far as I can tell it could be either:
1. piix4_reset shouldn't be call on resume.
2. memory_region_set_enabled (called in pm_io_space_update) shouldn't use
config[0x80].
3. the config[0x80] shouldn't be zero in piix4_reset (current solution).
4. something else?
I'm not well familiar with the PIIX4 emulation and your help will be
appreciated.
Thanks,
Gal.
- Original Message -
From: Michael S. Tsirkin m...@redhat.com
To: Paolo Bonzini pbonz...@redhat.com
Cc: Gal Hammer gham...@redhat.com, qemu-devel@nongnu.org,
qemu-sta...@nongnu.org
Sent: Wednesday, December 11, 2013 12:44:37 PM
Subject: Re: [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset.
On Wed, Dec 11, 2013 at 11:23:27AM +0100, Paolo Bonzini wrote:
Il 11/12/2013 10:21, Gal Hammer ha scritto:
Fix a bug that was introduced in commit c046e8c4. QEMU fails to
resume from suspend mode (S3).
Signed-off-by: Gal Hammer gham...@redhat.com
---
hw/acpi/piix4.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 93849c8..5c736a4 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -376,7 +376,6 @@ static void piix4_reset(void *opaque)
pci_conf[0x5b] = 0;
pci_conf[0x40] = 0x01; /* PM io base read only bit */
-pci_conf[0x80] = 0;
if (s-kvm_enabled) {
/* Mark SMM as already inited (until KVM supports SMM). */
Cc: qemu-sta...@nongnu.org
It's good to know this helps but I don't think we can apply
it as is without figuring out why,
otherwise it might break something else.
--
MST
Re: [Qemu-devel] [PULL 1/5] linux-headers: Update from v3.13-rc3
On Fri, 06 Dec 2013 13:48:25 -0700
Alex Williamson alex.william...@redhat.com wrote:
Update to tag v3.13-rc3 (374b105797c3d4f29c685f3be535c35f5689b30e)
Signed-off-by: Alex Williamson alex.william...@redhat.com
---
linux-headers/asm-arm/kvm.h |3 +
linux-headers/asm-powerpc/epapr_hcalls.h |4 +
linux-headers/asm-powerpc/kvm.h | 86
+- linux-headers/asm-x86/hyperv.h
| 19 +++ linux-headers/asm-x86/kvm.h |6 +-
linux-headers/linux/kvm.h| 11
6 files changed, 119 insertions(+), 10 deletions(-)
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
index c1ee007..c498b60 100644
--- a/linux-headers/asm-arm/kvm.h
+++ b/linux-headers/asm-arm/kvm.h
@@ -63,7 +63,8 @@ struct kvm_regs {
/* Supported Processor Types */
#define KVM_ARM_TARGET_CORTEX_A150
-#define KVM_ARM_NUM_TARGETS 1
+#define KVM_ARM_TARGET_CORTEX_A7 1
+#define KVM_ARM_NUM_TARGETS 2
/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
#define KVM_ARM_DEVICE_TYPE_SHIFT0
diff --git a/linux-headers/asm-powerpc/epapr_hcalls.h
b/linux-headers/asm-powerpc/epapr_hcalls.h index 33b3f89..06f7247 100644
--- a/linux-headers/asm-powerpc/epapr_hcalls.h
+++ b/linux-headers/asm-powerpc/epapr_hcalls.h
@@ -78,7 +78,7 @@
#define EV_SUCCESS 0
#define EV_EPERM 1 /* Operation not permitted */
#define EV_ENOENT2 /* Entry Not Found */
-#define EV_EIO 3 /* I/O error occurred */
+#define EV_EIO 3 /* I/O error occured */
#define EV_EAGAIN4 /* The operation had
insufficient
* resources to complete and
should be
* retried
@@ -89,7 +89,7 @@
#define EV_ENODEV7 /* No such device */
#define EV_EINVAL8 /* An argument supplied to the
hcall was out of range or invalid */
-#define EV_INTERNAL 9 /* An internal error
occurred */ +#define EV_INTERNAL 9 /* An internal
error occured */ #define EV_CONFIG10 /* A
configuration error was detected */ #define EV_INVALID_STATE
11/* The object is in an invalid state */ #define
EV_UNIMPLEMENTED 12 /* Unimplemented hypercall */ diff
--git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index 0fb1a6e..6836ec7 100644 --- a/linux-headers/asm-powerpc/kvm.h
+++ b/linux-headers/asm-powerpc/kvm.h
@@ -27,6 +27,7 @@
#define __KVM_HAVE_PPC_SMT
#define __KVM_HAVE_IRQCHIP
#define __KVM_HAVE_IRQ_LINE
+#define __KVM_HAVE_GUEST_DEBUG
This define breaks the build on ppc:
kvm-all.o: In function `kvm_update_guest_debug':
kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'
kvm-all.o: In function `kvm_insert_breakpoint':
kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint'
kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint'
kvm-all.o: In function `kvm_remove_breakpoint':
kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint'
kvm-all.o: In function `kvm_remove_all_breakpoints':
kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints'
The ppc support is missing...
Regards.
--
Greg
struct kvm_regs {
__u64 pc;
@@ -269,7 +270,24 @@ struct kvm_fpu {
__u64 fpr[32];
};
+/*
+ * Defines for h/w breakpoint, watchpoint (read, write or both) and
+ * software breakpoint.
+ * These are used as type in KVM_SET_GUEST_DEBUG ioctl and status
+ * for KVM_DEBUG_EXIT.
+ */
+#define KVMPPC_DEBUG_NONE0x0
+#define KVMPPC_DEBUG_BREAKPOINT (1UL 1)
+#define KVMPPC_DEBUG_WATCH_WRITE (1UL 2)
+#define KVMPPC_DEBUG_WATCH_READ (1UL 3)
struct kvm_debug_exit_arch {
+ __u64 address;
+ /*
+ * exiting to userspace because of h/w breakpoint, watchpoint
+ * (read, write or both) and software breakpoint.
+ */
+ __u32 status;
+ __u32 reserved;
};
/* for KVM_SET_GUEST_DEBUG */
@@ -281,10 +299,6 @@ struct kvm_guest_debug_arch {
* Type denotes h/w breakpoint, read watchpoint, write
* watchpoint or watchpoint (both read and write).
*/
-#define KVMPPC_DEBUG_NONE0x0
-#define KVMPPC_DEBUG_BREAKPOINT (1UL 1)
-#define KVMPPC_DEBUG_WATCH_WRITE (1UL 2)
-#define KVMPPC_DEBUG_WATCH_READ (1UL 3)
__u32 type;
__u32 reserved;
} bp[16];
@@ -429,6 +443,11 @@ struct kvm_get_htab_header {
#define KVM_REG_PPC_MMCR0(KVM_REG_PPC |
Re: [Qemu-devel] [PATCH 6/6] Add new vhost-user netdev backend
On Tue, Dec 10, 2013 at 11:29 PM, Eric Blake ebl...@redhat.com wrote:
On 12/09/2013 05:25 PM, Antonios Motakis wrote:
Add a new QEMU netdev backend that is intended to invoke vhost_net
with the vhost-user backend. Also decouple virtio-net from the tap
backend.
Signed-off-by: Antonios Motakis a.mota...@virtualopensystems.com
Signed-off-by: Nikolay Nikolaev n.nikol...@virtualopensystems.com
---
+++ b/include/net/vhost-user.h
@@ -0,0 +1,17 @@
+/*
+ * vhost-user.h
+ *
+ * Copyright (c) 2013 Virtual Open Systems Sarl.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
Can you please use GPLv2+ (that is, add the or later clause)? Yes, we
already have GPLv2-only files, but I'd like to avoid adding even more of
them.
+++ b/net/vhost-user.c
@@ -0,0 +1,95 @@
+/*
+ * vhost-user.c
+ *
+ * Copyright (c) 2013 Virtual Open Systems Sarl.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
Same question applies to all new files added throughout this series.
+++ b/qapi-schema.json
@@ -3009,11 +3009,24 @@
'hubid': 'int32' } }
##
+# @NetdevVhostUserOptions
+#
+# Vhost-user network backend
+#
+# @file: control socket path
What does it mean when 'file' is not present? Is there a default value?
Normally, we mark '#optional' in the docs for an optional argument.
+#
+# Since 2.0
+##
+{ 'type': 'NetdevVhostUserOptions',
+ 'data': {
+'*file': 'str' } }
Or is file always present, in which case this should be 'file' instead
of '*file'?
File should always be present, so we will change it to file without the
asterisk.
+
+##
# @NetClientOptions
#
# A discriminated record of network device traits.
#
-# Since 1.2
+# Since 2.0
Wrong. NetClientOptions has existed since 1.2; but some of the branches
of the union are newer. The way we have documented that elsewhere looks
more like:
# A discriminated record of network device traits.
# @vde: traits for VDE
# @dump: traits when using the device to dump all traffic
# @bridge: traits for a bridge device
# @hubport: traits for a hub port
# @vhost-user: traits for a vhost-user (since 2.0)
#
# Since 1.2
Thanks for your feedback, we will take it into account for the next version
of the series.
Antonios
##
{ 'union': 'NetClientOptions',
'data': {
@@ -3025,7 +3038,8 @@
'vde': 'NetdevVdeOptions',
'dump': 'NetdevDumpOptions',
'bridge': 'NetdevBridgeOptions',
-'hubport': 'NetdevHubPortOptions' } }
+'hubport': 'NetdevHubPortOptions',
+'vhost-user': 'NetdevVhostUserOptions' } }
##
# @NetLegacy
--
Eric Blake eblake redhat com+1-919-301-3266
Libvirt virtualization library http://libvirt.org
[Qemu-devel] [PATCH] Move hpet_find function from hpet.c to pc.c
From: Miroslav Rezanina mreza...@redhat.com
Function hpet_find could not be used for checking hpet availability becouse
it was not build when hpet was disabled.
To allow proper use of this function, moving it from hw/timer/hpet.c to
hw/i386/pc.c.
Signed-off-by: Miroslav Rezanina mreza...@redhat.com
---
hw/i386/pc.c| 5 +
hw/timer/hpet.c | 5 -
include/hw/i386/pc.h| 2 ++
include/hw/timer/hpet.h | 1 -
4 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 12c436e..7fd08dd 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1403,3 +1403,8 @@ void ioapic_init_gsi(GSIState *gsi_state, const char
*parent_name)
gsi_state-ioapic_irq[i] = qdev_get_gpio_in(dev, i);
}
}
+
+bool hpet_find(void)
+{
+return object_resolve_path_type(, hpet, NULL);
+}
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index 2eb75ea..fcd22ae 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -757,11 +757,6 @@ static void hpet_device_class_init(ObjectClass *klass,
void *data)
dc-props = hpet_device_properties;
}
-bool hpet_find(void)
-{
-return object_resolve_path_type(, TYPE_HPET, NULL);
-}
-
static const TypeInfo hpet_device_info = {
.name = TYPE_HPET,
.parent= TYPE_SYS_BUS_DEVICE,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 09652fb..f81b615 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -178,6 +178,8 @@ void piix4_smbus_register_device(SMBusDevice *dev, uint8_t
addr);
/* hpet.c */
extern int no_hpet;
+bool hpet_find(void);
+
/* piix_pci.c */
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;
diff --git a/include/hw/timer/hpet.h b/include/hw/timer/hpet.h
index ab44bd3..3fae8ad 100644
--- a/include/hw/timer/hpet.h
+++ b/include/hw/timer/hpet.h
@@ -72,5 +72,4 @@ struct hpet_fw_config
extern struct hpet_fw_config hpet_cfg;
-bool hpet_find(void);
#endif
--
1.8.3.1
[Qemu-devel] [PATCH] inet_listen_opts: add error checking
Don't use atoi() function which doesn't detect errors, switch to
strtol and error out on failures. Also add a range check while
being at it.
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
util/qemu-sockets.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/util/qemu-sockets.c b/util/qemu-sockets.c
index 6b97dc1..5636510 100644
--- a/util/qemu-sockets.c
+++ b/util/qemu-sockets.c
@@ -133,8 +133,20 @@ int inet_listen_opts(QemuOpts *opts, int port_offset,
Error **errp)
ai.ai_family = PF_INET6;
/* lookup */
-if (port_offset)
-snprintf(port, sizeof(port), %d, atoi(port) + port_offset);
+if (port_offset) {
+int baseport;
+errno = 0;
+baseport = strtol(port, NULL, 10);
+if (errno != 0) {
+error_setg(errp, can't convert to a number: %s, port);
+return -1;
+}
+if (baseport 0 || baseport + port_offset 65535) {
+error_setg(errp, port %s out of range, port);
+return -1;
+}
+snprintf(port, sizeof(port), %d, baseport + port_offset);
+}
rc = getaddrinfo(strlen(addr) ? addr : NULL, port, ai, res);
if (rc != 0) {
error_setg(errp, address resolution failed for %s:%s: %s, addr, port,
--
1.8.3.1
[Qemu-devel] [RFC PATCH 02/14] NUMA: check if the total numa memory size is equal to ram_size
From: Wanlong Gao gaowanl...@cn.fujitsu.com
If the total number of the assigned numa nodes memory is not
equal to the assigned ram size, it will write the wrong data
to ACPI talb, then the guest will ignore the wrong ACPI table
and recognize all memory to one node. It's buggy, we should
check it to ensure that we write the right data to ACPI table.
Signed-off-by: Wanlong Gao gaowanl...@cn.fujitsu.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
numa.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/numa.c b/numa.c
index ce7736a..beda80e 100644
--- a/numa.c
+++ b/numa.c
@@ -150,6 +150,16 @@ void set_numa_nodes(void)
node_mem[i] = ram_size - usedmem;
}
+uint64_t numa_total = 0;
+for (i = 0; i nb_numa_nodes; i++) {
+numa_total += node_mem[i];
+}
+if (numa_total != ram_size) {
+fprintf(stderr, qemu: numa nodes total memory size
+should equal to ram_size\n);
+exit(1);
+}
+
for (i = 0; i nb_numa_nodes; i++) {
if (!bitmap_empty(node_cpumask[i], MAX_CPUMASK_BITS)) {
break;
--
1.8.4.2
[Qemu-devel] [RFC PATCH 01/14] NUMA: move numa related code to new file numa.c
From: Wanlong Gao gaowanl...@cn.fujitsu.com
Signed-off-by: Wanlong Gao gaowanl...@cn.fujitsu.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
Makefile.target | 2 +-
cpus.c | 14
include/sysemu/cpus.h | 1 -
include/sysemu/sysemu.h | 3 +
numa.c | 182
vl.c| 139 +---
6 files changed, 187 insertions(+), 154 deletions(-)
create mode 100644 numa.c
diff --git a/Makefile.target b/Makefile.target
index af6ac7e..0197c17 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -109,7 +109,7 @@ endif #CONFIG_BSD_USER
#
# System emulator target
ifdef CONFIG_SOFTMMU
-obj-y += arch_init.o cpus.o monitor.o gdbstub.o balloon.o ioport.o
+obj-y += arch_init.o cpus.o monitor.o gdbstub.o balloon.o ioport.o numa.o
obj-y += qtest.o
obj-y += hw/
obj-$(CONFIG_FDT) += device_tree.o
diff --git a/cpus.c b/cpus.c
index 01d128d..53360b0 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1297,20 +1297,6 @@ static void tcg_exec_all(void)
exit_request = 0;
}
-void set_numa_modes(void)
-{
-CPUState *cpu;
-int i;
-
-CPU_FOREACH(cpu) {
-for (i = 0; i nb_numa_nodes; i++) {
-if (test_bit(cpu-cpu_index, node_cpumask[i])) {
-cpu-numa_node = i;
-}
-}
-}
-}
-
void list_cpus(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
{
/* XXX: implement xxx_cpu_list for targets that still miss it */
diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h
index 6502488..4f79081 100644
--- a/include/sysemu/cpus.h
+++ b/include/sysemu/cpus.h
@@ -23,7 +23,6 @@ extern int smp_threads;
#define smp_threads 1
#endif
-void set_numa_modes(void);
void list_cpus(FILE *f, fprintf_function cpu_fprintf, const char *optarg);
#endif
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 495dae8..2509649 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -136,6 +136,9 @@ extern QEMUClockType rtc_clock;
extern int nb_numa_nodes;
extern uint64_t node_mem[MAX_NODES];
extern unsigned long *node_cpumask[MAX_NODES];
+void numa_add(const char *optarg);
+void set_numa_nodes(void);
+void set_numa_modes(void);
#define MAX_OPTION_ROMS 16
typedef struct QEMUOptionRom {
diff --git a/numa.c b/numa.c
new file mode 100644
index 000..ce7736a
--- /dev/null
+++ b/numa.c
@@ -0,0 +1,182 @@
+/*
+ * QEMU System Emulator
+ *
+ * Copyright (c) 2013 Fujitsu Ltd.
+ * Author: Wanlong Gao gaowanl...@cn.fujitsu.com
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the Software), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include sysemu/sysemu.h
+
+static void numa_node_parse_cpus(int nodenr, const char *cpus)
+{
+char *endptr;
+unsigned long long value, endvalue;
+
+/* Empty CPU range strings will be considered valid, they will simply
+ * not set any bit in the CPU bitmap.
+ */
+if (!*cpus) {
+return;
+}
+
+if (parse_uint(cpus, value, endptr, 10) 0) {
+goto error;
+}
+if (*endptr == '-') {
+if (parse_uint_full(endptr + 1, endvalue, 10) 0) {
+goto error;
+}
+} else if (*endptr == '\0') {
+endvalue = value;
+} else {
+goto error;
+}
+
+if (endvalue = MAX_CPUMASK_BITS) {
+endvalue = MAX_CPUMASK_BITS - 1;
+fprintf(stderr,
+qemu: NUMA: A max of %d VCPUs are supported\n,
+ MAX_CPUMASK_BITS);
+}
+
+if (endvalue value) {
+goto error;
+}
+
+bitmap_set(node_cpumask[nodenr], value, endvalue-value+1);
+return;
+
+error:
+fprintf(stderr, qemu: Invalid NUMA CPU range: %s\n, cpus);
+exit(1);
+}
+
+void numa_add(const char *optarg)
+{
+char option[128];
+char *endptr;
+unsigned long long nodenr;
+
+optarg = get_opt_name(option, 128, optarg, ',');
+if (*optarg == ',') {
+
[Qemu-devel] [RFC PATCH 06/14] qapi: add SIZE type parser to string_input_visitor
From: Igor Mammedov imamm...@redhat.com
Signed-off-by: Igor Mammedov imamm...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
qapi/string-input-visitor.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/qapi/string-input-visitor.c b/qapi/string-input-visitor.c
index 8f1bc41..a152f5d 100644
--- a/qapi/string-input-visitor.c
+++ b/qapi/string-input-visitor.c
@@ -97,6 +97,23 @@ static void parse_type_number(Visitor *v, double *obj, const
char *name,
*obj = val;
}
+static void parse_type_size(Visitor *v, uint64_t *obj, const char *name,
+Error **errp)
+{
+StringInputVisitor *siv = DO_UPCAST(StringInputVisitor, visitor, v);
+int64_t val;
+char *endp;
+
+val = strtosz_suffix(siv-string ? siv-string : , endp,
+ STRTOSZ_DEFSUFFIX_B);
+if (val 0 || *endp != '\0') {
+error_set(errp, QERR_INVALID_PARAMETER_VALUE, name,
+ a size value representible as a non-negative int64);
+return;
+}
+*obj = val;
+}
+
static void parse_start_optional(Visitor *v, bool *present,
const char *name, Error **errp)
{
@@ -131,6 +148,7 @@ StringInputVisitor *string_input_visitor_new(const char
*str)
v-visitor.type_bool = parse_type_bool;
v-visitor.type_str = parse_type_str;
v-visitor.type_number = parse_type_number;
+v-visitor.type_size = parse_type_size;
v-visitor.start_optional = parse_start_optional;
v-string = str;
--
1.8.4.2
[Qemu-devel] [RFC PATCH 00/14] Common base for memory hotplug and NUMA policy work
Hi, this is a proposal for a common tree for memory hotplug and NUMA policy patches. The common base for these tree is Igor's memory device QOM hierarchy, that subsumes and improves on the -numa mem concept that I had proposed. These patches include a basic conversion of his QOM hierarchy to -object. Stefan and Igor are looking at improving -object, but this is not required to build on this series. Thanks to the memory device object, NUMA nodes' memory allocation be expressed easily via a new suboption -numa node,memdev=ID. For example: -object memory-ram,size=1024M,id=ram-node0 \ -numa node,nodeid=0,cpus=0,memdev=ram-node0 \ -object memory-ram,size=1024M,id=ram-node1 \ -numa node,nodeid=1,cpus=1,memdev=ram-node1 \ -m 2048 memdev=ID is alternative to mem=SIZE: if you use memdev for one node, you must use it for all of them. When memdev is in use, the single large RAM memory region is replaced by a container region, with all memdevs layed out one after another. The integration between boards and the NUMA subsystem is done by a new function in numa.c, memory_region_allocate_system_memory. Thus, boards have to request NUMA-aware allocation explicitly. This however is not a change compared to Wanlong's patches: both the early ones that hardcoded the pc.ram memory region name, and the latest version that similarly introduced a function for boards to call (memory_region_set_mem_policy in his patches). Wanlong can then proceed to add policy properties (hostnode, policy) to backends/hostmem-ram.c, and these will be automatically applicable to hotpluggable memory as well. I'm quite happy with the design of both series. It took quite a long time, but it shows the power of the host/guest separation that is already present in -blockdev/-chardev/-netdev. You can find this at refs/heads/numa in my github repository, where I included also the monitor object-add/object-del patches. Paolo Igor Mammedov (3): qapi: add SIZE type parser to string_input_visitor vl: convert -m to QemuOpts add memdev backend infrastructure Paolo Bonzini (6): QemuOpts: introduce qemu_find_opts_singleton qom: fix leak for objects created with -object qom: catch errors in object_property_add_child pc: pass QEMUMachineInitArgs to pc_memory_init numa: introduce memory_region_allocate_system_memory numa: add -numa node,memdev= option Wanlong Gao (5): NUMA: move numa related code to new file numa.c NUMA: check if the total numa memory size is equal to ram_size NUMA: Add numa_info structure to contain numa nodes info NUMA: convert -numa option to use OptsVisitor NUMA: expand MAX_NODES from 64 to 128 Makefile.target | 2 +- backends/Makefile.objs | 2 + backends/hostmem-ram.c | 46 backends/hostmem.c | 116 cpus.c | 14 --- hw/i386/pc.c| 27 ++--- hw/i386/pc_piix.c | 8 +- hw/i386/pc_q35.c| 4 +- include/hw/i386/pc.h| 7 +- include/qemu/config-file.h | 2 + include/sysemu/cpus.h | 1 - include/sysemu/hostmem.h| 63 +++ include/sysemu/sysemu.h | 21 +++- monitor.c | 2 +- numa.c | 259 qapi-schema.json| 34 ++ qapi/string-input-visitor.c | 18 +++ qemu-options.hx | 7 +- qom/object.c| 9 +- util/qemu-config.c | 14 +++ vl.c| 221 ++--- 21 files changed, 664 insertions(+), 213 deletions(-) create mode 100644 backends/hostmem-ram.c create mode 100644 backends/hostmem.c create mode 100644 include/sysemu/hostmem.h create mode 100644 numa.c -- 1.8.4.2
[Qemu-devel] [RFC PATCH 03/14] NUMA: Add numa_info structure to contain numa nodes info
From: Wanlong Gao gaowanl...@cn.fujitsu.com
Add the numa_info structure to contain the numa nodes memory,
VCPUs information and the future added numa nodes host memory
policies.
Reviewed-by: Eduardo Habkost ehabk...@redhat.com
Signed-off-by: Andre Przywara andre.przyw...@amd.com
Signed-off-by: Wanlong Gao gaowanl...@cn.fujitsu.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/i386/pc.c| 12
include/sysemu/sysemu.h | 8 ++--
monitor.c | 2 +-
numa.c | 23 ---
vl.c| 7 +++
5 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 12c436e..74c1f16 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -670,14 +670,14 @@ static FWCfgState *bochs_bios_init(void)
unsigned int apic_id = x86_cpu_apic_id_from_index(i);
assert(apic_id apic_id_limit);
for (j = 0; j nb_numa_nodes; j++) {
-if (test_bit(i, node_cpumask[j])) {
+if (test_bit(i, numa_info[j].node_cpu)) {
numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
break;
}
}
}
for (i = 0; i nb_numa_nodes; i++) {
-numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
+numa_fw_cfg[apic_id_limit + 1 + i] =
cpu_to_le64(numa_info[i].node_mem);
}
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
(1 + apic_id_limit + nb_numa_nodes) *
@@ -1072,8 +1072,12 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t
below_4g_mem_size,
guest_info-apic_id_limit = pc_apic_id_limit(max_cpus);
guest_info-apic_xrupt_override = kvm_allows_irq0_override();
guest_info-numa_nodes = nb_numa_nodes;
-guest_info-node_mem = g_memdup(node_mem, guest_info-numa_nodes *
+guest_info-node_mem = g_malloc0(guest_info-numa_nodes *
sizeof *guest_info-node_mem);
+for (i = 0; i nb_numa_nodes; i++) {
+guest_info-node_mem[i] = numa_info[i].node_mem;
+}
+
guest_info-node_cpu = g_malloc0(guest_info-apic_id_limit *
sizeof *guest_info-node_cpu);
@@ -1081,7 +1085,7 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t
below_4g_mem_size,
unsigned int apic_id = x86_cpu_apic_id_from_index(i);
assert(apic_id guest_info-apic_id_limit);
for (j = 0; j nb_numa_nodes; j++) {
-if (test_bit(i, node_cpumask[j])) {
+if (test_bit(i, numa_info[j].node_cpu)) {
guest_info-node_cpu[apic_id] = j;
break;
}
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 2509649..d873b42 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -9,6 +9,7 @@
#include qapi-types.h
#include qemu/notify.h
#include qemu/main-loop.h
+#include qemu/bitmap.h
/* vl.c */
@@ -134,8 +135,11 @@ extern QEMUClockType rtc_clock;
#define MAX_NODES 64
#define MAX_CPUMASK_BITS 255
extern int nb_numa_nodes;
-extern uint64_t node_mem[MAX_NODES];
-extern unsigned long *node_cpumask[MAX_NODES];
+typedef struct node_info {
+uint64_t node_mem;
+DECLARE_BITMAP(node_cpu, MAX_CPUMASK_BITS);
+} NodeInfo;
+extern NodeInfo numa_info[MAX_NODES];
void numa_add(const char *optarg);
void set_numa_nodes(void);
void set_numa_modes(void);
diff --git a/monitor.c b/monitor.c
index 845f608..b97b7d3 100644
--- a/monitor.c
+++ b/monitor.c
@@ -2004,7 +2004,7 @@ static void do_info_numa(Monitor *mon, const QDict *qdict)
}
monitor_printf(mon, \n);
monitor_printf(mon, node %d size: % PRId64 MB\n, i,
-node_mem[i] 20);
+numa_info[i].node_mem 20);
}
}
diff --git a/numa.c b/numa.c
index beda80e..1bc0fad 100644
--- a/numa.c
+++ b/numa.c
@@ -61,7 +61,7 @@ static void numa_node_parse_cpus(int nodenr, const char *cpus)
goto error;
}
-bitmap_set(node_cpumask[nodenr], value, endvalue-value+1);
+bitmap_set(numa_info[nodenr].node_cpu, value, endvalue-value+1);
return;
error:
@@ -101,7 +101,7 @@ void numa_add(const char *optarg)
}
if (get_param_value(option, 128, mem, optarg) == 0) {
-node_mem[nodenr] = 0;
+numa_info[nodenr].node_mem = 0;
} else {
int64_t sval;
sval = strtosz(option, endptr);
@@ -109,7 +109,7 @@ void numa_add(const char *optarg)
fprintf(stderr, qemu: invalid numa mem size: %s\n, optarg);
exit(1);
}
-node_mem[nodenr] = sval;
+numa_info[nodenr].node_mem = sval;
}
if (get_param_value(option, 128, cpus, optarg) != 0) {
numa_node_parse_cpus(nodenr, option);
@@ -134,7 +134,7 @@ void set_numa_nodes(void)
* and distribute the available memory equally across all nodes
*/
for (i = 0; i nb_numa_nodes; i++) {
-if
[Qemu-devel] [RFC PATCH 11/14] pc: pass QEMUMachineInitArgs to pc_memory_init
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/i386/pc.c | 11 +--
hw/i386/pc_piix.c| 8 +++-
hw/i386/pc_q35.c | 4 +---
include/hw/i386/pc.h | 7 +++
4 files changed, 12 insertions(+), 18 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 74c1f16..76c47a9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1148,10 +1148,8 @@ void pc_acpi_init(const char *default_dsdt)
}
}
-FWCfgState *pc_memory_init(MemoryRegion *system_memory,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
+FWCfgState *pc_memory_init(QEMUMachineInitArgs *args,
+ MemoryRegion *system_memory,
ram_addr_t below_4g_mem_size,
ram_addr_t above_4g_mem_size,
MemoryRegion *rom_memory,
@@ -1163,7 +1161,7 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
MemoryRegion *ram_below_4g, *ram_above_4g;
FWCfgState *fw_cfg;
-linux_boot = (kernel_filename != NULL);
+linux_boot = (args-kernel_filename != NULL);
/* Allocate RAM. We allocate it as a single memory region and use
* aliases to address portions of it, mostly for backwards compatibility
@@ -1204,7 +1202,8 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
rom_set_fw(fw_cfg);
if (linux_boot) {
-load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline,
below_4g_mem_size);
+load_linux(fw_cfg, args-kernel_filename, args-initrd_filename,
+ args-kernel_cmdline, below_4g_mem_size);
}
for (i = 0; i nb_option_roms; i++) {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index ab56285..cd3eda1 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -130,11 +130,9 @@ static void pc_init1(QEMUMachineInitArgs *args,
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
-fw_cfg = pc_memory_init(system_memory,
- args-kernel_filename, args-kernel_cmdline,
- args-initrd_filename,
- below_4g_mem_size, above_4g_mem_size,
- rom_memory, ram_memory, guest_info);
+fw_cfg = pc_memory_init(args, system_memory,
+below_4g_mem_size, above_4g_mem_size,
+rom_memory, ram_memory, guest_info);
}
gsi_state = g_malloc0(sizeof(*gsi_state));
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 97aa842..c2dcbae 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -115,9 +115,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
-pc_memory_init(get_system_memory(),
- args-kernel_filename, args-kernel_cmdline,
- args-initrd_filename,
+pc_memory_init(args, get_system_memory(),
below_4g_mem_size, above_4g_mem_size,
rom_memory, ram_memory, guest_info);
}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 09652fb..7dda9a6 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -3,6 +3,7 @@
#include qemu-common.h
#include exec/memory.h
+#include hw/boards.h
#include hw/isa/isa.h
#include hw/block/fdc.h
#include net/net.h
@@ -140,10 +141,8 @@ static inline uint64_t pci_host_get_hole64_size(uint64_t
pci_hole64_size)
void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
uint64_t pci_hole64_size);
-FWCfgState *pc_memory_init(MemoryRegion *system_memory,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
+FWCfgState *pc_memory_init(QEMUMachineInitArgs *args,
+ MemoryRegion *system_memory,
ram_addr_t below_4g_mem_size,
ram_addr_t above_4g_mem_size,
MemoryRegion *rom_memory,
--
1.8.4.2
[Qemu-devel] [RFC PATCH 05/14] NUMA: expand MAX_NODES from 64 to 128
From: Wanlong Gao gaowanl...@cn.fujitsu.com
libnuma choosed 128 for MAX_NODES, so we follow libnuma here.
Signed-off-by: Wanlong Gao gaowanl...@cn.fujitsu.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
include/sysemu/sysemu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 20b05a3..4c94cf5 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -132,7 +132,7 @@ extern size_t boot_splash_filedata_size;
extern uint8_t qemu_extra_params_fw[2];
extern QEMUClockType rtc_clock;
-#define MAX_NODES 64
+#define MAX_NODES 128
#define MAX_CPUMASK_BITS 255
extern int nb_numa_nodes;
typedef struct node_info {
--
1.8.4.2
[Qemu-devel] [RFC PATCH 07/14] QemuOpts: introduce qemu_find_opts_singleton
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
include/qemu/config-file.h | 2 ++
util/qemu-config.c | 14 ++
vl.c | 11 +--
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/include/qemu/config-file.h b/include/qemu/config-file.h
index 508428f..699c3a1 100644
--- a/include/qemu/config-file.h
+++ b/include/qemu/config-file.h
@@ -7,6 +7,8 @@
QemuOptsList *qemu_find_opts(const char *group);
QemuOptsList *qemu_find_opts_err(const char *group, Error **errp);
+QemuOpts *qemu_find_opts_singleton(const char *group);
+
void qemu_add_opts(QemuOptsList *list);
void qemu_add_drive_opts(QemuOptsList *list);
int qemu_set_option(const char *str);
diff --git a/util/qemu-config.c b/util/qemu-config.c
index 04da942..c6ac589 100644
--- a/util/qemu-config.c
+++ b/util/qemu-config.c
@@ -39,6 +39,20 @@ QemuOptsList *qemu_find_opts(const char *group)
return ret;
}
+QemuOpts *qemu_find_opts_singleton(const char *group)
+{
+QemuOptsList *list;
+QemuOpts *opts;
+
+list = qemu_find_opts(group);
+assert(list);
+opts = qemu_opts_find(list, NULL);
+if (!opts) {
+opts = qemu_opts_create_nofail(list);
+}
+return opts;
+}
+
static CommandLineParameterInfoList *query_option_descs(const QemuOptDesc
*desc)
{
CommandLineParameterInfoList *param_list = NULL, *entry;
diff --git a/vl.c b/vl.c
index 95181e0..ecda5ad 100644
--- a/vl.c
+++ b/vl.c
@@ -537,16 +537,7 @@ static QemuOptsList qemu_msg_opts = {
*/
QemuOpts *qemu_get_machine_opts(void)
{
-QemuOptsList *list;
-QemuOpts *opts;
-
-list = qemu_find_opts(machine);
-assert(list);
-opts = qemu_opts_find(list, NULL);
-if (!opts) {
-opts = qemu_opts_create_nofail(list);
-}
-return opts;
+return qemu_find_opts_singleton(machine);
}
const char *qemu_get_vm_name(void)
--
1.8.4.2
[Qemu-devel] [RFC PATCH 08/14] vl: convert -m to QemuOpts
From: Igor Mammedov imamm...@redhat.com
Adds option to -m
mem - startup memory amount
For compatibility with legacy CLI if suffix-less number is passed,
it assumes amount in Mb.
Otherwise user is free to use suffixed number using suffixes b,k/K,M,G
Signed-off-by: Igor Mammedov imamm...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
qemu-options.hx | 7 +--
vl.c| 52 +---
2 files changed, 46 insertions(+), 13 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index af34483..416f8e4 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -210,8 +210,11 @@ use is discouraged as it may be removed from future
versions.
ETEXI
DEF(m, HAS_ARG, QEMU_OPTION_m,
--m megs set virtual RAM size to megs MB [default=
-stringify(DEFAULT_RAM_SIZE) ]\n, QEMU_ARCH_ALL)
+-m [mem=]megs\n
+configure guest RAM\n
+mem: initial amount of guest memory (default:
+stringify(DEFAULT_RAM_SIZE) Mb)\n,
+QEMU_ARCH_ALL)
STEXI
@item -m @var{megs}
@findex -m
diff --git a/vl.c b/vl.c
index ecda5ad..68ba565 100644
--- a/vl.c
+++ b/vl.c
@@ -530,6 +530,20 @@ static QemuOptsList qemu_msg_opts = {
},
};
+static QemuOptsList qemu_mem_opts = {
+.name = memory-opts,
+.implied_opt_name = mem,
+.head = QTAILQ_HEAD_INITIALIZER(qemu_mem_opts.head),
+.merge_lists = true,
+.desc = {
+{
+.name = mem,
+.type = QEMU_OPT_SIZE,
+},
+{ /* end of list */ }
+},
+};
+
/**
* Get machine options
*
@@ -2746,6 +2760,7 @@ int main(int argc, char **argv, char **envp)
};
const char *trace_events = NULL;
const char *trace_file = NULL;
+const ram_addr_t default_ram_size = DEFAULT_RAM_SIZE * 1024 * 1024;
atexit(qemu_run_exit_notifiers);
error_set_progname(argv[0]);
@@ -2785,6 +2800,7 @@ int main(int argc, char **argv, char **envp)
qemu_add_opts(qemu_realtime_opts);
qemu_add_opts(qemu_msg_opts);
qemu_add_opts(qemu_numa_opts);
+qemu_add_opts(qemu_mem_opts);
runstate_init();
@@ -2800,7 +2816,7 @@ int main(int argc, char **argv, char **envp)
module_call_init(MODULE_INIT_MACHINE);
machine = find_default_machine();
cpu_model = NULL;
-ram_size = 0;
+ram_size = default_ram_size;
snapshot = 0;
cyls = heads = secs = 0;
translation = BIOS_ATA_TRANSLATION_AUTO;
@@ -3080,16 +3096,32 @@ int main(int argc, char **argv, char **envp)
exit(0);
break;
case QEMU_OPTION_m: {
-int64_t value;
uint64_t sz;
-char *end;
+const char *mem_str;
-value = strtosz(optarg, end);
-if (value 0 || *end) {
-fprintf(stderr, qemu: invalid ram size: %s\n, optarg);
+opts = qemu_opts_parse(qemu_find_opts(memory-opts),
+ optarg, 1);
+
+mem_str = qemu_opt_get(opts, mem);
+if (!mem_str) {
+fprintf(stderr, qemu: invalid -m option, missing
+ 'mem' option\n);
exit(1);
}
-sz = QEMU_ALIGN_UP((uint64_t)value, 8192);
+
+sz = qemu_opt_get_size(opts, mem, ram_size);
+
+/* Fix up legacy suffix-less format */
+if (g_ascii_isdigit(mem_str[strlen(mem_str) - 1])) {
+sz = 20;
+}
+
+/* backward compatibility behaviour for case -m 0 */
+if (sz == 0) {
+sz = default_ram_size;
+}
+
+sz = QEMU_ALIGN_UP(sz, 8192);
ram_size = sz;
if (ram_size != sz) {
fprintf(stderr, qemu: ram size too large\n);
@@ -3929,10 +3961,8 @@ int main(int argc, char **argv, char **envp)
exit(1);
}
-/* init the memory */
-if (ram_size == 0) {
-ram_size = DEFAULT_RAM_SIZE * 1024 * 1024;
-}
+/* store value for the future use */
+qemu_opt_set_number(qemu_find_opts_singleton(memory-opts), mem,
ram_size);
if (qemu_opts_foreach(qemu_find_opts(device), device_help_func, NULL, 0)
!= 0) {
--
1.8.4.2
[Qemu-devel] [RFC PATCH 04/14] NUMA: convert -numa option to use OptsVisitor
From: Wanlong Gao gaowanl...@cn.fujitsu.com
Signed-off-by: Wanlong Gao gaowanl...@cn.fujitsu.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
include/sysemu/sysemu.h | 3 +-
numa.c | 148 +++-
qapi-schema.json| 30 ++
vl.c| 11 +++-
4 files changed, 114 insertions(+), 78 deletions(-)
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index d873b42..20b05a3 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -140,9 +140,10 @@ typedef struct node_info {
DECLARE_BITMAP(node_cpu, MAX_CPUMASK_BITS);
} NodeInfo;
extern NodeInfo numa_info[MAX_NODES];
-void numa_add(const char *optarg);
void set_numa_nodes(void);
void set_numa_modes(void);
+extern QemuOptsList qemu_numa_opts;
+int numa_init_func(QemuOpts *opts, void *opaque);
#define MAX_OPTION_ROMS 16
typedef struct QEMUOptionRom {
diff --git a/numa.c b/numa.c
index 1bc0fad..c4fa665 100644
--- a/numa.c
+++ b/numa.c
@@ -24,101 +24,97 @@
*/
#include sysemu/sysemu.h
-
-static void numa_node_parse_cpus(int nodenr, const char *cpus)
+#include qapi-visit.h
+#include qapi/opts-visitor.h
+#include qapi/dealloc-visitor.h
+QemuOptsList qemu_numa_opts = {
+.name = numa,
+.implied_opt_name = type,
+.head = QTAILQ_HEAD_INITIALIZER(qemu_numa_opts.head),
+.desc = { { 0 } } /* validated with OptsVisitor */
+};
+
+static int numa_node_parse(NumaNodeOptions *opts)
{
-char *endptr;
-unsigned long long value, endvalue;
-
-/* Empty CPU range strings will be considered valid, they will simply
- * not set any bit in the CPU bitmap.
- */
-if (!*cpus) {
-return;
-}
+uint16_t nodenr;
+uint16List *cpus = NULL;
-if (parse_uint(cpus, value, endptr, 10) 0) {
-goto error;
-}
-if (*endptr == '-') {
-if (parse_uint_full(endptr + 1, endvalue, 10) 0) {
-goto error;
-}
-} else if (*endptr == '\0') {
-endvalue = value;
+if (opts-has_nodeid) {
+nodenr = opts-nodeid;
} else {
-goto error;
+nodenr = nb_numa_nodes;
}
-if (endvalue = MAX_CPUMASK_BITS) {
-endvalue = MAX_CPUMASK_BITS - 1;
-fprintf(stderr,
-qemu: NUMA: A max of %d VCPUs are supported\n,
- MAX_CPUMASK_BITS);
+if (nodenr = MAX_NODES) {
+fprintf(stderr, qemu: Max number of NUMA nodes reached: %
+PRIu16 \n, nodenr);
+return -1;
}
-if (endvalue value) {
-goto error;
+for (cpus = opts-cpus; cpus; cpus = cpus-next) {
+if (cpus-value MAX_CPUMASK_BITS) {
+fprintf(stderr, qemu: cpu number % PRIu16 is bigger than %d,
+cpus-value, MAX_CPUMASK_BITS);
+continue;
+}
+bitmap_set(numa_info[nodenr].node_cpu, cpus-value, 1);
}
-bitmap_set(numa_info[nodenr].node_cpu, value, endvalue-value+1);
-return;
+if (opts-has_mem) {
+int64_t mem_size;
+char *endptr;
+mem_size = strtosz(opts-mem, endptr);
+if (mem_size 0 || *endptr) {
+fprintf(stderr, qemu: invalid numa mem size: %s\n, opts-mem);
+return -1;
+}
+numa_info[nodenr].node_mem = mem_size;
+}
-error:
-fprintf(stderr, qemu: Invalid NUMA CPU range: %s\n, cpus);
-exit(1);
+return 0;
}
-void numa_add(const char *optarg)
+int numa_init_func(QemuOpts *opts, void *opaque)
{
-char option[128];
-char *endptr;
-unsigned long long nodenr;
-
-optarg = get_opt_name(option, 128, optarg, ',');
-if (*optarg == ',') {
-optarg++;
+NumaOptions *object = NULL;
+Error *err = NULL;
+int ret = 0;
+
+{
+OptsVisitor *ov = opts_visitor_new(opts);
+visit_type_NumaOptions(opts_get_visitor(ov), object, NULL, err);
+opts_visitor_cleanup(ov);
}
-if (!strcmp(option, node)) {
-
-if (nb_numa_nodes = MAX_NODES) {
-fprintf(stderr, qemu: too many NUMA nodes\n);
-exit(1);
-}
-if (get_param_value(option, 128, nodeid, optarg) == 0) {
-nodenr = nb_numa_nodes;
-} else {
-if (parse_uint_full(option, nodenr, 10) 0) {
-fprintf(stderr, qemu: Invalid NUMA nodeid: %s\n, option);
-exit(1);
-}
-}
-
-if (nodenr = MAX_NODES) {
-fprintf(stderr, qemu: invalid NUMA nodeid: %llu\n, nodenr);
-exit(1);
-}
+if (error_is_set(err)) {
+fprintf(stderr, qemu: %s\n, error_get_pretty(err));
+error_free(err);
+ret = -1;
+goto error;
+}
-if (get_param_value(option, 128, mem, optarg) == 0) {
-numa_info[nodenr].node_mem = 0;
-} else {
-int64_t sval;
-sval = strtosz(option, endptr);
-if (sval 0 || *endptr) {
-
[Qemu-devel] [RFC PATCH 12/14] numa: introduce memory_region_allocate_system_memory
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/i386/pc.c| 4 +---
include/sysemu/sysemu.h | 5 +
numa.c | 10 ++
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 76c47a9..61df5d4 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1168,9 +1168,7 @@ FWCfgState *pc_memory_init(QEMUMachineInitArgs *args,
* with older qemus that used qemu_ram_alloc().
*/
ram = g_malloc(sizeof(*ram));
-memory_region_init_ram(ram, NULL, pc.ram,
- below_4g_mem_size + above_4g_mem_size);
-vmstate_register_ram_global(ram);
+memory_region_allocate_system_memory(ram, NULL, pc.ram, args);
*ram_memory = ram;
ram_below_4g = g_malloc(sizeof(*ram_below_4g));
memory_region_init_alias(ram_below_4g, NULL, ram-below-4g, ram,
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 4c94cf5..e9da760 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -10,6 +10,8 @@
#include qemu/notify.h
#include qemu/main-loop.h
#include qemu/bitmap.h
+#include qom/object.h
+#include hw/boards.h
/* vl.c */
@@ -144,6 +146,9 @@ void set_numa_nodes(void);
void set_numa_modes(void);
extern QemuOptsList qemu_numa_opts;
int numa_init_func(QemuOpts *opts, void *opaque);
+void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
+ const char *name,
+ QEMUMachineInitArgs *args);
#define MAX_OPTION_ROMS 16
typedef struct QEMUOptionRom {
diff --git a/numa.c b/numa.c
index c4fa665..f903b9e 100644
--- a/numa.c
+++ b/numa.c
@@ -187,3 +187,13 @@ void set_numa_modes(void)
}
}
}
+
+void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
+ const char *name,
+ QEMUMachineInitArgs *args)
+{
+uint64_t ram_size = args-ram_size;
+
+memory_region_init_ram(mr, owner, name, ram_size);
+vmstate_register_ram_global(mr);
+}
--
1.8.4.2
[Qemu-devel] [RFC PATCH 13/14] add memdev backend infrastructure
From: Igor Mammedov imamm...@redhat.com
Provides framework for splitting host RAM allocation/
policies into a separate backend that could be used
by devices.
Initially only legacy RAM backend is provided, which
uses memory_region_init_ram() allocator and compatible
with every CLI option that affects memory_region_init_ram().
Signed-off-by: Igor Mammedov imamm...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
backends/Makefile.objs | 2 +
backends/hostmem-ram.c | 46 +++
backends/hostmem.c | 116 +++
include/sysemu/hostmem.h | 63 +
4 files changed, 227 insertions(+)
create mode 100644 backends/hostmem-ram.c
create mode 100644 backends/hostmem.c
create mode 100644 include/sysemu/hostmem.h
diff --git a/backends/Makefile.objs b/backends/Makefile.objs
index 42557d5..e6bdc11 100644
--- a/backends/Makefile.objs
+++ b/backends/Makefile.objs
@@ -6,3 +6,5 @@ common-obj-$(CONFIG_BRLAPI) += baum.o
$(obj)/baum.o: QEMU_CFLAGS += $(SDL_CFLAGS)
common-obj-$(CONFIG_TPM) += tpm.o
+
+common-obj-y += hostmem.o hostmem-ram.o
diff --git a/backends/hostmem-ram.c b/backends/hostmem-ram.c
new file mode 100644
index 000..3860cee
--- /dev/null
+++ b/backends/hostmem-ram.c
@@ -0,0 +1,46 @@
+/*
+ * QEMU Host Memory Backend
+ *
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Authors:
+ * Igor Mammedov imamm...@redhat.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include sysemu/hostmem.h
+
+#define TYPE_MEMORY_BACKEND_RAM memory-ram
+
+
+static void
+ram_backend_memory_init(HostMemoryBackend *backend, Error **errp)
+{
+if (!memory_region_size(backend-mr)) {
+memory_region_init_ram(backend-mr, OBJECT(backend),
+ object_get_canonical_path(OBJECT(backend)),
+ backend-size);
+}
+}
+
+static void
+ram_backend_class_init(ObjectClass *oc, void *data)
+{
+HostMemoryBackendClass *bc = MEMORY_BACKEND_CLASS(oc);
+
+bc-memory_init = ram_backend_memory_init;
+}
+
+static const TypeInfo ram_backend_info = {
+.name = TYPE_MEMORY_BACKEND_RAM,
+.parent = TYPE_MEMORY_BACKEND,
+.class_init = ram_backend_class_init,
+};
+
+static void register_types(void)
+{
+type_register_static(ram_backend_info);
+}
+
+type_init(register_types);
diff --git a/backends/hostmem.c b/backends/hostmem.c
new file mode 100644
index 000..91066e1
--- /dev/null
+++ b/backends/hostmem.c
@@ -0,0 +1,116 @@
+/*
+ * QEMU Host Memory Backend
+ *
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Authors:
+ * Igor Mammedov imamm...@redhat.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include sysemu/hostmem.h
+#include sysemu/sysemu.h
+#include qapi/visitor.h
+#include qapi/qmp/qerror.h
+#include qemu/config-file.h
+
+static void
+hostmemory_backend_get_size(Object *obj, Visitor *v, void *opaque,
+const char *name, Error **errp)
+{
+HostMemoryBackend *backend = MEMORY_BACKEND(obj);
+uint64_t value = backend-size;
+
+visit_type_size(v, value, name, errp);
+}
+
+static void
+hostmemory_backend_set_size(Object *obj, Visitor *v, void *opaque,
+const char *name, Error **errp)
+{
+HostMemoryBackend *backend = MEMORY_BACKEND(obj);
+uint64_t value;
+
+if (memory_region_size(backend-mr)) {
+error_setg(errp, cannot change property value\n);
+return;
+}
+
+visit_type_size(v, value, name, errp);
+if (error_is_set(errp)) {
+return;
+}
+if (!value) {
+error_setg(errp, Property '%s.%s' doesn't take value '% PRIu64 ',
+ object_get_typename(obj), name , value);
+return;
+}
+backend-size = value;
+}
+
+static void hostmemory_backend_initfn(Object *obj)
+{
+object_property_add(obj, size, int,
+hostmemory_backend_get_size,
+hostmemory_backend_set_size, NULL, NULL, NULL);
+}
+
+static void hostmemory_backend_finalize(Object *obj)
+{
+HostMemoryBackend *backend = MEMORY_BACKEND(obj);
+
+if (memory_region_size(backend-mr)) {
+memory_region_destroy(backend-mr);
+}
+}
+
+static void
+hostmemory_backend_memory_init(HostMemoryBackend *backend, Error **errp)
+{
+error_setg(errp, memory_init is not implemented for type [%s],
+ object_get_typename(OBJECT(backend)));
+}
+
+MemoryRegion *
+host_memory_backend_get_memory(HostMemoryBackend *backend, Error **errp)
+{
+HostMemoryBackendClass *bc = MEMORY_BACKEND_GET_CLASS(backend);
+Object *obj = OBJECT(backend);
+
+if (!backend-size) {
+error_setg(errp, Invalid property [%s.size] value: % PRIu64,
+ object_get_typename(obj), backend-size);
+return NULL;
+
[Qemu-devel] [RFC PATCH 09/14] qom: fix leak for objects created with -object
The object must be unref-ed when its variable goes out of scope.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
vl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/vl.c b/vl.c
index 68ba565..086a062 100644
--- a/vl.c
+++ b/vl.c
@@ -2717,12 +2717,13 @@ static int object_create(QemuOpts *opts, void *opaque)
obj = object_new(type);
if (qemu_opt_foreach(opts, object_set_property, obj, 1) 0) {
+object_unref(obj);
return -1;
}
object_property_add_child(container_get(object_get_root(), /objects),
id, obj, NULL);
-
+object_unref(obj);
return 0;
}
--
1.8.4.2
[Qemu-devel] [RFC PATCH 10/14] qom: catch errors in object_property_add_child
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
qom/object.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/qom/object.c b/qom/object.c
index fc19cf6..68fe07a 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -988,17 +988,22 @@ static void object_finalize_child_property(Object *obj,
const char *name,
void object_property_add_child(Object *obj, const char *name,
Object *child, Error **errp)
{
+Error *local_err = NULL;
gchar *type;
type = g_strdup_printf(child%s, object_get_typename(OBJECT(child)));
object_property_add(obj, name, type, object_get_child_property,
-NULL, object_finalize_child_property, child, errp);
-
+NULL, object_finalize_child_property, child,
local_err);
+if (error_is_set(local_err)) {
+error_propagate(errp, local_err);
+goto out;
+}
object_ref(child);
g_assert(child-parent == NULL);
child-parent = obj;
+out:
g_free(type);
}
--
1.8.4.2
Re: [Qemu-devel] [PATCH V17 02/11] NUMA: check if the total numa memory size is equal to ram_size
On Tue, Dec 10, 2013 at 05:01:02PM -0200, Eduardo Habkost wrote: On Tue, Dec 10, 2013 at 07:03:50PM +0100, Paolo Bonzini wrote: Il 10/12/2013 14:15, Eduardo Habkost ha scritto: If the total number of the assigned numa nodes memory is not equal to the assigned ram size, it will write the wrong data to ACPI talb, then the guest will ignore the wrong ACPI table and recognize all memory to one node. It's buggy, we should check it to ensure that we write the right data to ACPI table. Signed-off-by: Wanlong Gao gaowanl...@cn.fujitsu.com This will make configurations that could be running for years (except that the guest OS was ignoring the NUMA data) suddenly stop running. I just want to confirm: we really want that, right? Does libvirt allow this kind of broken configuration to be generated, or it already ensures the total NUMA node sizes match RAM size? It allows this. It just converts the numa XML to -numa node. In that case, if we apply this patch we may want to make libvirt validate the NUMA configuration instead of getting a cryptic QEMU aborted error message with the actual problem buried in a log file. (Well, even if we do not apply this patch, I believe it is a good idea to make libvirt validate the NUMA configuration.) Yes, libvirt really ought to validate this, since such inconsistency is a bogus configuration. It would be desirable for libvirt to reject it completely as an error, but we should check if there any common apps which are (accidentally) relying on such broken configs already. Daniel -- |: http://berrange.com -o-http://www.flickr.com/photos/dberrange/ :| |: http://libvirt.org -o- http://virt-manager.org :| |: http://autobuild.org -o- http://search.cpan.org/~danberr/ :| |: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
[Qemu-devel] [RFC PATCH 14/14] numa: add -numa node, memdev= option
This option provides the infrastructure for binding guest NUMA nodes
to host NUMA nodes. For example:
-object memory-ram,size=1024M,policy=membind,host-nodes=0,id=ram-node0 \
-numa node,nodeid=0,cpus=0,memdev=ram-node0 \
-object memory-ram,size=1024M,policy=interleave,host-nodes=1-3,id=ram-node1 \
-numa node,nodeid=1,cpus=1,memdev=ram-node1
The option replaces -numa mem.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
include/sysemu/sysemu.h | 2 ++
numa.c | 64 +++--
qapi-schema.json| 6 -
3 files changed, 69 insertions(+), 3 deletions(-)
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index e9da760..acfc0c7 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -12,6 +12,7 @@
#include qemu/bitmap.h
#include qom/object.h
#include hw/boards.h
+#include sysemu/hostmem.h
/* vl.c */
@@ -140,6 +141,7 @@ extern int nb_numa_nodes;
typedef struct node_info {
uint64_t node_mem;
DECLARE_BITMAP(node_cpu, MAX_CPUMASK_BITS);
+HostMemoryBackend *node_memdev;
} NodeInfo;
extern NodeInfo numa_info[MAX_NODES];
void set_numa_nodes(void);
diff --git a/numa.c b/numa.c
index f903b9e..686dbfa 100644
--- a/numa.c
+++ b/numa.c
@@ -27,6 +27,8 @@
#include qapi-visit.h
#include qapi/opts-visitor.h
#include qapi/dealloc-visitor.h
+#include qapi/qmp/qerror.h
+
QemuOptsList qemu_numa_opts = {
.name = numa,
.implied_opt_name = type,
@@ -34,10 +36,13 @@ QemuOptsList qemu_numa_opts = {
.desc = { { 0 } } /* validated with OptsVisitor */
};
+static int have_memdevs = -1;
+
static int numa_node_parse(NumaNodeOptions *opts)
{
uint16_t nodenr;
uint16List *cpus = NULL;
+Error *local_err = NULL;
if (opts-has_nodeid) {
nodenr = opts-nodeid;
@@ -60,6 +65,19 @@ static int numa_node_parse(NumaNodeOptions *opts)
bitmap_set(numa_info[nodenr].node_cpu, cpus-value, 1);
}
+if (opts-has_mem opts-has_memdev) {
+fprintf(stderr, qemu: cannot specify both mem= and memdev=\n);
+return -1;
+}
+
+if (have_memdevs == -1) {
+have_memdevs = opts-has_memdev;
+}
+if (opts-has_memdev != have_memdevs) {
+fprintf(stderr, qemu: memdev option must be specified for either
+all or no nodes\n);
+}
+
if (opts-has_mem) {
int64_t mem_size;
char *endptr;
@@ -70,7 +88,19 @@ static int numa_node_parse(NumaNodeOptions *opts)
}
numa_info[nodenr].node_mem = mem_size;
}
+if (opts-has_memdev) {
+Object *o;
+o = object_resolve_path_type(opts-memdev, TYPE_MEMORY_BACKEND, NULL);
+if (!o) {
+error_setg(local_err, memdev=%s is ambiguous, opts-memdev);
+qerror_report_err(local_err);
+return -1;
+}
+object_ref(o);
+numa_info[nodenr].node_mem = object_property_get_int(o, size, NULL);
+numa_info[nodenr].node_memdev = MEMORY_BACKEND(o);
+}
return 0;
}
@@ -188,12 +218,42 @@ void set_numa_modes(void)
}
}
+static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner,
+ const char *name,
+ QEMUMachineInitArgs *args)
+{
+uint64_t ram_size = args-ram_size;
+
+memory_region_init_ram(mr, owner, name, ram_size);
+vmstate_register_ram_global(mr);
+}
+
void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
const char *name,
QEMUMachineInitArgs *args)
{
uint64_t ram_size = args-ram_size;
+uint64_t addr = 0;
+int i;
-memory_region_init_ram(mr, owner, name, ram_size);
-vmstate_register_ram_global(mr);
+if (nb_numa_nodes == 0 || !have_memdevs) {
+allocate_system_memory_nonnuma(mr, owner, name, args);
+return;
+}
+
+memory_region_init(mr, owner, name, ram_size);
+for (i = 0; i nb_numa_nodes; i++) {
+Error *local_err = NULL;
+uint64_t size = numa_info[i].node_mem;
+HostMemoryBackend *backend = numa_info[i].node_memdev;
+MemoryRegion *seg = host_memory_backend_get_memory(backend,
local_err);
+if (local_err) {
+qerror_report_err(local_err);
+exit(1);
+}
+
+memory_region_add_subregion(mr, addr, seg);
+vmstate_register_ram_global(seg);
+addr += size;
+}
}
diff --git a/qapi-schema.json b/qapi-schema.json
index d99e39d..e449316 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -4256,7 +4256,10 @@
#
# @cpus: #optional VCPUs belong to this node
#
-# @mem: #optional memory size of this node
+# @memdev: #optional memory backend object. If specified for one node,
+# it must be specified for all nodes.
+#
+# @mem: #optional memory size of this node; mutually exclusive with @memdev.
#
#
[Qemu-devel] [PATCH] ds18s20: Add onewire thermal sensor
Support for a dallas/maxim onewire sensor, enough of it to
fool linux's w1-gpio driver
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/misc/Makefile.objs | 2 +
hw/misc/w1-ds18s20.c | 332
++
2 files changed, 334 insertions(+)
create mode 100644 hw/misc/w1-ds18s20.c
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index f674365..b42c231 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -42,3 +42,5 @@ obj-$(CONFIG_SLAVIO) += slavio_misc.o
obj-$(CONFIG_ZYNQ) += zynq_slcr.o
obj-$(CONFIG_PVPANIC) += pvpanic.o
+
+obj-y += w1-ds18s20.o
diff --git a/hw/misc/w1-ds18s20.c b/hw/misc/w1-ds18s20.c
new file mode 100644
index 000..cea3d6e
--- /dev/null
+++ b/hw/misc/w1-ds18s20.c
@@ -0,0 +1,332 @@
+/*
+ * w1-ds18s20.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+/*
+ * This device will behave like a DS18S20 onewire temperature sensor,
+ * Linux's w1-gpio driver will be fooled into talking to it.
+ *
+ * w1-gpio (and other onewire masters?) attempts to fudge the bit timing
+ * to try to adapt to 'bad' wires, most real hardware sensors must have a
+ * PLL of sort are seems to be able to adapt, this implementation doesn't
+ * and 'sometime' drops from the bus for a short time, in a way it's
+ * rather nice as it simulates a moderately bad wire.
+ *
+ * To instantiate this driver, you just need one IRQ in and out, there
+ * is a second input IRQ to set the temperature. A nice 'todo' would
+ * possibly to have a monitor command to do so.
+ *
+ * Another nice todo would possibly be to handle a proper qemu 'bus'
+ * and have a way to specify the hardware ID of the device.
+ *
+ * Example instantiation for this device:
+{
+DeviceState * dev = sysbus_create_simple(ds18s20, -1, 0);
+
+qdev_connect_gpio_out(gpio, GPIO_W1, qdev_get_gpio_in(dev, 0));
+qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(gpio, GPIO_W1));
+}
+ * Test case (assuming your w1-gpio knows it's GPIO from a .dts):
+/ # modprobe w1-therm
+/ # modprobe w1-gpio
+/ # cat /sys/bus/w1/devices/28-deadbeeff00d/w1_slave
+50 05 8d e0 ff fd 03 40 14 : crc=cb NO
+00 00 00 00 00 00 00 00 00 t=85000
+/ # cat /sys/bus/w1/devices/28-deadbeeff00d/w1_slave
+50 05 0d f0 7f ff 00 10 45 : crc=45 YES
+50 05 0d f0 7f ff 00 10 45 t=85000
+ *
+ */
+#include hw/sysbus.h
+
+
+#define D(w)
+
+typedef struct OneWireDevice {
+SysBusDevice busdev;
+MemoryRegion dummy_iomem;
+
+qemu_irqout;
+
+int current_temp_mc;// in millicelcius
+uint64_tw1_id; // full w1 ID, including CRC
+uint64_tw1_id_received; // for comparisons
+int muted; // set to 1 when 'offline' awaiting
start
+int addr_bit; // current address bit sent/received
+
+int64_t stamp; // timestamp of last low edge
+
+uint8_t write_buffer; // incoming bits from master
+int write_count;
+uint64_tread_buffer;// outgoing bits to master
+int read_count;
+uint8_t read_crc; // CRC, for scratchpad
+uint8_t command;// current command
+} OneWireDevice;
+
+enum {
+W1_CMD_SEARCH_ROM = 0xf0,
+W1_CMD_MATCH_ROM = 0x55,
+W1_CMD_SKIP_ROM = 0xcc,
+W1_CMD_READ_PSU = 0xb4,
+W1_CMD_CONVERT_TEMP = 0x44,
+W1_CMD_READ_SCRATCHPAD = 0xbe,
+// MISSING write scratchpad, unused in linux
+};
+
+/* CRC bits here were nicked from linux's */
+static uint8_t w1_crc8_table[] = {
+0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
+157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
+35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
+190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
+70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89,
7,
+219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196,
154,
+101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122,
36,
+248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231,
185,
+140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147,
205,
+17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14,
80,
+175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176,
238,
+50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45,
115,
+202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213,
139,
+87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72,
22,
+233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246,
168,
+116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107,
53
+};
+
+static uint8_t w1_calc_crc8(uint8_t * data, int len)
+{
+uint8_t crc = 0;
+while (len--)
+crc =
Re: [Qemu-devel] [PATCH] ds18s20: Add onewire thermal sensor
On 11 December 2013 12:22, M P buser...@gmail.com wrote: Support for a dallas/maxim onewire sensor, enough of it to fool linux's w1-gpio driver Is there a board in QEMU's current set that would use this, or is this part of a larger set of patches that would add a board that uses it? thanks -- PMM
[Qemu-devel] [PATCH] target-ppc: add stubs for KVM breakpoints
The latest update to v3.13-rc3 (bf63839f) breaks the
ppc build with KVM:
kvm-all.o: In function `kvm_update_guest_debug':
kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'
kvm-all.o: In function `kvm_insert_breakpoint':
kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint'
kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint'
kvm-all.o: In function `kvm_remove_breakpoint':
kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint'
kvm-all.o: In function `kvm_remove_all_breakpoints':
kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints'
We need stubs until something gets implemented.
Signed-off-by: Greg Kurz gk...@linux.vnet.ibm.com
---
target-ppc/kvm.c | 28
1 file changed, 28 insertions(+)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 10d0cd9..781b72f 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1906,3 +1906,31 @@ int kvm_arch_on_sigbus(int code, void *addr)
void kvm_arch_init_irq_routing(KVMState *s)
{
}
+
+int kvm_arch_insert_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
+{
+return -EINVAL;
+}
+
+int kvm_arch_remove_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
+{
+return -EINVAL;
+}
+
+int kvm_arch_insert_hw_breakpoint(target_ulong addr, target_ulong len, int
type)
+{
+return -EINVAL;
+}
+
+int kvm_arch_remove_hw_breakpoint(target_ulong addr, target_ulong len, int
type)
+{
+return -EINVAL;
+}
+
+void kvm_arch_remove_all_hw_breakpoints(void)
+{
+}
+
+void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
+{
+}
Re: [Qemu-devel] [PATCH] target-ppc: add stubs for KVM breakpoints
On 11.12.2013, at 14:15, Greg Kurz gk...@linux.vnet.ibm.com wrote: The latest update to v3.13-rc3 (bf63839f) breaks the ppc build with KVM: kvm-all.o: In function `kvm_update_guest_debug': kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug' kvm-all.o: In function `kvm_insert_breakpoint': kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint' kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint' kvm-all.o: In function `kvm_remove_breakpoint': kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint' kvm-all.o: In function `kvm_remove_all_breakpoints': kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints' We need stubs until something gets implemented. Signed-off-by: Greg Kurz gk...@linux.vnet.ibm.com Anthony, can you please directly apply this one? Thanks! Reviewed-by: Alexander Graf ag...@suse.de Alex
Re: [Qemu-devel] [PATCH V4 4/7] qmp: Allow to change password on names block driver states.
On Wed, 11 Dec 2013 11:52:28 +0800
Fam Zheng f...@redhat.com wrote:
On 2013年12月10日 23:16, Luiz Capitulino wrote:
On Tue, 10 Dec 2013 15:25:07 +0100
Kevin Wolf kw...@redhat.com wrote:
My objection to your approach is strong because Benoît already sent an
alternative which I believe is less worse because with it, arguments
actually mean what their names tell instead of having additional bools
for oh, and I said A, but I didn't mean it, I really want B.
Current proposal:
{ 'command': 'block_passwd', 'data': {'*device': 'str',
'*node-name': 'str', 'password':
'str'} }
I vote for this.
Ok. As it's clear that I've failed to demonstrate how I think we're
going to move all those commands into the wrong direction, I think it's
time to withdrawn my suggestion.
[Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're essentially the layer before
the first code that gets executed inside the guest.
The guest expects that its data and instruction cache view of the world
is 100% consistent when it initially boots. This works just fine on
initial rom population for the first boot.
However, when we reboot and then repopulate the rom region there could
be old code still stuck in the instruction cache, giving the guest an
inconsistent view of the world when we're using kvm.
So we need to invalidate the icache every time we write a rom into guest
address space. We do not need to do this for every DMA since the guest
expects it has to flush the icache manually in that case.
This fixes random reboot issues on e5500 (booke ppc) for me.
Signed-off-by: Alexander Graf ag...@suse.de
---
exec.c | 8
hw/core/loader.c | 10 ++
2 files changed, 18 insertions(+)
diff --git a/exec.c b/exec.c
index f4b9ef2..cc63eb6 100644
--- a/exec.c
+++ b/exec.c
@@ -50,6 +50,7 @@
#include translate-all.h
#include exec/memory-internal.h
+#include qemu/cache-utils.h
//#define DEBUG_SUBPAGE
@@ -2033,6 +2034,13 @@ void cpu_physical_memory_write_rom(hwaddr addr,
ptr = qemu_get_ram_ptr(addr1);
memcpy(ptr, buf, l);
invalidate_and_set_dirty(addr1, l);
+if (kvm_enabled()) {
+/*
+ * The guest may want to directly execute from the rom region,
+ * so we better invalidate its icache
+ */
+flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
+}
}
len -= l;
buf += l;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 60d2ebd..4f809f3 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -51,6 +51,7 @@
#include hw/nvram/fw_cfg.h
#include exec/memory.h
#include exec/address-spaces.h
+#include qemu/cache-utils.h
#include zlib.h
@@ -619,6 +620,7 @@ static void *rom_set_mr(Rom *rom, Object *owner, const char
*name)
data = memory_region_get_ram_ptr(rom-mr);
memcpy(data, rom-data, rom-datasize);
+flush_icache_range((uintptr_t)data, (uintptr_t)data + rom-datasize);
return data;
}
@@ -777,6 +779,14 @@ static void rom_reset(void *unused)
if (rom-mr) {
void *host = memory_region_get_ram_ptr(rom-mr);
memcpy(host, rom-data, rom-datasize);
+if (kvm_enabled()) {
+/*
+ * The guest may want to directly execute from the rom region,
+ * so we better invalidate its icache
+ */
+flush_icache_range((uintptr_t)host,
+ (uintptr_t)host + rom-datasize);
+}
} else {
cpu_physical_memory_write_rom(rom-addr, rom-data, rom-datasize);
}
--
1.8.1.4
Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
Il 11/12/2013 14:23, Alexander Graf ha scritto:
+if (kvm_enabled()) {
+/*
+ * The guest may want to directly execute from the rom
region,
+ * so we better invalidate its icache
+ */
+flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
+}
Shouldn't KVM itself do that when a memslot is registered? There should
be no reason for non-TCG QEMU to flush the icache.
Paolo
Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
On 11.12.2013, at 14:27, Paolo Bonzini pbonz...@redhat.com wrote:
Il 11/12/2013 14:23, Alexander Graf ha scritto:
+if (kvm_enabled()) {
+/*
+ * The guest may want to directly execute from the rom
region,
+ * so we better invalidate its icache
+ */
+flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
+}
Shouldn't KVM itself do that when a memslot is registered? There should
be no reason for non-TCG QEMU to flush the icache.
How would KVM know when things changed inside of a memory region? It's up to
user space to manage the contents of a memory region, no?
Alex
[Qemu-devel] [PATCH 04/13] mxs/imx23: Add DMA driver
This driver works sufficiently well that linux can use it to access
the SD card using the SD-DMA-SSI-SD. It hasn't been tested for
much else.
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/dma/Makefile.objs | 1 +
hw/dma/mxs_dma.c | 347 +++
2 files changed, 348 insertions(+)
create mode 100644 hw/dma/mxs_dma.c
diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
index 0e65ed0..3373aa1 100644
--- a/hw/dma/Makefile.objs
+++ b/hw/dma/Makefile.objs
@@ -8,6 +8,7 @@ common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
common-obj-$(CONFIG_STP2000) += sparc32_dma.o
common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
+common-obj-$(CONFIG_MXS) += mxs_dma.o
obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
diff --git a/hw/dma/mxs_dma.c b/hw/dma/mxs_dma.c
new file mode 100644
index 000..9ac787b
--- /dev/null
+++ b/hw/dma/mxs_dma.c
@@ -0,0 +1,347 @@
+/*
+ * mxs_dma.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+/*
+ * Implements the DMA block of the mxs.
+ * The current implementation can run chains of commands etc, however it's only
+ * been tested with SSP for SD/MMC card access. It ought to work with normal
SPI
+ * too, and possibly other peripherals, however it's entirely untested
+ */
+#include hw/sysbus.h
+#include hw/arm/mxs.h
+
+/*
+ * DMA IO block register numbers
+ */
+enum {
+DMA_CTRL0 = 0x0,
+DMA_CTRL1 = 0x1,
+DMA_CTRL2 = 0x2,
+DMA_DEVSEL1 = 0x3,
+DMA_DEVSEL2 = 0x4,
+DMA_MAX,
+
+/*
+ * The DMA block for APBH and APBX have a different base address,
+ * but they share a 7 words stride between channels.
+ */
+DMA_STRIDE = 0x70,
+/*
+ * Neither blocks uses that many, but there is space for them...
+ */
+DMA_MAX_CHANNELS = 16,
+};
+
+/*
+ * DMA channel register numbers
+ */
+enum {
+CH_CURCMD = 0,
+CH_NEXTCMD = 1,
+CH_CMD = 2,
+CH_BUFFER_ADDR = 3,
+CH_SEMA = 4,
+CH_DEBUG1 = 5,
+CH_DEBUG2 = 6,
+};
+
+/*
+ * Channel command bit numbers
+ */
+enum {
+CH_CMD_IRQ_COMPLETE = 3,
+CH_CMD_SEMAPHORE = 6,
+};
+
+/*
+ * nicked from linux
+ * this is the memory representation of a DMA request
+ */
+struct mxs_dma_ccw {
+uint32_t next;
+uint16_t bits;
+uint16_t xfer_bytes;
+#define MAX_XFER_BYTES 0xff00
+uint32_t bufaddr;
+#define MXS_PIO_WORDS 16
+uint32_t pio_words[MXS_PIO_WORDS];
+}__attribute__((packed));
+
+/*
+ * Per channel DMA description
+ */
+typedef struct mxs_dma_channel {
+QEMUTimer *timer;
+struct mxs_dma_state *dma;
+int channel; // channel index
+hwaddr base; // base of peripheral
+hwaddr dataoffset; // offset of the true in/out data latch register
+uint32_t r[10];
+qemu_irq irq;
+} mxs_dma_channel;
+
+
+typedef struct mxs_dma_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+const char * name;
+
+struct soc_dma_s * dma;
+uint32_t r[DMA_MAX];
+
+hwaddr base; // base of peripheral
+mxs_dma_channel channel[DMA_MAX_CHANNELS];
+} mxs_dma_state;
+
+static void mxs_dma_ch_update(mxs_dma_channel *s)
+{
+struct mxs_dma_ccw req;
+int i;
+
+/* increment the semaphore, if needed */
+s-r[CH_SEMA] = (((s-r[CH_SEMA] 16) 0xff) +
+(s-r[CH_SEMA] 0xff)) 16;
+if (!((s-r[CH_SEMA] 16) 0xff)) {
+return;
+}
+/* read the request from memory */
+cpu_physical_memory_read(s-r[CH_NEXTCMD], req, sizeof(req));
+/* update the latch registers accordingly */
+s-r[CH_CURCMD] = s-r[CH_NEXTCMD];
+s-r[CH_NEXTCMD] = req.next;
+s-r[CH_CMD] = (req.xfer_bytes 16) | req.bits;
+s-r[CH_BUFFER_ADDR] = req.bufaddr;
+
+/* write PIO registers first, if any */
+for (i = 0; i (req.bits 12); i++) {
+cpu_physical_memory_rw(s-base + (i 4),
+(uint8_t*) req.pio_words[i], 4, 1);
+}
+/* next handle any data requests */
+switch (req.bits 0x3) {
+case 0:
+break; // PIO only
+case 0x1: { // WRITE (from periph to memory)
+uint32_t buf = req.bufaddr;
+uint8_t b = 0;
+while (req.xfer_bytes--) {
+cpu_physical_memory_rw(s-base + s-dataoffset, b, 1, 0);
+cpu_physical_memory_rw(buf, b, 1, 1);
+buf++;
+}
+} break;
+case 0x2: { // READ (from memory to periph)
+uint32_t buf = req.bufaddr;
+uint8_t b = 0;
+while (req.xfer_bytes--) {
+cpu_physical_memory_rw(buf, b, 1, 0);
+cpu_physical_memory_rw(s-base + s-dataoffset, b, 1, 1);
+buf++;
+}
+} break;
+}
+
+s-dma-r[DMA_CTRL1] |= 1 s-channel;
+/* trigger IRQ if requested */
+if ((s-dma-r[DMA_CTRL1] 16) (1 s-channel)) {
+if (req.bits (1 CH_CMD_IRQ_COMPLETE)) {
+
[Qemu-devel] [PATCH 03/13] mxs/imx23: Add uart driver
Prototype driver for the mxs/imx23 uart IO block. This has no
real 'uart' functional code, apart from letting itself be
initialized by linux without generating a timeout error.
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/char/Makefile.objs | 1 +
hw/char/mxs_uart.c| 146 ++
2 files changed, 147 insertions(+)
create mode 100644 hw/char/mxs_uart.c
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index cbd6a00..8ea5670 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -19,6 +19,7 @@ common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
common-obj-$(CONFIG_GRLIB) += grlib_apbuart.o
common-obj-$(CONFIG_IMX) += imx_serial.o
+common-obj-$(CONFIG_MXS) += mxs_uart.o
common-obj-$(CONFIG_LM32) += lm32_juart.o
common-obj-$(CONFIG_LM32) += lm32_uart.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-uart.o
diff --git a/hw/char/mxs_uart.c b/hw/char/mxs_uart.c
new file mode 100644
index 000..79b2582
--- /dev/null
+++ b/hw/char/mxs_uart.c
@@ -0,0 +1,146 @@
+/*
+ * mxs_uart.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+/*
+ * Work in progress ! Right now there's just enough so that linux driver
+ * will instantiate after a probe, there is no functional code.
+ */
+#include hw/sysbus.h
+#include hw/arm/mxs.h
+
+#define D(w) w
+
+enum {
+UART_CTRL = 0x0,
+UART_CTRL1 = 0x1,
+UART_CTRL2 = 0x2,
+UART_LINECTRL = 0x3,
+UART_LINECTRL2 = 0x4,
+UART_INTR = 0x5,
+UART_APP_DATA = 0x6,
+UART_APP_STAT = 0x7,
+UART_APP_DEBUG = 0x8,
+UART_APP_VERSION = 0x9,
+UART_APP_AUTOBAUD = 0xa,
+
+UART_MAX,
+};
+typedef struct mxs_uart_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t r[UART_MAX];
+
+struct {
+uint16_t b[16];
+int w, r;
+} fifo[2];
+qemu_irq irq;
+CharDriverState *chr;
+} mxs_uart_state;
+
+static uint64_t mxs_uart_read(
+void *opaque, hwaddr offset, unsigned size)
+{
+mxs_uart_state *s = (mxs_uart_state *) opaque;
+uint32_t res = 0;
+
+D(printf(%s %04x (%d) = , __func__, (int)offset, size);)
+switch (offset 4) {
+case 0 ... UART_MAX:
+res = s-r[offset 4];
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+break;
+}
+D(printf(%08x\n, res);)
+
+return res;
+}
+
+static void mxs_uart_write(void *opaque, hwaddr offset,
+uint64_t value, unsigned size)
+{
+mxs_uart_state *s = (mxs_uart_state *) opaque;
+uint32_t oldvalue = 0;
+
+D(printf(%s %04x %08x(%d)\n, __func__, (int)offset, (int)value, size);)
+switch (offset 4) {
+case 0 ... UART_MAX:
+mxs_write(s-r[offset 4], offset, value, size);
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+break;
+}
+switch (offset 4) {
+case UART_CTRL:
+if ((oldvalue ^ s-r[UART_CTRL]) == 0x8000
+ !(oldvalue 0x8000)) {
+printf(%s reseting, anding clockgate\n, __func__);
+s-r[UART_CTRL] |= 0x4000;
+}
+break;
+}
+}
+
+static void mxs_uart_set_irq(void *opaque, int irq, int level)
+{
+//mxs_uart_state *s = (mxs_uart_state *)opaque;
+printf(%s %3d = %d\n, __func__, irq, level);
+}
+
+static const MemoryRegionOps mxs_uart_ops = {
+.read = mxs_uart_read,
+.write = mxs_uart_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+
+static int mxs_uart_init(SysBusDevice *dev)
+{
+mxs_uart_state *s = OBJECT_CHECK(mxs_uart_state, dev, mxs_uart);
+DeviceState *qdev = DEVICE(dev);
+
+qdev_init_gpio_in(qdev, mxs_uart_set_irq, 32 * 3);
+sysbus_init_irq(dev, s-irq);
+memory_region_init_io(s-iomem, OBJECT(s), mxs_uart_ops, s, mxs_uart,
0x2000);
+sysbus_init_mmio(dev, s-iomem);
+
+s-r[UART_CTRL] = 0xc003;
+s-r[UART_CTRL2] = 0x00220180;
+s-r[UART_APP_STAT] = 0x89f0;
+s-r[UART_APP_VERSION] = 0x0300;
+return 0;
+}
+
+
+static void mxs_uart_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc-init = mxs_uart_init;
+}
+
+static TypeInfo uart_info = {
+.name = mxs_uart,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(mxs_uart_state),
+.class_init= mxs_uart_class_init,
+};
+
+static void mxs_uart_register(void)
+{
+type_register_static(uart_info);
+}
+
+type_init(mxs_uart_register)
+
--
1.8.5.1
[Qemu-devel] [PATCH 01/13] mxs/imx23: Add main header file
Header file containing most of the base addresses and IO registers needed for the Freescale mxs/imx23 SoC emumation. Also contains a generic helper to implement the SET/AND/OR/XOR trick shared by pretty much all of the IO blocks on this SoC Signed-off-by: Michel Pollet buser...@gmail.com --- hw/arm/mxs.h | 208 +++ 1 file changed, 208 insertions(+) create mode 100644 hw/arm/mxs.h diff --git a/hw/arm/mxs.h b/hw/arm/mxs.h new file mode 100644 index 000..91d3ddb --- /dev/null +++ b/hw/arm/mxs.h @@ -0,0 +1,208 @@ +/* + * mxs.h + * + * Copyright: Michel Pollet buser...@gmail.com + * + * QEMU Licence, the bits that aren't from linux's + */ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef MXS_H_ +#define MXS_H_ + +/* + * OCRAM + */ +#define MX23_OCRAM_BASE_ADDR 0x +#define MX23_OCRAM_SIZESZ_32K + +/* + * IO + */ +#define MX23_IO_BASE_ADDR 0x8000 +#define MX23_IO_SIZE SZ_1M + +#define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00) +#define MX23_APBH_DMA_BASE_ADDR(MX23_IO_BASE_ADDR + 0x004000) +#define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000) +#define MX23_GPMI_BASE_ADDR(MX23_IO_BASE_ADDR + 0x00c000) +#define MX23_SSP1_BASE_ADDR(MX23_IO_BASE_ADDR + 0x01) +#define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000) +#define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000) +#define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02) +#define MX23_APBX_DMA_BASE_ADDR(MX23_IO_BASE_ADDR + 0x024000) +#define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000) +#define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000) +#define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000) +#define MX23_AXI_AHB0_BASE_ADDR(MX23_IO_BASE_ADDR + 0x02e000) +#define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x03) +#define MX23_SSP2_BASE_ADDR(MX23_IO_BASE_ADDR + 0x034000) +#define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000) +#define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04) +#define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000) +#define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000) +#define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000) +#define MX23_AUDIOOUT_BASE_ADDR(MX23_IO_BASE_ADDR + 0x048000) +#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000) +#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05) +#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000) +#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000) +#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000) +#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000) +#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000) +#define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000) +#define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000) +#define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07) +#define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000) +#define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x08) +#define MX23_DRAM_BASE_ADDR(MX23_IO_BASE_ADDR + 0x0e) + +#define MX23_IO_P2V(x) MXS_IO_P2V(x) +#define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x)) + +/* + * IRQ + */ +#define MX23_INT_DUART 0 +#define MX23_INT_COMMS_RX 1 +#define MX23_INT_COMMS_TX 1 +#define MX23_INT_SSP2_ERROR2 +#define MX23_INT_VDD5V 3 +#define MX23_INT_HEADPHONE_SHORT 4 +#define MX23_INT_DAC_DMA 5 +#define MX23_INT_DAC_ERROR 6 +#define MX23_INT_ADC_DMA 7 +#define MX23_INT_ADC_ERROR 8 +#define MX23_INT_SPDIF_DMA 9 +#define MX23_INT_SAIF2_DMA 9 +#define MX23_INT_SPDIF_ERROR 10 +#define MX23_INT_SAIF1_IRQ 10 +#define
[Qemu-devel] [PATCH 07/13] mxs/imx23: Implements the pin mux, GPIOs
Implements the pinctrl and GPIO block for the imx23
It handles GPIO output, and GPIO input from qemu translated
into pin values and interrupts, if appropriate.
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/arm/Makefile.objs | 2 +-
hw/arm/imx23_pinctrl.c | 293 +
2 files changed, 294 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/imx23_pinctrl.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 9adcb96..ea53988 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,4 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o
z2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-y += omap1.o omap2.o strongarm.o
-obj-$(CONFIG_MXS) += imx23_digctl.o
+obj-$(CONFIG_MXS) += imx23_digctl.o imx23_pinctrl.o
diff --git a/hw/arm/imx23_pinctrl.c b/hw/arm/imx23_pinctrl.c
new file mode 100644
index 000..ecfb755
--- /dev/null
+++ b/hw/arm/imx23_pinctrl.c
@@ -0,0 +1,293 @@
+/*
+ * imx23_pinctrl.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+/*
+ * Implements the pinctrl and GPIO block for the imx23
+ * It handles GPIO output, and GPIO input from qemu translated
+ * into pin values and interrupts, if appropriate.
+ */
+#include hw/sysbus.h
+#include hw/arm/mxs.h
+
+#define D(w)
+
+enum {
+PINCTRL_BANK_COUNT = 3,
+
+PINCTRL_CTRL = 0,
+PINCTRL_BANK_MUXSEL = 0x10,
+PINCTRL_BANK_BASE = 0x40,
+
+/* these are not 4 register numbers, these are 8 register numbers */
+PINCTRL_BANK_PULL = 0x4,
+PINCTRL_BANK_OUT = 0x5,
+PINCTRL_BANK_DIN = 0x6,
+PINCTRL_BANK_DOE = 0x7,
+PINCTRL_BANK_PIN2IRQ = 0x8,
+PINCTRL_BANK_IRQEN = 0x9,
+PINCTRL_BANK_IRQLEVEL = 0xa,
+PINCTRL_BANK_IRQPOL = 0xb,
+PINCTRL_BANK_IRQSTAT = 0xc,
+
+PINCTRL_BANK_INTERNAL_STATE = 0xd,
+PINCTRL_MAX = 0xe0,
+};
+
+#define PINCTRL_BANK_REG(_bank, _reg) ((_reg 8) | (_bank 4))
+
+enum {
+MUX_GPIO = 0x3,
+};
+
+
+typedef struct imx23_pinctrl_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t r[PINCTRL_MAX];
+qemu_irq irq_in[3];
+qemu_irq irq_out[PINCTRL_BANK_COUNT * 32];
+
+uint32_t state[PINCTRL_BANK_COUNT];
+} imx23_pinctrl_state;
+
+static uint64_t imx23_pinctrl_read(
+void *opaque, hwaddr offset, unsigned size)
+{
+imx23_pinctrl_state *s = (imx23_pinctrl_state *) opaque;
+uint32_t res = 0;
+
+switch (offset 4) {
+case 0 ... PINCTRL_MAX:
+res = s-r[offset 4];
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+break;
+}
+
+return res;
+}
+
+static uint8_t imx23_pinctrl_getmux(
+imx23_pinctrl_state *s, int pin)
+{
+int base = pin / 16, offset = pin % 16;
+return (s-r[PINCTRL_BANK_MUXSEL + base] (offset * 2)) 0x3;
+}
+
+/*
+ * usage imx23_pinctrl_getbit(s, PINCTRL_BANK_IRQEN, 48)...
+ */
+static uint8_t imx23_pinctrl_getbit(
+imx23_pinctrl_state *s, uint16_t reg, int pin)
+{
+int bank = pin / 32, offset = pin % 32;
+uint32_t * latch = s-r[PINCTRL_BANK_REG(bank, reg) 4];
+//printf(%s bank %d offset %d reg %d : %04x=%08x\n, __func__, bank,
offset, reg,
+//PINCTRL_BANK_REG(bank, reg),
+//*latch);
+return (*latch offset) 0x1;
+}
+
+static void imx23_pinctrl_setbit(
+imx23_pinctrl_state *s, uint16_t reg, int pin, int value)
+{
+int bank = pin / 32, offset = pin % 32;
+uint32_t * latch = s-r[PINCTRL_BANK_REG(bank, reg) 4];
+*latch = (*latch ~(1 offset)) | (!!value offset);
+}
+
+static void imx23_pinctrl_write_bank(
+imx23_pinctrl_state *s, int bank,
+int reg, uint32_t value,
+uint32_t mask)
+{
+int set, pin;
+switch (reg) {
+/*
+ * Linux has a way of using the DOEPULL register to toggle the pin
+ */
+case PINCTRL_BANK_PULL:
+case PINCTRL_BANK_DOE:
+/*
+ * Writing to the Data OUT register just triggers the
+ * output qemu IRQ for any further peripherals
+ */
+case PINCTRL_BANK_OUT: {
+while ((set = ffs(mask)) 0) {
+set--;
+mask = ~(1 set);
+pin = (bank * 32) + set;
+/*
+ * For a reason that is not clear, the pullup bit appears
+ * inverted (!) ignoring for now, assume hardware pullup
+ */
+// imx23_pinctrl_getbit(s, PINCTRL_BANK_PULL, pin)
+int val =
+imx23_pinctrl_getbit(s, PINCTRL_BANK_DOE, pin) ?
+imx23_pinctrl_getbit(s, PINCTRL_BANK_OUT, pin)
:
+1;
+D(printf(%s set %2d to OUT:%d DOE:%d (PULL:%d) = %d\n,
__func__,
+pin,
+
[Qemu-devel] [PATCH 05/13] mxs/imx23: Add the interrupt collector
Implements the interrupt collector IO block
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/intc/Makefile.objs | 1 +
hw/intc/mxs_icoll.c | 200 ++
2 files changed, 201 insertions(+)
create mode 100644 hw/intc/mxs_icoll.c
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..e934b3c 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -24,3 +24,4 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
obj-$(CONFIG_SH4) += sh_intc.o
obj-$(CONFIG_XICS) += xics.o
obj-$(CONFIG_XICS_KVM) += xics_kvm.o
+obj-$(CONFIG_MXS) += mxs_icoll.o
diff --git a/hw/intc/mxs_icoll.c b/hw/intc/mxs_icoll.c
new file mode 100644
index 000..a1fd7d9
--- /dev/null
+++ b/hw/intc/mxs_icoll.c
@@ -0,0 +1,200 @@
+/*
+ * mxs_icoll.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+/*
+ * This block implements the interrupt collector of the mxs
+ * Currently no priority is handled, as linux doesn't use them anyway
+ */
+
+#include hw/sysbus.h
+#include hw/arm/mxs.h
+
+enum {
+ICOLL_VECTOR = 0,
+ICOLL_LEVELACK = 1,
+ICOLL_CTRL = 2,
+// 3, reserved?
+ICOLL_VBASE = 4,
+ICOLL_STAT = 7,
+
+ICOLL_REG_MAX,
+
+ICOLL_RAW0 = 0xa,
+ICOLL_RAW1,
+ICOLL_RAW2,
+ICOLL_RAW3,
+
+ICOLL_INT0 = 0x12,
+ICOLL_INT127 = 0x91,
+};
+
+typedef struct mxs_icoll_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+uint32_t reg[ICOLL_REG_MAX];
+
+uint32_t raised[4];
+uint32_t fiq[4];
+uint32_t irq[4];
+
+uint8_tr[128];
+
+qemu_irq parent_irq;
+qemu_irq parent_fiq;
+} mxs_icoll_state;
+
+static void mxs_icoll_update(mxs_icoll_state *s)
+{
+int fiq = 0, irq = 0;
+int i;
+
+for (i = 0; i 4; i++) {
+int id = ffs(s-raised[i]);
+int vector = (i * 32) + id - 1;
+if (s-raised[i] s-fiq[i]) {
+fiq++;
+s-reg[ICOLL_STAT] = vector;
+break;
+}
+if (s-raised[i] s-irq[i]) {
+irq++;
+s-reg[ICOLL_STAT] = vector;
+break;
+}
+}
+qemu_set_irq(s-parent_irq, irq != 0);
+qemu_set_irq(s-parent_fiq, fiq != 0);
+}
+
+static void mxs_icoll_set_irq(void *opaque, int irq, int level)
+{
+mxs_icoll_state *s = (mxs_icoll_state *) opaque;
+if (level)
+s-raised[(irq / 32)] |= 1 (irq % 32);
+else
+s-raised[(irq / 32)] = ~(1 (irq % 32));
+mxs_icoll_update(s);
+}
+
+static uint64_t mxs_icoll_read(void *opaque, hwaddr offset, unsigned size)
+{
+mxs_icoll_state *s = (mxs_icoll_state *) opaque;
+
+switch (offset 4) {
+case 0 ... ICOLL_REG_MAX:
+return s-reg[offset 4];
+case ICOLL_RAW0 ... ICOLL_RAW3:
+return s-raised[(offset 4) - ICOLL_RAW0];
+case ICOLL_INT0 ... ICOLL_INT127:
+return s-r[(offset 4) - ICOLL_INT0];
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+break;
+}
+return 0;
+}
+
+static void mxs_icoll_write(
+void *opaque, hwaddr offset, uint64_t value, unsigned size)
+{
+mxs_icoll_state *s = (mxs_icoll_state *) opaque;
+uint32_t irqval, irqi = 0;
+uint32_t * dst = NULL;
+uint32_t oldvalue = 0;
+
+switch (offset 4) {
+case 0 ... ICOLL_REG_MAX:
+dst = s-reg + (offset 4);
+break;
+case ICOLL_INT0 ... ICOLL_INT127:
+irqi = (offset 4) - ICOLL_INT0;
+irqval = s-r[irqi];
+dst = irqval;
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+break;
+}
+if (!dst) {
+return;
+}
+oldvalue = mxs_write(dst, offset, value, size);
+
+switch (offset 4) {
+case ICOLL_CTRL:
+if ((oldvalue ^ s-r[ICOLL_CTRL]) == 0x8000
+ !(oldvalue 0x8000)) {
+// printf(%s reseting, anding clockgate\n, __func__);
+s-r[ICOLL_CTRL] |= 0x4000;
+}
+break;
+case ICOLL_LEVELACK:
+irqi = s-reg[ICOLL_STAT] 0x7f;
+s-raised[(irqi / 32)] = ~(1 (irqi % 32));
+s-reg[ICOLL_STAT] = 0x7f;
+break;
+case ICOLL_INT0 ... ICOLL_INT127:
+s-r[irqi] = irqval ~(0x40); // dont' set softirq bit
+if (irqval 0x4) // ENABLE
+s-irq[irqi / 32] |= (1 (irqi % 32));
+else
+s-irq[irqi / 32] = ~(1 (irqi % 32));
+if (irqval 0x10) // ENFIQ
+s-fiq[irqi / 32] |= (1 (irqi % 32));
+else
+s-fiq[irqi / 32] = ~(1 (irqi % 32));
+if (irqval 0x8) // SOFTIRQ
+mxs_icoll_set_irq(s, irqi, 1);
+break;
+}
+
+mxs_icoll_update(s);
[Qemu-devel] [PATCH 00/13] Freescale mxs/imx23 + Olimex Olinuxino support
This series adds support for the imx233 SoC, and also adds support for emulating an Olinux Olinuxino board with a few peripherals, as a test harness. The emulation works pretty well, boots linux 3.12 vanilla from an emulated SD card, has USB bridge support (but no support for USB 1.1 devices like mouse+keyboard), RTC and quite a few other bits (some of them fairly skeletal) This series has been in used for quite a few months; it was posted here a few month back and one of the question was to wether I would stick around to support it. Perhaps the fact that I reworked it all on trunk and reposted it will help answer this question. This patch series is also available on this github branch, in case its' more convenient to use the inline comment function there. https://github.com/buserror-uk/qemu-buserror/commits/dev-imx233 Michel Pollet (13): mxs/imx23: Add main header file mxs: Add CONFIG_MXS to the arm-softmmu config mxs/imx23: Add uart driver mxs/imx23: Add DMA driver mxs/imx23: Add the interrupt collector mxs/imx23: Add digctl driver mxs/imx23: Implements the pin mux, GPIOs mxs/imx23: Add SSP/SPI driver mxs/imx23: Add the RTC block mxs/imx23: Add the timers mxs/imx23: Add the USB driver mxs/imx23: Main core instantiation and minor IO blocks mxs/imx23: Adds support for an Olinuxino board default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs| 2 + hw/arm/imx233-olinuxino.c | 169 + hw/arm/imx23_digctl.c | 110 hw/arm/imx23_pinctrl.c | 293 ++ hw/arm/mxs.c| 388 hw/arm/mxs.h| 208 + hw/char/Makefile.objs | 1 + hw/char/mxs_uart.c | 146 +++ hw/dma/Makefile.objs| 1 + hw/dma/mxs_dma.c| 347 +++ hw/intc/Makefile.objs | 1 + hw/intc/mxs_icoll.c | 200 + hw/ssi/Makefile.objs| 1 + hw/ssi/mxs_spi.c| 239 + hw/timer/Makefile.objs | 1 + hw/timer/mxs_rtc.c | 147 +++ hw/timer/mxs_timrot.c | 271 hw/usb/Makefile.objs| 1 + hw/usb/mxs_usb.c| 254 ++ 20 files changed, 2781 insertions(+) create mode 100644 hw/arm/imx233-olinuxino.c create mode 100644 hw/arm/imx23_digctl.c create mode 100644 hw/arm/imx23_pinctrl.c create mode 100644 hw/arm/mxs.c create mode 100644 hw/arm/mxs.h create mode 100644 hw/char/mxs_uart.c create mode 100644 hw/dma/mxs_dma.c create mode 100644 hw/intc/mxs_icoll.c create mode 100644 hw/ssi/mxs_spi.c create mode 100644 hw/timer/mxs_rtc.c create mode 100644 hw/timer/mxs_timrot.c create mode 100644 hw/usb/mxs_usb.c -- 1.8.5.1
Re: [Qemu-devel] [PATCH] ds18s20: Add onewire thermal sensor
I've just posted the imx233 patch series, with a board that uses this driver. M On Wed, Dec 11, 2013 at 12:44 PM, Peter Maydell peter.mayd...@linaro.orgwrote: On 11 December 2013 12:22, M P buser...@gmail.com wrote: Support for a dallas/maxim onewire sensor, enough of it to fool linux's w1-gpio driver Is there a board in QEMU's current set that would use this, or is this part of a larger set of patches that would add a board that uses it? thanks -- PMM
[Qemu-devel] [PATCH 08/13] mxs/imx23: Add SSP/SPI driver
This implements the SSP port(s) of the mxs. Currently hardcoded for
the SD card interface, but as TODO it could rather easily be made
to be generic and support 'generic' SPI too.
It is geared toward working with DMA, as the linux drivers uses it that
way.
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/ssi/Makefile.objs | 1 +
hw/ssi/mxs_spi.c | 239 +++
2 files changed, 240 insertions(+)
create mode 100644 hw/ssi/mxs_spi.c
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index 9555825..72ec849 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -4,3 +4,4 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
obj-$(CONFIG_OMAP) += omap_spi.o
+obj-$(CONFIG_MXS) += mxs_spi.o
diff --git a/hw/ssi/mxs_spi.c b/hw/ssi/mxs_spi.c
new file mode 100644
index 000..8bc70f9
--- /dev/null
+++ b/hw/ssi/mxs_spi.c
@@ -0,0 +1,239 @@
+/*
+ * mxs_ssp.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+/*
+ * This implements the SSP port(s) of the mxs. Currently hardcoded for the
+ * SD card interface, but as TODO it could rather easily be made to be generic
+ * and support 'generic' SPI too.
+ * It is geared toward working with DMA, as the linux drivers uses it that way.
+ */
+#include hw/sysbus.h
+#include hw/arm/mxs.h
+#include sysemu/blockdev.h
+#include hw/sd.h
+
+/*
+ * SSP register indexes, most of the useful ones
+ */
+enum {
+SSP_CTRL = 0x0,
+SSP_SD_CMD0 = 0x1,
+SSP_SD_CMD1 = 0x2,
+SSP_COMPREF = 0x3,
+SSP_COMPMASK = 0x4,
+SSP_TIMING = 0x5,
+SSP_CTRL1 = 0x6,
+SSP_DATA = 0x7,
+SSP_SDRESP0 = 0x8,
+SSP_SDRESP1 = 0x9,
+SSP_SDRESP2 = 0xa,
+SSP_SDRESP3 = 0xb,
+SSP_STATUS = 0xc,
+
+SSP_VERSION = 0x11,
+SSP_MAX,
+};
+
+/*
+ * SSP_CTRL bit numbers
+ */
+enum {
+CTRL_READ = 25,
+CTRL_DATA_XFER = 24,
+CTRL_ENABLE = 16,
+CTRL_LONG_REST = 19,
+};
+/*
+ * SSP_STAT bit numbers
+ */
+enum {
+STAT_BUSY = 0,
+STAT_DATA_BUSY = 2,
+STAT_CMD_BUSY = 3,
+STAT_CARD_DETECT = 28,
+};
+
+typedef struct mxs_ssp_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t r[SSP_MAX];
+qemu_irq irq_dma, irq_error;
+SDState *sd;
+} mxs_ssp_state;
+
+static uint64_t mxs_ssp_read(
+void *opaque, hwaddr offset, unsigned size)
+{
+mxs_ssp_state *s = (mxs_ssp_state *) opaque;
+uint32_t res = 0;
+
+switch (offset 4) {
+case 0 ... SSP_MAX:
+res = s-r[offset 4];
+switch (offset 4) {
+case SSP_STATUS:
+s-r[SSP_STATUS] = ~((1 STAT_BUSY) |
+(1 STAT_DATA_BUSY) | (1 STAT_CMD_BUSY));
+break;
+/* dma polls this register to read the data from the card
+ * this is not very efficient, perhaps a better data
conduit
+ * is available. It does work as the real hardware tho...
+ */
+case SSP_DATA:
+res = sd_read_data(s-sd);
+break;
+}
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+break;
+}
+
+return res;
+}
+
+static uint32_t __swap(uint32_t w)
+{
+ return (w 24) | ((w 0x00ff) 8) |
+ ((w 0xff00) 8) | (w 24);
+}
+
+/*
+ * processes one SD/MMC command train. It always have a 'command' but
+ * can also have datas attached, this case is not handled here, it's
+ * handled by the SD layer.
+ * The command can either be short or long, wierdly, the mxs returns
+ * the bytes in some funky order that needs to be restored.
+ * TODO: Make big endian compatible
+ */
+static void mxs_process_cmd(mxs_ssp_state *s)
+{
+if (!(s-r[SSP_CTRL] (1 CTRL_ENABLE)))
+return;
+uint32_t r[4]; // temporary buffer
+
+s-r[SSP_SDRESP0] = s-r[SSP_SDRESP1] =
+s-r[SSP_SDRESP2] = s-r[SSP_SDRESP3] = 0;
+
+SDRequest cmd = {
+.cmd = s-r[SSP_SD_CMD0] 0xff,
+.arg = s-r[SSP_SD_CMD1],
+.crc = 0,
+};
+sd_enable(s-sd, 1);
+sd_do_command(s-sd, cmd, (uint8_t*) r);
+if (s-r[SSP_CTRL] (1 CTRL_LONG_REST)) {
+s-r[SSP_SDRESP0] = __swap(r[3]);
+s-r[SSP_SDRESP1] = __swap(r[2]);
+s-r[SSP_SDRESP2] = __swap(r[1]);
+s-r[SSP_SDRESP3] = __swap(r[0]);
+} else
+s-r[SSP_SDRESP0] = __swap(r[0]);
+
+/* mark these flags as busy, they will be read once
+ * as 'busy' before being cleared by a read. */
+s-r[SSP_STATUS] |= (1 STAT_CMD_BUSY);
+s-r[SSP_STATUS] |= (1 STAT_BUSY);
+if (s-r[SSP_CTRL] (1 CTRL_DATA_XFER))
+s-r[SSP_STATUS] |= (1 STAT_DATA_BUSY);
+}
+
+static void mxs_ssp_write(void *opaque, hwaddr offset,
+uint64_t value,
[Qemu-devel] [PATCH 06/13] mxs/imx23: Add digctl driver
This implements just enough of the digctl IO block to allow
linux to believe it's running on (currently only) an imx23.
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/arm/Makefile.objs | 1 +
hw/arm/imx23_digctl.c | 110 ++
2 files changed, 111 insertions(+)
create mode 100644 hw/arm/imx23_digctl.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 78b5614..9adcb96 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,3 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o
z2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-y += omap1.o omap2.o strongarm.o
+obj-$(CONFIG_MXS) += imx23_digctl.o
diff --git a/hw/arm/imx23_digctl.c b/hw/arm/imx23_digctl.c
new file mode 100644
index 000..b7cd1ff
--- /dev/null
+++ b/hw/arm/imx23_digctl.c
@@ -0,0 +1,110 @@
+/*
+ * imx23_digctl.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+/*
+ * This module implements a very basic IO block for the digctl of the imx23
+ * Basically there is no real logic, just constant registers return, the most
+ * used one bing the chip id that is used by the various linux drivers
+ * to differentiate between imx23 and 28.
+ *
+ * The module consists mostly of read/write registers that the bootloader and
+ * kernel are quite happy to 'set' to whatever value they believe they set...
+ */
+
+#include hw/sysbus.h
+#include hw/arm/mxs.h
+
+enum {
+HW_DIGCTL_RAMCTL = 0x3,
+HW_DIGCTL_CHIPID = 0x31,
+};
+
+typedef struct imx23_digctl_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t reg[0x2000 / 4];
+} imx23_digctl_state;
+
+static uint64_t imx23_digctl_read(
+void *opaque, hwaddr offset, unsigned size)
+{
+imx23_digctl_state *s = (imx23_digctl_state *)opaque;
+uint32_t res = 0;
+
+switch (offset 4) {
+ case 0 ... 0x2000/4:
+ res = s-reg[offset 4];
+ break;
+default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ %s: bad offset 0x%x\n, __func__, (int)offset);
+ return 0;
+}
+return res;
+}
+
+static void imx23_digctl_write(
+void *opaque, hwaddr offset, uint64_t value, unsigned size)
+{
+imx23_digctl_state *s = (imx23_digctl_state *) opaque;
+uint32_t * dst = NULL;
+
+switch (offset 4) {
+case 0 ... 0x2000 / 4:
+dst = s-reg[(offset 4)];
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+return;
+}
+if (!dst) {
+return;
+}
+mxs_write(dst, offset, value, size);
+}
+
+static const MemoryRegionOps imx23_digctl_ops = {
+.read = imx23_digctl_read,
+.write = imx23_digctl_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int imx23_digctl_init(SysBusDevice *dev)
+{
+imx23_digctl_state *s = OBJECT_CHECK(imx23_digctl_state, dev,
imx23_digctl);
+
+memory_region_init_io(s-iomem, OBJECT(s), imx23_digctl_ops, s,
+imx23_digctl, 0x2000);
+sysbus_init_mmio(dev, s-iomem);
+s-reg[HW_DIGCTL_RAMCTL] = 0x6d676953; /* default reset value */
+s-reg[HW_DIGCTL_CHIPID] = 0x3780; /* i.mX233 */
+return 0;
+}
+
+static void imx23_digctl_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc-init = imx23_digctl_init;
+}
+
+static TypeInfo digctl_info = {
+.name = imx23_digctl,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(imx23_digctl_state),
+.class_init= imx23_digctl_class_init,
+};
+
+static void imx23_digctl_register(void)
+{
+type_register_static(digctl_info);
+}
+
+type_init(imx23_digctl_register)
--
1.8.5.1
[Qemu-devel] [PATCH 02/13] mxs: Add CONFIG_MXS to the arm-softmmu config
Allows selective compilation of the MXS bits Signed-off-by: Michel Pollet buser...@gmail.com --- default-configs/arm-softmmu.mak | 1 + 1 file changed, 1 insertion(+) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index e48f102..0d4cf95 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -71,6 +71,7 @@ CONFIG_BLIZZARD=y CONFIG_ONENAND=y CONFIG_TUSB6010=y CONFIG_IMX=y +CONFIG_MXS=y CONFIG_MAINSTONE=y CONFIG_NSERIES=y CONFIG_REALVIEW=y -- 1.8.5.1
Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
On 11 December 2013 13:23, Alexander Graf ag...@suse.de wrote:
The guest expects that its data and instruction cache view of the world
is 100% consistent when it initially boots. This works just fine on
initial rom population for the first boot.
However, when we reboot and then repopulate the rom region there could
be old code still stuck in the instruction cache, giving the guest an
inconsistent view of the world when we're using kvm.
So we need to invalidate the icache every time we write a rom into guest
address space. We do not need to do this for every DMA since the guest
expects it has to flush the icache manually in that case.
@@ -2033,6 +2034,13 @@ void cpu_physical_memory_write_rom(hwaddr addr,
ptr = qemu_get_ram_ptr(addr1);
memcpy(ptr, buf, l);
invalidate_and_set_dirty(addr1, l);
+if (kvm_enabled()) {
+/*
+ * The guest may want to directly execute from the rom
region,
+ * so we better invalidate its icache
+ */
+flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
+}
I bet these aren't the only places where code gets written
to guest memory. Also are you sure flush_icache_range()
works correctly when multiple threads (multiple vCPUs,
potentially executing on different host CPUs) are involved? The
TCG case only needs to care about this thread writes code
to memory that it will itself later execute, not any kind of
cross-host-CPU flushing.
There was a huge thread on kvmarm earlier this year
https://lists.cs.columbia.edu/pipermail/kvmarm/2013-August/006716.html
about a similar sort of issue, and I think the conclusion was that
the kernel basically had to deal with the problem itself [though
the thread is rather confusing...]. I've cc'd Marc Z in the hope
he remembers the ARM specific detail...
thanks
-- PMM
Re: [Qemu-devel] [PATCH v3 0/6] Add error_abort and associated cleanups
Peter Crosthwaite peter.crosthwa...@xilinx.com writes: Following our discussion RE self asserting API calls, here is a spin of my proposal. This series obsoletes the need for _nofail variants for Error ** accepting APIs. Is also greatly reduces the verbosity of calls sites that are currently asserting against errors. Patch 1 is the main event - addition of error_abort. The following patches then cleanup uses of _nofail and assert_no_error(). To give it a smoke test, I introduce a (critical) bug into QOM: [...] Reviewed-by: Markus Armbruster arm...@redhat.com
Re: [Qemu-devel] [PATCH rebased for-1.8] i386: pc: align gpa-hpa on 1GB boundary (v6)
On Tue, Dec 10, 2013 at 11:02:41PM +0200, Michael S. Tsirkin wrote: On Tue, Dec 10, 2013 at 03:21:44PM -0200, Marcelo Tosatti wrote: On Tue, Dec 10, 2013 at 01:05:42PM -0200, Marcelo Tosatti wrote: On Tue, Dec 10, 2013 at 02:18:36PM +0100, Paolo Bonzini wrote: Il 28/11/2013 11:26, Michael S. Tsirkin ha scritto: On Mon, Nov 25, 2013 at 06:43:13PM +0100, Paolo Bonzini wrote: v2: condition enablement of new mapping to new machine types (Paolo) v3: fix changelog v4: rebase v5: ensure alignment of piecetwo on 2MB GPA (Igor) do not register zero-sized piece-one(Igor) v6: fix memory leak (Igor) fix integer overflow(Igor) Align guest physical address and host physical address beyond guest 4GB on a 1GB boundary. Otherwise 1GB TLBs cannot be cached for the range. Signed-off-by: Marcelo Tosatti mtosa...@redhat.com [Reorganize code, keep same logic. - Paolo] Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- Applied, thanks. As discussed offlist, I'm not sure anymore that this is the right approach to the problem. No doubt it is very clever, in that it is absolutely transparent to the guest. However, the non-contiguous mapping of ram_addr_t makes it more complex to associate the right NUMA policy to the ranges. Please explain what is the difference, and why the complexity does not exist with non-contiguous mapping of ram_addr_t. You are right - it forces the 1GB page which contains the hole to be on the same NUMA node as the tail 1GB page - otherwise incorrect NUMA assignment is not possible. What does this phrase mean? Are we all in agreement that we want this patch, in addition to resizing below 4g memory? It means that its necessary to expose that 3-4GB physical memory region in QEMU belongs to the same node (that is, guest must be aware that 3-3.75GB and the tail of RAM are on the same node). So the problem Paolo mentions is fixable.
[Qemu-devel] [PATCH 13/13] mxs/imx23: Adds support for an Olinuxino board
Adds support for creating a basic imx23 dev board from Olimex, with
a few peripherals, a bitbang i2c bus with a RTC attached, a DS18S20
thermal sensor, and a rather crude 'relay' that increases/decreases
the thermal sensor temperature.
Basicaly, it's a complete emulation of the hardware used for my real
life boiler controller system; but it's a nice starting point for
any other imx233 board prototyping.
https://plus.google.com/111387094029238541867/posts/Smwc7yFK3Vk
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/arm/Makefile.objs | 1 +
hw/arm/imx233-olinuxino.c | 169 ++
2 files changed, 170 insertions(+)
create mode 100644 hw/arm/imx233-olinuxino.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 45bbdb8..d2bf180 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -6,3 +6,4 @@ obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o
z2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-y += omap1.o omap2.o strongarm.o
obj-$(CONFIG_MXS) += imx23_digctl.o imx23_pinctrl.o mxs.o
+obj-$(CONFIG_MXS) += imx233-olinuxino.o
diff --git a/hw/arm/imx233-olinuxino.c b/hw/arm/imx233-olinuxino.c
new file mode 100644
index 000..3b1df95
--- /dev/null
+++ b/hw/arm/imx233-olinuxino.c
@@ -0,0 +1,169 @@
+/*
+ * imx233-olinuxino.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ *
+ * Support for a iMX233 development board. You can find reference for the
+ * olinuxino boards on Olimex's website at:
+ * https://www.olimex.com/Products/OLinuXino/iMX233/
+ *
+ * A typical instance of qemu can be created with the following command line:
+./arm-softmmu/qemu-system-arm -M imx233o -m 64M \
+-serial stdio -display none \
+-kernel /opt/minifs/build-imx233/vmlinuz-bare.dtb \
+-monitor telnet::,server,nowait -s \
+-sd /dev/loop0
+The kernel command line can also be specified with -append. However the
default
+one should get a 3.x kernel booting with a working console.
+ */
+
+#include hw/boards.h
+#include hw/arm/mxs.h
+#include hw/arm/arm.h
+#include hw/sysbus.h
+#include hw/i2c/bitbang_i2c.h
+
+
+static struct arm_boot_info imx233o_binfo = {
+/*
+ * theorically, the load address 0 is for the 'bootlets'
+ * however we don't support the bootlets yet, and the
+ * kernel is happy decompressing itself from 0x0 as well
+ * so it's not a big problem to start it from there.
+ */
+.loader_start = 0x0,
+.board_id = 4005, /* from linux's mach-types */
+.is_linux = 1,
+};
+
+enum {
+GPIO_SOFT_I2C_SDA = (0 * 32) + 25, // GPMI_RDN
+GPIO_SOFT_I2C_SCL = (0 * 32) + 23, // GPMI_WPN
+
+GPIO_W1 = (1 * 32) + 21,
+GPIO_HEATER = 51,
+};
+
+typedef struct {
+float temp;
+int on;
+qemu_irq set_temp;
+qemu_irq * in;
+QEMUTimer * timer;
+} GPIOHeater;
+
+static void gpio_heater_set(void *opaque, int irq, int level)
+{
+GPIOHeater *h = opaque;
+h-on = !level;
+printf(QEMU %s %s\n, __func__, h-on ? ON : OFF);
+}
+
+static void gpio_heater_timer(void *opaque)
+{
+GPIOHeater *h = opaque;
+if (h-on)
+h-temp *= 1.001;
+else
+h-temp *= 0.9995;
+if (h-temp 10.0)
+ h-temp = 10.0;
+else if (h-temp 40)
+ h-temp = 40;
+//printf(QEMU %s %s %.2f\n, __func__, h-on ? ON : OFF, h-temp);
+qemu_set_irq(h-set_temp, (int)(h-temp * 1000.0f));
+timer_mod(h-timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
+}
+
+static int
+gpio_heater_init(GPIOHeater *h, qemu_irq set_temp)
+{
+h-set_temp = set_temp;
+h-temp = 13.0f;
+h-on = 0;
+h-in = qemu_allocate_irqs(gpio_heater_set, h, 1);
+h-timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, gpio_heater_timer, h);
+timer_mod(h-timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
+return 0;
+}
+
+GPIOHeater heater;
+
+ARMCPU * imx233_init(struct arm_boot_info * board_info);
+
+static void imx233o_init(QEMUMachineInitArgs *args)
+{
+struct arm_boot_info * board_info = imx233o_binfo;
+ARMCPU *cpu = NULL;
+
+board_info-ram_size = ram_size;
+board_info-kernel_filename = args-kernel_filename;
+board_info-kernel_cmdline =
+args-kernel_cmdline ?
+args-kernel_cmdline :
+console=ttyAMA0,115200 ro root=/dev/mmcblk0p2 ssp1=mmc
loglevel=7;
+board_info-nb_cpus = 1;
+
+cpu = imx233_init(board_info);
+
+/*
+ * Recover the pin controller of the imx23.
+ * NOTE: that the device has to explicitly set it's 'name' for
+ * qdev_find_recursive() to work
+ */
+DeviceState * gpio = qdev_find_recursive(sysbus_get_default(),
imx23_pinctrl);
+/*
+ * Hook up a gpio-i2c bus to the pins that are reserved for that in
+ * the olinuxino .dts file, and add a RTC and an eeprom on it, because
+ * we can.
+ */
+{
+DeviceState * dev =
[Qemu-devel] [PATCH 12/13] mxs/imx23: Main core instantiation and minor IO blocks
This adds support for creating an imx23 instance. This also contains
some of the more minor IO blocks, and a 'catchall' driver that helps
debugging access to undocumented IO registers.
Currently the instance can boot a linux kernel, but does not support
booting from the 'special' signed Freescale binary blobs.
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/arm/Makefile.objs | 2 +-
hw/arm/mxs.c | 388 +++
2 files changed, 389 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/mxs.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index ea53988..45bbdb8 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,4 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o
z2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-y += omap1.o omap2.o strongarm.o
-obj-$(CONFIG_MXS) += imx23_digctl.o imx23_pinctrl.o
+obj-$(CONFIG_MXS) += imx23_digctl.o imx23_pinctrl.o mxs.o
diff --git a/hw/arm/mxs.c b/hw/arm/mxs.c
new file mode 100644
index 000..bee7880
--- /dev/null
+++ b/hw/arm/mxs.c
@@ -0,0 +1,388 @@
+/*
+ * mxs.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+#include hw/sysbus.h
+#include hw/arm/mxs.h
+#include hw/arm/arm.h
+#include target-arm/cpu.h
+#include hw/boards.h
+
+#include exec/address-spaces.h
+
+#define D(w)
+//#define D(w) w
+/*
+ * 0x - 0x7fff On Chip SRAM
+ *- 0x5fff External DRAM
+ * 0x6000 - 0x7fff Default Slave
+ * 0x8000 - 0x800f Peripheral Space (128KB)
+ * 0x8000 0x8000 APBH
+ *
+ * 0x8000 0x2000 icol
+ * 0x80004000 0x2000 DMA
+ * 0x80008000 0x2000 ECC
+ * 0x8000c000 0x2000 GPMI-NAND
+ * 0x8000a000 0x2000 GPMI-NAND
+ * 0x8001 0x2000 SSP0
+ * 0x80014000 0x2000 ETM
+ * 0x80018000 0x2000 pinctrl
+ * 0x8001c000 0x2000 digctl
+ * 0x8002 0x2000 EMI
+ * 0x80024000 0x2000 DMA APBX
+ * 0x80028000 0x2000 DCP
+ * 0x8002a000 0x2000 PXP
+ * 0x8002c000 0x2000 ocotp
+ * 0x8002e000 0x2000 axi-ahb
+ * 0x8003 0x2000 lcdif
+ * 0x80034000 0x2000 SSP1
+ * 0x80038000 0x2000 TVEnc
+ *
+ * 0x8004 0x4 APBX
+ *
+ * 0x8004 0x2000 clkctrl
+ * 0x80042000 0x2000 saif0
+ * 0x80044000 0x2000 power
+ * 0x80046000 0x2000 saif1
+ * 0x80048000 0x2000 audio-out
+ * 0x8004c000 0x2000 audio-in
+ * 0x8005 0x2000 LRADC
+ * 0x80054000 0x2000 SPDIF
+ * 0x80058000 0x2000 i2c
+ * 0x8005c000 0x2000 RTC fsl,imx23-rtc -
fsl,stmp3xxx-rtc
+ * 0x80064000 0x2000 PWM
+ * 0x80068000 0x2000 Timrot
+ * 0x8006c000 0x2000 UART0
+ * 0x8006e000 0x2000 UART1
+ * 0x8007 0x2000 DUART PL011
+ * 0x8007c000 0x2000 USB PHY
+ * 0x8010 - 0xc000 Default Slave
+ * 0xc000 - 0xfffe ROM Alias
+ * 0x - 0x On Chip ROM
+ */
+
+enum {
+HW_CLKCTRL_CPU = 2,
+HW_CLKCTRL_HBUS = 3,
+HW_CLKCTRL_XBUS = 4,
+HW_CLKCTRL_XTAL = 0x5,
+HW_CLKCTRL_PIX = 0x6,
+HW_CLKCTRL_SSP = 0x7,
+HW_CLKCTRL_GPMI = 0x8,
+HW_CLKCTRL_SPDIF = 0x9,
+HW_CLKCTRL_EMI = 0xa,
+HW_CLKCTRL_SAIF = 0xc,
+HW_CLKCTRL_TV = 0xd,
+HW_CLKCTRL_ETM = 0xe,
+HW_CLKCTRL_FRAC = 0xf,
+HW_CLKCTRL_FRAC1 = 0x10,
+HW_CLKCTRL_CLKSEQ = 0x11,
+HW_CLKCTRL_RESET = 0x12,
+HW_CLKCTRL_STATUS = 0x13,
+HW_CLKCTRL_VERSION = 0x14,
+HW_CLKCTRL_MAX
+};
+typedef struct imx23_clkctrl_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+uint32_t r[HW_CLKCTRL_MAX];
+} imx23_clkctrl_state;
+
+static uint64_t imx23_clkctrl_read(
+void *opaque, hwaddr offset, unsigned size)
+{
+imx23_clkctrl_state *s = (imx23_clkctrl_state *) opaque;
+uint32_t res = 0;
+
+switch (offset 4) {
+case 0 ... HW_CLKCTRL_MAX:
+res = s-r[offset 4];
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+break;
+}
+
[Qemu-devel] [PATCH 11/13] mxs/imx23: Add the USB driver
Add the USB IO block, and the USB PHY IO block. This just wraps
an ehci instance, and support some of the 'extra' mxs registers
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/usb/Makefile.objs | 1 +
hw/usb/mxs_usb.c | 254 +++
2 files changed, 255 insertions(+)
create mode 100644 hw/usb/mxs_usb.c
diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index a3eac3e..58d9cf1 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -8,6 +8,7 @@ common-obj-$(CONFIG_USB_OHCI) += hcd-ohci.o
common-obj-$(CONFIG_USB_EHCI) += hcd-ehci.o hcd-ehci-pci.o hcd-ehci-sysbus.o
common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
+common-obj-$(CONFIG_MXS) += mxs_usb.o
# emulated usb devices
common-obj-y += dev-hub.o
diff --git a/hw/usb/mxs_usb.c b/hw/usb/mxs_usb.c
new file mode 100644
index 000..1be5f37
--- /dev/null
+++ b/hw/usb/mxs_usb.c
@@ -0,0 +1,254 @@
+/*
+ * mxs_usb.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+/*
+ * Implements the USB block of the mxs. This is just a case of
+ * instantiating a ehci block, and have a few read only registers
+ * for mxs specific bits
+ */
+#include hw/sysbus.h
+#include hw/arm/mxs.h
+#include hw/usb/hcd-ehci.h
+#include hw/qdev.h
+
+#define D(w)
+
+enum {
+USB_MAX = 256 / 4,
+};
+
+typedef struct mxs_usb_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t r[USB_MAX];
+qemu_irq irq_dma, irq_error;
+
+EHCIState ehci;
+} mxs_usb_state;
+
+static uint64_t mxs_usb_read(
+void *opaque, hwaddr offset, unsigned size)
+{
+mxs_usb_state *s = (mxs_usb_state *) opaque;
+uint32_t res = 0;
+
+D(printf(%s %04x (%d) = , __func__, (int)offset, size);)
+switch (offset 2) {
+case 0 ... USB_MAX:
+res = s-r[offset 2];
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+break;
+}
+D(printf(%08x\n, res);)
+
+return res;
+}
+
+static void mxs_usb_write(void *opaque, hwaddr offset,
+uint64_t value, unsigned size)
+{
+mxs_usb_state *s = (mxs_usb_state *) opaque;
+
+D(printf(%s %04x %08x(%d)\n, __func__, (int)offset, (int)value, size);)
+switch (offset) {
+case 0 ... USB_MAX:
+s-r[offset] = value;
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
+break;
+}
+}
+
+static const MemoryRegionOps mxs_usb_ops = {
+.read = mxs_usb_read,
+.write = mxs_usb_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int mxs_usb_init(SysBusDevice *dev)
+{
+mxs_usb_state *s = OBJECT_CHECK(mxs_usb_state, dev, mxs_usb);
+EHCIState *u = s-ehci;
+
+memory_region_init_io(s-iomem, OBJECT(s), mxs_usb_ops, s,
+mxs_usb, 0x100);
+
+s-r[0] = 0xe241fa05;
+s-r[0x04 2] = 0x0015;
+s-r[0x08 2] = 0x10020001;
+s-r[0x0c 2] = 0x000b;
+s-r[0x10 2] = 0x40060910;
+s-r[0x14 2] = 0x0710;
+
+u-capsbase = 0x100;
+u-opregbase = 0x140;
+// FIXME ?!?!?
+//u-dma = dma_context_memory;
+
+usb_ehci_init(u, DEVICE(dev));
+sysbus_init_irq(dev, u-irq);
+
+memory_region_add_subregion(u-mem, 0x0, s-iomem);
+sysbus_init_mmio(dev, u-mem);
+
+D(printf(%s created bus %s\n, __func__, u-bus.qbus.name);)
+#if 0
+/*
+ * This is suposed to make companion ports that will support
+ * slower speed devices (mouse/keyboard etc). It's inspired
+ * from ehci/pci however it doesn't work, right now...
+ */
+int i;
+for (i = 0; i NB_PORTS; i += 2) {
+DeviceState * d = qdev_create(NULL, sysbus-ohci);
+qdev_prop_set_string(d, masterbus, u-bus.qbus.name);
+qdev_prop_set_uint32(d, firstport, i);
+qdev_prop_set_uint32(d, num-ports, 2);
+qdev_init_nofail(d);
+sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, u-irq);
+}
+#endif
+return 0;
+}
+
+static void mxs_usb_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc-init = mxs_usb_init;
+}
+
+static TypeInfo mxs_usb_info = {
+.name = mxs_usb,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(mxs_usb_state),
+.class_init= mxs_usb_class_init,
+};
+
+static void mxs_usb_register(void)
+{
+type_register_static(mxs_usb_info);
+}
+
+type_init(mxs_usb_register)
+
+#undef D
+#define D(w)
+
+enum {
+USBPHY_PWD = 0x0,
+USBPHY_TX = 0x1,
+USBPHY_RX = 0x2,
+USBPHY_CTRL = 0x3,
+USBPHY_MAX = 10,
+};
+typedef struct mxs_usbphy_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t r[USBPHY_MAX];
+} mxs_usbphy_state;
+
+static uint64_t mxs_usbphy_read(void *opaque, hwaddr offset,
+unsigned size)
+{
+
[Qemu-devel] [PATCH 10/13] mxs/imx23: Add the timers
Support for the timer IO block of the mxs/imx23. Does not support
any of the fancy function, just the 32khz based timers used by
linux.
Signed-off-by: Michel Pollet buser...@gmail.com
---
hw/timer/Makefile.objs | 2 +-
hw/timer/mxs_timrot.c | 271 +
2 files changed, 272 insertions(+), 1 deletion(-)
create mode 100644 hw/timer/mxs_timrot.c
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 1003169..8d2933a 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -26,6 +26,6 @@ obj-$(CONFIG_OMAP) += omap_synctimer.o
obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o
obj-$(CONFIG_SH4) += sh_timer.o
obj-$(CONFIG_TUSB6010) += tusb6010.o
-obj-$(CONFIG_MXS) += mxs_rtc.o
+obj-$(CONFIG_MXS) += mxs_rtc.o mxs_timrot.o
obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
diff --git a/hw/timer/mxs_timrot.c b/hw/timer/mxs_timrot.c
new file mode 100644
index 000..b54c0b1
--- /dev/null
+++ b/hw/timer/mxs_timrot.c
@@ -0,0 +1,271 @@
+/*
+ * mxs_timrot.c
+ *
+ * Copyright: Michel Pollet buser...@gmail.com
+ *
+ * QEMU Licence
+ */
+
+/*
+ * Implements the timer block for the mxs. Currently supports only the
+ * 32khz based clock, and not all the of the options, nor the input counters,
+ * PWM etc etc.
+ * Basically, it supports enough for the linux kernel
+ */
+#include hw/sysbus.h
+#include hw/arm/mxs.h
+#include hw/ptimer.h
+#include qemu/main-loop.h
+
+enum {
+TIMROT_ROTCTRL = 0,
+TIMROT_CTRL0 = 0x2,
+TIMROT_COUNT0 = 0x3,
+TIMROT_CTRL1 = 0x4,
+TIMROT_COUNT1 = 0x5,
+TIMROT_CTRL2 = 0x6,
+TIMROT_COUNT2 = 0x7,
+TIMROT_CTRL3 = 0x8,
+TIMROT_COUNT3 = 0x9,
+TIMROT_VERSION = 0xa,
+};
+
+enum {
+TIM_IRQ = 15,
+TIM_IRQ_EN = 14,
+TIM_UPDATE = 7,
+TIM_RELOAD = 6,
+TIM_PRESCALE = 4,
+TIM_SELECT = 0,
+};
+
+typedef struct mxs_tim_state {
+struct mxs_timrot_state * s;
+uint8_t tid;
+uint8_t fired;
+uint32_t control, count;
+qemu_irq irq;
+ptimer_state * timer;
+} mxs_tim_state;
+
+typedef struct mxs_timrot_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t rotctrl;
+
+mxs_tim_state t[4];
+} mxs_timrot_state;
+
+static void tim_set_count(mxs_tim_state * t, uint32_t count)
+{
+if (count != (t-count 0x) || t-fired) {
+t-count = (t-count ~0x) | (count 0x);
+ptimer_set_limit(t-timer, t-count 0x, 1);
+if (t-count 0x) {
+t-fired = 0;
+ptimer_run(t-timer, t-control (1 TIM_RELOAD) ? 0 : 1);
+}
+}
+}
+
+static void tim_set_control(mxs_tim_state * t, uint16_t control)
+{
+uint32_t change = t-control ^ control;
+if (!change) {
+return;
+}
+
+uint32_t freq = 0;
+switch ((control TIM_SELECT) 0xf) {
+case 0x8:
+freq = 32000;
+break;
+case 0x9:
+freq = 8000;
+break;
+case 0xa:
+freq = 4000;
+break;
+case 0xc:
+freq = 1000;
+break;
+}
+switch ((control TIM_PRESCALE) 0x3) {
+/* TODO */
+}
+if (!(control (1 TIM_IRQ))) {
+qemu_irq_lower(t-irq);
+}
+if (freq == 0) {
+ptimer_stop(t-timer);
+} else if (change 0xff) {
+printf(%s[%d] %04x freq %d\n, __func__, t-tid, control, (int) freq);
+ptimer_set_freq(t-timer, freq);
+ptimer_set_limit(t-timer, t-count 0x, 1);
+if (t-count 0x) {
+t-fired = 0;
+ptimer_run(t-timer, control (1 TIM_RELOAD) ? 0 : 1);
+}
+}
+t-control = control;
+}
+
+static uint32_t tim_get_count(mxs_tim_state * t)
+{
+t-count = 0x;
+t-count |= (ptimer_get_count(t-timer) 16);
+return t-count;
+}
+
+static void mxs_timrot_timer_trigger(void *opaque)
+{
+mxs_tim_state * t = opaque;
+t-fired = 1;
+t-control |= (1 TIM_IRQ);
+if (t-control (1 TIM_IRQ_EN))
+qemu_irq_raise(t-irq);
+}
+
+static inline int tim_get_tid(hwaddr offset)
+{
+return ((offset 4) - TIMROT_CTRL0) 1;
+}
+
+static uint64_t mxs_timrot_read(void *opaque, hwaddr offset,
+unsigned size)
+{
+mxs_timrot_state *s = (mxs_timrot_state *) opaque;
+uint32_t res = 0;
+
+switch (offset 4) {
+case TIMROT_ROTCTRL:
+res = s-rotctrl | (0xf 25);
+break;
+case TIMROT_VERSION:
+res = 0x0101;
+break;
+case TIMROT_CTRL0:
+case TIMROT_CTRL1:
+case TIMROT_CTRL2:
+case TIMROT_CTRL3:
+res = s-t[tim_get_tid(offset)].control;
+break;
+case TIMROT_COUNT0:
+case TIMROT_COUNT1:
+case TIMROT_COUNT2:
+case TIMROT_COUNT3:
+res = tim_get_count(s-t[tim_get_tid(offset)]);
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+%s: bad offset 0x%x\n, __func__, (int) offset);
Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
Il 11/12/2013 14:35, Alexander Graf ha scritto:
+if (kvm_enabled()) {
+/*
+ * The guest may want to directly execute from the rom
region,
+ * so we better invalidate its icache
+ */
+flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
+}
Shouldn't KVM itself do that when a memslot is registered? There should
be no reason for non-TCG QEMU to flush the icache.
How would KVM know when things changed inside of a memory region? It's up to
user space to manage the contents of a memory region, no?
Yeah, that is true. BTW, shouldn't the same happen when you do migration?
I'd prefer the above snippet to be replaced by a function in
kvm-stub.c/kvm-all.c (kvm_flush_icache_range).
I wonder if there would be a reason to add a KVM_FLUSH_ICACHE ioctl
though. Could a virtually-indexed/virtually-tagged icache require
flushing by guest address instead of host address?
Paolo
Re: [Qemu-devel] Qemu on android
noxi...@gmail.com writes: Hi, I'm trying to use the latest version of QEMU (1.7) in user mode in Android 1.7. I tried compiling it, but it seems there is a very hard dependency on glib which is standing in the way. Has anyone tried building qemu 1.7 for android, if so where can I get the information? The hard dependency on glib has been in quite some time (e18df14185e817ba735bce57ecdef9a55fb3d093) so I don't think you can build without it. However it should be possible to build glib for android and bundle it with your qemu if needed. Thanks, Tervel -- Alex Bennée QEMU/KVM Hacker for Linaro
Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
On 11 December 2013 13:35, Alexander Graf ag...@suse.de wrote: How would KVM know when things changed inside of a memory region? It's up to user space to manage the contents of a memory region, no? If the architecture spec says that a freshly reset physical CPU has coherent icache and dcache, then resetting the vCPU should also ensure the icache and dcache are coherent, so one way to solve this would be just to make sure that vcpu reset did the right thing. -- PMM
Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
On 11.12.2013, at 15:07, Peter Maydell peter.mayd...@linaro.org wrote: On 11 December 2013 13:35, Alexander Graf ag...@suse.de wrote: How would KVM know when things changed inside of a memory region? It's up to user space to manage the contents of a memory region, no? If the architecture spec says that a freshly reset physical CPU has coherent icache and dcache, then resetting the vCPU should also ensure the icache and dcache are coherent, so one way to solve this would be just to make sure that vcpu reset did the right thing. Well, this really is a simplified view of the world. On real hardware the system boots up with caches disabled. Firmware is then responsible for enabling caches and flushing things as it goes. Firmware loads the kernel into ram, flushing the icache on those regions it wrote to along the way. The kernel boots and every time it faults in a page, it flushes caches for that page. So really the problem is that we're skipping the cache disabled firmware step. With this patch, we're simulating a bootloader's behavior when writing a blob into guest memory. Since that's really what we are trying to behave like - a bootloader. Alex
Re: [Qemu-devel] [PATCH rebased for-1.8] i386: pc: align gpa-hpa on 1GB boundary (v6)
On Wed, Dec 11, 2013 at 11:41:18AM -0200, Marcelo Tosatti wrote: On Tue, Dec 10, 2013 at 11:02:41PM +0200, Michael S. Tsirkin wrote: On Tue, Dec 10, 2013 at 03:21:44PM -0200, Marcelo Tosatti wrote: On Tue, Dec 10, 2013 at 01:05:42PM -0200, Marcelo Tosatti wrote: On Tue, Dec 10, 2013 at 02:18:36PM +0100, Paolo Bonzini wrote: Il 28/11/2013 11:26, Michael S. Tsirkin ha scritto: On Mon, Nov 25, 2013 at 06:43:13PM +0100, Paolo Bonzini wrote: v2: condition enablement of new mapping to new machine types (Paolo) v3: fix changelog v4: rebase v5: ensure alignment of piecetwo on 2MB GPA (Igor) do not register zero-sized piece-one(Igor) v6: fix memory leak (Igor) fix integer overflow(Igor) Align guest physical address and host physical address beyond guest 4GB on a 1GB boundary. Otherwise 1GB TLBs cannot be cached for the range. Signed-off-by: Marcelo Tosatti mtosa...@redhat.com [Reorganize code, keep same logic. - Paolo] Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- Applied, thanks. As discussed offlist, I'm not sure anymore that this is the right approach to the problem. No doubt it is very clever, in that it is absolutely transparent to the guest. However, the non-contiguous mapping of ram_addr_t makes it more complex to associate the right NUMA policy to the ranges. Please explain what is the difference, and why the complexity does not exist with non-contiguous mapping of ram_addr_t. You are right - it forces the 1GB page which contains the hole to be on the same NUMA node as the tail 1GB page - otherwise incorrect NUMA assignment is not possible. What does this phrase mean? Are we all in agreement that we want this patch, in addition to resizing below 4g memory? It means that its necessary to expose that 3-4GB physical memory region in QEMU belongs to the same node (that is, guest must be aware that 3-3.75GB and the tail of RAM are on the same node). So the problem Paolo mentions is fixable. Okay so Marcelo - do you ack this patch for 2.0? Paolo - do you re-ack this patch for 2.0? Thanks, -- MST
Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
On 11.12.2013, at 15:03, Paolo Bonzini pbonz...@redhat.com wrote:
Il 11/12/2013 14:35, Alexander Graf ha scritto:
+if (kvm_enabled()) {
+/*
+ * The guest may want to directly execute from the rom
region,
+ * so we better invalidate its icache
+ */
+flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
+}
Shouldn't KVM itself do that when a memslot is registered? There should
be no reason for non-TCG QEMU to flush the icache.
How would KVM know when things changed inside of a memory region? It's up to
user space to manage the contents of a memory region, no?
Yeah, that is true. BTW, shouldn't the same happen when you do migration?
Fortunately no, because migration always happens on a clean plate, so the
icache is not populated yet for the regions that the guest's memory get written
to :).
I'd prefer the above snippet to be replaced by a function in
kvm-stub.c/kvm-all.c (kvm_flush_icache_range).
That makes sense.
I wonder if there would be a reason to add a KVM_FLUSH_ICACHE ioctl
though. Could a virtually-indexed/virtually-tagged icache require
flushing by guest address instead of host address?
No PPC platform I care about has vi/vt icache. I don't know if ARM has any -
but I'd prefer to keep this as simple as possible for as long as we can. Newer
POWER chips even just do cache snooping and don't need all this manual cache
synchronization nonsense anymore.
Alex
Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
On 11 December 2013 14:18, mihai.cara...@freescale.com mihai.cara...@freescale.com wrote: From: Peter Maydell [mailto:peter.mayd...@linaro.org] If the architecture spec says that a freshly reset physical CPU has coherent icache and dcache, then resetting the vCPU should also ensure the icache and dcache are coherent, so one way to solve this would be just to make sure that vcpu reset did the right thing. This is not related to reset operation. Freescale e500 core family does not assure the coherency between data and instruction cache. This is an extract from reference manual: 'When a processor modifies any memory location that can contain an instruction, software must ensure that the instruction cache is made consistent with data memory and that the modifications are made visible to the instruction fetching mechanism. This must be done even if the cache is disabled or if the page is marked caching-inhibited.' So it's the loader duty to synchronize the instruction cache. But these are (emulated) ROMs, not an emulated bootloader. They ought to work like actual ROMs: QEMU as the emulator of the system/devices provides the contents of physical address space; KVM as the emulator of the CPU provides a CPU which doesn't start up executing from rubbish in its icache. (This matches how a real physical CPU executes its first instruction by really going out to the ROM, not by looking at its cache.) thanks -- PMM
Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
On 11.12.2013, at 15:25, Peter Maydell peter.mayd...@linaro.org wrote: On 11 December 2013 14:18, mihai.cara...@freescale.com mihai.cara...@freescale.com wrote: From: Peter Maydell [mailto:peter.mayd...@linaro.org] If the architecture spec says that a freshly reset physical CPU has coherent icache and dcache, then resetting the vCPU should also ensure the icache and dcache are coherent, so one way to solve this would be just to make sure that vcpu reset did the right thing. This is not related to reset operation. Freescale e500 core family does not assure the coherency between data and instruction cache. This is an extract from reference manual: 'When a processor modifies any memory location that can contain an instruction, software must ensure that the instruction cache is made consistent with data memory and that the modifications are made visible to the instruction fetching mechanism. This must be done even if the cache is disabled or if the page is marked caching-inhibited.' So it's the loader duty to synchronize the instruction cache. But these are (emulated) ROMs, not an emulated bootloader. They ought to work like actual ROMs: QEMU as the emulator No, they don't. Real ROMs lie in cache inhibited memory and are only copied / shadowed into RAM by firmware. We don't do that with QEMU. of the system/devices provides the contents of physical address space; KVM as the emulator of the CPU provides a CPU which doesn't start up executing from rubbish in its icache. (This matches how a real physical CPU executes its first instruction by really going out to the ROM, not by looking at its cache.) KVM can't even execute from real ROM (MMIO) regions. Alex
Re: [Qemu-devel] KVM call agenda for 2013-12-10
Anthony Liguori anth...@codemonkey.ws writes: On Tue, Dec 10, 2013 at 4:54 AM, Markus Armbruster arm...@redhat.com wrote Paolo Bonzini pbonz...@redhat.com writes: Il 10/12/2013 12:42, Juan Quintela ha scritto: Hi Please, send any topic that you are interested in covering. May not need a phone call, but I'll drop it here: what happened to acknowledgement emails from the patches script? Also, Anthony, it looks like you're still adjusting to the new job. If you need help with anything, I guess today's call could be a good place to discuss it. And someone needs to send out the email saying that 1.7.0 is out and that the next version will be 2.0! Speaking of sending out e-mail: did I miss the promised followup to the key signing party? I need to find the papers from KVM Forum which are somewhere among the stacks of boxes here :-/ Please do, because the longer the delay, the fewer participants will be willing and able to find *their* papers.
Re: [Qemu-devel] [PATCH V4 2/7] block: Allow the user to define node-name option.
Le Monday 09 Dec 2013 à 17:15:26 (+0100), Kevin Wolf a écrit :
Am 05.12.2013 um 18:14 hat Benoît Canet geschrieben:
Signed-off-by: Benoit Canet ben...@irqsave.net
---
block.c | 44 +++-
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/block.c b/block.c
index 4f6b36a..61f5ba0 100644
--- a/block.c
+++ b/block.c
@@ -873,6 +873,7 @@ int bdrv_file_open(BlockDriverState **pbs, const char
*filename,
const char *drvname;
bool allow_protocol_prefix = false;
Error *local_err = NULL;
+const char *node_name = NULL;
int ret;
/* NULL means an empty set of options */
@@ -880,7 +881,15 @@ int bdrv_file_open(BlockDriverState **pbs, const char
*filename,
options = qdict_new();
}
-bs = bdrv_new(, );
+node_name = qdict_get_try_str(options, node-name);
+if (node_name bdrv_find_node(node_name)) {
+error_setg(errp, Duplicate node name);
+QDECREF(options);
+return -EINVAL;
+}
+bs = bdrv_new(, node_name ? node_name : );
+qdict_del(options, node-name);
+
bs-options = options;
options = qdict_clone_shallow(options);
@@ -980,6 +989,7 @@ int bdrv_open_backing_file(BlockDriverState *bs, QDict
*options, Error **errp)
int back_flags, ret;
BlockDriver *back_drv = NULL;
Error *local_err = NULL;
+const char *node_name = NULL;
if (bs-backing_hd != NULL) {
QDECREF(options);
@@ -1002,7 +1012,14 @@ int bdrv_open_backing_file(BlockDriverState *bs,
QDict *options, Error **errp)
sizeof(backing_filename));
}
-bs-backing_hd = bdrv_new(, );
+node_name = qdict_get_try_str(options, node-name);
+if (node_name bdrv_find_node(node_name)) {
+error_setg(errp, Duplicate node name);
+QDECREF(options);
+return -EINVAL;
+}
+bs-backing_hd = bdrv_new(, node_name ? node_name : );
+qdict_del(options, node-name);
if (bs-backing_format[0] != '\0') {
back_drv = bdrv_find_format(bs-backing_format);
@@ -1046,6 +1063,7 @@ int bdrv_open(BlockDriverState *bs, const char
*filename, QDict *options,
BlockDriverState *file = NULL;
QDict *file_options = NULL;
const char *drvname;
+const char *node_name = NULL;
Error *local_err = NULL;
/* NULL means an empty set of options */
@@ -1053,6 +1071,22 @@ int bdrv_open(BlockDriverState *bs, const char
*filename, QDict *options,
options = qdict_new();
}
+node_name = qdict_get_try_str(options, node-name);
+if (node_name bdrv_find_node(node_name)) {
+error_setg(errp, Duplicate node name);
+QDECREF(options);
+return -EINVAL;
+}
+
+if (node_name) {
+pstrcpy(bs-node_name, sizeof(bs-node_name), node_name);
+if (node_name[0] != '\0') {
+QTAILQ_INSERT_TAIL(graph_bdrv_states, bs, node_list);
+}
+}
+
+qdict_del(options, node-name);
We duplicate some code all over the place. In general you seem to be
trying to let the caller of bdrv_new() already figure out what the node
name is by parsing the options QDict; here however, you do it after
bdrv_new().
Can't we consolidate this and only ever set the node name in
bdrv_open_common(), so that the option is parsed only once, there is
only once place adding BDSes to the list, and there is only one place
checking for duplicates?
Nice idea it will make the patches much smaller and cleaner.
Best regards
Benoît
Kevin
Re: [Qemu-devel] [PULL 1/5] linux-headers: Update from v3.13-rc3
On Wed, 2013-12-11 at 12:09 +0100, Greg Kurz wrote:
On Fri, 06 Dec 2013 13:48:25 -0700
Alex Williamson alex.william...@redhat.com wrote:
Update to tag v3.13-rc3 (374b105797c3d4f29c685f3be535c35f5689b30e)
Signed-off-by: Alex Williamson alex.william...@redhat.com
---
linux-headers/asm-arm/kvm.h |3 +
linux-headers/asm-powerpc/epapr_hcalls.h |4 +
linux-headers/asm-powerpc/kvm.h | 86
+- linux-headers/asm-x86/hyperv.h
| 19 +++ linux-headers/asm-x86/kvm.h |6 +-
linux-headers/linux/kvm.h| 11
6 files changed, 119 insertions(+), 10 deletions(-)
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
index c1ee007..c498b60 100644
--- a/linux-headers/asm-arm/kvm.h
+++ b/linux-headers/asm-arm/kvm.h
@@ -63,7 +63,8 @@ struct kvm_regs {
/* Supported Processor Types */
#define KVM_ARM_TARGET_CORTEX_A15 0
-#define KVM_ARM_NUM_TARGETS1
+#define KVM_ARM_TARGET_CORTEX_A7 1
+#define KVM_ARM_NUM_TARGETS2
/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
#define KVM_ARM_DEVICE_TYPE_SHIFT 0
diff --git a/linux-headers/asm-powerpc/epapr_hcalls.h
b/linux-headers/asm-powerpc/epapr_hcalls.h index 33b3f89..06f7247 100644
--- a/linux-headers/asm-powerpc/epapr_hcalls.h
+++ b/linux-headers/asm-powerpc/epapr_hcalls.h
@@ -78,7 +78,7 @@
#define EV_SUCCESS 0
#define EV_EPERM 1 /* Operation not permitted */
#define EV_ENOENT 2 /* Entry Not Found */
-#define EV_EIO 3 /* I/O error occurred */
+#define EV_EIO 3 /* I/O error occured */
#define EV_EAGAIN 4 /* The operation had
insufficient
* resources to complete and
should be
* retried
@@ -89,7 +89,7 @@
#define EV_ENODEV 7 /* No such device */
#define EV_EINVAL 8 /* An argument supplied to the
hcall was out of range or invalid */
-#define EV_INTERNAL9 /* An internal error
occurred */ +#define EV_INTERNAL9 /* An internal
error occured */ #define EV_CONFIG 10 /* A
configuration error was detected */ #define EV_INVALID_STATE
11 /* The object is in an invalid state */ #define
EV_UNIMPLEMENTED12 /* Unimplemented hypercall */ diff
--git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index 0fb1a6e..6836ec7 100644 --- a/linux-headers/asm-powerpc/kvm.h
+++ b/linux-headers/asm-powerpc/kvm.h
@@ -27,6 +27,7 @@
#define __KVM_HAVE_PPC_SMT
#define __KVM_HAVE_IRQCHIP
#define __KVM_HAVE_IRQ_LINE
+#define __KVM_HAVE_GUEST_DEBUG
This define breaks the build on ppc:
kvm-all.o: In function `kvm_update_guest_debug':
kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'
kvm-all.o: In function `kvm_insert_breakpoint':
kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint'
kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint'
kvm-all.o: In function `kvm_remove_breakpoint':
kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint'
kvm-all.o: In function `kvm_remove_all_breakpoints':
kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints'
The ppc support is missing...
This was added by:
commit ce11e48b7fdd256ec68b932a89b397a790566031
Author: Bharat Bhushan r65...@freescale.com
Date: Thu Jul 4 12:27:47 2013 +0530
KVM: PPC: E500: Add userspace debug stub support
Bharat? Alex?
Re: [Qemu-devel] [PATCH rebased for-1.8] i386: pc: align gpa-hpa on 1GB boundary (v6)
Il 11/12/2013 15:20, Michael S. Tsirkin ha scritto: It means that its necessary to expose that 3-4GB physical memory region in QEMU belongs to the same node (that is, guest must be aware that 3-3.75GB and the tail of RAM are on the same node). So the problem Paolo mentions is fixable. I'm not sure if it is fixable. You need a 2M mountpoint to bind the 3G-4G range correctly, a 1G mountpoint for everything else, and QEMU only allows to specify one path. Without Marcelo's patch there is a workaround; if you know the size of the 4G hole and configure the first two nodes with unequal sizes. For example -m 8192 \ -object memory-ram,id=ram-node0,size=3840M,hostnode=0 -numa node,memdev=ram-node0 \ -object memory-ram,id=ram-node1,size=4352M,hostnode=1 -numa node,memdev=ram-node1 RAM addressHost virtual address low bits Guest physical addresses 0M-3840M 0 0M-3840M 3840M-8192M0 4096M-8448M Then you'll waste 1GB of RAM (you'll use 9 hugepages instead of 8), but everything will be aligned. Or you just make your guest 7680M and not waste the memory. But with Marcelo's patch, ram-node1 will be split in two. QEMU will try to realign the second part of ram-node1, but the result is that the second part is misaligned and only the first 256M (the tail of guest physical memory) stays aligned: RAM addressHost virtual address low bits Guest physical addresses 0M-3840M 0 0M-3840M 4096M-8192M256M 4096M-8192M 3840M-4096M0 8192M-8448M So you still waste memory, _and_ get incorrect alignment. Okay so Marcelo - do you ack this patch for 2.0? Paolo - do you re-ack this patch for 2.0? I very much prefer Gerd's approach. 2GB low memory for q35 is a bit wasteful, but we have some time to fix that before release. Paolo
Re: [Qemu-devel] [PULL 1/5] linux-headers: Update from v3.13-rc3
On 11.12.2013, at 15:44, Alex Williamson alex.william...@redhat.com wrote:
On Wed, 2013-12-11 at 12:09 +0100, Greg Kurz wrote:
On Fri, 06 Dec 2013 13:48:25 -0700
Alex Williamson alex.william...@redhat.com wrote:
Update to tag v3.13-rc3 (374b105797c3d4f29c685f3be535c35f5689b30e)
Signed-off-by: Alex Williamson alex.william...@redhat.com
---
linux-headers/asm-arm/kvm.h |3 +
linux-headers/asm-powerpc/epapr_hcalls.h |4 +
linux-headers/asm-powerpc/kvm.h | 86
+- linux-headers/asm-x86/hyperv.h
| 19 +++ linux-headers/asm-x86/kvm.h |6 +-
linux-headers/linux/kvm.h| 11
6 files changed, 119 insertions(+), 10 deletions(-)
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
index c1ee007..c498b60 100644
--- a/linux-headers/asm-arm/kvm.h
+++ b/linux-headers/asm-arm/kvm.h
@@ -63,7 +63,8 @@ struct kvm_regs {
/* Supported Processor Types */
#define KVM_ARM_TARGET_CORTEX_A15 0
-#define KVM_ARM_NUM_TARGETS1
+#define KVM_ARM_TARGET_CORTEX_A7 1
+#define KVM_ARM_NUM_TARGETS2
/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
#define KVM_ARM_DEVICE_TYPE_SHIFT 0
diff --git a/linux-headers/asm-powerpc/epapr_hcalls.h
b/linux-headers/asm-powerpc/epapr_hcalls.h index 33b3f89..06f7247 100644
--- a/linux-headers/asm-powerpc/epapr_hcalls.h
+++ b/linux-headers/asm-powerpc/epapr_hcalls.h
@@ -78,7 +78,7 @@
#define EV_SUCCESS 0
#define EV_EPERM1 /* Operation not permitted */
#define EV_ENOENT 2 /* Entry Not Found */
-#define EV_EIO 3 /* I/O error occurred */
+#define EV_EIO 3 /* I/O error occured */
#define EV_EAGAIN 4 /* The operation had
insufficient
* resources to complete and
should be
* retried
@@ -89,7 +89,7 @@
#define EV_ENODEV 7 /* No such device */
#define EV_EINVAL 8 /* An argument supplied to the
hcall was out of range or invalid */
-#define EV_INTERNAL9 /* An internal error
occurred */ +#define EV_INTERNAL9 /* An internal
error occured */ #define EV_CONFIG 10 /* A
configuration error was detected */ #define EV_INVALID_STATE
11 /* The object is in an invalid state */ #define
EV_UNIMPLEMENTED12 /* Unimplemented hypercall */ diff
--git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index 0fb1a6e..6836ec7 100644 --- a/linux-headers/asm-powerpc/kvm.h
+++ b/linux-headers/asm-powerpc/kvm.h
@@ -27,6 +27,7 @@
#define __KVM_HAVE_PPC_SMT
#define __KVM_HAVE_IRQCHIP
#define __KVM_HAVE_IRQ_LINE
+#define __KVM_HAVE_GUEST_DEBUG
This define breaks the build on ppc:
kvm-all.o: In function `kvm_update_guest_debug':
kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'
kvm-all.o: In function `kvm_insert_breakpoint':
kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint'
kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint'
kvm-all.o: In function `kvm_remove_breakpoint':
kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint'
kvm-all.o: In function `kvm_remove_all_breakpoints':
kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints'
The ppc support is missing...
This was added by:
commit ce11e48b7fdd256ec68b932a89b397a790566031
Author: Bharat Bhushan r65...@freescale.com
Date: Thu Jul 4 12:27:47 2013 +0530
KVM: PPC: E500: Add userspace debug stub support
Bharat? Alex?
The kernel now supports debug registers and I do have patches to make use of
them in my queue. The fact that QEMU expects internal code to provide certain
functions depending on some random #define in a header file is just plain
broken though.
Hence we want an intermediate quick fix to at least get upstream buildable
again and then implement the real deal.
Alex
Re: [Qemu-devel] [RFC PATCH 0/3] Add realize unrealize interfaces for BusState
Bandan Das b...@redhat.com writes: These patches add realize and unrealize interfaces to BusState just like we have for DeviceState. 1/3 and 2/3 implement the interface and attempt to integrate it to the existing DeviceState call path. 3/3 is an example user of the interface, pci in this case. Please see individual patches for more details. Bandan Das (3): qdev: add realize/unrealize interfaces for BusState qdev: Integrate the bus realized property to get called when device realized property changes pci: move vmstate_pcibus registration/unregistration to realize and unrealize interfaces hw/core/qdev.c | 130 - hw/pci/pci.c | 49 +++ include/hw/qdev-core.h | 8 +++ 3 files changed, 153 insertions(+), 34 deletions(-) Ping ? Any comments ?
Re: [Qemu-devel] [PATCH rebased for-1.8] i386: pc: align gpa-hpa on 1GB boundary (v6)
On Wed, Dec 11, 2013 at 03:45:29PM +0100, Paolo Bonzini wrote: Il 11/12/2013 15:20, Michael S. Tsirkin ha scritto: It means that its necessary to expose that 3-4GB physical memory region in QEMU belongs to the same node (that is, guest must be aware that 3-3.75GB and the tail of RAM are on the same node). So the problem Paolo mentions is fixable. I'm not sure if it is fixable. You need a 2M mountpoint to bind the 3G-4G range correctly, a 1G mountpoint for everything else, and QEMU only allows to specify one path. Without Marcelo's patch there is a workaround; if you know the size of the 4G hole and configure the first two nodes with unequal sizes. For example -m 8192 \ -object memory-ram,id=ram-node0,size=3840M,hostnode=0 -numa node,memdev=ram-node0 \ -object memory-ram,id=ram-node1,size=4352M,hostnode=1 -numa node,memdev=ram-node1 RAM addressHost virtual address low bits Guest physical addresses 0M-3840M 0 0M-3840M 3840M-8192M0 4096M-8448M Then you'll waste 1GB of RAM (you'll use 9 hugepages instead of 8), but everything will be aligned. Or you just make your guest 7680M and not waste the memory. But with Marcelo's patch, ram-node1 will be split in two. QEMU will try to realign the second part of ram-node1, but the result is that the second part is misaligned and only the first 256M (the tail of guest physical memory) stays aligned: RAM addressHost virtual address low bits Guest physical addresses 0M-3840M 0 0M-3840M 4096M-8192M256M 4096M-8192M 3840M-4096M0 8192M-8448M So you still waste memory, _and_ get incorrect alignment. Okay so Marcelo - do you ack this patch for 2.0? Paolo - do you re-ack this patch for 2.0? I very much prefer Gerd's approach. Thanks, I will drop this from my tree for now. Please re-submit if you reconsider. 2GB low memory for q35 is a bit wasteful, but we have some time to fix that before release. Paolo How would you fix that? -- MST
