Reviewed-by: Wenchao Xia
On 12/20/2013 10:43 PM, Alexey Kardashevskiy wrote:
> On 12/20/2013 10:29 PM, Andreas Färber wrote:
>> Am 19.12.2013 12:38, schrieb Alexey Kardashevskiy:
>>> On 12/16/2013 08:23 AM, Andreas Färber wrote:
Am 04.12.2013 06:51, schrieb Peter Crosthwaite:
> On Wed, Dec 4, 2013 at 1:42 AM, Paol
Andreas Färber a écrit :
Am 24.12.2013 01:32, schrieb Alexander Graf:
On 23.12.2013, at 22:54, Hervé Poussineau wrote:
Andreas Färber a écrit :
Am 23.12.2013 19:13, schrieb Hervé Poussineau:
Alexander Graf a écrit :
On 23.12.2013, at 07:48, Hervé Poussineau wrote:
Hi,
Andreas Färber a
I am not sure the win32 API usage, except that part, patch looks OK.
On 12/24/2013 03:24 AM, Michael S. Tsirkin wrote:
> On Mon, Dec 23, 2013 at 02:01:13AM +1100, Alexey Kardashevskiy wrote:
>> On 12/23/2013 01:46 AM, Alexey Kardashevskiy wrote:
>>> On 12/22/2013 09:56 PM, Michael S. Tsirkin wrote:
On Sun, Dec 22, 2013 at 02:01:23AM +1100, Alexey Kardashevskiy
On Tue, 2013-12-24 at 03:38 +0100, Andreas Färber wrote:
> Replace growing numbers of inline x86_env_get_cpu() with x86_cpu variable.
>
> Signed-off-by: Andreas Färber
> ---
> cpu-exec.c | 14 ++
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/cpu-exec.c b/cpu-ex
If the surface switch involved a resize, we were doing the redraw
at the old size rather than the new, because the update of
screen.width and screen.height was being done after the setFrame
method calls which triggered a redraw. Normally this isn't very
noticeable because typically after the guest
If our redraw method is called before we have any data from the guest,
then draw a black rectangle rather than leaving the window empty.
This mostly only matters when the guest machine has no framebuffer
device, but it is more in line with the behaviour of other QEMU UIs.
Signed-off-by: Peter Mayd
This patch series fixes a couple of bugs in drawing the display
which are only really visible if you run guests with no graphics
device or which never get round to using the graphics device.
The first is a fix for a bug in the order in which we handled
surface switching which meant that if the sur
Ah, I hadn't tried -nographic. However, my general point still stands:
whether you run this on MacOS or Linux, you get the same behaviour.
Experimenting I see that all that's happening here is that '-nographic'
gives you a serial console, which the ROM outputs to. You can also
specify that with '-
Replace growing numbers of inline x86_env_get_cpu() with x86_cpu variable.
Signed-off-by: Andreas Färber
---
cpu-exec.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 2711c58..f7a215c 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -
On 13 December 2013 20:18, Stefan Weil wrote:
> PS. Does anybody know how to add the QEMU mascot as a Cocoa application
> icon for all QEMU applications?
I have some code which programmatically sets the icon for QEMU
from a file when it runs:
+const char *iconfile = "qemu-icon.bmp";
+con
On Mon, 2013-12-23 at 16:36 +0100, Andreas Färber wrote:
> Am 23.12.2013 10:04, schrieb Chen Fan:
> > This motion is preparing for refactoring vCPU apic subsequently.
> >
> > Signed-off-by: Chen Fan
> > ---
> > cpu-exec.c| 2 +-
> > cpus.c| 5 ++---
> > hw/i
Am 24.12.2013 01:32, schrieb Alexander Graf:
>
> On 23.12.2013, at 22:54, Hervé Poussineau wrote:
>
>> Andreas Färber a écrit :
>>> Am 23.12.2013 19:13, schrieb Hervé Poussineau:
Alexander Graf a écrit :
> On 23.12.2013, at 07:48, Hervé Poussineau wrote:
>
>> Hi,
>>
>>
The DAR and DSISR can be very useful when debugging issues, so add
them to ppc_cpu_dump_state. We had another bug in this area: all
of the v2.06 MMU types were missing.
Signed-off-by: Anton Blanchard
---
Index: b/target-ppc/translate.c
===
On 23.12.2013, at 22:54, Hervé Poussineau wrote:
> Andreas Färber a écrit :
>> Am 23.12.2013 19:13, schrieb Hervé Poussineau:
>>> Alexander Graf a écrit :
On 23.12.2013, at 07:48, Hervé Poussineau wrote:
> Hi,
>
> Andreas Färber a écrit :
>> Hi,
>> Am 05.11.2013
Am 20.12.2013 22:14, schrieb Igor Mammedov:
> Add basic regression testing for QOM Interface usage.
> Test checks casting to interface type/class for following cases:
> - interface implementation in leaf class
> - interface implementation in intermediate (parent) class
>
> Signed-off-by: Igor
Am 20.12.2013 22:54, schrieb Paolo Bonzini:
> The interface type rework had two bugs with interfaces that are inherited
> from a superclass. First of all, the implementation type name was wrong
> (for example it was subclass::superclass::interface rather than
> just subclass::interface). Second,
On Dec 23, 2013, at 3:50 PM, Peter Maydell wrote:
> On 13 December 2013 01:04, Peter Bartoli wrote:
>> Public bug reported:
>>
>>
>> The 32-bit SPARC emulator's TCX emulation seems to work with
>> OpenBIOS, but doesn't work with a SparcStation ROM on Cocoa
>
> This is actually two separate iss
On 13 December 2013 01:04, Peter Bartoli wrote:
> Public bug reported:
>
>
> The 32-bit SPARC emulator's TCX emulation seems to work with
> OpenBIOS, but doesn't work with a SparcStation ROM on Cocoa
This is actually two separate issues.
(1) This SS-5 ROM doesn't boot on QEMU. You can see this i
On 23 December 2013 20:15, Richard Henderson wrote:
> Ping.
I made it through as far as patch 38, but really I think this
series is just way too big to review as a single set. There
doesn't seem to be any particularly significant reason for
it to be a single set either. I'll try to work through t
On 23 December 2013 21:27, Richard Jones wrote:
> It's an Aarch64 binary so it won't run on 32 bit ARM at all. However I
> guess you meant does the equivalent program run on 32 bit ARM, and the
> answer is yes, but that doesn't tell us much because OCaml uses separate
> code generators for 32 and
On 23 December 2013 22:00, Richard W.M. Jones wrote:
> From: "Richard W.M. Jones"
>
> Fixes https://bugs.launchpad.net/qemu/+bug/1263747
>
> Signed-off-by: Richard W.M. Jones
> Tested-by: Richard W.M. Jones
> ---
I'm guessing this is against the SuSE tree? Probably best to
say so specifically,
The attached patch fixes the ret xM variant of ret. I verified that it
fixes the bug.
** Patch added: "0001-arm64-Set-source-for-ret-instruction-correctly.patch"
https://bugs.launchpad.net/qemu/+bug/1263747/+attachment/3934836/+files/0001-arm64-Set-source-for-ret-instruction-correctly.patch
One thing I notice is that caml_c_call is the only function that uses
the instruction "ret xM" (in all other places the code uses the default
"ret" with implicit x30). Hmmm .. do we emulate "ret xM"?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subsc
From: "Richard W.M. Jones"
Fixes https://bugs.launchpad.net/qemu/+bug/1263747
Signed-off-by: Richard W.M. Jones
Tested-by: Richard W.M. Jones
---
target-arm/translate-a64.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 36ebb0f
Andreas Färber a écrit :
Am 23.12.2013 19:13, schrieb Hervé Poussineau:
Alexander Graf a écrit :
On 23.12.2013, at 07:48, Hervé Poussineau wrote:
Hi,
Andreas Färber a écrit :
Hi,
Am 05.11.2013 00:09, schrieb Hervé Poussineau:
Raven datasheet explains where firmware lives in system memory,
Also reproduced with today's git HEAD, after doing
git clone git://git.qemu.org/qemu.git
cd qemu
./configure --target-list=s390x-linux-user --static --disable-system
make clean && make -j4
sudo cp s390x-linux-user/qemu-s390x /usr/bin/qemu-s390x-static
sudo qemu-debootstrap --verbose --components=m
On 12/22/2013 02:50 PM, Peter Maydell wrote:
> From: Will Newton
>
> Use the helpers provided for getting the correct FPSR and FPCR
> values for the signal context.
>
> Signed-off-by: Will Newton
> Signed-off-by: Peter Maydell
> ---
> linux-user/signal.c | 10 +++---
> 1 file changed, 7 i
On 12/22/2013 02:50 PM, Peter Maydell wrote:
> From: Claudio Fontana
>
> The AArch64 linux-user support was written before but merged after
> commit 4ce6243dc621 which cleaned up the handling of the clone()
> syscall argument order, so we failed to notice that AArch64 also needs
> TARGET_CLONE_BA
It's an Aarch64 binary so it won't run on 32 bit ARM at all. However I
guess you meant does the equivalent program run on 32 bit ARM, and the
answer is yes, but that doesn't tell us much because OCaml uses separate
code generators for 32 and 64 bit ARM.
The binary is single threaded.
I enabled t
On 12/22/2013 02:50 PM, Peter Maydell wrote:
> From: Michael Matz
>
> This implement exclusive loads/stores for aarch64 along the lines of
> arm32 and ppc implementations. The exclusive load remembers the address
> and loaded value. The exclusive store throws an an exception which uses
> those va
On 12/22/2013 02:50 PM, Peter Maydell wrote:
> In preparation for adding support for A64 load/store exclusive instructions,
> widen the fields in the CPU state struct that deal with address and data
> values
> for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32
> exclusive
I can confirm, by the way, that the QEMU,tcx.bin replacement does indeed allow
the
On Dec 23, 2013, at 12:05 AM, Mark Cave-Ayland
wrote:
> Thanks for the feedback. Actually it does boot in TCX mode with the
> FCode ROM attached to this bug report - well at least you can boot into
> OBP. If y
On 12/22/2013 02:50 PM, Peter Maydell wrote:
> From: Claudio Fontana
>
> this patch adds support for C3.5.4 - C3.5.5
> Conditional compare (both immediate and register)
>
> Signed-off-by: Claudio Fontana
> Signed-off-by: Peter Maydell
> ---
> target-arm/translate-a64.c | 73
> +++
On 12/22/2013 02:49 PM, Peter Maydell wrote:
> The common pattern for system registers in a 64-bit capable ARM
> CPU is that when in AArch32 the cp15 register is a view of the
> bottom 32 bits of the 64-bit AArch64 system register; writes in
> AArch32 leave the top half unchanged. The most natural
Ping.
r~
On 11/28/2013 06:59 PM, Richard Henderson wrote:
> Changes v1-v2:
> * Rebased on master, with one of the patches already applied to 1.7.
>
>
> r~
>
>
>
> Richard Henderson (60):
> exec: Delay CPU_LOG_TB_CPU until we actually execute a TB
> target-i386: Push DisasContext into l
On 23 December 2013 18:38, Richard Jones wrote:
> This binary:
>
> http://oirase.annexia.org/tmp/test.gz
>
> runs OK on real aarch64 hardware. It is a statically linked Linux
> binary which (if successful) will print "hello, world" and exit cleanly.
>
> On qemu-arm64 userspace emulator it doesn't
On 12/22/2013 02:49 PM, Peter Maydell wrote:
> The cpregs APIs used by the decoder (get_arm_cp_reginfo() and
> cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.
> This is problematic for the A64 decoder, which doesn't pass the
> environment pointer around everywhere the way the 32
Thanks for the fast response, I really appreciate it. I implemented all of
your suggestions and now it all works perfectly!
On Mon, Dec 23, 2013 at 3:02 AM, Peter Maydell wrote:
> On 23 December 2013 03:45, Lauren E Guckert wrote:
> > IN TRANSLATE.C:
> > DISAS_INSN FUNCTION:
> >
> > ++TCGv
Am 23.12.2013 19:13, schrieb Hervé Poussineau:
> Alexander Graf a écrit :
>> On 23.12.2013, at 07:48, Hervé Poussineau wrote:
>>
>>> Hi,
>>>
>>> Andreas Färber a écrit :
Hi,
Am 05.11.2013 00:09, schrieb Hervé Poussineau:
> Raven datasheet explains where firmware lives in system memor
On 12/22/2013 02:49 PM, Peter Maydell wrote:
> define_one_arm_cp_reg_with_opaque() has a set of nested loops which
> insert a cpreg entry into the hashtable for each of the possible
> opc/crn/crm values allowed by wildcard specifications. We're about
> to add an extra loop to this nesting, so pull
On 12/22/2013 02:49 PM, Peter Maydell wrote:
> This patch support the basic load and store pair instructions and
> includes the generic helper functions:
>
> * do_gpr_st()
> * do_fp_st()
> * do_gpr_ld()
> * do_fp_ld()
> * read_cpu_reg_sp()
> * gen_check_sp_alignment()
>
> The last fun
On Tue, Dec 17, 2013 at 01:37:06AM +0100, Laszlo Ersek wrote:
> When qemu dies unexpectedly, for example in response to an explicit
> abort() call, or (more importantly) when an external signal is delivered
> to it that results in a coredump, sometimes it is useful to extract the
> guest vmcore fro
Peter Maydell a écrit :
On 23 December 2013 06:48, Hervé Poussineau wrote:
So, this patch is a small functional change, as it adds a copy of the
firmware in a new range 0xfff0-0xfff7, but I think we can live with
it.
We'll be able to remove it once we switch to another firmware which u
Public bug reported:
Note this is using the not-yet-upstream aarch64 patches from:
https://github.com/susematz/qemu/tree/aarch64-1.6
This binary:
http://oirase.annexia.org/tmp/test.gz
runs OK on real aarch64 hardware. It is a statically linked Linux
binary which (if successful) wil
On 23 December 2013 06:48, Hervé Poussineau wrote:
> So, this patch is a small functional change, as it adds a copy of the
> firmware in a new range 0xfff0-0xfff7, but I think we can live with
> it.
>
> We'll be able to remove it once we switch to another firmware which uses the
> right re
Alexander Graf a écrit :
On 23.12.2013, at 07:48, Hervé Poussineau wrote:
Hi,
Andreas Färber a écrit :
Hi,
Am 05.11.2013 00:09, schrieb Hervé Poussineau:
Raven datasheet explains where firmware lives in system memory, so do
it there instead of in board code. Other boards using the same PCI
On 23.12.2013, at 19:08, Andreas Färber wrote:
> Am 20.12.2013 02:00, schrieb Alexander Graf:
>> Tom Musta (19):
>> Declare and Enable VSX
>> Add MSR VSX and Associated Exception
>> Add VSX Instruction Decoders
>> Add VSR to Global Registers
>> Add lxvd2x
>> Add stx
Am 20.12.2013 02:00, schrieb Alexander Graf:
> Tom Musta (19):
> Declare and Enable VSX
> Add MSR VSX and Associated Exception
> Add VSX Instruction Decoders
> Add VSR to Global Registers
> Add lxvd2x
> Add stxvd2x
> Add xxpermdi
> Add lxsdx
> A
Am 23.12.2013 16:40, schrieb Aneesh Kumar K.V:
> From: "Aneesh Kumar K.V"
>
> Targets like ppc64 support different typed of KVM, one which use
"types" - Alex, please fix. :)
> hypervisor mode and the other which doesn't. Add a new machine
> property kvm-type that helps in selecting the respecti
The 1.7.4 version of SeaBIOS has now been released. For more
information on the release, please see:
http://seabios.org/Releases
New in this release:
* Support for obtaining ACPI tables directly from QEMU.
* Initial support for XHCI USB controllers (initially for QEMU only).
* Support for boot
From: "Aneesh Kumar K.V"
With kvm enabled, we store the hash page table information in the hypervisor.
Use ioctl to read the htab contents. Without this we get the below error when
trying to read the guest address
(gdb) x/10 do_fork
0xc0098660 : Cannot access memory at address
0xc00
From: "Aneesh Kumar K.V"
We will use this in later patches to make sure we use the right load
functions when copying hpte entries.
Signed-off-by: Aneesh Kumar K.V
---
hw/ppc/spapr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e99a66170661..3
From: "Aneesh Kumar K.V"
Correctly update the htab_mask using the return value of
KVM_PPC_ALLOCATE_HTAB ioctl. Also we don't update sdr1
on GET_SREGS for HV. So don't update htab_mask if sdr1
is found to be zero. Fix the pte index calculation to be
same as that found in the kernel
Signed-off-by:
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Signed-off-by: Michael S. Tsirkin
---
hw/i386/acpi-dsdt-cpu-hotplug.dsl | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl
b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
index c96ac42..995b415 100644
--- a/hw/i386/acpi-ds
On 23.12.2013, at 16:40, Aneesh Kumar K.V
wrote:
> From: "Aneesh Kumar K.V"
>
> Targets like ppc64 support different typed of KVM, one which use
> hypervisor mode and the other which doesn't. Add a new machine
> property kvm-type that helps in selecting the respective ones
> We also add a new
On 8 December 2013 22:59, Peter Maydell wrote:
> This patchset is a collection of minor Cocoa UI patches:
> * the 'pass command key through when mousegrabbed' patch I sent
>earlier (included here for convenience since the others in
>the series would otherwise trivially conflict)
> * typo
On Mon, Dec 23, 2013 at 05:24:30PM +0100, Igor Mammedov wrote:
> On Mon, 23 Dec 2013 16:48:49 +0200
> "Michael S. Tsirkin" wrote:
>
> > On Mon, Dec 23, 2013 at 02:06:27PM +0100, Igor Mammedov wrote:
> > > On Mon, 23 Dec 2013 13:26:37 +0200
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On Sun,
On 12/23/13 17:24, Igor Mammedov wrote:
> On Mon, 23 Dec 2013 16:48:49 +0200
> "Michael S. Tsirkin" wrote:
>
>> On Mon, Dec 23, 2013 at 02:06:27PM +0100, Igor Mammedov wrote:
>>> On Mon, 23 Dec 2013 13:26:37 +0200
>>> "Michael S. Tsirkin" wrote:
Interesting. This seems to imply that it can
On Fri, Dec 20, 2013 at 03:10:37PM +0100, Mian M. Hamayun wrote:
> From: Antonios Motakis
>
> Add structures for passing vhost-user messages over a unix domain socket.
> This is the equivalent to the existing vhost-kernel ioctls.
>
> Connect to the named unix domain socket. The system call sendm
On Mon, 23 Dec 2013 16:48:49 +0200
"Michael S. Tsirkin" wrote:
> On Mon, Dec 23, 2013 at 02:06:27PM +0100, Igor Mammedov wrote:
> > On Mon, 23 Dec 2013 13:26:37 +0200
> > "Michael S. Tsirkin" wrote:
> >
> > > On Sun, Dec 22, 2013 at 03:51:28PM +0100, Igor Mammedov wrote:
> > > > On Mon, 16 Dec
On Mon, Dec 23, 2013 at 02:01:13AM +1100, Alexey Kardashevskiy wrote:
> On 12/23/2013 01:46 AM, Alexey Kardashevskiy wrote:
> > On 12/22/2013 09:56 PM, Michael S. Tsirkin wrote:
> >> On Sun, Dec 22, 2013 at 02:01:23AM +1100, Alexey Kardashevskiy wrote:
> >>> Hi!
> >>>
> >>> I am having a problem wi
From: Igor Mammedov
it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.
Signed-off-by: Igor Mammedov
Signed-off-by: Michael S. Tsirkin
---
hw/acpi/ich9.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich
From: Laszlo Ersek
The blob is 64K in size and contains 0x00..0xFF repeatedly.
The client code added to main() wouldn't make much sense in the long term.
It helps with debugging and it silences gcc about create_blob_file() being
unused, and we'll replace it in the next patch anyway.
Signed-off-
From: Paolo Bonzini
This got lost in a rebase.
Reported-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
Signed-off-by: Michael S. Tsirkin
---
hw/virtio/virtio.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 144b9ca..a001e66 100644
--- a/
From: Igor Mammedov
Fix bogus CPU hotplug GPE handler.
Make Q35 CPU hotplug GPE handler match PIIX4 one, since
CPU hotplug event is triggered by GPE0.2 register.
Signed-off-by: Igor Mammedov
Signed-off-by: Michael S. Tsirkin
---
hw/i386/q35-acpi-dsdt.dsl | 4 ++--
1 file changed, 2 insertions
From: Paolo Bonzini
Resetting should be done in post-order, not pre-order. However,
qdev_walk_children and qbus_walk_children do not allow this. Fix
it by adding two extra arguments to the functions.
Signed-off-by: Paolo Bonzini
Signed-off-by: Michael S. Tsirkin
---
include/hw/qdev-core.h |
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under gcc 4.8.2:
CCaarch64-s
From: Igor Mammedov
Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized
with all bits cleared and only QEMU itself can set bits there (i.e.
guest can only clear bits in it). So guest can't triger SCI
by setting _STS & _EN bits and there is not reason to mask out not
supported _STS
From: Paolo Bonzini
pci_device_reset will deassert the INTX pins, and this will make the
irq_count array all-zeroes. Check that this is the case, and remove
the existing loop which might even unsync irq_count and irq_state.
Signed-off-by: Paolo Bonzini
Signed-off-by: Michael S. Tsirkin
---
h
From: Laszlo Ersek
Similarly to commit 1d9358e6
("libqtest: New qtest_end() to go with qtest_start()").
Signed-off-by: Laszlo Ersek
Signed-off-by: Michael S. Tsirkin
---
tests/i440fx-test.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/tests/i440fx-test.c b/te
From: Laszlo Ersek
The current two GTest cases, /i440fx/defaults and /i440fx/pam can share a
qemu process, but the next two cases will need dedicated instances. It is
messy (and order-dependent) to dynamically configure GTest cases one by
one to start, stop, or keep the current qtest (*); let's j
From: Gerd Hoffmann
Make the 32bit pci hole start at end of ram, so all possible address
space is covered.
We used to try and make addresses aligned so they are easier to cover
with MTRRs, but since they are cosmetic on KVM, this is probably not
worth worrying about.
Of course the firmware can u
From: Paolo Bonzini
qbus_reset_all can be used instead. There is no semantic change
because pcibus_reset returns 1 and takes care of the device
tree traversal.
Signed-off-by: Paolo Bonzini
Signed-off-by: Michael S. Tsirkin
---
include/hw/pci/pci.h | 1 -
hw/pci/pci.c | 8 ++--
hw
From: Laszlo Ersek
This patch allows the user to usefully specify
-drive file=img_1,if=pflash,format=raw,readonly \
-drive file=img_2,if=pflash,format=raw
on the command line. The flash images will be mapped under 4G in their
reverse unit order -- that is, with their base addresses progress
From: Gerd Hoffmann
Map 3G (i440fx) of memory below 4G, so the RAM pieces
are nicely aligned to gigabyte borders.
Keep old memory layout for (a) old machine types and (b) in case all
memory fits below 4G and thus we don't have to split RAM into pieces
in the first place. The later makes sure th
From: Paolo Bonzini
Post-order is the only sensible direction for the reset signals.
For example, suppose pre-order is used and the parent has some data
structures that cache children state (for example a list of active
requests). When the reset method is invoked on the parent, these caches
coul
From: Igor Mammedov
... and rename it into acpi_update_sci() since it changes
SCI on only on PM registers status.
Signed-off-by: Igor Mammedov
Signed-off-by: Michael S. Tsirkin
---
include/hw/acpi/acpi.h | 8
hw/acpi/core.c | 18 ++
hw/acpi/ich9.c | 2
Document the logic behind the below/above 4G split.
Signed-off-by: Michael S. Tsirkin
---
hw/i386/pc_piix.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index acb9445..832e20c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -61,
From: Laszlo Ersek
Check whether the firmware is not hidden by other memory regions.
Qemu is started in paused mode: it shouldn't try to interpret generated
garbage.
Signed-off-by: Laszlo Ersek
Signed-off-by: Michael S. Tsirkin
---
tests/i440fx-test.c | 81 +++
The following changes since commit f976b09ea2493fd41c98aaf6512908db0bae:
PPC: Fix compilation with TCG debug (2013-12-22 19:15:55 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_anthony
for you to fetch changes up to 5bf58abf1cb
Alexander Graf writes:
> On Dec 20, 2013, at 11:55 AM, Alexander Graf wrote:
>
>>
>> On 19.12.2013, at 17:04, Aneesh Kumar K.V
>> wrote:
>>
>>> From: "Aneesh Kumar K.V"
>>>
>>> Targets like ppc64 support different typed of KVM, one which use
>>> hypervisor mode and the other which doesn't.
From: "Aneesh Kumar K.V"
Targets like ppc64 support different typed of KVM, one which use
hypervisor mode and the other which doesn't. Add a new machine
property kvm-type that helps in selecting the respective ones
We also add a new QEMUMachine callback get_vm_type that helps
in mapping the strin
Am 23.12.2013 10:04, schrieb Chen Fan:
> This motion is preparing for refactoring vCPU apic subsequently.
>
> Signed-off-by: Chen Fan
> ---
> cpu-exec.c| 2 +-
> cpus.c| 5 ++---
> hw/i386/kvmvapic.c| 8 +++-
> hw/i386/pc.c | 17 +++
On Mon, Dec 23, 2013 at 02:22:38PM +0200, Marcel Apfelbaum wrote:
> On Mon, 2013-12-23 at 14:06 +0200, Michael S. Tsirkin wrote:
> > On Mon, Dec 23, 2013 at 12:13:26PM +0200, Marcel Apfelbaum wrote:
> > > This test will run only if iasl is installed on the host machine.
> > > The test plan:
> > >
On 23 December 2013 14:52, Michael S. Tsirkin wrote:
> commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
> "target-arm: A64: add set_pc cpu method"
>
> introduces an array aarch64_cpus which is zero
> size if this code is built without CONFIG_USER_ONLY.
> In particular an attempt to iterate over
On Mon, Dec 23, 2013 at 02:18:47PM +0200, Marcel Apfelbaum wrote:
> On Mon, 2013-12-23 at 14:02 +0200, Michael S. Tsirkin wrote:
> > On Mon, Dec 23, 2013 at 12:13:23PM +0200, Marcel Apfelbaum wrote:
> > > The test:
> > > - runs only if iasl is installed on the host machine.
> > > - the test plan:
Am 23.12.2013 15:52, schrieb Michael S. Tsirkin:
> commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
> "target-arm: A64: add set_pc cpu method"
>
> introduces an array aarch64_cpus which is zero
> size if this code is built without CONFIG_USER_ONLY.
> In particular an attempt to iterate over this
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under gcc 4.8.2:
CCaarch64-s
On Mon, Dec 23, 2013 at 02:06:27PM +0100, Igor Mammedov wrote:
> On Mon, 23 Dec 2013 13:26:37 +0200
> "Michael S. Tsirkin" wrote:
>
> > On Sun, Dec 22, 2013 at 03:51:28PM +0100, Igor Mammedov wrote:
> > > On Mon, 16 Dec 2013 21:53:07 +0200
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On Fri,
Am 22.12.2013 19:04, schrieb Aurelien Jarno:
> On Sat, Dec 07, 2013 at 10:44:51AM +1300, Richard Henderson wrote:
>> The size of tlb_table is 4k on a 64-bit host. For overwriting
>> memory at this size, cacheline tricks can help.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> cputlb.c | 19 ++-
On 23 December 2013 14:24, Michael S. Tsirkin wrote:
> Changes from v1:
> added a TODO so we remember why the extra line is here.
>
> target-arm/cpu64.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index 04ce879..a9d6939 100644
> ---
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under gcc 4.8.2:
CCaarch64-s
On 23 December 2013 14:15, Michael S. Tsirkin wrote:
> OK, ack my patch then? I'll add a comment
> /* TODO: remove when we support more CPUs. */
Post an updated patch (with TODO comments in both
places) and I'll ack it.
thanks
-- PMM
On Mon, Dec 23, 2013 at 12:37:41PM +, Peter Maydell wrote:
> On 23 December 2013 11:56, Michael S. Tsirkin wrote:
> > commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
> > "target-arm: A64: add set_pc cpu method"
> >
> > introduces an array aarch64_cpus which is zero
> > size if this code is
On Mon, Dec 23, 2013 at 01:41:50PM +, Peter Maydell wrote:
> On 23 December 2013 13:32, Stefan Weil wrote:
> > Am 23.12.2013 13:59, schrieb Peter Maydell:
> >> On 23 December 2013 12:50, Paolo Bonzini wrote:
> >>> Il 23/12/2013 13:37, Peter Maydell ha scritto:
> At a minimum, if we take
On 23 December 2013 13:45, Andreas Färber wrote:
> While I share your sentiment wrt this workaround, what's the status of
> getting a real 64-bit CPU applied? Isn't the Cortex-A57/A53 CPU
> independent of whether we have all MPCore etc. pieces in place? That
> would seem the most elegant solution
On Dec 20, 2013, at 11:55 AM, Alexander Graf wrote:
>
> On 19.12.2013, at 17:04, Aneesh Kumar K.V
> wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> Targets like ppc64 support different typed of KVM, one which use
>> hypervisor mode and the other which doesn't. Add a new machine
>> property kvm-
Am 23.12.2013 13:37, schrieb Peter Maydell:
> On 23 December 2013 11:56, Michael S. Tsirkin wrote:
>> commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
>> "target-arm: A64: add set_pc cpu method"
>>
>> introduces an array aarch64_cpus which is zero
>> size if this code is built without CONFIG_US
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