Stefan, do you know if this patch was applied?
Thanks
On Tue, Mar 31, 2015 at 8:16 PM, Emil Condrea emilcond...@gmail.com wrote:
Thanks, Stefan.
On Mon, Mar 30, 2015 at 4:01 PM, Stefan Hajnoczi stefa...@redhat.com
wrote:
On Sat, Mar 28, 2015 at 06:22:11PM +0200, Emil Condrea wrote:
This
On Sun, Jul 05, 2015 at 09:28:28AM +1000, Benjamin Herrenschmidt wrote:
Under some circumstances, pci_intx() can return -1 (when the interrupt
pin in the config space is 0 which normally means no interrupt).
I have seen cases of pci_set_irq() being called on such devices, in
turn causing
On Sun, 2015-07-05 at 09:03 +0200, Michael S. Tsirkin wrote:
On Sun, Jul 05, 2015 at 09:28:28AM +1000, Benjamin Herrenschmidt wrote:
Under some circumstances, pci_intx() can return -1 (when the interrupt
pin in the config space is 0 which normally means no interrupt).
I have seen cases
On Fri, Jul 03, 2015 at 03:50:19PM +0200, Paolo Bonzini wrote:
On 03/07/2015 15:08, Don Slutz wrote:
Creating it at the pc level and propagating makes code
messy but I'd go along with it if it made sense from
user's point of view, but it does not seem to make sense:
to me this looks
On systems with guest visible IOMMU, adding a new memory region onto
PCI bus calls vfio_listener_region_add() for every DMA window. This
installs a notifier for IOMMU memory regions. The notifier is supposed
to be removed vfio_listener_region_del(), however in the case of mixed
PHB (emulated +
On Sun, Jul 05, 2015 at 09:36:38AM +1000, Benjamin Herrenschmidt wrote:
On Thu, 2015-07-02 at 15:53 +1000, David Gibson wrote:
default-configs/ppc64-softmmu.mak | 2 +-
Note: My native POWER8 work will need ISA back here, so maybe don't
remove it ?
So far this series doesn't remove
Hello guys,
Once qemu has been successfully built, where can I find the runtime
dependencies?
I cannot find any qemu.spec file; maybe there's a way to generate it
--
*Jean-Christophe Manciot*
* [image: Architecte réseaux et Sécurité]
It's possible to set system time with dates after 2070, however, it's
not possible to set the RTC. It has limitation to up to year
2070 (1970+100). In order to keep both clock in sync and before the
kernel complains on invalid values, bail out early.
Signed-off-by: Marc-André Lureau
On Tue, Jun 30, 2015 at 09:20:40PM -0400, John Snow wrote:
The 2.88 drive is more suitable as a default because
it can still read 1.44 images correctly, but the reverse
is not true.
Since there exist virtio-win drivers that are shipped on
2.88 floppy images, this patch will allow VMs booted
Hello, this is V2 of arm_mptimer patch series. Comments and suggestion from V1
has been addressed and the series was re-tested, including new test for IT bit
masking/unmasking.
[PATCH 1/2] arm_mptimer: Fix timer shutdown and mode change
[PATCH v2 2/2] arm_mptimer: Respect IT bit state
Timer, running in periodic mode, can't be stopped or coming one-shot
tick won't be canceled because timer control code just doesn't handle
timer disabling. Fix it by deleting the timer if enable bit isn't set.
Timer won't start periodic ticking if ONE-SHOT - PERIODIC mode change
happened after
Timer should fire interrupt only if IT(interrupt enable) bit state of control
register is enabled and timer should update IRQ status on IT bit change as it
would mask/unmask the interrupt line.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
---
v2: Added missed IRQ status update on control
On 3 July 2015 at 21:47, Eduardo Habkost ehabk...@redhat.com wrote:
The following changes since commit 35360642d043c2a5366e8a04a10e5545e7353bd5:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20150703-1'
into staging (2015-07-03 12:05:31 +0100)
are available in the git
On Sun, Jul 5, 2015 at 8:39 AM, Dmitry Osipenko dig...@gmail.com wrote:
Timer, running in periodic mode, can't be stopped or coming one-shot
tick won't be canceled because timer control code just doesn't handle
timer disabling. Fix it by deleting the timer if enable bit isn't set.
Timer won't
05.07.2015 22:07, Peter Crosthwaite пишет:
-if (((old 1) == 0) (value 1)) {
-if (tb-count == 0 (tb-control 2)) {
+if (value 1) {
+if ((old 1) (tb-count != 0)) {
+/* Do nothing if timer is ticking right now. */
+
05.07.2015 22:52, Peter Crosthwaite пишет:
This series doesn't show up in the patch tracking system due to irregular cover.
BTW, doesn't QEMU use patchwork for tracking? I see both patches there.
--
Dmitry
Ping!
If this or orphaned, I'd like to send the PULL on the H-freeze.
Regards,
Peter
On Tue, Jun 23, 2015 at 8:57 PM, Peter Crosthwaite
crosthwaitepe...@gmail.com wrote:
These two functions are mostly trying to do the same thing, which is
disassemble a target instruction (sequence) for
On Sun, Jul 5, 2015 at 8:39 AM, Dmitry Osipenko dig...@gmail.com wrote:
Timer, running in periodic mode, can't be stopped or coming one-shot
tick won't be canceled because timer control code just doesn't handle
timer disabling. Fix it by deleting the timer if enable bit isn't set.
You don't
On Sun, Jul 5, 2015 at 8:39 AM, Dmitry Osipenko dig...@gmail.com wrote:
Timer should fire interrupt only if IT(interrupt enable) bit state of control
register is enabled and timer should update IRQ status on IT bit change as it
would mask/unmask the interrupt line.
Signed-off-by: Dmitry
It does not work in multi-arch as it requires the CPU specific
TARGET_VIRT_ADDR_SPACE_BITS global define. Just use the generic
version that does no masking. Targets should be responsible for
passing in a sane virtual address.
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
On 4 July 2015 at 07:06, John Snow js...@redhat.com wrote:
The following changes since commit 35360642d043c2a5366e8a04a10e5545e7353bd5:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20150703-1'
into staging (2015-07-03 12:05:31 +0100)
are available in the git repository at:
On Sun, Jul 5, 2015 at 1:58 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko dig...@gmail.com wrote:
05.07.2015 23:26, Peter Crosthwaite пишет:
Hi Dmitry,
Based on my comment earlier, this is what I came up with RE consolidation
of
There was a complicated subtractive arithmetic for determining the
padding on the CPUTLBEntry structure. Simplify this with a union.
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
include/exec/cpu-defs.h | 23 ---
1 file changed, 12 insertions(+), 11
It probably needs a quirk like this to avoid bus resets:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/pci/quirks.c?id=c3e59ee4e76686b0c84ca8faa1011d10cd4ca1b8
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed
On 3 July 2015 at 21:50, Eduardo Habkost ehabk...@redhat.com wrote:
The following changes since commit 35360642d043c2a5366e8a04a10e5545e7353bd5:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20150703-1'
into staging (2015-07-03 12:05:31 +0100)
are available in the git
On Sun, Jul 5, 2015 at 8:39 AM, Dmitry Osipenko dig...@gmail.com wrote:
Hello, this is V2 of arm_mptimer patch series. Comments and suggestion from V1
has been addressed and the series was re-tested, including new test for IT bit
masking/unmasking.
[PATCH 1/2] arm_mptimer: Fix timer shutdown
05.07.2015 22:52, Peter Crosthwaite пишет:
On Sun, Jul 5, 2015 at 8:39 AM, Dmitry Osipenko dig...@gmail.com wrote:
Hello, this is V2 of arm_mptimer patch series. Comments and suggestion from V1
has been addressed and the series was re-tested, including new test for IT bit
masking/unmasking.
Factor out the code that calculates the runtime value of the timer.
Updates tb-count to the calculated value. Prepares support for pausing
the timer where the timer disable event should sync the counter to its
current value.
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
Hi Dmitry,
Based on my comment earlier, this is what I came up with RE consolidation of
those arm_mptimer code paths that were giving you problems. I have not done the
interrupt mask fix, as that one from your series is reasonably independent.
Regards,
Peter
Peter Crosthwaite (2):
timer:
Writing to any of the load, counter or control registers can require a
reload of the timer. Currently load and counter share a code path, but
the control logic is separate. Consolidate them by reducing the switch
to only sync the timer state. For load/counter this just means setting
tb-count to
On Sun, Jul 5, 2015 at 6:06 AM, jean-christophe Manciot
manciot.jeanchristo...@gmail.com wrote:
Hello guys,
Once qemu has been successfully built, where can I find the runtime
dependencies?
I cannot find any qemu.spec file; maybe there's a way to generate it
Not sure about spec files,
On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko dig...@gmail.com wrote:
05.07.2015 23:26, Peter Crosthwaite пишет:
Hi Dmitry,
Based on my comment earlier, this is what I came up with RE consolidation
of
those arm_mptimer code paths that were giving you problems. I have not
done the
IOW, add a line like this below the line added by the above patch:
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c,
quirk_no_bus_reset);
Double check that vendor:device ID against 'lspci -nn', that's
168c:003c.
--
You received this bug notification because you are a member of qemu-
05.07.2015 23:26, Peter Crosthwaite пишет:
Hi Dmitry,
Based on my comment earlier, this is what I came up with RE consolidation of
those arm_mptimer code paths that were giving you problems. I have not done the
interrupt mask fix, as that one from your series is reasonably independent.
Public bug reported:
CPU: Intel(R) Xeon(R) CPU E3-1265L v3 @ 2.50GHz
KVM: qemu-kvm-1.5.3-86.el7_1.2.x86_64
Kernel: 4.1.1-1.el7.elrepo.x86_64, and kernel-3.10.0-229.7.2.el7.x86_64
Host Guest: CentOS 7.1
Using virt-manager-1.1.0-12.el7.noarch to create, configure, and start guest
I am trying
On 5 July 2015 at 22:01, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
On Sun, Jul 5, 2015 at 1:58 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko dig...@gmail.com wrote:
Hi Peter, thanks a lot! Generally, I don't have any
On Sun, Jul 5, 2015 at 2:06 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 5 July 2015 at 22:01, Peter Crosthwaite peter.crosthwa...@xilinx.com
wrote:
On Sun, Jul 5, 2015 at 1:58 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko
06.07.2015 00:06, Peter Maydell пишет:
On 5 July 2015 at 22:01, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
On Sun, Jul 5, 2015 at 1:58 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko dig...@gmail.com wrote:
Hi Peter, thanks
06.07.2015 00:19, Peter Crosthwaite пишет:
On Sun, Jul 5, 2015 at 8:39 AM, Dmitry Osipenko dig...@gmail.com wrote:
Timer, running in periodic mode, can't be stopped or coming one-shot
tick won't be canceled because timer control code just doesn't handle
timer disabling. Fix it by deleting the
On Wed, Jul 1, 2015 at 3:02 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
@@ -153,5 +153,6 @@ void cpu_mips_clock_init (CPUMIPSState *env)
*/
if (!kvm_enabled()) {
env-timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mips_timer_cb,
On Wed, Jul 1, 2015 at 3:11 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/cputimer.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
Move constructor to DeviceClass methods
* imx_serial_init
* imx_serial_realize
imx32_serial_properties is renamed to imx_serial_properties.
The Qdev construction helper is moved to an include file as an
inline function. This function is going to be removed soon.
Signed-off-by: Jean-Christophe
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
On Thu, Jul 2, 2015 at 12:52 AM, Antony Pavlov antonynpav...@gmail.com wrote:
On Tue, 30 Jun 2015 21:12:31 -0700
Serge Vakulenko serge.vakule...@gmail.com wrote:
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/cputimer.c | 18 +-
1 file changed, 5
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* Added a ds1338 I2C device for qtest purpose.
Changes since v2:
* none
Changes since v3:
* Rework GPL header
* use I2C constructor helper.
Changes since v4:
* use
This is using a ds1338 RTC chip on the I2C bus. This RTC chip is
not present on the real 3DS PDK board.
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* use a common header file for I2C regs definition
Changes
This is based on mcf_fec.c FEC implementation for Coldfire
* A generic PHY was added (borrowwed from LAN9118)
* The buffer management is also modified as buffers are
slightly different between Coldfire and i.MX
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
On 07/04/2015 11:12 AM, Alexey Kardashevskiy wrote:
On 05/27/2015 05:05 PM, Paolo Bonzini wrote:
On 27/05/2015 01:55, Alexey Kardashevskiy wrote:
One step back :) Whole dance is what here? There are:
1) del+set_size(0)
2) set_size(not zero)+add
Then no need for begin/commit. :)
I got a
The running timer can't be stopped because timer control code just
doesn't handle disabling the timer. Fix it by deleting the timer if
the enable bit is cleared.
The timer won't start periodic ticking if a ONE-SHOT - PERIODIC mode
change happens after a one-shot tick was completed. Fix it by
The timer should fire interrupt only if IT(interrupt enable) bit state of
control register is enabled and the timer should update IRQ status on IT
bit change as it would mask/unmask the interrupt line.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Reviewed-by: Peter Crosthwaite
Hello, this is V3 of arm_mptimer patch series. No code changes here, just
grammar fixes for shutdown and mode change patch and general re-send, as
V2 was screwed for patchtracker.
Dmitry Osipenko (2):
arm_mptimer: Fix timer shutdown and mode change
arm_mptimer: Respect IT bit state
The slave mode is not implemented.
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
Changes since v1:
* none
Changes since v2:
* use QOM cast
* reworked debug printf
* use CamelCase for state type
*
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
Tested by booting a minimal linux system on the emulated plateform
Note: Qdev construction helper functions are removed with this patch.
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
On Wed, Jul 1, 2015 at 10:31 PM, Antony Pavlov antonynpav...@gmail.com wrote:
On Tue, 30 Jun 2015 21:12:29 -0700
Serge Vakulenko serge.vakule...@gmail.com wrote:
Please find below a set of patches, which allow to simulate Microchip PIC32
microcontrollers on QEMU. For examples of real PIC32
This series of patches add the support for the i.MX25 processor through the
Freescale 3DS evaluation board.
For now a limited set of devices are supported.
* GPT timers (from i.MX31)
* EPIT timers (from i.MX31)
* Serial ports (from i.MX31)
* Ethernet FEC port
* I2C controller
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
On Fri, Jul 3, 2015 at 2:39 PM, Maciej W. Rozycki ma...@linux-mips.org wrote:
On Wed, 1 Jul 2015, Aurelien Jarno wrote:
Secondly, I don't think calling random() is the correct thing to do.
It's an expensive function that is not thread safe. Quoting the
specification:
Within the required
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
v2: Added missed IRQ status update on control register write as per
Peter Crosthwaite comment.
Oh, no! Turned out, that is wrong. I wasn't testing that case properly on HW, V1
is correct. Quote from ARM doc If the timer interrupt is enabled, Interrupt ID
29 is set as Pending in the
The timer should fire the interrupt only if the IT (interrupt enable) bit
state of the control register is enabled.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
v2: Added missed IRQ status update on control register write as per
On 2015/7/4 1:51, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
configure --enable-colo/--disable-colo to switch COLO
support on/off.
COLO support is off by default.
Signed-off-by: zhanghailiang zhang.zhanghaili...@huawei.com
Signed-off-by: Yang Hongyang
On Fri, Jul 3, 2015 at 3:04 PM, Maciej W. Rozycki ma...@linux-mips.org wrote:
On Wed, 1 Jul 2015, Aurelien Jarno wrote:
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index ddfaff8..430a547 100644
--- a/target-mips/translate_init.c
+++
On Wed, Jul 1, 2015 at 6:41 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/Makefile.objs |3 +
hw/mips/mips_pic32mx7.c | 1652 +
Cc: qemu-sta...@nongnu.org
Signed-off-by: Fam Zheng f...@redhat.com
---
block.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block.c b/block.c
index 7e130cc..42eb8e3 100644
--- a/block.c
+++ b/block.c
@@ -1271,7 +1271,7 @@ int bdrv_append_temp_snapshot(BlockDriverState *bs,
On Wed, Jul 1, 2015 at 10:56 PM, Antony Pavlov antonynpav...@gmail.com wrote:
On Tue, 30 Jun 2015 21:12:34 -0700
Serge Vakulenko serge.vakule...@gmail.com wrote:
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/Makefile.objs |3 +
hw/mips/mips_pic32mx7.c |
The following patch might fix this (I have not yet tested this patch
myself): https://lkml.org/lkml/2015/7/5/217
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1435359
Title:
Booting kernel 3.19.2
On Sat, 07/04 10:47, Max Filippov wrote:
Hello,
I'm using QEMU with TAP network and after the commit
0a2df857a703 Merge remote-tracking branch
'remotes/stefanha/tags/net-pull-request' into staging
I've noticed that activation of debugger connected to QEMU's
gdbstub during network I/O
This updates linux-headers against master 4.2-rc1 (commit
d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754). This is the result of
./scripts/update-linux-headers.sh work.
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
This enables multiple IOMMU groups in one VFIO container which means
that multiple devices from different groups can share the same IOMMU
table (or tables if DDW).
This removes a group id from vfio_container_ioctl(). The kernel support
is required for this; if the host kernel does not have the
This makes use of the new memory registering feature. The idea is
to provide the userspace ability to notify the host kernel about pages
which are going to be used for DMA. Having this information, the host
kernel can pin them all once per user process, do locked pages
accounting (once) and not
sPAPRTCETable has a vfio_accel flag which is passed to
kvmppc_create_spapr_tce() and controls whether to create a guest view
table in KVM as this depends on the host kernel ability to accelerate
H_PUT_TCE for VFIO devices. We would set this flag at the moment
when sPAPRTCETable is created in
This adds support for Dynamic DMA Windows (DDW) option defined by
the SPAPR specification which allows to have additional DMA window(s)
This implements DDW for emulated and VFIO devices. As all TCE root regions
are mapped at 0 and 64bit long (and actual tables are child regions),
this replaces
On systems with guest visible IOMMU, adding a new memory region onto
PCI bus calls vfio_listener_region_add() for every DMA window. This
installs a notifier for IOMMU memory regions. The notifier is supposed
to be removed by vfio_listener_region_del(), however in the case of mixed
PHB (emulated +
Ping?
Regards,
Ting
On 2015-6-26 17:37, Ting Wang wrote:
There is job resource leak in function mirror_start_job,
although bdrv_create_dirty_bitmap is unlikely failed.
Add block_job_release for each release when needed.
Signed-off-by: Ting Wang kathy.wangt...@huawei.com
---
On 07/02/2015 08:46 PM, Stefan Hajnoczi wrote:
On Tue, Jun 30, 2015 at 04:35:24PM +0800, Jason Wang wrote:
On 06/30/2015 11:06 AM, Fam Zheng wrote:
virtio_net_receive still does the check by calling
virtio_net_can_receive, if the device or driver is not ready, the packet
is dropped.
This
On Sun, Jul 5, 2015 at 8:05 PM, Serge Vakulenko
serge.vakule...@gmail.com wrote:
On Wed, Jul 1, 2015 at 4:07 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index c476166..ab830ee 100644
---
On 7/5/2015 2:25, Michael S. Tsirkin wrote:
On Fri, Jul 03, 2015 at 07:09:59PM +0800, Hong Bo Li wrote:
But I would like to note that pci device drivers require driver handshake
before device goes away.
IIUC s390 hotplug is immediate, which is a problem.
Maybe doing the change will help make
This allows dynamic allocation for migrating arrays.
Already existing VMSTATE_VARRAY_UINT32 requires an array to be
pre-allocated, however there are cases when the size is not known in
advance and there is no real need to enforce it.
This defines another variant of VMSTATE_VARRAY_UINT32 with
At the moment presence of vfio-pci devices on a bus affect the way
the guest view table is allocated. If there is no vfio-pci on a PHB
and the host kernel supports KVM acceleration of H_PUT_TCE, a table
is allocated in KVM. However, if there is vfio-pci and we do yet not
KVM acceleration for
This reworks finish_realize() which used to finalize DMA setup with
an assumption that it will not change later.
New callbacks supports various window parameters such as page and
windows sizes. The new callback return error code rather than Error**.
This is a mechanical change so no change in
(cut-n-paste from kernel patchset)
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA window, 1 or 2GB big, mapped at zero
on a PCI bus.
PAPR defines a DDW RTAS
On a system reset, DMA configuration has to reset too. At the moment
it clears the table content. This is enough for the single table case
but with DDW, we will also have to disable all DMA windows except
the default one. Furthermore according to sPAPR, if the guest removed
the default window and
We are going to have multiple DMA windows at different offsets on
a PCI bus. For the sake of migration, we will have as many TCE table
objects pre-created as many windows supported.
So we need a way to map windows dynamically onto a PCI bus
when migration of a table is completed but at this stage
sPAPR IOMMU is managing two copies of an TCE table:
1) a guest view of the table - this is what emulated devices use and
this is where H_GET_TCE reads from;
2) a hardware TCE table - only present if there is at least one vfio-pci
device on a PHB; it is updated via a memory listener on a PHB
Currently TCE tables are created once at start and their size never
changes. We are going to change that by introducing a Dynamic DMA windows
support where DMA configuration may change during the guest execution.
This changes spapr_tce_new_table() to create an empty stub object. Only
LIOBN is
sPAPRTCETable is handling 2 TCE tables already:
1) guest view of the TCE table - emulated devices use only this table;
2) hardware IOMMU table - VFIO PCI devices use it for actual work but
it does not replace 1) and it is not visible to the guest.
The initialization of this table is driven by
On 2015-7-3 20:43, Markus Armbruster wrote:
Copying the HMP maintainer Luiz. You can feed your patch to
scripts/get_maintainer to find people to cc yourself.
OK, thanks.
Ting
Ting Wang kathy.wangt...@huawei.com writes:
Make info iothreads available on the HMP monitor.
For example, the
On Wed, Jul 1, 2015 at 4:07 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/cputimer.c | 17 +++--
hw/mips/mips_int.c | 12 ++--
target-mips/cpu.h| 9
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