[Qemu-devel] [PATCH] arm: Use g_new() friends where that makes obvious sense
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer,
for two reasons. One, it catches multiplication overflowing size_t.
Two, it returns T * rather than void *, which lets the compiler catch
more type errors.
This commit only touches allocations with size arguments of the form
sizeof(T).
Coccinelle semantic patch:
@@
type T;
@@
-g_malloc(sizeof(T))
+g_new(T, 1)
@@
type T;
@@
-g_try_malloc(sizeof(T))
+g_try_new(T, 1)
@@
type T;
@@
-g_malloc0(sizeof(T))
+g_new0(T, 1)
@@
type T;
@@
-g_try_malloc0(sizeof(T))
+g_try_new0(T, 1)
@@
type T;
expression n;
@@
-g_malloc(sizeof(T) * (n))
+g_new(T, n)
@@
type T;
expression n;
@@
-g_try_malloc(sizeof(T) * (n))
+g_try_new(T, n)
@@
type T;
expression n;
@@
-g_malloc0(sizeof(T) * (n))
+g_new0(T, n)
@@
type T;
expression n;
@@
-g_try_malloc0(sizeof(T) * (n))
+g_try_new0(T, n)
@@
type T;
expression p, n;
@@
-g_realloc(p, sizeof(T) * (n))
+g_renew(T, p, n)
@@
type T;
expression p, n;
@@
-g_try_realloc(p, sizeof(T) * (n))
+g_try_renew(T, p, n)
@@
type T;
expression n;
@@
-(T *)g_new(T, n)
+g_new(T, n)
@@
type T;
expression n;
@@
-(T *)g_new0(T, n)
+g_new0(T, n)
@@
type T;
expression p, n;
@@
-(T *)g_renew(T, p, n)
+g_renew(T, p, n)
Signed-off-by: Markus Armbruster arm...@redhat.com
---
hw/arm/omap1.c | 30 ++
hw/arm/omap2.c | 15 +--
hw/arm/pxa2xx.c| 11 +--
hw/arm/stellaris.c | 2 +-
hw/arm/strongarm.c | 2 +-
hw/char/omap_uart.c| 3 +--
hw/display/omap_dss.c | 3 +--
hw/display/omap_lcdc.c | 3 +--
hw/dma/omap_dma.c | 6 ++
hw/gpio/omap_gpio.c| 4 ++--
hw/input/stellaris_input.c | 4 ++--
hw/misc/omap_clk.c | 2 +-
hw/misc/omap_gpmc.c| 3 +--
hw/misc/omap_sdrc.c| 3 +--
hw/sd/omap_mmc.c | 6 ++
hw/ssi/omap_spi.c | 3 +--
hw/timer/omap_gptimer.c| 3 +--
17 files changed, 38 insertions(+), 65 deletions(-)
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index de2b289..8873f94 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -258,8 +258,7 @@ static struct omap_mpu_timer_s
*omap_mpu_timer_init(MemoryRegion *system_memory,
hwaddr base,
qemu_irq irq, omap_clk clk)
{
-struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
-g_malloc0(sizeof(struct omap_mpu_timer_s));
+struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1);
s-irq = irq;
s-clk = clk;
@@ -388,8 +387,7 @@ static struct omap_watchdog_timer_s
*omap_wd_timer_init(MemoryRegion *memory,
hwaddr base,
qemu_irq irq, omap_clk clk)
{
-struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
-g_malloc0(sizeof(struct omap_watchdog_timer_s));
+struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1);
s-timer.irq = irq;
s-timer.clk = clk;
@@ -495,8 +493,7 @@ static struct omap_32khz_timer_s
*omap_os_timer_init(MemoryRegion *memory,
hwaddr base,
qemu_irq irq, omap_clk clk)
{
-struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
-g_malloc0(sizeof(struct omap_32khz_timer_s));
+struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1);
s-timer.irq = irq;
s-timer.clk = clk;
@@ -1236,8 +1233,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
MemoryRegion *memory, hwaddr base,
qemu_irq abort_irq, omap_clk clk)
{
-struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
-g_malloc0(sizeof(struct omap_tipb_bridge_s));
+struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1);
s-abort = abort_irq;
omap_tipb_bridge_reset(s);
@@ -2099,8 +2095,7 @@ static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion
*memory,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
-struct omap_mpuio_s *s = (struct omap_mpuio_s *)
-g_malloc0(sizeof(struct omap_mpuio_s));
+struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1);
s-irq = gpio_int;
s-kbd_irq = kbd_int;
@@ -2292,8 +2287,7 @@ static struct omap_uwire_s *omap_uwire_init(MemoryRegion
*system_memory,
qemu_irq dma,
omap_clk clk)
{
-struct omap_uwire_s *s = (struct omap_uwire_s *)
-g_malloc0(sizeof(struct omap_uwire_s));
+struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1);
s-txirq = txirq;
s-rxirq = rxirq;
@@ -2932,8 +2926,7 @@ static struct omap_rtc_s
Re: [Qemu-devel] [PATCH 12/12] qga: start a man page
Quoting Marc-André Lureau (2015-07-01 06:47:47)
Add a simple man page for the qemu agent.
Signed-off-by: Marc-André Lureau marcandre.lur...@gmail.com
---
Makefile | 14 +-
qemu-doc.texi | 6 +++
qemu-ga.texi | 135
++
3 files changed, 153 insertions(+), 2 deletions(-)
create mode 100644 qemu-ga.texi
diff --git a/Makefile b/Makefile
index c9be643..45b1a12 100644
--- a/Makefile
+++ b/Makefile
@@ -88,7 +88,8 @@ LIBS+=-lz $(LIBS_TOOLS)
HELPERS-$(CONFIG_LINUX) = qemu-bridge-helper$(EXESUF)
ifdef BUILD_DOCS
-DOCS=qemu-doc.html qemu-tech.html qemu.1 qemu-img.1 qemu-nbd.8
qmp-commands.txt
+DOCS=qemu-doc.html qemu-tech.html qemu.1 qemu-img.1 qemu-nbd.8 qemu-ga.8
+DOCS+=qmp-commands.txt
ifdef CONFIG_LINUX
DOCS+=kvm_stat.1
endif
@@ -400,6 +401,9 @@ ifneq ($(TOOLS),)
$(INSTALL_DIR) $(DESTDIR)$(mandir)/man8
$(INSTALL_DATA) qemu-nbd.8 $(DESTDIR)$(mandir)/man8
endif
+ifneq (,$(findstring qemu-ga,$(TOOLS)))
+ $(INSTALL_DATA) qemu-ga.8 $(DESTDIR)$(mandir)/man8
+endif
endif
ifdef CONFIG_VIRTFS
$(INSTALL_DIR) $(DESTDIR)$(mandir)/man1
@@ -538,6 +542,12 @@ qemu-nbd.8: qemu-nbd.texi
$(POD2MAN) --section=8 --center= --release= qemu-nbd.pod
$@, \
GEN $@)
+qemu-ga.8: qemu-ga.texi
+ $(call quiet-command, \
+ perl -Ww -- $(SRC_PATH)/scripts/texi2pod.pl $ qemu-ga.pod \
+ $(POD2MAN) --section=8 --center= --release= qemu-ga.pod $@,
\
+ GEN $@)
+
kvm_stat.1: scripts/kvm/kvm_stat.texi
$(call quiet-command, \
perl -Ww -- $(SRC_PATH)/scripts/texi2pod.pl $ kvm_stat.pod \
@@ -551,7 +561,7 @@ pdf: qemu-doc.pdf qemu-tech.pdf
qemu-doc.dvi qemu-doc.html qemu-doc.info qemu-doc.pdf: \
qemu-img.texi qemu-nbd.texi qemu-options.texi \
- qemu-monitor.texi qemu-img-cmds.texi
+ qemu-monitor.texi qemu-img-cmds.texi qemu-ga.texi
ifdef CONFIG_WIN32
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 0125bc7..aa3d165 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -412,6 +412,7 @@ snapshots.
* vm_snapshots:: VM snapshots
* qemu_img_invocation:: qemu-img Invocation
* qemu_nbd_invocation:: qemu-nbd Invocation
+* qemu_ga_invocation::qemu-ga Invocation
* disk_images_formats:: Disk image file formats
* host_drives:: Using host drives
* disk_images_fat_images::Virtual FAT disk images
@@ -505,6 +506,11 @@ state is not saved or restored properly (in particular
USB).
@include qemu-nbd.texi
+@node qemu_ga_invocation
+@subsection @code{qemu-ga} Invocation
+
+@include qemu-ga.texi
+
@node disk_images_formats
@subsection Disk image file formats
diff --git a/qemu-ga.texi b/qemu-ga.texi
new file mode 100644
index 000..a5e8002
--- /dev/null
+++ b/qemu-ga.texi
@@ -0,0 +1,135 @@
+@example
+@c man begin SYNOPSIS
+usage: qemu-ga [-m method -p path] [OPTION]...
+@c man end
+@end example
+
+@c man begin DESCRIPTION
+
+The QEMU Guest Agent is a deamon that allows the host to perform
+various operations in the guest.
Maybe:
various operations in the guest, such as:
Makes it clearer it's not an exhaustive list.
+
+@itemize
+@item
+get information from the guest
+@item
+set the guest's system time
+@item
+read/write a file
+@item
+sync an freeze the filesystems
*and freeze
+@item
+suspend the guest
+@item
+reconfigugre guest local processors
*reconfigure
+@item
+set user's password
+@item
+...
+@end itemize
+
+qemu-ga will read a system configuration file on startup (located at
+q@file{/etc/qemu/qemu-ga.conf} by default). Then parse remaining
, then parse remaining
+configuration options on the command line. For the same key, the last
+option wins, but the lists accumulate.
Maybe an added:
(see below for configuration file format)
would be useful. Might lose less thorough readers (such as myself) here
(initially I assumed there wouldn't be examples below and starting
writing a comment about it).
+
+@c man end
+
+@c man begin OPTIONS
+@table @option
+@item -m, --method=@var{method}
+ Transport method: one of @samp{unix-listen}, @samp{virtio-serial}, or
+ @samp{isa-serial} (@samp{virtio-serial} is the default).
+
+@item -p, --path=@var{path}
+ Device/socket path (the default for virtio-serial is:
+ @samp{/dev/virtio-ports/org.qemu.guest_agent.0},
+ the default for isa-serial is: @samp{/dev/ttyS0})
I'm not sure if it's possible, but would be nice if we could use the
#defines from QGA to grab these values. Would help keep things in sync.
Not a huge deal if there's no simple method.
+
+@item -l, --logfile=@var{path}
+ Set log file path, logs to stderr by default.
+
+@item -f, --pidfile=@var{path}
+ Specify pid file (default is @samp{/var/run/qemu-ga.pid}).
+
+@item -F, --fsfreeze-hook=@var{path}
+ Enable fsfreeze hook.
Re: [Qemu-devel] [ARM SMBIOS V4 PATCH 1/2] smbios: add smbios 3.0 support
On 08/25/2015 10:29 AM, Leif Lindholm wrote:
On Tue, Aug 25, 2015 at 04:17:42PM +0100, Peter Maydell wrote:
On 13 August 2015 at 18:09, Wei Huang w...@redhat.com wrote:
This patch adds support for SMBIOS 3.0 entry point. When caller invokes
smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
smbios_get_tables() will return the entry point table in right format.
-/* SMBIOS entry point (anchor).
- * BIOS must place this at a 16-bit-aligned address between 0xf and
0xf.
+/* SMBIOS entry point
+ * BIOS must place this at a 16-bit-aligned address between 0xf
+ * and 0xf.
*/
-struct smbios_entry_point {
+struct smbios_21_entry_point {
uint8_t anchor_string[4];
uint8_t checksum;
uint8_t length;
@@ -58,6 +52,25 @@ struct smbios_entry_point {
uint8_t smbios_bcd_revision;
} QEMU_PACKED;
This breaks 'make check' for x86, because tests/bios-tables-test.c
still uses 'struct smbios_entry_point' and no longer compiles
if this patch is applied.
Urgh.
I'm removing these two patches from my target-arm queue.
Fair enough.
Wei - is there actually any particular point in renaming this
structure? In all versions of the specification before 3.0, this was
only known as the smbios entry point. Only with the introduction of
SMBIOS 3.0 this was retrospectively renamed.
I can take this suggestion, with clear comment in header file so nobody
will get confused. Peter, please let me know if you object.
The new patches should be out in a short while.
Thanks,
-Wei
(And personally, I find that renaming a bit counterintuitive, since it
is still a valid 32-bit entry point in SMBIOS3, and was the only entry
point up until and including SMBIOS 2.8.)
/
Leif
[Qemu-devel] [PATCH v2 2/8] s390x: Create QOM device for s390 storage keys
From: Jason J. Herne jjhe...@linux.vnet.ibm.com
A new QOM style device is provided to back guest storage keys. A special
version for KVM is created, which handles the storage key access via
KVM_S390_GET_SKEYS and KVM_S390_SET_SKEYS ioctl.
Reviewed-by: David Hildenbrand d...@linux.vnet.ibm.com
Signed-off-by: Jason J. Herne jjhe...@linux.vnet.ibm.com
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
---
MAINTAINERS | 1 +
hw/s390x/Makefile.objs | 2 +
hw/s390x/s390-skeys-kvm.c | 75 +
hw/s390x/s390-skeys.c | 141
include/hw/s390x/storage-keys.h | 55
5 files changed, 274 insertions(+)
create mode 100644 hw/s390x/s390-skeys-kvm.c
create mode 100644 hw/s390x/s390-skeys.c
create mode 100644 include/hw/s390x/storage-keys.h
diff --git a/MAINTAINERS b/MAINTAINERS
index a059d5d..c7a90a9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -560,6 +560,7 @@ F: hw/s390x/css.[hc]
F: hw/s390x/sclp*.[hc]
F: hw/s390x/ipl*.[hc]
F: hw/s390x/*pci*.[hc]
+F: hw/s390x/s390-skeys*.c
F: include/hw/s390x/
F: pc-bios/s390-ccw/
T: git git://github.com/cohuck/qemu virtio-ccw-upstr
diff --git a/hw/s390x/Makefile.objs b/hw/s390x/Makefile.objs
index 27cd75a..527d754 100644
--- a/hw/s390x/Makefile.objs
+++ b/hw/s390x/Makefile.objs
@@ -9,3 +9,5 @@ obj-y += css.o
obj-y += s390-virtio-ccw.o
obj-y += virtio-ccw.o
obj-y += s390-pci-bus.o s390-pci-inst.o
+obj-y += s390-skeys.o
+obj-$(CONFIG_KVM) += s390-skeys-kvm.o
diff --git a/hw/s390x/s390-skeys-kvm.c b/hw/s390x/s390-skeys-kvm.c
new file mode 100644
index 000..682949a
--- /dev/null
+++ b/hw/s390x/s390-skeys-kvm.c
@@ -0,0 +1,75 @@
+/*
+ * s390 storage key device
+ *
+ * Copyright 2015 IBM Corp.
+ * Author(s): Jason J. Herne jjhe...@linux.vnet.ibm.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at
+ * your option) any later version. See the COPYING file in the top-level
+ * directory.
+ */
+
+#include hw/s390x/storage-keys.h
+#include sysemu/kvm.h
+#include qemu/error-report.h
+
+static int kvm_s390_skeys_enabled(S390SKeysState *ss)
+{
+S390SKeysClass *skeyclass = S390_SKEYS_GET_CLASS(ss);
+uint8_t single_key;
+int r;
+
+r = skeyclass-get_skeys(ss, 0, 1, single_key);
+if (r != 0 r != KVM_S390_GET_SKEYS_NONE) {
+error_report(S390_GET_KEYS error %d\n, r);
+}
+return (r == 0);
+}
+
+static int kvm_s390_skeys_get(S390SKeysState *ss, uint64_t start_gfn,
+ uint64_t count, uint8_t *keys)
+{
+struct kvm_s390_skeys args = {
+.start_gfn = start_gfn,
+.count = count,
+.skeydata_addr = (__u64)keys
+};
+
+return kvm_vm_ioctl(kvm_state, KVM_S390_GET_SKEYS, args);
+}
+
+static int kvm_s390_skeys_set(S390SKeysState *ss, uint64_t start_gfn,
+ uint64_t count, uint8_t *keys)
+{
+struct kvm_s390_skeys args = {
+.start_gfn = start_gfn,
+.count = count,
+.skeydata_addr = (__u64)keys
+};
+
+return kvm_vm_ioctl(kvm_state, KVM_S390_SET_SKEYS, args);
+}
+
+static void kvm_s390_skeys_class_init(ObjectClass *oc, void *data)
+{
+S390SKeysClass *skeyclass = S390_SKEYS_CLASS(oc);
+
+skeyclass-skeys_enabled = kvm_s390_skeys_enabled;
+skeyclass-get_skeys = kvm_s390_skeys_get;
+skeyclass-set_skeys = kvm_s390_skeys_set;
+}
+
+static const TypeInfo kvm_s390_skeys_info = {
+.name = TYPE_KVM_S390_SKEYS,
+.parent= TYPE_S390_SKEYS,
+.instance_size = sizeof(S390SKeysState),
+.class_init= kvm_s390_skeys_class_init,
+.class_size= sizeof(S390SKeysClass),
+};
+
+static void kvm_s390_skeys_register_types(void)
+{
+type_register_static(kvm_s390_skeys_info);
+}
+
+type_init(kvm_s390_skeys_register_types)
diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c
new file mode 100644
index 000..77c42ff
--- /dev/null
+++ b/hw/s390x/s390-skeys.c
@@ -0,0 +1,141 @@
+/*
+ * s390 storage key device
+ *
+ * Copyright 2015 IBM Corp.
+ * Author(s): Jason J. Herne jjhe...@linux.vnet.ibm.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at
+ * your option) any later version. See the COPYING file in the top-level
+ * directory.
+ */
+
+#include hw/boards.h
+#include hw/s390x/storage-keys.h
+#include qemu/error-report.h
+
+S390SKeysState *s390_get_skeys_device(void)
+{
+S390SKeysState *ss;
+
+ss = S390_SKEYS(object_resolve_path_type(, TYPE_S390_SKEYS, NULL));
+assert(ss);
+return ss;
+}
+
+void s390_skeys_init(void)
+{
+Object *obj;
+
+if (kvm_enabled()) {
+obj = object_new(TYPE_KVM_S390_SKEYS);
+} else {
+obj = object_new(TYPE_QEMU_S390_SKEYS);
+}
+object_property_add_child(qdev_get_machine(), TYPE_S390_SKEYS,
+ obj, NULL);
+object_unref(obj);
+
+qdev_init_nofail(DEVICE(obj));
+}
+
+static void qemu_s390_skeys_init(Object *obj)
[Qemu-devel] [PATCH v2 6/8] s390x: Info skeys sub-command
From: Jason J. Herne jjhe...@linux.vnet.ibm.com
Provide an info skeys hmp sub-command to allow the end user to dump a storage
key for a given address. This is useful for guest operating system developers.
Reviewed-by: Thomas Huth th...@linux.vnet.ibm.com
Reviewed-by: David Hildenbrand d...@linux.vnet.ibm.com
Signed-off-by: Jason J. Herne jjhe...@linux.vnet.ibm.com
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
---
hmp-commands.hx | 2 ++
hw/s390x/s390-skeys.c | 23 +++
include/hw/s390x/storage-keys.h | 2 ++
monitor.c | 9 +
4 files changed, 36 insertions(+)
diff --git a/hmp-commands.hx b/hmp-commands.hx
index 803ff91..c61468e 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -1806,6 +1806,8 @@ show roms
show the TPM device
@item info memory-devices
show the memory devices
+@item info skeys
+Display the value of a storage key (s390 only)
@end table
ETEXI
diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c
index f6a29ab..0b13d77 100644
--- a/hw/s390x/s390-skeys.c
+++ b/hw/s390x/s390-skeys.c
@@ -72,6 +72,29 @@ static void write_keys(QEMUFile *f, uint8_t *keys, uint64_t
startgfn,
g_free(buf);
}
+void hmp_info_skeys(Monitor *mon, const QDict *qdict)
+{
+S390SKeysState *ss = s390_get_skeys_device();
+S390SKeysClass *skeyclass = S390_SKEYS_GET_CLASS(ss);
+uint64_t addr = qdict_get_int(qdict, addr);
+uint8_t key;
+int r;
+
+/* Quick check to see if guest is using storage keys*/
+if (!skeyclass-skeys_enabled(ss)) {
+monitor_printf(mon, Error: This guest is not using storage keys.\n);
+return;
+}
+
+r = skeyclass-get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, key);
+if (r 0) {
+monitor_printf(mon, Error: %s\n, strerror(-r));
+return;
+}
+
+monitor_printf(mon, key: 0x%X\n, key);
+}
+
void hmp_dump_skeys(Monitor *mon, const QDict *qdict)
{
const char *filename = qdict_get_str(qdict, filename);
diff --git a/include/hw/s390x/storage-keys.h b/include/hw/s390x/storage-keys.h
index 0d04f19..18e08d2 100644
--- a/include/hw/s390x/storage-keys.h
+++ b/include/hw/s390x/storage-keys.h
@@ -54,4 +54,6 @@ void s390_skeys_init(void);
S390SKeysState *s390_get_skeys_device(void);
void hmp_dump_skeys(Monitor *mon, const QDict *qdict);
+void hmp_info_skeys(Monitor *mon, const QDict *qdict);
+
#endif /* __S390_STORAGE_KEYS_H */
diff --git a/monitor.c b/monitor.c
index 3deba38..451af6f 100644
--- a/monitor.c
+++ b/monitor.c
@@ -2881,6 +2881,15 @@ static mon_cmd_t info_cmds[] = {
.help = Show rocker OF-DPA groups,
.mhandler.cmd = hmp_rocker_of_dpa_groups,
},
+#if defined(TARGET_S390X)
+{
+.name = skeys,
+.args_type = addr:l,
+.params = address,
+.help = Display the value of a storage key,
+.mhandler.cmd = hmp_info_skeys,
+},
+#endif
{
.name = NULL,
},
--
2.5.0
[Qemu-devel] [PATCH v2 0/8] s390x: storage key migration
Here's the second edition of the storage key migration patches. Changes from v1: - have the dump-skeys qmp command use qemu_fopen() and friends - handle failures of the skeys-obtaining commands by filling the stream with zeroes and setting an error flag Would like to send a pull request soonish. Cornelia Huck (1): s390x: add 2.5 compat s390-ccw-virtio machine Jason J. Herne (7): s390x: Create QOM device for s390 storage keys s390x: Enable new s390-storage-keys device s390x: Dump storage keys qmp command s390x: Dump-skeys hmp support s390x: Info skeys sub-command s390x: Migrate guest storage keys (initial memory only) s390x: Disable storage key migration on old machine type MAINTAINERS | 1 + hmp-commands.hx | 18 ++ hw/s390x/Makefile.objs | 2 + hw/s390x/s390-skeys-kvm.c | 75 +++ hw/s390x/s390-skeys.c | 425 hw/s390x/s390-virtio-ccw.c | 39 +++- hw/s390x/s390-virtio.c | 11 +- hw/s390x/s390-virtio.h | 2 +- include/hw/s390x/storage-keys.h | 60 ++ monitor.c | 20 ++ qapi-schema.json| 13 ++ qmp-commands.hx | 25 +++ target-s390x/cpu.h | 2 - target-s390x/mem_helper.c | 46 - target-s390x/mmu_helper.c | 28 ++- trace-events| 4 + 16 files changed, 745 insertions(+), 26 deletions(-) create mode 100644 hw/s390x/s390-skeys-kvm.c create mode 100644 hw/s390x/s390-skeys.c create mode 100644 include/hw/s390x/storage-keys.h -- 2.5.0
[Qemu-devel] [PATCH v2 1/8] s390x: add 2.5 compat s390-ccw-virtio machine
Reviewed-by: Jason J. Herne jjhe...@linux.vnet.ibm.com
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
Acked-by: Christian Borntraeger borntrae...@de.ibm.com
---
hw/s390x/s390-virtio-ccw.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 4c51d1a..71df282 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -287,9 +287,7 @@ static void ccw_machine_2_4_class_init(ObjectClass *oc,
void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc-name = s390-ccw-virtio-2.4;
-mc-alias = s390-ccw-virtio;
mc-desc = VirtIO-ccw based S390 machine v2.4;
-mc-is_default = 1;
}
static const TypeInfo ccw_machine_2_4_info = {
@@ -298,10 +296,27 @@ static const TypeInfo ccw_machine_2_4_info = {
.class_init= ccw_machine_2_4_class_init,
};
+static void ccw_machine_2_5_class_init(ObjectClass *oc, void *data)
+{
+MachineClass *mc = MACHINE_CLASS(oc);
+
+mc-name = s390-ccw-virtio-2.5;
+mc-alias = s390-ccw-virtio;
+mc-desc = VirtIO-ccw based S390 machine v2.5;
+mc-is_default = 1;
+}
+
+static const TypeInfo ccw_machine_2_5_info = {
+.name = TYPE_S390_CCW_MACHINE 2.5,
+.parent= TYPE_S390_CCW_MACHINE,
+.class_init= ccw_machine_2_5_class_init,
+};
+
static void ccw_machine_register_types(void)
{
type_register_static(ccw_machine_info);
type_register_static(ccw_machine_2_4_info);
+type_register_static(ccw_machine_2_5_info);
}
type_init(ccw_machine_register_types)
--
2.5.0
Re: [Qemu-devel] [PATCH v2 10/18] nvdimm: init the address region used by DSM method
On Fri, Aug 14, 2015 at 10:52:03PM +0800, Xiao Guangrong wrote:
@@ -257,14 +258,91 @@ static void build_nfit_table(GSList *device_list, char
*buf)
}
}
+struct dsm_buffer {
+/* RAM page. */
+uint32_t handle;
+uint8_t arg0[16];
+uint32_t arg1;
+uint32_t arg2;
+union {
+char arg3[PAGE_SIZE - 3 * sizeof(uint32_t) - 16 * sizeof(uint8_t)];
+};
+
+/* MMIO page. */
+union {
+uint32_t notify;
+char pedding[PAGE_SIZE];
s/pedding/padding/
+};
+};
+
+static ram_addr_t dsm_addr;
+static size_t dsm_size;
+
+static uint64_t dsm_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+return 0;
+}
+
+static void dsm_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+}
+
+static const MemoryRegionOps dsm_ops = {
+.read = dsm_read,
+.write = dsm_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static int build_dsm_buffer(void)
+{
+MemoryRegion *dsm_ram_mr, *dsm_mmio_mr;
+ram_addr_t addr;;
s/;;/;/
Re: [Qemu-devel] [PATCH v2 15/18] nvdimm: support NFIT_CMD_GET_CONFIG_SIZE function
On Fri, Aug 14, 2015 at 10:52:08PM +0800, Xiao Guangrong wrote: Function 4 is used to get Namespace lable size s/lable/label/
Re: [Qemu-devel] [PATCH 1/1] MAINTAINERS: add responsible person for Parallels format driver
On Fri, Aug 21, 2015 at 08:44:16PM +0300, Denis V. Lunev wrote: Denis has spent 6 years working with this format in Parallels and QEMU code was rewritten almost completely by his. Thus it would be quite natural to add him as a maintainer and point of contact. Patches are going to flow though Stefan's tree. Signed-off-by: Denis V. Lunev d...@openvz.org CC: Stefan Hajnoczi stefa...@redhat.com --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) Thanks, applied to my block tree: https://github.com/stefanha/qemu/commits/block Stefan
Re: [Qemu-devel] [PATCH v2 4/8] s390x: Dump storage keys qmp command
On 08/25/2015 10:10 AM, Cornelia Huck wrote:
From: Jason J. Herne jjhe...@linux.vnet.ibm.com
Provide a dump-skeys qmp command to allow the end user to dump storage
keys. This is useful for debugging problems with guest storage key support
within Qemu and for guest operating system developers.
Reviewed-by: Thomas Huth th...@linux.vnet.ibm.com
Reviewed-by: David Hildenbrand d...@linux.vnet.ibm.com
Signed-off-by: Jason J. Herne jjhe...@linux.vnet.ibm.com
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
---
+static void write_keys(QEMUFile *f, uint8_t *keys, uint64_t startgfn,
+ uint64_t count, Error **errp)
+{
+uint64_t curpage = startgfn;
+uint64_t maxpage = curpage + count - 1;
+const char *fmt = page=%03 PRIx64 : key(%d) = ACC=%X, FP=%d, REF=%d,
+ ch=%d, reserved=%d\n;
+char *buf = g_try_malloc(128);
+int len;
+
+if (!buf) {
+error_setg(errp, Out of memory);
+return;
+}
128 bytes is small enough to just stack-allocate, and forget about
malloc(). Even if you insist on malloc'ing, a simple g_malloc() is
nicer than g_try_malloc(), as it is unlikely to fail (and if it DOES
fail, something else is likely to fail soon) - we tend to reserve
g_try_malloc() for potentially large allocations where failure is more
likely.
+
+for (; curpage = maxpage; curpage++) {
+uint8_t acc = (*keys 0xF0) 4;
+int fp = (*keys 0x08);
+int ref = (*keys 0x04);
+int ch = (*keys 0x02);
+int res = (*keys 0x01);
+
+len = snprintf(buf, 128, fmt, curpage,
If you stack-allocate buf, then sizeof(buf) is nicer than hard-coded 128
here.
+ *keys, acc, fp, ref, ch, res);
+qemu_put_buffer(f, (uint8_t *)buf, len);
Potential bug. snprintf() returns how many bytes WOULD have been printed
if the buffer is large enough, and may therefore be larger than 128 if
your buffer size guess was wrong or the format string is edited. The
only way to safely use snprintf is to first check that the result is no
larger than the input, before passing the string on to qemu_put_buffer().
+void qmp_dump_skeys(const char *filename, Error **errp)
+{
+S390SKeysState *ss = s390_get_skeys_device();
+S390SKeysClass *skeyclass = S390_SKEYS_GET_CLASS(ss);
+const uint64_t total_count = ram_size / TARGET_PAGE_SIZE;
+uint64_t handled_count = 0, cur_count;
+Error *lerr = NULL;
+vaddr cur_gfn = 0;
+uint8_t *buf;
+int ret;
+QEMUFile *f;
+
+/* Quick check to see if guest is using storage keys*/
+if (!skeyclass-skeys_enabled(ss)) {
+error_setg(lerr, This guest is not using storage keys.
+ Nothing to dump.);
Error messages don't usually end in '.'
+error_propagate(errp, lerr);
Instead of setting the local error just to propagate it, just write the
error message directly into errp, as in:
error_setg(errp, ...)
+return;
+}
+
+f = qemu_fopen(filename, wb);
+if (!f) {
+error_setg(lerr, Could not open file);
+error_propagate(errp, lerr);
Same story. Also, we have error_setg_file_open() which is more
appropriate to use here.
+ret = skeyclass-get_skeys(ss, cur_gfn, cur_count, buf);
+if (ret 0) {
+error_setg(lerr, get_keys error %d, ret);
+error_propagate(errp, lerr);
+goto out_free;
+}
+
+/* write keys to stream */
+write_keys(f, buf, cur_gfn, cur_count, lerr);
+if (lerr) {
+error_propagate(errp, lerr);
+goto out_free;
Instead of propagating the error on every caller...
+}
+
+cur_gfn += cur_count;
+handled_count += cur_count;
+}
+
+out_free:
+g_free(buf);
you could do it just once here unconditionally (it is safe to call
error_propagate(..., NULL) when no error occurred).
+++ b/qapi-schema.json
@@ -2058,6 +2058,19 @@
'returns': 'DumpGuestMemoryCapability' }
##
+# @dump-skeys
+#
+# Dump guest's storage keys. @filename: the path to the file to dump to.
Newline before @filename, please.
+# This command is only supported on s390 architecture.
It would be nice if we fixed the qapi generator to allow conditional
compilation of the .json files, so that the command is not even exposed
on other platforms. Markus mentioned that at KVM Forum as one of the
possible followups to pursue after his current pending series on
introspection lands. [1]
+#
+# Returns: nothing on success
The 'Returns' line adds no information, so it is better omitted.
+#
+# Since: 2.5
+##
+{ 'command': 'dump-skeys',
+ 'data': { 'filename': 'str' } }
+
+##
# @netdev_add:
#
# Add a network backend.
diff --git a/qmp-commands.hx b/qmp-commands.hx
index ba630b1..9848fd8 100644
--- a/qmp-commands.hx
+++ b/qmp-commands.hx
@@ -872,6 +872,31 @@ Example:
Re: [Qemu-devel] [PATCH 06/12] qga: move option parsing to seperate function
Quoting Marc-André Lureau (2015-07-01 06:47:41)
Move option parsing out of giant main().
Signed-off-by: Marc-André Lureau marcandre.lur...@gmail.com
---
qga/main.c | 41 +
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/qga/main.c b/qga/main.c
index b776d16..b965f61 100644
--- a/qga/main.c
+++ b/qga/main.c
@@ -941,19 +941,25 @@ static GList *split_list(gchar *str, const gchar
separator)
return list;
}
-int main(int argc, char **argv)
-{
-const char *sopt = hVvdm:p:l:f:F::b:s:t:;
-char *method = NULL, *device_path = NULL;
-char *log_filepath = NULL;
-char *pid_filepath = NULL;
+static char *device_path;
+static char *method;
+static char *log_filepath;
+static char *pid_filepath;
Since we want to pass these around as a representation of the
configuration state, I'd rather we package them into a GAConfig
structure or something of the sort that and pass it around as arguments
rather than as globals. Between parse/load_config/load_defaults it's
becoming a little difficult to keep track of where all these values are
being modified.
Otherwise, looks good, and makes for a nice cleanup.
#ifdef CONFIG_FSFREEZE
-char *fsfreeze_hook = NULL;
+static char *fsfreeze_hook;
#endif
-char *state_dir = NULL;
+static char *state_dir;
#ifdef _WIN32
-const char *service = NULL;
+static const char *service;
#endif
+static GList *blacklist;
+static int daemonize;
+static GLogLevelFlags log_level = G_LOG_LEVEL_ERROR | G_LOG_LEVEL_CRITICAL;
+
+static void option_parse(int argc, char **argv)
+{
+const char *sopt = hVvdm:p:l:f:F::b:s:t:D;
+int opt_ind = 0, ch;
const struct option lopt[] = {
{ help, 0, NULL, 'h' },
{ version, 0, NULL, 'V' },
@@ -973,14 +979,7 @@ int main(int argc, char **argv)
{ statedir, 1, NULL, 't' },
{ NULL, 0, NULL, 0 }
};
-int opt_ind = 0, ch, daemonize = 0;
-GLogLevelFlags log_level = G_LOG_LEVEL_ERROR | G_LOG_LEVEL_CRITICAL;
-GList *blacklist = NULL;
-GAState *s;
-module_call_init(MODULE_INIT_QAPI);
-
-init_dfl_pathnames();
while ((ch = getopt_long(argc, argv, sopt, lopt, opt_ind)) != -1) {
switch (ch) {
case 'm':
@@ -1058,6 +1057,16 @@ int main(int argc, char **argv)
exit(EXIT_FAILURE);
}
}
+}
+
+int main(int argc, char **argv)
+{
+GAState *s;
+
+module_call_init(MODULE_INIT_QAPI);
+
+init_dfl_pathnames();
+option_parse(argc, argv);
if (pid_filepath == NULL) {
pid_filepath = g_strdup(dfl_pathnames.pidfile);
--
2.4.3
[Qemu-devel] [PATCH v2 7/8] s390x: Migrate guest storage keys (initial memory only)
From: Jason J. Herne jjhe...@linux.vnet.ibm.com
Routines to save/load guest storage keys are provided. register_savevm is
called to register them as migration handlers.
We prepare the protocol to support more complex parameters. So we will
later be able to support standby memory (having empty holes), compression
and state live migration like done for ram.
Reviewed-by: David Hildenbrand d...@linux.vnet.ibm.com
Signed-off-by: Jason J. Herne jjhe...@linux.vnet.ibm.com
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
---
hw/s390x/s390-skeys.c | 125 ++
1 file changed, 125 insertions(+)
diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c
index 0b13d77..9d4a79d 100644
--- a/hw/s390x/s390-skeys.c
+++ b/hw/s390x/s390-skeys.c
@@ -11,10 +11,14 @@
#include hw/boards.h
#include qmp-commands.h
+#include migration/qemu-file.h
#include hw/s390x/storage-keys.h
#include qemu/error-report.h
#define S390_SKEYS_BUFFER_SIZE 131072 /* Room for 128k storage keys */
+#define S390_SKEYS_SAVE_FLAG_EOS 0x01
+#define S390_SKEYS_SAVE_FLAG_SKEYS 0x02
+#define S390_SKEYS_SAVE_FLAG_ERROR 0x04
S390SKeysState *s390_get_skeys_device(void)
{
@@ -247,6 +251,126 @@ static const TypeInfo qemu_s390_skeys_info = {
.instance_size = sizeof(S390SKeysClass),
};
+static void s390_storage_keys_save(QEMUFile *f, void *opaque)
+{
+S390SKeysState *ss = S390_SKEYS(opaque);
+S390SKeysClass *skeyclass = S390_SKEYS_GET_CLASS(ss);
+uint64_t pages_left = ram_size / TARGET_PAGE_SIZE;
+uint64_t read_count, eos = S390_SKEYS_SAVE_FLAG_EOS;
+vaddr cur_gfn = 0;
+int error = 0;
+uint8_t *buf;
+
+if (!skeyclass-skeys_enabled(ss)) {
+goto end_stream;
+}
+
+buf = g_try_malloc(S390_SKEYS_BUFFER_SIZE);
+if (!buf) {
+error_report(storage key save could not allocate memory\n);
+goto end_stream;
+}
+
+/* We only support initial memory. Standby memory is not handled yet. */
+qemu_put_be64(f, (cur_gfn * TARGET_PAGE_SIZE) |
S390_SKEYS_SAVE_FLAG_SKEYS);
+qemu_put_be64(f, pages_left);
+
+while (pages_left) {
+read_count = MIN(pages_left, S390_SKEYS_BUFFER_SIZE);
+
+if (!error) {
+error = skeyclass-get_skeys(ss, cur_gfn, read_count, buf);
+if (error) {
+/*
+ * If error: we want to fill the stream with valid data instead
+ * of stopping early so we pad the stream with 0x00 values and
+ * use S390_SKEYS_SAVE_FLAG_ERROR to indicate failure to the
+ * reading side.
+ */
+error_report(S390_GET_KEYS error %d\n, error);
+memset(buf, 0, S390_SKEYS_BUFFER_SIZE);
+eos = S390_SKEYS_SAVE_FLAG_ERROR;
+}
+}
+
+qemu_put_buffer(f, buf, read_count);
+cur_gfn += read_count;
+pages_left -= read_count;
+}
+
+g_free(buf);
+end_stream:
+qemu_put_be64(f, eos);
+}
+
+static int s390_storage_keys_load(QEMUFile *f, void *opaque, int version_id)
+{
+S390SKeysState *ss = S390_SKEYS(opaque);
+S390SKeysClass *skeyclass = S390_SKEYS_GET_CLASS(ss);
+int ret = 0;
+
+while (!ret) {
+ram_addr_t addr;
+int flags;
+
+addr = qemu_get_be64(f);
+flags = addr ~TARGET_PAGE_MASK;
+addr = TARGET_PAGE_MASK;
+
+switch (flags) {
+case S390_SKEYS_SAVE_FLAG_SKEYS: {
+const uint64_t total_count = qemu_get_be64(f);
+uint64_t handled_count = 0, cur_count;
+uint64_t cur_gfn = addr / TARGET_PAGE_SIZE;
+uint8_t *buf = g_try_malloc(S390_SKEYS_BUFFER_SIZE);
+
+if (!buf) {
+error_report(storage key load could not allocate memory\n);
+ret = -ENOMEM;
+break;
+}
+
+while (handled_count total_count) {
+cur_count = MIN(total_count - handled_count,
+S390_SKEYS_BUFFER_SIZE);
+qemu_get_buffer(f, buf, cur_count);
+
+ret = skeyclass-set_skeys(ss, cur_gfn, cur_count, buf);
+if (ret 0) {
+error_report(S390_SET_KEYS error %d\n, ret);
+break;
+}
+handled_count += cur_count;
+cur_gfn += cur_count;
+}
+g_free(buf);
+break;
+}
+case S390_SKEYS_SAVE_FLAG_ERROR: {
+error_report(Storage key data is incomplete.);
+ret = -EINVAL;
+break;
+}
+case S390_SKEYS_SAVE_FLAG_EOS:
+/* normal exit */
+return 0;
+default:
+error_report(Unexpected storage key flag data: %#x, flags);
+ret = -EINVAL;
+}
+}
+
+return ret;
+}
+
+static void s390_skeys_instance_init(Object *obj)
+{
+S390SKeysState *ss =
Re: [Qemu-devel] [PATCH 08/12] qga: move agent run in a seperate function
Quoting Marc-André Lureau (2015-07-01 06:47:43)
Once the options are populated, move the running state to
a run_agent() function.
Signed-off-by: Marc-André Lureau marcandre.lur...@gmail.com
---
qga/main.c | 123
+
1 file changed, 67 insertions(+), 56 deletions(-)
diff --git a/qga/main.c b/qga/main.c
index 5575637..aaf0e10 100644
--- a/qga/main.c
+++ b/qga/main.c
@@ -1042,39 +1042,13 @@ static void option_parse(int argc, char **argv)
}
}
-int main(int argc, char **argv)
+static int run_agent(GAState *s)
{
-GAState *s;
-
-module_call_init(MODULE_INIT_QAPI);
-
-init_dfl_pathnames();
-option_parse(argc, argv);
-
-if (pid_filepath == NULL) {
-pid_filepath = g_strdup(dfl_pathnames.pidfile);
-}
-
-if (state_dir == NULL) {
-state_dir = g_strdup(dfl_pathnames.state_dir);
-}
-
-if (method == NULL) {
-method = g_strdup(virtio-serial);
-}
+ga_state = s;
-if (device_path == NULL) {
-if (strcmp(method, virtio-serial) == 0) {
-/* try the default path for the virtio-serial port */
-device_path = g_strdup(QGA_VIRTIO_PATH_DEFAULT);
-} else if (strcmp(method, isa-serial) == 0) {
-/* try the default path for the serial port - COM1 */
-device_path = g_strdup(QGA_SERIAL_PATH_DEFAULT);
-} else {
-g_critical(must specify a path for this channel);
-goto out_bad;
-}
-}
+g_log_set_default_handler(ga_log, s);
+g_log_set_fatal_mask(NULL, G_LOG_LEVEL_ERROR);
+ga_enable_logging(s);
#ifdef _WIN32
/* On win32 the state directory is application specific (be it the
default
@@ -1090,20 +1064,6 @@ int main(int argc, char **argv)
}
#endif
-s = g_malloc0(sizeof(GAState));
-s-log_level = log_level;
-s-log_file = stderr;
-#ifdef CONFIG_FSFREEZE
-s-fsfreeze_hook = fsfreeze_hook;
-#endif
-g_log_set_default_handler(ga_log, s);
-g_log_set_fatal_mask(NULL, G_LOG_LEVEL_ERROR);
-ga_enable_logging(s);
-s-state_filepath_isfrozen = g_strdup_printf(%s/qga.state.isfrozen,
- state_dir);
-s-pstate_filepath = g_strdup_printf(%s/qga.state, state_dir);
-s-frozen = false;
-
#ifndef _WIN32
/* check if a previous instance of qemu-ga exited with filesystems' state
* marked as frozen. this could be a stale value (a non-qemu-ga process
@@ -1154,7 +1114,7 @@ int main(int argc, char **argv)
if (!log_file) {
g_critical(unable to open specified log file: %s,
strerror(errno));
-goto out_bad;
+return EXIT_FAILURE;
}
s-log_file = log_file;
}
@@ -1165,7 +1125,7 @@ int main(int argc, char **argv)
s-pstate_filepath,
ga_is_frozen(s))) {
g_critical(failed to load persistent state);
-goto out_bad;
+return EXIT_FAILURE;
}
blacklist = ga_command_blacklist_init(blacklist);
@@ -1185,14 +1145,14 @@ int main(int argc, char **argv)
#ifndef _WIN32
if (!register_signal_handlers()) {
g_critical(failed to register signal handlers);
-goto out_bad;
+return EXIT_FAILURE;
}
#endif
s-main_loop = g_main_loop_new(NULL, false);
if (!channel_init(ga_state, method, device_path)) {
g_critical(failed to initialize guest agent channel);
-goto out_bad;
+return EXIT_FAILURE;
}
#ifndef _WIN32
g_main_loop_run(ga_state-main_loop);
@@ -1206,15 +1166,65 @@ int main(int argc, char **argv)
}
#endif
-ga_command_state_cleanup_all(ga_state-command_state);
-ga_channel_free(ga_state-channel);
+return EXIT_SUCCESS;
+}
-if (daemonize) {
-unlink(pid_filepath);
+int main(int argc, char **argv)
+{
+int ret = EXIT_SUCCESS;
+GAState *s = g_new0(GAState, 1);
+
+module_call_init(MODULE_INIT_QAPI);
+
+init_dfl_pathnames();
+option_parse(argc, argv);
+
+if (pid_filepath == NULL) {
+pid_filepath = g_strdup(dfl_pathnames.pidfile);
+}
+
+if (state_dir == NULL) {
+state_dir = g_strdup(dfl_pathnames.state_dir);
+}
+
+if (method == NULL) {
+method = g_strdup(virtio-serial);
+}
+
+if (device_path == NULL) {
+if (strcmp(method, virtio-serial) == 0) {
+/* try the default path for the virtio-serial port */
+device_path = g_strdup(QGA_VIRTIO_PATH_DEFAULT);
+} else if (strcmp(method, isa-serial) == 0) {
+/* try the default path for the serial port - COM1 */
+device_path = g_strdup(QGA_SERIAL_PATH_DEFAULT);
+} else {
+
Re: [Qemu-devel] [PATCH 10/12] qga: add --dump-conf option
Quoting Marc-André Lureau (2015-07-01 06:47:45)
This new option allows to review the agent configuration,
and ease the task of writing a configuration file.
Signed-off-by: Marc-André Lureau marcandre.lur...@gmail.com
---
qga/main.c | 46 +-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/qga/main.c b/qga/main.c
index bd87050..f6dbb3e 100644
--- a/qga/main.c
+++ b/qga/main.c
@@ -215,6 +215,7 @@ static void usage(const char *cmd)
#endif
-b, --blacklist comma-separated list of RPCs to disable (no spaces,
\?\\n
to list available RPCs)\n
+ -D, --dump-conf dump the configuration and exit\n
-h, --helpdisplay this help and exit\n
\n
Report bugs to mdr...@linux.vnet.ibm.com\n
@@ -904,6 +905,21 @@ static void ga_print_cmd(QmpCommand *cmd, void *opaque)
printf(%s\n, qmp_command_name(cmd));
}
+static gchar *list_join(GList *list, const gchar separator)
+{
+GString *str = g_string_new();
+
+while (list) {
+str = g_string_append(str, (gchar *)list-data);
+list = g_list_next(list);
+if (list) {
+str = g_string_append_c(str, separator);
+}
+}
+
+return g_string_free(str, FALSE);
+}
+
static GList *split_list(gchar *str, const gchar separator)
{
GList *list = NULL;
@@ -936,9 +952,28 @@ static char *state_dir;
static const char *service;
#endif
static GList *blacklist;
-static int daemonize;
+static int daemonize, dumpconf;
static GLogLevelFlags log_level = G_LOG_LEVEL_ERROR | G_LOG_LEVEL_CRITICAL;
+static void dump_config(void)
+{
+gchar *bl = list_join(blacklist, ',');
+
+printf([general]\n);
+printf(daemonize = %d\n, daemonize);
+printf(pidfile = %s\n, pid_filepath);
+if (log_filepath) {
+printf(logfile = %s\n, log_filepath);
+}
+printf(verbose = %d\n, log_level == G_LOG_LEVEL_MASK);
+printf(method = %s\n, method);
+printf(path = %s\n, device_path);
+printf(statedir = %s\n, state_dir);
+printf(blacklist = %s\n, bl);
I think we're missing fsfreeze_hook option here.
To me it seems cleaner to actually create the GKeyFile from current
options, then let GLib do all the work of generation a config file
we can spit out (g_key_file_to_data() should do it i think).
That, paired with the idea of having a GAConfig structure to
encapulate all the config options, might warrant restructuring
things a bit so that we have a
gkeyfile_to_gaconfig()/gkeyfile_from_gaconfig() pair to use for
reading/dumping configs while keeping all the options in an
easily trackable place.
+
+g_free(bl);
+}
+
static void option_parse(int argc, char **argv)
{
const char *sopt = hVvdm:p:l:f:F::b:s:t:D;
@@ -946,6 +981,7 @@ static void option_parse(int argc, char **argv)
const struct option lopt[] = {
{ help, 0, NULL, 'h' },
{ version, 0, NULL, 'V' },
+{ dump-conf, 0, NULL, 'D' },
{ logfile, 1, NULL, 'l' },
{ pidfile, 1, NULL, 'f' },
#ifdef CONFIG_FSFREEZE
@@ -1031,6 +1067,9 @@ static void option_parse(int argc, char **argv)
}
break;
#endif
+case 'D':
+dumpconf = 1;
+break;
case 'h':
usage(argv[0]);
exit(EXIT_SUCCESS);
@@ -1205,6 +1244,11 @@ int main(int argc, char **argv)
}
}
+if (dumpconf) {
+dump_config();
+goto end;
+}
+
s-log_level = log_level;
s-log_file = stderr;
#ifdef CONFIG_FSFREEZE
--
2.4.3
[Qemu-devel] [PATCH v2 0/2] qom: Fix misuse of Error API
v1 was posted for possible inclusion into 2.4, but the maintainer didn't bite ;-) v2: * Commit messages updated. Markus Armbruster (2): qom: Do not reuse errp after a possible error qom: Fix invalid error check in property_get_str() qom/object.c | 53 +++-- 1 file changed, 43 insertions(+), 10 deletions(-) -- 2.4.3
[Qemu-devel] [PATCH v2 1/2] qom: Do not reuse errp after a possible error
The argument for an Error **errp parameter must point to a null
pointer. If it doesn't, and an error happens, error_set() fails its
assertion.
Instead of
foo(foos, errp);
bar(bars, errp);
you need to do something like
Error *err = NULL;
foo(foos, err);
if (err) {
error_propagate(errp, err);
goto out;
}
bar(bars, errp);
out:
Screwed up in commit 0e55884 (v1.3.0): property_get_bool().
Screwed up in commit 1f21772 (v2.1.0): object_property_get_enum() and
object_property_get_uint16List().
Screwed up in commit a8e3fbe (v2.4.0): property_get_enum(),
property_set_enum().
Found by inspection, no actual crashes observed.
Fix them up.
Cc: Andreas Färber afaer...@suse.de
Cc: Anthony Liguori anth...@codemonkey.ws
Cc: Hu Tao hu...@cn.fujitsu.com
Cc: Daniel P. Berrange berra...@redhat.com
Signed-off-by: Markus Armbruster arm...@redhat.com
Reviewed-by: Daniel P. Berrange berra...@redhat.com
---
qom/object.c | 41 +++--
1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/qom/object.c b/qom/object.c
index eea8edf..6173da8 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -1079,6 +1079,7 @@ typedef struct EnumProperty {
int object_property_get_enum(Object *obj, const char *name,
const char *typename, Error **errp)
{
+Error *err = NULL;
StringOutputVisitor *sov;
StringInputVisitor *siv;
char *str;
@@ -1100,7 +1101,12 @@ int object_property_get_enum(Object *obj, const char
*name,
enumprop = prop-opaque;
sov = string_output_visitor_new(false);
-object_property_get(obj, string_output_get_visitor(sov), name, errp);
+object_property_get(obj, string_output_get_visitor(sov), name, err);
+if (err) {
+error_propagate(errp, err);
+string_output_visitor_cleanup(sov);
+return 0;
+}
str = string_output_get_string(sov);
siv = string_input_visitor_new(str);
string_output_visitor_cleanup(sov);
@@ -1116,21 +1122,27 @@ int object_property_get_enum(Object *obj, const char
*name,
void object_property_get_uint16List(Object *obj, const char *name,
uint16List **list, Error **errp)
{
+Error *err = NULL;
StringOutputVisitor *ov;
StringInputVisitor *iv;
char *str;
ov = string_output_visitor_new(false);
object_property_get(obj, string_output_get_visitor(ov),
-name, errp);
+name, err);
+if (err) {
+error_propagate(errp, err);
+goto out;
+}
str = string_output_get_string(ov);
iv = string_input_visitor_new(str);
visit_type_uint16List(string_input_get_visitor(iv),
list, NULL, errp);
g_free(str);
-string_output_visitor_cleanup(ov);
string_input_visitor_cleanup(iv);
+out:
+string_output_visitor_cleanup(ov);
}
void object_property_parse(Object *obj, const char *string,
@@ -1644,10 +1656,16 @@ typedef struct BoolProperty
static void property_get_bool(Object *obj, Visitor *v, void *opaque,
const char *name, Error **errp)
{
+Error *err = NULL;
BoolProperty *prop = opaque;
bool value;
-value = prop-get(obj, errp);
+value = prop-get(obj, err);
+if (err) {
+error_propagate(errp, err);
+return;
+}
+
visit_type_bool(v, value, name, errp);
}
@@ -1699,20 +1717,31 @@ void object_property_add_bool(Object *obj, const char
*name,
static void property_get_enum(Object *obj, Visitor *v, void *opaque,
const char *name, Error **errp)
{
+Error *err = NULL;
EnumProperty *prop = opaque;
int value;
-value = prop-get(obj, errp);
+value = prop-get(obj, err);
+if (err) {
+error_propagate(errp, err);
+return;
+}
+
visit_type_enum(v, value, prop-strings, NULL, name, errp);
}
static void property_set_enum(Object *obj, Visitor *v, void *opaque,
const char *name, Error **errp)
{
+Error *err = NULL;
EnumProperty *prop = opaque;
int value;
-visit_type_enum(v, value, prop-strings, NULL, name, errp);
+visit_type_enum(v, value, prop-strings, NULL, name, err);
+if (err) {
+error_propagate(errp, err);
+return;
+}
prop-set(obj, value, errp);
}
--
2.4.3
Re: [Qemu-devel] [PATCH] qdev-monitor.c: Add device id generation
On Aug 25, 2015, at 11:33 AM, Peter Maydell wrote:
On 25 August 2015 at 16:25, Programmingkid programmingk...@gmail.com wrote:
On Aug 25, 2015, at 8:42 AM, Markus Armbruster wrote:
Eric Blake ebl...@redhat.com writes:
On 08/24/2015 12:53 PM, Programmingkid wrote:
+/* USB's max number of devices is 127. This number is 3 digits long. */
+#define MAX_NUM_DIGITS_FOR_USB_ID 3
This limit makes no sense to me.
The limit is used to decide how many characters the device_id string is
going to have.
Three digits would be 0 to 999 device ID's would be supported. I can't
imagine
anyone spending the time to add that many devices.
Arbitrary limits are often a bad idea, especially when
they're easy to avoid, as here.
Knowing QEMU's limits can save the user from crashes and other problems. There
is
only a finite amount of memory available to QEMU.
+/* Add one for '\0' character */
+char *device_id = (char *) malloc(sizeof(char) *
+MAX_NUM_DIGITS_FOR_USB_ID +
1);
+sprintf(device_id, %d, device_id_count++);
g_strdup_printf() is a lot nicer about avoiding the risk of arbitrary
overflow...
+dev-id = (const char *) device_id;
+
+/* if device_id_count = 10^MAX_NUM_DIGITS_FOR_USB_ID */
+if (device_id_count = pow(10, MAX_NUM_DIGITS_FOR_USB_ID)) {
+printf(Warning: Maximum number of device ID's
generated!\n\a);
+printf(Time for you to make your own device ID's.\n);
besides, printf() is probably the wrong way to do error reporting, and
we don't use \a BEL sequences anywhere else in qemu code.
+}
}
When device_id_count reaches the limit, you warn. Next time around, you
overrun the buffer. Not good.
I could change it so next time around, only the warning is displayed.
Eric is right, g_strdup_printf() is easier and safer.
If you say so. I have never heard of it myself.
It's a glib function. Glib has a lot of useful utility functions
for this kind of thing (and the general idea of have an
sprintf-alike which allocates the buffer for you has been
around long before glib came along). Note that HACKING says that
you shouldn't use 'malloc' anyway, but 'malloc and then sprintf
into the buffer' is a particular antipattern that will get picked
up on in code review.
Thank you very much for this info. Once the generated device ID
issue has been hammered down, I will make a new patch that
implements g_malloc and g_strdup_printf().
Re: [Qemu-devel] [PATCH v2 08/18] nvdimm: init backend memory mapping and config data area
On Fri, Aug 14, 2015 at 10:52:01PM +0800, Xiao Guangrong wrote:
The parameter @file is used as backed memory for NVDIMM which is
divided into two parts if @dataconfig is true:
s/dataconfig/configdata/
@@ -76,13 +109,87 @@ static void pc_nvdimm_init(Object *obj)
set_configdata, NULL);
}
+static uint64_t get_file_size(int fd)
+{
+struct stat stat_buf;
+uint64_t size;
+
+if (fstat(fd, stat_buf) 0) {
+return 0;
+}
+
+if (S_ISREG(stat_buf.st_mode)) {
+return stat_buf.st_size;
+}
+
+if (S_ISBLK(stat_buf.st_mode) !ioctl(fd, BLKGETSIZE64, size)) {
+return size;
+}
#ifdef __linux__ for ioctl(fd, BLKGETSIZE64, size)?
There is nothing Linux-specific about emulating NVDIMMs so this code
should compile on all platforms.
+
+return 0;
+}
+
static void pc_nvdimm_realize(DeviceState *dev, Error **errp)
{
PCNVDIMMDevice *nvdimm = PC_NVDIMM(dev);
+char name[512];
+void *buf;
+ram_addr_t addr;
+uint64_t size, nvdimm_size, config_size = MIN_CONFIG_DATA_SIZE;
+int fd;
if (!nvdimm-file) {
error_setg(errp, file property is not set);
}
Missing return here.
+
+fd = open(nvdimm-file, O_RDWR);
Does it make sense to support read-only NVDIMMs?
It could be handy for sharing a read-only file between unprivileged
guests. The permissions on the file would only allow read, not write.
+if (fd 0) {
+error_setg(errp, can not open %s, nvdimm-file);
s/can not/cannot/
+return;
+}
+
+size = get_file_size(fd);
+buf = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
I guess the user will want to choose between MAP_SHARED and MAP_PRIVATE.
This can be added in the future.
+if (buf == MAP_FAILED) {
+error_setg(errp, can not do mmap on %s, nvdimm-file);
+goto do_close;
+}
+
+nvdimm-config_data_size = config_size;
+if (nvdimm-configdata) {
+/* reserve MIN_CONFIGDATA_AREA_SIZE for configue data. */
+nvdimm_size = size - config_size;
+nvdimm-config_data_addr = buf + nvdimm_size;
+} else {
+nvdimm_size = size;
+nvdimm-config_data_addr = NULL;
+}
+
+if ((int64_t)nvdimm_size = 0) {
The error cases can be detected before mmap(2). That avoids the int64_t
cast and also avoids nvdimm_size underflow and the bogus
nvdimm-config_data_addr calculation above.
size = get_file_size(fd);
if (size == 0) {
error_setg(errp, empty file or unable to get file size);
goto do_close;
} else if (nvdimm-configdata size config_size) {{
error_setg(errp, file size is too small to store NVDIMM
configure data);
goto do_close;
}
+error_setg(errp, file size is too small to store NVDIMM
+ configure data);
+goto do_unmap;
+}
+
+addr = reserved_range_push(nvdimm_size);
+if (!addr) {
+error_setg(errp, do not have enough space for size %#lx.\n, size);
error_setg() messages must not have a newline at the end.
Please use %# PRIx64 instead of %#lx so compilation works on 32-bit
hosts where sizeof(long) == 4.
+goto do_unmap;
+}
+
+nvdimm-device_index = new_device_index();
+sprintf(name, NVDIMM-%d, nvdimm-device_index);
+memory_region_init_ram_ptr(nvdimm-mr, OBJECT(dev), name, nvdimm_size,
+ buf);
How is the autogenerated name used?
Why not just use pc-nvdimm.memory?
+vmstate_register_ram(nvdimm-mr, DEVICE(dev));
+memory_region_add_subregion(get_system_memory(), addr, nvdimm-mr);
+
+return;
fd is leaked.
[Qemu-devel] [PATCH v2 5/8] s390x: Dump-skeys hmp support
From: Jason J. Herne jjhe...@linux.vnet.ibm.com
Add dump-skeys command to the human monitor.
Reviewed-by: Thomas Huth th...@linux.vnet.ibm.com
Reviewed-by: David Hildenbrand d...@linux.vnet.ibm.com
Signed-off-by: Jason J. Herne jjhe...@linux.vnet.ibm.com
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
---
hmp-commands.hx | 16
hw/s390x/s390-skeys.c | 12
include/hw/s390x/storage-keys.h | 2 ++
monitor.c | 4
4 files changed, 34 insertions(+)
diff --git a/hmp-commands.hx b/hmp-commands.hx
index d3b7932..803ff91 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -1053,6 +1053,22 @@ gdb. Without -z|-l|-s, the dump format is ELF.
together with begin.
ETEXI
+#if defined(TARGET_S390X)
+{
+.name = dump-skeys,
+.args_type = filename:F,
+.params = ,
+.help = Save guest storage keys into file 'filename'.\n,
+.mhandler.cmd = hmp_dump_skeys,
+},
+#endif
+
+STEXI
+@item dump-skeys @var{filename}
+@findex dump-skeys
+Save guest storage keys to a file.
+ETEXI
+
{
.name = snapshot_blkdev,
.args_type = reuse:-n,device:B,snapshot-file:s?,format:s?,
diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c
index ebf6a54..f6a29ab 100644
--- a/hw/s390x/s390-skeys.c
+++ b/hw/s390x/s390-skeys.c
@@ -72,6 +72,18 @@ static void write_keys(QEMUFile *f, uint8_t *keys, uint64_t
startgfn,
g_free(buf);
}
+void hmp_dump_skeys(Monitor *mon, const QDict *qdict)
+{
+const char *filename = qdict_get_str(qdict, filename);
+Error *err = NULL;
+
+qmp_dump_skeys(filename, err);
+if (err) {
+monitor_printf(mon, %s\n, error_get_pretty(err));
+error_free(err);
+}
+}
+
void qmp_dump_skeys(const char *filename, Error **errp)
{
S390SKeysState *ss = s390_get_skeys_device();
diff --git a/include/hw/s390x/storage-keys.h b/include/hw/s390x/storage-keys.h
index cfd7da7..0d04f19 100644
--- a/include/hw/s390x/storage-keys.h
+++ b/include/hw/s390x/storage-keys.h
@@ -13,6 +13,7 @@
#define __S390_STORAGE_KEYS_H
#include hw/qdev.h
+#include monitor/monitor.h
#define TYPE_S390_SKEYS s390-skeys
#define S390_SKEYS(obj) \
@@ -52,4 +53,5 @@ void s390_skeys_init(void);
S390SKeysState *s390_get_skeys_device(void);
+void hmp_dump_skeys(Monitor *mon, const QDict *qdict);
#endif /* __S390_STORAGE_KEYS_H */
diff --git a/monitor.c b/monitor.c
index daa3d98..3deba38 100644
--- a/monitor.c
+++ b/monitor.c
@@ -82,6 +82,10 @@
#endif
#include hw/lm32/lm32_pic.h
+#if defined(TARGET_S390X)
+#include hw/s390x/storage-keys.h
+#endif
+
/*
* Supported types:
*
--
2.5.0
Re: [Qemu-devel] [PATCH] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt
On 18/08/2015 18:35, Petar Jovanovic wrote:
From: Petar Jovanovic petar.jovano...@imgtec.com
Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.
This seems to be correct starting from MIPS32R2, but I'm not sure about older
cores. Do we really want to remove the restrictions for them as well?
@@ -9839,7 +9837,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
opn = movn.d;
break;
case OPC_RECIP_D:
-check_cp1_64bitmode(ctx);
I think this needs check_cp1_registers() now, i.e. check for odd fpu register
access when Status.FR = 0.
{
TCGv_i64 fp0 = tcg_temp_new_i64();
@@ -9851,7 +9848,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
opn = recip.d;
break;
case OPC_RSQRT_D:
-check_cp1_64bitmode(ctx);
same
Thanks,
Leon
[Qemu-devel] [PATCH v2 2/2] qom: Fix invalid error check in property_get_str()
When a function returns a null pointer on error and only on error, you
can do
if (!foo(foos, errp)) {
... handle error ...
}
instead of the more cumbersome
Error *err = NULL;
if (!foo(foos, err)) {
error_propagate(errp, err);
... handle error ...
}
A StringProperty's getter, however, may return null on success! We
then fail to call visit_type_str().
Screwed up in 6a146eb, v1.1.
Fails tests/qom-test in my current, heavily hacked QAPI branch. No
reproducer for master known (but I didn't look hard).
Cc: Andreas Färber afaer...@suse.de
Cc: Anthony Liguori anth...@codemonkey.ws
Signed-off-by: Markus Armbruster arm...@redhat.com
Reviewed-by: Eric Blake ebl...@redhat.com
---
qom/object.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/qom/object.c b/qom/object.c
index 6173da8..4c4df55 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -1591,14 +1591,18 @@ typedef struct StringProperty
static void property_get_str(Object *obj, Visitor *v, void *opaque,
const char *name, Error **errp)
{
+Error *err = NULL;
StringProperty *prop = opaque;
char *value;
-value = prop-get(obj, errp);
-if (value) {
-visit_type_str(v, value, name, errp);
-g_free(value);
+value = prop-get(obj, err);
+if (err) {
+error_propagate(errp, err);
+return;
}
+
+visit_type_str(v, value, name, errp);
+g_free(value);
}
static void property_set_str(Object *obj, Visitor *v, void *opaque,
--
2.4.3
Re: [Qemu-devel] [PATCH 4/4] bsd-user: add helper to set current_cpu before cpu_loop()
On Mon, Aug 24, 2015 at 20:41:10 -0400, Emilio G. Cota wrote:
Note: cannot compile bsd-user here (linux), please compile-test.
Signed-off-by: Emilio G. Cota c...@braap.org
---
(snip)
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 5902614..751efd5 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -163,6 +163,12 @@ int get_osversion(void);
void fork_start(void);
void fork_end(int child);
+static inline void do_cpu_loop(CPUArchState *env)
+{
Here we should also call rcu_register_thread().
+current_cpu = ENV_GET_CPU(env);
+cpu_loop(env);
+}
Emilio
Re: [Qemu-devel] [PATCH] target-sparc: Store mmu index in TB flags
On 08/25/2015 07:37 AM, Dennis Luehring wrote: Am 25.08.2015 um 16:25 schrieb Richard Henderson: Er, no, it should. The primary vector by which I expect improvement is via not encoding dmmu.mmu_primary_context into the TB flags. I.e. ASI_DMMU, which sun4u certainly uses. The fact that the patch_also_ fixes a sun4v problem is secondary. please, can you(or someone else) give me a feedback about my tests/numbers - and the relevance of them - the stream benchmarks results seems to be worser then before and the compilespeed is just a little bit better - so i don't understand (at all) what problems are fixed or what is improved now The fact that stream degraded means that stream is unreliable as a benchmark. I suspect that if you simply run it N times with the exact same setup you'll see a very large variance in its runtime. This particular patch cannot possibly have degraded performance, as it could only result in a reduction, not expansion, of the number of TBs created. As to why stream should be unreliable, I have no clue. - the compilation test is still 180 times slower then on my host I'll have to compare that test vs an Alpha guest and see what I get. I only remember one factor of 10, not two... But you're right, it would be nice to put together a coherent set of benchmarks. Ideally, a guest kernel plus minimal ramdisk with the tests pre-loaded so that we can boot and run ./benchmark at the prompt. That's the sort of thing we can easily upload to the wiki and share. r~
Re: [Qemu-devel] [PATCH v6 1/8] scripts: Allow include stdint.h in virtio headers
On 24/08/15 14:03, Gavin Shan wrote:
This allows to include stdint.h in virtio header files. Otherwise,
scripts/update-linux-headers.sh fails when updating headers from
Linux 4.2.rc8 kernel. include/uapi/linux/virtio_ring.h starts to
include stdint.h from commit d768f32a (virtio: Fix typecast of
pointer in vring_init()).
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
scripts/update-linux-headers.sh | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index f0e830c..2fddf2e 100755
--- a/scripts/update-linux-headers.sh
+++ b/scripts/update-linux-headers.sh
@@ -37,7 +37,8 @@ cp_virtio() {
mkdir -p $to
for f in $virtio; do
if
-grep '#include' $f | grep -v -e 'linux/virtio' \
+grep '#include' $f | grep -v -e 'stdint' \
+ -e 'linux/virtio' \
-e 'linux/types' \
-e 'linux/if_ether' \
-e 'sys/' \
Reviewed-by: Thomas Huth th...@redhat.com
Re: [Qemu-devel] [PATCH] include/hw: field 'offset' in struct Property should be ptrdiff_t as int causes overflow
On 25 August 2015 at 15:17, Markus Armbruster arm...@redhat.com wrote: Stumbled over this while throwing away old mail. Andreas, what do you think? Seems right to me -- I suspect the original properties code was written with the assumption that the property field would be inside the device struct (and so offsets are small). The array properties code breaks that assumption by allocating a separate lump of memory with the properties in it; so now there's no guarantee that the two pointers being subtracted will be within 4G of each other. Reviewed-by: Peter Maydell peter.mayd...@linaro.org Arguably for consistency the 'arrayoffset' struct member should also be a ptrdiff_t, though our current uses of it are such that it'll always be within int range. -- PMM
Re: [Qemu-devel] [PULL 00/18] Queued TCG patches
On 24 August 2015 at 20:36, Richard Henderson r...@twiddle.net wrote: Third time's the charm, right? This time with the arm crash fixed, and two new patches from Laurent that came in just as I was preparing this rebase. r~ The following changes since commit a30878e708c2149ce07d709a8b62edd944628449: configure: Don't permit SDL or GTK on OSX (2015-08-19 20:29:30 +0100) are available in the git repository at: git://github.com/rth7680/qemu.git tags/pull-tcg-20150824 for you to fetch changes up to b76f21a70748b735d6ac84fec4bb9bdaafa339b1: linux-user: remove useless macros GUEST_BASE and RESERVED_VA (2015-08-24 11:14:30 -0700) queued tcg patches Applied, thanks. -- PMM
Re: [Qemu-devel] [PATCH v2 06/18] pc: implement NVDIMM device abstract
On Fri, Aug 14, 2015 at 10:51:59PM +0800, Xiao Guangrong wrote:
+static void set_file(Object *obj, const char *str, Error **errp)
+{
+PCNVDIMMDevice *nvdimm = PC_NVDIMM(obj);
+
+if (nvdimm-file) {
+g_free(nvdimm-file);
+}
g_free(NULL) is a nop so it's safe to replace the if with just
g_free(nvdimm-file).
Re: [Qemu-devel] [PATCH] target-sparc: Store mmu index in TB flags
Am 25.08.2015 um 16:25 schrieb Richard Henderson: Er, no, it should. The primary vector by which I expect improvement is via not encoding dmmu.mmu_primary_context into the TB flags. I.e. ASI_DMMU, which sun4u certainly uses. The fact that the patch_also_ fixes a sun4v problem is secondary. please, can you(or someone else) give me a feedback about my tests/numbers - and the relevance of them - the stream benchmarks results seems to be worser then before and the compilespeed is just a little bit better - so i don't understand (at all) what problems are fixed or what is improved now - the compilation test is still 180 times slower then on my host
Re: [Qemu-devel] qemu-doc.texi: Improve USB documentation... and maybe even QEMU also
On Aug 25, 2015, at 3:43 AM, Markus Armbruster wrote:
Programmingkid programmingk...@gmail.com writes:
On Aug 24, 2015, at 12:38 PM, Markus Armbruster wrote:
Programmingkid programmingk...@gmail.com writes:
On Aug 24, 2015, at 5:45 AM, Markus Armbruster wrote:
Copying the USB maintainer.
Programmingkid programmingk...@gmail.com writes:
On Aug 8, 2015, at 8:48 AM, Programmingkid wrote:
On Aug 8, 2015, at 2:04 AM, Markus Armbruster wrote:
USB devices can be connected with the @option{-usbdevice}
commandline option
-or the @code{usb_add} monitor command. Available devices are:
+or the @code{usb_add} monitor command. Note: some devices may
only work if
+added like this: -usb -device usb device. Available devices are:
I'm afraid may only work is a bit misleading. All of them work with
-device. Old ones are also supported by -usbdevice for backward
compatibility. The whole section should be rewritten to point to
-device instead of legacy -usbdevice, but that's no reason to hold up
your patch.
I did not know -usbdevice was considered legacy. If that is the
case, then it should probably
be removed from the documentation in favor for -usb -device
device name.
Right now using -usb -device mouse doesn't work.
You need to say -device usb-mouse. See docs/qdev-device-use.txt. Does
it work for you when you do that?
It does. Thank you for this information.
My pleasure.
Neither does
-usbdevice usb-audio.
Yes. Legacy -usbdevice only supports the devices that predate -device.
I think we can all agree that consistency among all the USB devices is
a good thing.
Should all USB devices be added like this: -usb -device device name ?
Should is perhaps a bit strong. While -device is the recommended way
to add a USB device, -usbdevice is still a supported (if legacy) way to
do it.
Of course, supported, but legacy interfaces such as -usbdevice may
become deprecated, and then you should really move to newer interfaces,
because deprecated ones may go away. Doesn't look terribly probable to
me for -usbdevice, though.
This is an experimental patch of not how QEMU currently works, but how
I think it should work.
This documentation adds an usb_remove monitor command. This isn't
available right now,
but a patch could be made to change this. Any suggestions or additions
are welcomed.
Why do you think we need usb_remove in addition to device_del?
Ok. usb_remove isn't needed. Why is it that device_add usb-kbd works, but
device_del usb-kbd doesn't work? I am given this error message:
Device 'usb-kbd' not found.
device_del's argument isn't a driver, it's a device ID. Try this:
(qemu) device_add usb-mouse,id=mouse0
(qemu) info usb
Device 0.0, Port 1, Speed 12 Mb/s, Product QEMU USB Mouse
(qemu) device_del mouse0
(qemu) info usb
(qemu)
The problem is with info usb. It doesn't print the id you gave it. I
will make a patch that
will print the id's.
Yes, info usb doesn't show the qdev ID. Neither does info pci.
info qom and info qtree do.
It sounds like these info's could use some improving...
[Qemu-devel] [PULL 04/20] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only
two which we had implemented the 32-bit Secure equivalents of but
not the 64-bit Secure versions.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1438281398-18746-2-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1568aa6..749749e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1022,6 +1022,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
.resetvalue = 0 },
+{ .name = MAIR_EL3, .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
+ .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
+ .resetvalue = 0 },
/* For non-long-descriptor page tables these are PRRR and NMRR;
* regardless they still act as reads-as-written for QEMU.
*/
@@ -3089,6 +3093,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
+{ .name = TPIDR_EL3, .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
+ .access = PL3_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
REGINFO_SENTINEL
};
--
1.9.1
[Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operations
Implement the AArch32 ATS1H* operations which perform
Hyp mode stage 1 translations.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1437751263-21913-6-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4b2fc090..6c55cc4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1849,6 +1849,17 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
+static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
+{
+int access_type = ri-opc2 1;
+uint64_t par64;
+
+par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
+
+A32_BANKED_CURRENT_REG_SET(env, par, par64);
+}
+
static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (arm_current_el(env) == 3 !(env-cp15.scr_el3 SCR_NS)) {
@@ -3066,6 +3077,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
.access = PL2_W, .accessfn = at_s1e2_access,
.type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+/* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
+ * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
+ * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
+ * to behave as if SCR.NS was 1.
+ */
+{ .name = ATS1HR, .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
+ .access = PL2_W,
+ .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
+{ .name = ATS1HW, .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
+ .access = PL2_W,
+ .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
{ .name = CNTHCTL_EL2, .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
/* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
--
1.9.1
[Qemu-devel] [PULL 17/20] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
Now we have the ability to flush the TLB only for specific MMU indexes,
update the AArch64 TLB maintenance instruction implementations to only
flush the parts of the TLB they need to, rather than doing full flushes.
We take the opportunity to remove some duplicate functions (the per-asid
tlb ops work like the non-per-asid ones because we don't support
flushing a TLB only by ASID) and to bring the function names in line
with the architectural TLBI operation names.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1439548879-1972-4-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 172 +++-
1 file changed, 129 insertions(+), 43 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index becc6f8..c8d07d9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2507,65 +2507,151 @@ static CPAccessResult aa64_cacheop_access(CPUARMState
*env,
* Page D4-1736 (DDI0487A.b)
*/
-static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
+static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
{
-/* Invalidate by VA (AArch64 version) */
ARMCPU *cpu = arm_env_get_cpu(env);
-uint64_t pageaddr = sextract64(value 12, 0, 56);
+CPUState *cs = CPU(cpu);
-tlb_flush_page(CPU(cpu), pageaddr);
+if (arm_is_secure_below_el3(env)) {
+tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
+} else {
+tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
+}
}
-static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
-uint64_t value)
+static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
{
-/* Invalidate by VA, all ASIDs (AArch64 version) */
-ARMCPU *cpu = arm_env_get_cpu(env);
-uint64_t pageaddr = sextract64(value 12, 0, 56);
+bool sec = arm_is_secure_below_el3(env);
+CPUState *other_cs;
-tlb_flush_page(CPU(cpu), pageaddr);
+CPU_FOREACH(other_cs) {
+if (sec) {
+tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0,
-1);
+} else {
+tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
+ARMMMUIdx_S12NSE0, -1);
+}
+}
}
-static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
+static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
{
-/* Invalidate by ASID (AArch64 version) */
+/* Note that the 'ALL' scope must invalidate both stage 1 and
+ * stage 2 translations, whereas most other scopes only invalidate
+ * stage 1 translations.
+ */
ARMCPU *cpu = arm_env_get_cpu(env);
-int asid = extract64(value, 48, 16);
-tlb_flush(CPU(cpu), asid == 0);
+CPUState *cs = CPU(cpu);
+
+if (arm_is_secure_below_el3(env)) {
+tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
+} else {
+if (arm_feature(env, ARM_FEATURE_EL2)) {
+tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
+ARMMMUIdx_S2NS, -1);
+} else {
+tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
+}
+}
}
-static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ARMCPU *cpu = arm_env_get_cpu(env);
+CPUState *cs = CPU(cpu);
+
+tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
+}
+
+static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
+{
+/* Note that the 'ALL' scope must invalidate both stage 1 and
+ * stage 2 translations, whereas most other scopes only invalidate
+ * stage 1 translations.
+ */
+bool sec = arm_is_secure_below_el3(env);
+bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
CPUState *other_cs;
-uint64_t pageaddr = sextract64(value 12, 0, 56);
CPU_FOREACH(other_cs) {
-tlb_flush_page(other_cs, pageaddr);
+if (sec) {
+tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0,
-1);
+} else if (has_el2) {
+tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
+ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
+} else {
+tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
+ARMMMUIdx_S12NSE0, -1);
+}
}
}
-static void
Re: [Qemu-devel] [PATCH v6 3/8] scripts: Submit changes while updating linux headers
On 25 August 2015 at 00:58, Gavin Shan gws...@linux.vnet.ibm.com wrote: On Mon, Aug 24, 2015 at 03:08:33PM +0100, Peter Maydell wrote: On 24 August 2015 at 13:03, Gavin Shan gws...@linux.vnet.ibm.com wrote: +cd $to +name=$(git config --get user.name) +email=$(git config --get user.email) +git commit -a -m $subject -m $message -m Signed-off-by: $name $email Is git commit's --signoff option not present on all the git versions we care about? We needn't care about if user.name and user.email are existing or not. If they're invalid, the commit log needs to be fixed manually. Or just to give explicit message like below to remind users to fix it? Anyway, the commit log isn't complete without correct name/email in SOB if I'm correct. name=$(git config --get user.name) email=$(git config --get user.email) if ! [ $name ]; then name=FIXME fi if ! [ '$(echo $email | grep -v -e '@' /dev/null)' ]; then email=FIXME fi My point is that you appear to be manually reimplementing the built in git commit function for adding the SOB line, and you haven't explained why you need to do that. thanks -- PMM
[Qemu-devel] [PULL 16/20] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the
whole set of AArch64 TLBI regdefs is arranged in numeric order.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1439548879-1972-3-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6c55cc4..becc6f8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2701,14 +2701,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
.access = PL1_W, .type = ARM_CP_NOP },
/* TLBI operations */
-{ .name = TLBI_ALLE1, .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
- .access = PL2_W, .type = ARM_CP_NO_RAW,
- .writefn = tlbiall_write },
-{ .name = TLBI_ALLE1IS, .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
- .access = PL2_W, .type = ARM_CP_NO_RAW,
- .writefn = tlbiall_is_write },
{ .name = TLBI_VMALLE1IS, .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NO_RAW,
@@ -2757,6 +2749,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
.access = PL1_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vaa_write },
+{ .name = TLBI_ALLE1IS, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbiall_is_write },
+{ .name = TLBI_ALLE1, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbiall_write },
#ifndef CONFIG_USER_ONLY
/* 64 bit address translation operations */
{ .name = AT_S1E1R, .state = ARM_CP_STATE_AA64,
--
1.9.1
Re: [Qemu-devel] [PATCH v6 6/8] sPAPR: Introduce rtas_ldq()
On 24/08/15 14:03, Gavin Shan wrote: This introduces rtas_ldq() to load 64-bits parameter from continuous two 4-bytes memory chunk of RTAS parameter buffer, to simplify the code. Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com --- hw/ppc/spapr_pci.c | 20 ++-- include/hw/ppc/spapr.h | 5 + 2 files changed, 15 insertions(+), 10 deletions(-) Reviewed-by: Thomas Huth th...@redhat.com
[Qemu-devel] [PULL 13/20] smbios: add smbios 3.0 support
From: Wei Huang w...@redhat.com
This patch adds support for SMBIOS 3.0 entry point. When caller invokes
smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
smbios_get_tables() will return the entry point table in right format.
Acked-by: Gabriel Somlo so...@cmu.edu
Tested-by: Gabriel Somlo so...@cmu.edu
Tested-by: Leif Lindholm leif.lindh...@linaro.org
Signed-off-by: Wei Huang w...@redhat.com
Reviewed-by: Laszlo Ersek ler...@redhat.com
Message-id: 1439485767-20259-2-git-send-email-...@redhat.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/i386/pc_piix.c | 3 +-
hw/i386/pc_q35.c | 3 +-
hw/smbios/smbios.c | 84 +-
include/hw/smbios/smbios.h | 51
4 files changed, 102 insertions(+), 39 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 9558467..b82921d 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -173,7 +173,8 @@ static void pc_init1(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
/* These values are guest ABI, do not change */
smbios_set_defaults(QEMU, Standard PC (i440FX + PIIX, 1996),
-mc-name, smbios_legacy_mode, smbios_uuid_encoded);
+mc-name, smbios_legacy_mode, smbios_uuid_encoded,
+SMBIOS_ENTRY_POINT_21);
}
/* allocate ram and load rom/bios */
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index c07d65b..7217cbf 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -165,7 +165,8 @@ static void pc_q35_init(MachineState *machine)
if (smbios_defaults) {
/* These values are guest ABI, do not change */
smbios_set_defaults(QEMU, Standard PC (Q35 + ICH9, 2009),
-mc-name, smbios_legacy_mode, smbios_uuid_encoded);
+mc-name, smbios_legacy_mode, smbios_uuid_encoded,
+SMBIOS_ENTRY_POINT_21);
}
/* allocate ram and load rom/bios */
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index efdbb5d..b81a1d3 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -55,7 +55,9 @@ static uint8_t *smbios_tables;
static size_t smbios_tables_len;
static unsigned smbios_table_max;
static unsigned smbios_table_cnt;
-static struct smbios_entry_point ep;
+static SmbiosEntryPointType smbios_ep_type = SMBIOS_ENTRY_POINT_21;
+
+static SmbiosEntryPoint ep;
static int smbios_type4_count = 0;
static bool smbios_immutable;
@@ -771,11 +773,12 @@ void smbios_set_cpuid(uint32_t version, uint32_t features)
void smbios_set_defaults(const char *manufacturer, const char *product,
const char *version, bool legacy_mode,
- bool uuid_encoded)
+ bool uuid_encoded, SmbiosEntryPointType ep_type)
{
smbios_have_defaults = true;
smbios_legacy = legacy_mode;
smbios_uuid_encoded = uuid_encoded;
+smbios_ep_type = ep_type;
/* drop unwanted version of command-line file blob(s) */
if (smbios_legacy) {
@@ -808,26 +811,53 @@ void smbios_set_defaults(const char *manufacturer, const
char *product,
static void smbios_entry_point_setup(void)
{
-memcpy(ep.anchor_string, _SM_, 4);
-memcpy(ep.intermediate_anchor_string, _DMI_, 5);
-ep.length = sizeof(struct smbios_entry_point);
-ep.entry_point_revision = 0; /* formatted_area reserved, per spec v2.1+ */
-memset(ep.formatted_area, 0, 5);
-
-/* compliant with smbios spec v2.8 */
-ep.smbios_major_version = 2;
-ep.smbios_minor_version = 8;
-ep.smbios_bcd_revision = 0x28;
-
-/* set during table construction, but BIOS may override: */
-ep.structure_table_length = cpu_to_le16(smbios_tables_len);
-ep.max_structure_size = cpu_to_le16(smbios_table_max);
-ep.number_of_structures = cpu_to_le16(smbios_table_cnt);
-
-/* BIOS must recalculate: */
-ep.checksum = 0;
-ep.intermediate_checksum = 0;
-ep.structure_table_address = cpu_to_le32(0);
+switch (smbios_ep_type) {
+case SMBIOS_ENTRY_POINT_21:
+memcpy(ep.ep21.anchor_string, _SM_, 4);
+memcpy(ep.ep21.intermediate_anchor_string, _DMI_, 5);
+ep.ep21.length = sizeof(struct smbios_21_entry_point);
+ep.ep21.entry_point_revision = 0; /* formatted_area reserved */
+memset(ep.ep21.formatted_area, 0, 5);
+
+/* compliant with smbios spec v2.8 */
+ep.ep21.smbios_major_version = 2;
+ep.ep21.smbios_minor_version = 8;
+ep.ep21.smbios_bcd_revision = 0x28;
+
+/* set during table construction, but BIOS may override: */
+ep.ep21.structure_table_length = cpu_to_le16(smbios_tables_len);
+ep.ep21.max_structure_size = cpu_to_le16(smbios_table_max);
+ep.ep21.number_of_structures = cpu_to_le16(smbios_table_cnt);
+
+/* BIOS must recalculate */
+
Re: [Qemu-devel] [PATCH v11 5/5] hw/arm/virt: Add gic-version option to virt machine
Hello! In KVM case instead of assigning GICv2 as default, can we probe the KVM for GICv3 presence using KVM_CREATE_DEVICE_TEST and give priority to GICv3? We could, but i think this would hurt usability. I suggest that when the user chooses a configuration, he/she expects to get something particular. And IMHO it's much better to default to GICv2 (to be backwards-compatible), and just report error in case if this is not supported by KVM, than to default to something, which is different on different machines and different kernels. Libvirt guys already blame virt machine for being too flexible... Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia
[Qemu-devel] KVM guest gets aborted if blockcommit is called
Hello,
I wrote this mail to the qemu-discuss mailing list, but today I am unsure, if I
chose the right list. So I copy and paste this mail here in hope someone can
respond :-)
I have reproducable problems with some code in qemu-coroutine.c:
void qemu_coroutine_enter(Coroutine *co, void *opaque)
{
Coroutine *self = qemu_coroutine_self();
CoroutineAction ret;
trace_qemu_coroutine_enter(self, co, opaque);
if (co-caller) {
fprintf(stderr, Co-routine re-entered recursively\n);
abort(); — This one triggers 4 or 5 out of ten tests to use
the blockcommit feature
}
Unfortunately a normal system administrator like me does not understand the
error message. I have no idea what causes it nor how to prevent it. Or if this
is just a bug ;-)
Original mail to qemu-discuss:
-
I spent now full five days to debug a major problem with backing up VMs. I run
a HP ProLiant Server SE316M1-R2 aka DL160G6) with two Xeon L5520 and 48GB RAM
tripple channel. On this server I do monitoring and Qemu/libvirt. I run 7
guests on this server, which runs with Gentoo Linux (hardened; Grsecurity
patched kernel, PaX, no RBAC).
All guests use raw images as disks (also tested QED and QCOW2). The systems are
all Gentoo and Ubuntu. All having qemu-guest-agent running.
app-emulation/libvirt-1.2.18-r1::gentoo was built with the following:
USE=caps fuse iscsi libvirtd lvm lxc macvtap nfs nls parted pcap qemu sasl
systemd udev vepa -apparmor -audit -avahi -firewalld -glusterfs -numa -openvz
-phyp -policykit -rbd (-selinux) -uml -virt-network -virtualbox
(-wireshark-plugins) -xen
app-emulation/qemu-2.4.0::gentoo was built with the following:
USE=aio caps curl fdt filecaps jpeg ncurses nls pin-upstream-blobs png python
sasl seccomp spice ssh threads tls uuid vhost-net vnc xattr -accessibility
-alsa -bluetooth -debug -glusterfs -gtk -gtk2 -infiniband -iscsi -lzo -nfs
-numa -opengl -pulseaudio -rbd -sdl -sdl2 (-selinux) -smartcard -snappy -static
-static-softmmu -static-user -systemtap -tci -test -usb -usbredir -vde -virtfs
-vte -xen -xfs PYTHON_TARGETS=python2_7 QEMU_SOFTMMU_TARGETS=i386 x86_64
-aarch64 (-alpha) (-arm) -cris -lm32 (-m68k) -microblaze -microblazeel (-mips)
-mips64 -mips64el -mipsel -moxie -or32 (-ppc) (-ppc64) -ppcemb -s390x -sh4
-sh4eb (-sparc) -sparc64 -unicore32 -xtensa -xtensaeb QEMU_USER_TARGETS=i386
x86_64 -aarch64 (-alpha) (-arm) -armeb -cris (-m68k) -microblaze -microblazeel
(-mips) -mips64 -mips64el -mipsel -mipsn32 -mipsn32el -or32 (-ppc) (-ppc64)
-ppc64abi32 -s390x -sh4 -sh4eb (-sparc) -sparc32plus -sparc64 -unicore32
I wrote a bash script hat shall backup all guests. It works like this:
1. Create external snapshot
2. Copy/rsync away the image
3. blockcommit snapshot
4. blockjob pivot
5. Copy/rsync away the XML description for the guest
6. Remove Snapshot file
I did some test running the script in a cron job. For this I found out that
copying the image file takes round about 15 minutes. So I did a 30 minute cycle
for the script.
4 or 5 cycles work perfectly. (1) and (2) are working and when it comes to
blockcommit, the guest may (random) be aborted and the command fails to
continue, because the guest is no longer running. Starting the guest again, I
found two situations:
1. I can directly call blockjob … —pivot, because the last blockcommit that
failed reached 100%, or
2. Run a blockjob abort action. Re-sync and pivot on command line and that
might work.
Anyways, blockcommit is not stable here. I tested this on qemu-2.3.0 and 2.4.0
In the logs I only get this:
…
2015-08-24 18:38:13.077+: starting up libvirt version: 1.2.18, qemu
version: 2.4.0
LC_ALL=C PATH=/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
QEMU_AUDIO_DRV=none /usr/bin/qemu-system-x86_64 -name mx.roessner-net.de
http://mx.roessner-net.de/-TESTING -S -machine
pc-i440fx-2.1,accel=kvm,usb=off -cpu qemu64,+kvm_pv_eoi -m 4096 -realtime
mlock=off -smp 4,sockets=4,cores=1,threads=1 -uuid
d86b82d5-153f-4dd9-aa66-d98c2e65db8c -no-user-config -nodefaults -device sga
-chardev socket,id=charmonitor,path=/var/lib/libvirt/qemu/mx.roessner-net.de
http://mx.roessner-net.de/-TESTING.monitor,server,nowait -mon
chardev=charmonitor,id=monitor,mode=control -rtc base=utc,driftfix=slew -global
kvm-pit.lost_tick_policy=discard -no-shutdown -boot order=cd,menu=on,strict=on
-device piix3-usb-uhci,id=usb,bus=pci.0,addr=0x1.0x2 -device
virtio-serial-pci,id=virtio-serial0,bus=pci.0,addr=0x8 -drive
file=/var/lib/libvirt/images/mx.roessner-net.de
http://mx.roessner-net.de/-TESTING.img,if=none,id=drive-virtio-disk0,format=raw,cache=writeback
-device
virtio-blk-pci,scsi=off,bus=pci.0,addr=0x4,drive=drive-virtio-disk0,id=virtio-disk0
-drive if=none,id=drive-ide0-1-0,readonly=on,format=raw -device
ide-cd,bus=ide.1,unit=0,drive=drive-ide0-1-0,id=ide0-1-0 -netdev
Re: [Qemu-devel] [PATCH v6 7/8] sPAPR: Support RTAS call ibm, {open, close}-errinjct
On 24/08/15 14:03, Gavin Shan wrote:
This supports RTAS calls ibm,{open,close}-errinjct to manupliate
the token, which is passed to RTAS call ibm,errinjct to indicate
the valid context for error injection. Each VM is permitted to have
only one token at once and we simply have sequential number for that.
It's notable that the least bit of the token is reserved to indicate
if the token has been opened, meaning the valid token should be always
odd.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
hw/ppc/spapr.c | 6 -
hw/ppc/spapr_rtas.c| 60
++
include/hw/ppc/spapr.h | 9 +++-
3 files changed, 73 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 06d000d..591a1a7 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1191,7 +1191,7 @@ static bool version_before_3(void *opaque, int
version_id)
static const VMStateDescription vmstate_spapr = {
.name = spapr,
-.version_id = 3,
+.version_id = 4,
.minimum_version_id = 1,
.post_load = spapr_post_load,
.fields = (VMStateField[]) {
@@ -1202,6 +1202,10 @@ static const VMStateDescription vmstate_spapr = {
VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
+
+/* Error injection token */
+VMSTATE_UINT32_V(errinjct_token, sPAPRMachineState, 4),
+
VMSTATE_END_OF_LIST()
},
};
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index e99e25f..64924c6 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -604,6 +604,62 @@ out:
rtas_st(rets, 0, rc);
}
+static void rtas_ibm_open_errinjct(PowerPCCPU *cpu,
+ sPAPRMachineState *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+int32_t ret;
+
+/* Sanity check on number of arguments */
+if (nargs != 0 || nret != 2) {
+ret = RTAS_OUT_PARAM_ERROR;
+goto out;
+}
+
+/* Check if we already had token */
+if (spapr-errinjct_token 1) {
+ret = RTAS_OUT_TOKEN_OPENED;
+goto out;
+}
+
+/* Grab the token */
+rtas_st(rets, 0, ++spapr-errinjct_token);
+ret = RTAS_OUT_SUCCESS;
+out:
+rtas_st(rets, 1, ret);
+}
+
+static void rtas_ibm_close_errinjct(PowerPCCPU *cpu,
+sPAPRMachineState *spapr,
+uint32_t token, uint32_t nargs,
+target_ulong args, uint32_t nret,
+target_ulong rets)
+{
+uint32_t open_token;
+int32_t ret;
+
+/* Sanity check on number of arguments */
+if (nargs != 1 || nret != 1) {
+ret = RTAS_OUT_PARAM_ERROR;
+goto out;
+}
+
+/* Match with the passed token */
+open_token = rtas_ld(args, 0);
+if (!(spapr-errinjct_token 1) ||
+spapr-errinjct_token != open_token) {
+ret = RTAS_OUT_CLOSE_ERROR;
+goto out;
+}
+
+spapr-errinjct_token++;
+ret = RTAS_OUT_SUCCESS;
+out:
+rtas_st(rets, 0, ret);
+}
This basically now looks fine to me! I am just wondering what happens
when the guest opens a token, but then resets the system before it
closes it again?
I.e. shouldn't the errinjct_token be set to 0 back again during the
reset handler?
Thomas
[Qemu-devel] [PULL 05/20] target-arm: Implement missing AMAIR registers
The AMAIR registers are for providing auxiliary implementation
defined memory attributes. We already implemented a RAZ/WI
AMAIR_EL1; add the EL2 and EL3 versions for consistency.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1438281398-18746-3-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 749749e..54f99ae 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2840,6 +2840,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = HMAIR1, .state = ARM_CP_STATE_AA32,
.opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = AMAIR_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+{ .name = HMAIR1, .state = ARM_CP_STATE_AA32,
+ .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
{ .name = TCR_EL2, .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2955,6 +2963,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_ALIAS,
.fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
+{ .name = AMAIR_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+/* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
+{ .name = HMAIR1, .state = ARM_CP_STATE_AA32,
+ .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
{ .name = TCR_EL2, .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
.access = PL2_RW, .writefn = vmsa_tcr_el1_write,
@@ -3097,6 +3114,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
.access = PL3_RW, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
+{ .name = AMAIR_EL3, .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
+ .access = PL3_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
REGINFO_SENTINEL
};
--
1.9.1
[Qemu-devel] [PULL 06/20] target-arm: Implement missing AFSR registers
The AFSR registers are implementation dependent auxiliary fault
status registers. We already implemented a RAZ/WI AFSR0_EL1 and
AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1438281398-18746-4-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 24
1 file changed, 24 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 54f99ae..f6119be 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2848,6 +2848,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
.opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST,
.resetvalue = 0 },
+{ .name = AFSR0_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+{ .name = AFSR1_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
{ .name = TCR_EL2, .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2972,6 +2980,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST,
.resetvalue = 0 },
+{ .name = AFSR0_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+{ .name = AFSR1_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
{ .name = TCR_EL2, .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
.access = PL2_RW, .writefn = vmsa_tcr_el1_write,
@@ -3118,6 +3134,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
.access = PL3_RW, .type = ARM_CP_CONST,
.resetvalue = 0 },
+{ .name = AFSR0_EL3, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
+ .access = PL3_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+{ .name = AFSR1_EL3, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
+ .access = PL3_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
REGINFO_SENTINEL
};
--
1.9.1
Re: [Qemu-devel] Should we auto-generate IDs? (was: [PATCH] qdev-monitor.c: Add device id generation)
On Aug 25, 2015, at 8:38 AM, Markus Armbruster wrote: You're proposing to revise a qdev design decision, namely the purpose of IDs. This has been discussed before, and IDs remained unchanged. Perhaps it's time to revisit this issue. Cc'ing a few more people. Relevant prior threads: * [PATCH] qdev: Reject duplicate and anti-social device IDs http://thread.gmane.org/gmane.comp.emulators.qemu/71230/focus=72272 * [PATCH 6/6] qdev: Generate IDs for anonymous devices http://thread.gmane.org/gmane.comp.emulators.qemu/114853/focus=114858 * [PATCH] qdev: Assign a default device ID when none is provided. http://thread.gmane.org/gmane.comp.emulators.qemu/249702 * IDs in QOM (was: [PATCH] util: Emancipate id_wellformed() from QemuOpt http://thread.gmane.org/gmane.comp.emulators.qemu/299945/focus=300381 Probably more I can't remember anymore :) Programmingkid programmingk...@gmail.com writes: Add device ID generation to each device if an ID isn't given. Signed-off-by: John Arbuckle programmingk...@gmail.com --- This patch can be tested by adding adding usb devices using the monitor. Start QEMU with the -usb option. Then go to the monitor and type device_add usb-mouse. The ID of the device will be set to a number. Since QEMU will not allow an user to add a device with an ID set to a number, there is no chance for ID collisions. The second sentence should really be part of your commit message. The first sentence wouldn't hurt, either. Ok. Another useful addition would be *why* you want generated IDs. I believe you do because you need them for device_del. Sounds like a good idea. In prior discussion, we always concluded that device_del should accept QOM paths. It still doesn't. Many things in QEMU have IDs. They all work pretty much the same: 1. The ID is set by the user. If the user doesn't, there is none. Exception: a few old interfaces set well-known IDs. If the user uses these interfaces, he needs to take care that his own IDs don't clash. Example: drive_add picks an ID based on interface type, media type, bus and unit number. blockdev_add doesn't. Instead, it requires the user to pick one. 2. The ID must be well-formed. Exception: inconsistently enforced for QOM, see last thread quoted above. This is a definite possibility. All USB devices could be given a id like this: USBnumber. All block devices could be HDnumber. 3. If the user may need to address the thing, either the ID must be mandatory, or there has to be another way to address it. Example: netdev-add requires ID. Rationale: the only way to put it to use is referencing it from a device, and that requires an ID. Example: device_add doesn't require ID. If you don't specify one, you can't device_del it. Annoying trap for the unwary. There are *two* other ways to address it: qdev path and QOM path. qdev path is basically too botched to be usable. QOM path should do just fine, but device_del doesn't accept it. It could. After looking up what a QOM path looks like (/i440fx/slot[1.0]/bus/piix3/i8042/aux) I'm thinking that would not be a good idea. It is an awful lot to type. It isn't as user friendly as using something simple like USB1 or HD3. We could revise rule 1 to always generate IDs, in a way that can't clash with the user's IDs (impossible unless rule 2 is actually observed). I think if we follow the rule that only QEMU can give an ID that is only a number, we should be fine. That seems to be the rule now. Rule 3 then becomes moot. Whatever we do, I want it done consistently. I don't want different rules for different kinds of IDs. Agreed. Maybe we should include an easy and consistent way of finding out these ID's. Wow, didn't think this patch to fix USB device removal would have such consequences.
[Qemu-devel] [PULL 15/20] cputlb: Add functions for flushing TLB for a single MMU index
Guest CPU TLB maintenance operations may be sufficiently
specialized to only need to flush TLB entries corresponding
to a particular MMU index. Implement cputlb functions for
this, to avoid the inefficiency of flushing TLB entries
which we don't need to.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1439548879-1972-2-git-send-email-peter.mayd...@linaro.org
---
cputlb.c| 97 +
include/exec/exec-all.h | 47
2 files changed, 144 insertions(+)
diff --git a/cputlb.c b/cputlb.c
index a506086..4bc6c24 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -69,6 +69,47 @@ void tlb_flush(CPUState *cpu, int flush_global)
tlb_flush_count++;
}
+static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
+{
+CPUArchState *env = cpu-env_ptr;
+
+#if defined(DEBUG_TLB)
+printf(tlb_flush_by_mmuidx:);
+#endif
+/* must reset current TB so that interrupts cannot modify the
+ links while we are modifying them */
+cpu-current_tb = NULL;
+
+for (;;) {
+int mmu_idx = va_arg(argp, int);
+
+if (mmu_idx 0) {
+break;
+}
+
+#if defined(DEBUG_TLB)
+printf( %d, mmu_idx);
+#endif
+
+memset(env-tlb_table[mmu_idx], -1, sizeof(env-tlb_table[0]));
+memset(env-tlb_v_table[mmu_idx], -1, sizeof(env-tlb_v_table[0]));
+}
+
+#if defined(DEBUG_TLB)
+printf(\n);
+#endif
+
+memset(cpu-tb_jmp_cache, 0, sizeof(cpu-tb_jmp_cache));
+}
+
+void tlb_flush_by_mmuidx(CPUState *cpu, ...)
+{
+va_list argp;
+va_start(argp, cpu);
+v_tlb_flush_by_mmuidx(cpu, argp);
+va_end(argp);
+}
+
static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
{
if (addr == (tlb_entry-addr_read
@@ -121,6 +162,62 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
tb_flush_jmp_cache(cpu, addr);
}
+void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
+{
+CPUArchState *env = cpu-env_ptr;
+int i, k;
+va_list argp;
+
+va_start(argp, addr);
+
+#if defined(DEBUG_TLB)
+printf(tlb_flush_page_by_mmu_idx: TARGET_FMT_lx, addr);
+#endif
+/* Check if we need to flush due to large pages. */
+if ((addr env-tlb_flush_mask) == env-tlb_flush_addr) {
+#if defined(DEBUG_TLB)
+printf( forced full flush (
+ TARGET_FMT_lx / TARGET_FMT_lx )\n,
+ env-tlb_flush_addr, env-tlb_flush_mask);
+#endif
+v_tlb_flush_by_mmuidx(cpu, argp);
+va_end(argp);
+return;
+}
+/* must reset current TB so that interrupts cannot modify the
+ links while we are modifying them */
+cpu-current_tb = NULL;
+
+addr = TARGET_PAGE_MASK;
+i = (addr TARGET_PAGE_BITS) (CPU_TLB_SIZE - 1);
+
+for (;;) {
+int mmu_idx = va_arg(argp, int);
+
+if (mmu_idx 0) {
+break;
+}
+
+#if defined(DEBUG_TLB)
+printf( %d, mmu_idx);
+#endif
+
+tlb_flush_entry(env-tlb_table[mmu_idx][i], addr);
+
+/* check whether there are vltb entries that need to be flushed */
+for (k = 0; k CPU_VTLB_SIZE; k++) {
+tlb_flush_entry(env-tlb_v_table[mmu_idx][k], addr);
+}
+}
+va_end(argp);
+
+#if defined(DEBUG_TLB)
+printf(\n);
+#endif
+
+tb_flush_jmp_cache(cpu, addr);
+}
+
/* update the TLBs so that writes to code in the virtual page 'addr'
can be detected */
void tlb_protect_code(ram_addr_t ram_addr)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 29775c0..fbc6dcb 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -96,8 +96,46 @@ bool qemu_in_vcpu_thread(void);
void cpu_reload_memory_map(CPUState *cpu);
void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
+/**
+ * tlb_flush_page:
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of page to be flushed
+ *
+ * Flush one page from the TLB of the specified CPU, for all
+ * MMU indexes.
+ */
void tlb_flush_page(CPUState *cpu, target_ulong addr);
+/**
+ * tlb_flush:
+ * @cpu: CPU whose TLB should be flushed
+ * @flush_global: ignored
+ *
+ * Flush the entire TLB for the specified CPU.
+ * The flush_global flag is in theory an indicator of whether the whole
+ * TLB should be flushed, or only those entries not marked global.
+ * In practice QEMU does not implement any global/not global flag for
+ * TLB entries, and the argument is ignored.
+ */
void tlb_flush(CPUState *cpu, int flush_global);
+/**
+ * tlb_flush_page_by_mmuidx:
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of page to be flushed
+ * @...: list of MMU indexes to flush, terminated by a negative value
+ *
+ * Flush one page from the TLB of the specified CPU, for the specified
+ * MMU indexes.
+ */
+void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...);
+/**
+ *
Re: [Qemu-devel] [PATCH] include/hw: field 'offset' in struct Property should be ptrdiff_t as int causes overflow
Stumbled over this while throwing away old mail. Andreas, what do you
think?
Ildar Isaev i...@inbox.ru writes:
'offset' field in struct Property is calculated as a diff between two
pointers (hw/core/qdev-properties.c:802)
arrayprop-prop.offset = eltptr - (void *)dev;
If offset is declared as int, this subtraction can cause type overflow
thus leading to the fall of the subsequent assert
(hw/core/qdev-properties.c:803)
assert(qdev_get_prop_ptr(dev, arrayprop-prop) == eltptr);
So ptrdiff_t should be used instead
Signed-off-by: Ildar Isaev i...@inbox.ru
---
include/hw/qdev-core.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 4e673f9..f0e2a73 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -224,7 +224,7 @@ struct BusState {
struct Property {
const char *name;
PropertyInfo *info;
-int offset;
+ptrdiff_toffset;
uint8_t bitnr;
uint8_t qtype;
int64_t defval;
Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
On 08/25/2015 06:12 AM, Chen Gang wrote:
From: xili_gchen_5...@hotmail.com
To: r...@twiddle.net; qemu-devel@nongnu.org
CC: w...@tilera.com; cmetc...@ezchip.com; peter.mayd...@linaro.org
Subject: Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic
instructions
Date: Tue, 25 Aug 2015 21:11:11 +0800
On 8/25/15 12:15, Richard Henderson wrote:
On 08/24/2015 09:17 AM, Richard Henderson wrote:
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-tilegx/translate.c | 50 ++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 210e912..2a0798a 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -180,6 +180,19 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv
tsrcb,
tcg_temp_free(t0);
}
+static void gen_atomic_excp(DisasContext *dc, unsigned dest, unsigned srca,
+ unsigned srcb, TileExcp excp)
+{
+#ifdef CONFIG_USER_ONLY
+ TCGv_i32 t = tcg_const_i32((dest 16) | (srca 8) | srcb);
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, excparam));
+ tcg_temp_free_i32(t);
+ gen_exception(dc, excp);
+#else
+ gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
+#endif
+}
Originally, I used set_exception(), not gen_exception().
This is broken. While it does work well enough for Hello World, implementing a
non-trap instruction with an exception is extremely dicey for TileGX. The issue
is that TileGX bundles operate atomically, with no RAW issues between the
instructions of the bundle.
Consider a bundle like
{ add r0, r0, r1 ; exch r2, r0, r3 }
In Chen's implementation, the writeback to r0 would occur before the exception,
and so the exch would happen to the wrong address. In my implementation here,
the exception would occur before the writeback, and so the result of the add
would be discarded.
We use tmp regs for buffering the r0.
- calculate x1 pipe, and save result to r0 tmp reg.
Oh, typo, calculate x0 pipe, and save result to r0 tmp reg.
- exch the original r0 and r3 to r2 tmp reg.
- set exception flag (which will cause exception, later).
- save the result tmp regs to r0 or r2.
- gen exception.
Exactly. Now re-read what I wrote and see if you can spot the problem with
this.
r~
[Qemu-devel] Creating snapshots with specific runtime options
As far as I can see there's no way to create a snapshot and either a) inherit the runtime options from the original image b) specify a new set of options This comment in external_snapshot_prepare() before calling bdrv_open() suggests that the problem is known but the discussion was postponed. /* TODO Inherit bs-options or only take explicit options with an * extended QMP command? */ I would like to retake this and make it possible. I discussed it briefly with Stefan on IRC and he said that Kevin might have some ideas. In principle extending the QMP command sounds as simple as adding 'options': 'BlockdevOptions' to 'blockdev-snapshot-sync', but it's surely more complicated than that :) Is the 'BlockdevOptions' API even stable? Berto
Re: [Qemu-devel] [PATCH] qdev-monitor.c: Add device id generation
On Aug 24, 2015, at 6:21 PM, Eric Blake wrote:
On 08/24/2015 12:53 PM, Programmingkid wrote:
Add device ID generation to each device if an ID isn't given.
Signed-off-by: John Arbuckle programmingk...@gmail.com
---
dev-id = id;
+} else { /* create an id for a device if none is provided */
+static int device_id_count;
+
+/* Add one for '\0' character */
+char *device_id = (char *) malloc(sizeof(char) *
+MAX_NUM_DIGITS_FOR_USB_ID + 1);
+sprintf(device_id, %d, device_id_count++);
g_strdup_printf() is a lot nicer about avoiding the risk of arbitrary
overflow...
I prefer to use well known functions that work well, but I guess it shouldn't
be too
painful to use the g_strdup_printf() function. Do you really think there is a
possible
overflow condition here?
+dev-id = (const char *) device_id;
+
+/* if device_id_count = 10^MAX_NUM_DIGITS_FOR_USB_ID */
+if (device_id_count = pow(10, MAX_NUM_DIGITS_FOR_USB_ID)) {
+printf(Warning: Maximum number of device ID's generated!\n\a);
+printf(Time for you to make your own device ID's.\n);
besides, printf() is probably the wrong way to do error reporting, and
Why do you believe this?
we don't use \a BEL sequences anywhere else in qemu code.
Innovation has to start somewhere :)
+}
}
if (dev-id) {
This if would now be a dead check if your patch is applied.
I think you are right. It will be removed.
object_property_add_child(qdev_get_peripheral(), dev-id,
OBJECT(dev), NULL);
-} else {
-static int anon_count;
-gchar *name = g_strdup_printf(device[%d], anon_count++);
-object_property_add_child(qdev_get_peripheral_anon(), name,
- OBJECT(dev), NULL);
-g_free(name);
}
It looks like your goal was to move this code earlier, but you changed
enough aspects of it that I'm not sure what the right fix should be.
I didn't want to move the code. It just was in a condition that would never
be true, so I thought why keep it.
--
Eric Blake eblake redhat com+1-919-301-3266
Thank you very much for reviewing my patch.
Libvirt virtualization library http://libvirt.org
You work with this project? Any chance libvirt could support Mac OS X?
[Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops
Apply the correct conditions in the ats_access() function for
the ATS12NSO* address translation operations:
* succeed at EL2 or EL3
* normal UNDEF trap from NS EL1
* trap to EL3 from S EL1 (only possible if EL3 is AArch64)
(This change means they're now available in our EL3-supporting
CPUs when they would previously always UNDEF.)
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1437751263-21913-5-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8603660..4b2fc090 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1719,12 +1719,17 @@ static void par_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (ri-opc2 4) {
-/* Other states are only available with TrustZone; in
- * a non-TZ implementation these registers don't exist
- * at all, which is an Uncategorized trap. This underdecoding
- * is safe because the reginfo is NO_RAW.
+/* The ATS12NSO* operations must trap to EL3 if executed in
+ * Secure EL1 (which can only happen if EL3 is AArch64).
+ * They are simply UNDEF if executed from NS EL1.
+ * They function normally from EL2 or EL3.
*/
-return CP_ACCESS_TRAP_UNCATEGORIZED;
+if (arm_current_el(env) == 1) {
+if (arm_is_secure_below_el3(env)) {
+return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
+}
+return CP_ACCESS_TRAP_UNCATEGORIZED;
+}
}
return CP_ACCESS_OK;
}
@@ -1899,6 +1904,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
offsetoflow32(CPUARMState, cp15.par_ns) },
.writefn = par_write },
#ifndef CONFIG_USER_ONLY
+/* This underdecoding is safe because the reginfo is NO_RAW. */
{ .name = ATS, .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_W, .accessfn = ats_access,
.writefn = ats_write, .type = ARM_CP_NO_RAW },
--
1.9.1
[Qemu-devel] [PULL 08/20] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
For EL2 stage 1 translations, there is no TTBR1. We were already
handling this for 64-bit EL2; add the code to take the 'no TTBR1'
code path for 64-bit EL2 as well.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1437751263-21913-2-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 97ca86a..86d0baf 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5999,6 +5999,11 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
if (el 1) {
ttbr1_valid = false;
}
+} else {
+/* There is no TTBR1 for EL2 */
+if (el == 2) {
+ttbr1_valid = false;
+}
}
/* Determine whether this address is in the region controlled by
--
1.9.1
Re: [Qemu-devel] [ARM SMBIOS V4 PATCH 1/2] smbios: add smbios 3.0 support
On 13 August 2015 at 18:09, Wei Huang w...@redhat.com wrote:
This patch adds support for SMBIOS 3.0 entry point. When caller invokes
smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
smbios_get_tables() will return the entry point table in right format.
-/* SMBIOS entry point (anchor).
- * BIOS must place this at a 16-bit-aligned address between 0xf and
0xf.
+/* SMBIOS entry point
+ * BIOS must place this at a 16-bit-aligned address between 0xf
+ * and 0xf.
*/
-struct smbios_entry_point {
+struct smbios_21_entry_point {
uint8_t anchor_string[4];
uint8_t checksum;
uint8_t length;
@@ -58,6 +52,25 @@ struct smbios_entry_point {
uint8_t smbios_bcd_revision;
} QEMU_PACKED;
This breaks 'make check' for x86, because tests/bios-tables-test.c
still uses 'struct smbios_entry_point' and no longer compiles
if this patch is applied.
I'm removing these two patches from my target-arm queue.
thanks
-- PMM
[Qemu-devel] [PULL 19/20] target-arm: Implement missing EL3 TLB invalidate operations
Implement the remaining stage 1 TLB invalidate operations
visible from EL3.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1439548879-1972-6-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 76 +
1 file changed, 76 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6c38d66..00ecda9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2567,6 +2567,15 @@ static void tlbi_aa64_alle2_write(CPUARMState *env,
const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
}
+static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ARMCPU *cpu = arm_env_get_cpu(env);
+CPUState *cs = CPU(cpu);
+
+tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
+}
+
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -2601,6 +2610,16 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
}
}
+static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
+{
+CPUState *other_cs;
+
+CPU_FOREACH(other_cs) {
+tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
+}
+}
+
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -2636,6 +2655,20 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const
ARMCPRegInfo *ri,
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
}
+static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+/* Invalidate by VA, EL3
+ * Currently handles both VAE3 and VALE3, since we don't support
+ * flush-last-level-only.
+ */
+ARMCPU *cpu = arm_env_get_cpu(env);
+CPUState *cs = CPU(cpu);
+uint64_t pageaddr = sextract64(value 12, 0, 56);
+
+tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
+}
+
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -2665,6 +2698,17 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
}
}
+static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+CPUState *other_cs;
+uint64_t pageaddr = sextract64(value 12, 0, 56);
+
+CPU_FOREACH(other_cs) {
+tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
+}
+}
+
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* We don't implement EL2, so the only control on DC ZVA is the
@@ -2849,10 +2893,18 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_alle1is_write },
+{ .name = TLBI_VMALLS12E1IS, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_alle1is_write },
{ .name = TLBI_ALLE1, .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_alle1_write },
+{ .name = TLBI_VMALLS12E1, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_alle1is_write },
#ifndef CONFIG_USER_ONLY
/* 64 bit address translation operations */
{ .name = AT_S1E1R, .state = ARM_CP_STATE_AA64,
@@ -3317,6 +3369,30 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
.access = PL3_RW, .type = ARM_CP_CONST,
.resetvalue = 0 },
+{ .name = TLBI_ALLE3IS, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_alle3is_write },
+{ .name = TLBI_VAE3IS, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae3is_write },
+{ .name = TLBI_VALE3IS, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae3is_write },
+{ .name = TLBI_ALLE3, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
+ .access = PL3_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_alle3_write },
+{ .name = TLBI_VAE3, .state =
[Qemu-devel] [PULL 00/20] target-arm queue
Here's the ARM queue. I know I have a pile of backed-up code review to do, but I wanted to get these patches out rather than accumulating a fifty-patch queue... thanks -- PMM The following changes since commit 34a4450434f1a5daee06fca223afcbb9c8f1ee24: Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150824' into staging (2015-08-25 13:34:57 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150825 for you to fetch changes up to ff4657fa18b08279ce1f79da35a0e9e0b9574dd5: target-arm: Implement AArch64 TLBI operations on IPAs (2015-08-25 15:45:10 +0100) target-arm queue: * add missing EL2/EL3 TLBI operations * add missing EL2/EL3 ATS operations * add missing EL2/EL3 registers * update Xilinx MAINTAINERS info * Xilinx: connect the four OCM banks * virt: add SMBIOS support Alistair Francis (3): xlnx-zynqmp: Connect the four OCM banks MAINTAINERS: Update Xilinx Maintainership MAINTAINERS: Add ZynqMP to MAINTAINERS file Peter Maydell (15): target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers target-arm: Implement missing AMAIR registers target-arm: Implement missing AFSR registers target-arm: Implement missing ACTLR registers target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations target-arm: Wire up AArch64 EL2 and EL3 address translation ops target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 target-arm: Enable the AArch32 ATS12NSO ops target-arm: Implement AArch32 ATS1H* operations cputlb: Add functions for flushing TLB for a single MMU index target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch target-arm: Implement missing EL2 TLBI operations target-arm: Implement missing EL3 TLB invalidate operations target-arm: Implement AArch64 TLBI operations on IPAs Wei Huang (2): smbios: add smbios 3.0 support smbios: implement smbios support for mach-virt MAINTAINERS | 27 ++- cputlb.c| 97 default-configs/arm-softmmu.mak | 1 + hw/arm/virt.c | 26 +++ hw/arm/xlnx-zynqmp.c| 15 ++ hw/i386/pc_piix.c | 3 +- hw/i386/pc_q35.c| 3 +- hw/smbios/smbios.c | 84 +-- include/exec/exec-all.h | 47 include/hw/arm/xlnx-zynqmp.h| 6 + include/hw/smbios/smbios.h | 51 +++-- qemu-options.hx | 2 +- target-arm/cpu.h| 3 + target-arm/helper.c | 489 +++- target-arm/op_helper.c | 8 + 15 files changed, 759 insertions(+), 103 deletions(-)
[Qemu-devel] [PULL 03/20] MAINTAINERS: Add ZynqMP to MAINTAINERS file
From: Alistair Francis alistair.fran...@xilinx.com Add the Xilinx ZynqMP SoC and EP108 machine to the maintainers file. Signed-off-by: Alistair Francis alistair.fran...@xilinx.com Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com Message-id: fed078103a0b02cfb3adadbe8e80e4420d554505.1436486024.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell peter.mayd...@linaro.org --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d0268f9..08f356a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -357,6 +357,14 @@ F: hw/misc/zynq_slcr.c F: hw/*/cadence_* F: hw/ssi/xilinx_spips.c +Xilinx ZynqMP +M: Alistair Francis alistair.fran...@xilinx.com +M: Peter Crosthwaite crosthwaite.pe...@gmail.com +S: Maintained +F: hw/arm/xlnx-zynqmp.c +F: hw/arm/xlnx-ep108.c +F: include/hw/arm/xlnx-zynqmp.h + ARM ACPI Subsystem M: Shannon Zhao zhaoshengl...@huawei.com M: Shannon Zhao shannon.z...@linaro.org -- 1.9.1
[Qemu-devel] [PULL 14/20] smbios: implement smbios support for mach-virt
From: Wei Huang w...@redhat.com
This patch generates smbios tables for ARM mach-virt. Also add
CONFIG_SMBIOS=y for ARM default config.
Acked-by: Gabriel Somlo so...@cmu.edu
Tested-by: Gabriel Somlo so...@cmu.edu
Reviewed-by: Laszlo Ersek ler...@redhat.com
Reviewed-by: Shannon Zhao shannon.z...@linaro.org
Tested-by: Leif Lindholm leif.lindh...@linaro.org
Signed-off-by: Wei Huang w...@redhat.com
Message-id: 1439485767-20259-3-git-send-email-...@redhat.com
[PMM: Added missing braces on if ()]
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/virt.c | 26 ++
qemu-options.hx | 2 +-
3 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 74f1db3..99b41e9 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -102,3 +102,4 @@ CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
CONFIG_ACPI=y
+CONFIG_SMBIOS=y
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d5a8417..bbd061b 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -50,6 +50,7 @@
#include hw/arm/fdt.h
#include hw/intc/arm_gic_common.h
#include kvm_arm.h
+#include hw/smbios/smbios.h
/* Number of external interrupt lines to configure the GIC with */
#define NUM_IRQS 256
@@ -788,12 +789,37 @@ static void *machvirt_dtb(const struct arm_boot_info
*binfo, int *fdt_size)
return board-fdt;
}
+static void virt_build_smbios(VirtGuestInfo *guest_info)
+{
+FWCfgState *fw_cfg = guest_info-fw_cfg;
+uint8_t *smbios_tables, *smbios_anchor;
+size_t smbios_tables_len, smbios_anchor_len;
+
+if (!fw_cfg) {
+return;
+}
+
+smbios_set_defaults(QEMU, QEMU Virtual Machine,
+1.0, false, true, SMBIOS_ENTRY_POINT_30);
+
+smbios_get_tables(NULL, 0, smbios_tables, smbios_tables_len,
+ smbios_anchor, smbios_anchor_len);
+
+if (smbios_anchor) {
+fw_cfg_add_file(fw_cfg, etc/smbios/smbios-tables,
+smbios_tables, smbios_tables_len);
+fw_cfg_add_file(fw_cfg, etc/smbios/smbios-anchor,
+smbios_anchor, smbios_anchor_len);
+}
+}
+
static
void virt_guest_info_machine_done(Notifier *notifier, void *data)
{
VirtGuestInfoState *guest_info_state = container_of(notifier,
VirtGuestInfoState,
machine_done);
virt_acpi_setup(guest_info_state-info);
+virt_build_smbios(guest_info_state-info);
}
static void machvirt_init(MachineState *machine)
diff --git a/qemu-options.hx b/qemu-options.hx
index 77f5853..efce775 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1412,7 +1412,7 @@ DEF(smbios, HAS_ARG, QEMU_OPTION_smbios,
-smbios
type=17[,loc_pfx=str][,bank=str][,manufacturer=str][,serial=str]\n
[,asset=str][,part=str][,speed=%d]\n
specify SMBIOS type 17 fields\n,
-QEMU_ARCH_I386)
+QEMU_ARCH_I386 | QEMU_ARCH_ARM)
STEXI
@item -smbios file=@var{binary}
@findex -smbios
--
1.9.1
Re: [Qemu-devel] [PATCH v2 07/18] nvdimm: reserve address range for NVDIMM
On Fri, Aug 14, 2015 at 10:52:00PM +0800, Xiao Guangrong wrote: diff --git a/hw/mem/nvdimm/pc-nvdimm.c b/hw/mem/nvdimm/pc-nvdimm.c index a53d235..7a270a8 100644 --- a/hw/mem/nvdimm/pc-nvdimm.c +++ b/hw/mem/nvdimm/pc-nvdimm.c @@ -24,6 +24,19 @@ #include hw/mem/pc-nvdimm.h +#define PAGE_SIZE (1UL 12) This macro name is likely to collide with system headers or other code. Could you use the existing TARGET_PAGE_SIZE constant instead?
Re: [Qemu-devel] [PATCH] qdev-monitor.c: Add device id generation
On 25 August 2015 at 16:25, Programmingkid programmingk...@gmail.com wrote:
On Aug 25, 2015, at 8:42 AM, Markus Armbruster wrote:
Eric Blake ebl...@redhat.com writes:
On 08/24/2015 12:53 PM, Programmingkid wrote:
+/* USB's max number of devices is 127. This number is 3 digits long. */
+#define MAX_NUM_DIGITS_FOR_USB_ID 3
This limit makes no sense to me.
The limit is used to decide how many characters the device_id string is going
to have.
Three digits would be 0 to 999 device ID's would be supported. I can't imagine
anyone spending the time to add that many devices.
Arbitrary limits are often a bad idea, especially when
they're easy to avoid, as here.
+/* Add one for '\0' character */
+char *device_id = (char *) malloc(sizeof(char) *
+MAX_NUM_DIGITS_FOR_USB_ID +
1);
+sprintf(device_id, %d, device_id_count++);
g_strdup_printf() is a lot nicer about avoiding the risk of arbitrary
overflow...
+dev-id = (const char *) device_id;
+
+/* if device_id_count = 10^MAX_NUM_DIGITS_FOR_USB_ID */
+if (device_id_count = pow(10, MAX_NUM_DIGITS_FOR_USB_ID)) {
+printf(Warning: Maximum number of device ID's
generated!\n\a);
+printf(Time for you to make your own device ID's.\n);
besides, printf() is probably the wrong way to do error reporting, and
we don't use \a BEL sequences anywhere else in qemu code.
+}
}
When device_id_count reaches the limit, you warn. Next time around, you
overrun the buffer. Not good.
I could change it so next time around, only the warning is displayed.
Eric is right, g_strdup_printf() is easier and safer.
If you say so. I have never heard of it myself.
It's a glib function. Glib has a lot of useful utility functions
for this kind of thing (and the general idea of have an
sprintf-alike which allocates the buffer for you has been
around long before glib came along). Note that HACKING says that
you shouldn't use 'malloc' anyway, but 'malloc and then sprintf
into the buffer' is a particular antipattern that will get picked
up on in code review.
thanks
-- PMM
Re: [Qemu-devel] [RFC 2/4] hw/i386: Introduce AMD IOMMU
Hi,
On 25.08.2015 04:19, David Kiarie wrote:
From: David davidkiar...@gmail.com
Add AMD IOMMU emulation to Qemu. This is a very basic AMD IOMMU
emulation that only does translation and some basic Event logging.
Guest translation enables nested PCI passthrough
Signed-off-by: David Kiarie davidkiar...@gmail.com
---
hw/i386/Makefile.objs | 1 +
hw/i386/amd_iommu.c | 993 ++
hw/i386/amd_iommu.h | 298 +++
3 files changed, 1292 insertions(+)
create mode 100644 hw/i386/amd_iommu.c
create mode 100644 hw/i386/amd_iommu.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index ebd1015..2bae11c 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -3,6 +3,7 @@ obj-y += multiboot.o
obj-y += pc.o pc_piix.o pc_q35.o
obj-y += pc_sysfw.o
obj-y += intel_iommu.o
+obj-y += amd_iommu.o
obj-$(CONFIG_XEN) += ../xenpv/ xen/
obj-y += kvmvapic.o
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
new file mode 100644
index 000..a3a0b20
--- /dev/null
+++ b/hw/i386/amd_iommu.c
@@ -0,0 +1,993 @@
+/*
+ * QEMU emulation of an AMD IOMMU (AMD-Vi)
+ *
+ * Copyright (C) 2011 Eduard - Gabriel Munteanu
+ * Copyright (C) 2015 David Kiarie, davidkiar...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ *
+ */
+#include hw/i386/amd_iommu.h
+
+#define PCI_EXT_CAP_ID_PASID 0x1B
+#define PCI_EXT_CAP_ID_PRI 0x13
+
+#define PCI_SLOT(devfn) (((devfn) 3) 0x1f)
+#define PCI_FUNC(devfn) ((devfn) 0x07)
+
+#define MAX_VA_ADDR (64UL 5)
+#define MAX_PH_ADDR (48UL 8)
+#define MAX_GVA_ADDR (64UL 15)
+
+//#define DEBUG_AMD_IOMMU
+#ifdef DEBUG_AMD_IOMMU
+enum {
+DEBUG_GENERAL, DEBUG_CAPAB, DEBUG_MMIO, DEBUG_ELOG,
+DEBUG_CACHE, DEBUG_COMMAND, DEBUG_MMU
+};
+
+#define IOMMU_DBGBIT(x) (1 DEBUG_##x)
+static int iommu_dbgflags = IOMMU_DBGBIT(GENERAL) | IOMMU_DBGBIT(MMU) |
IOMMU_DBGBIT(MMIO);
+//| IOMMU_DBGBIT(CAPAB) | IOMMU_DBGBIT(ELOG) | IOMMU_DBGBIT(CACHE) |
IOMMU_DBGBIT(COMMAND);
+
+#define IOMMU_DPRINTF(what, fmt, ...) do { \
+if (iommu_dbgflags IOMMU_DBGBIT(what)) { \
+fprintf(stderr, (amd-iommu)%s: fmt \n, __func__, \
+## __VA_ARGS__); } \
+} while (0)
+#else
+#define IOMMU_DPRINTF(what, fmt, ...) do {} while (0)
+#endif
+
+/* helper functions - FIXME - provide for reading one byte */
+static uint16_t amd_iommu_readw(AMDIOMMUState *s, hwaddr addr)
+{
+return lduw_le_p(s-mmior[addr]);
+}
+
+static uint32_t amd_iommu_readl(AMDIOMMUState *s, hwaddr addr)
+{
+return ldl_le_p(s-mmior[addr]);
+}
+
+static uint64_t amd_iommu_readq(AMDIOMMUState *s, hwaddr addr)
+{
+return ldq_le_p(s-mmior[addr]);
+}
+
+static void amd_iommu_writew(AMDIOMMUState *s, hwaddr addr, uint16_t val)
+{
+stw_le_p(s-mmior[addr], val);
+}
+
+static void amd_iommu_writel(AMDIOMMUState *s, hwaddr addr, uint32_t val)
+{
+stl_le_p(s-mmior[addr], val);
+}
+
+static void amd_iommu_writeq(AMDIOMMUState *s, hwaddr addr, uint64_t val)
+{
+stq_le_p(s-mmior[addr], val);
+}
+
+/* execute a completion wait command */
+static void amd_iommu_completion_wait(AMDIOMMUState *s, uint8_t *cmd)
+{
+unsigned int addr;
+
+/* completion store */
+if(cmd[0] COM_COMPLETION_STORE_MASK){
+addr = le64_to_cpu(*(uint64_t*)cmd) COM_STORE_ADDRESS_MASK;
+if(dma_memory_write(address_space_memory, addr, cmd + 8, 8)){
+IOMMU_DPRINTF(ELOG, error: fail to write at address 0%xPRIx64,
addr);
+}
+
+}
+
+/* set completion interrupt */
When I was experimenting with a real IOMMU, it all looked like if both
COM_COMPLETION_STORE_MASK and COM_COMPLETION_BIT are set in the command,
only an interrupt is generated. Could someone comment on this?
+if (cmd[0] COM_COMPLETION_INTR){
+s-mmior[MMIO_STATUS] |= MMIO_STATUS_COMWAIT_INTR;
+}
+}
+
+static void amd_iommu_cmdbuf_exec(AMDIOMMUState *s)
+{
+unsigned type;
+uint8_t cmd[IOMMU_COMMAND_SIZE];
+
+IOMMU_DPRINTF(COMMAND, );
+memset(cmd, 0, IOMMU_COMMAND_SIZE);
+
+if(dma_memory_read(address_space_memory, s-cmdbuf + s-cmdbuf_head, cmd,
IOMMU_COMMAND_SIZE)){
+IOMMU_DPRINTF(COMMAND, error: fail to access memory at 0x%PRIx64
+ + %PRIu8, s-cmdbuf, s-cmdbuf_head);
+}
+
+type = cmd[CMDBUF_ID_BYTE] CMDBUF_ID_RSHIFT;
+
+
Re: [Qemu-devel] [PATCH] target-sparc: Store mmu index in TB flags
On 08/24/2015 11:44 PM, Artyom Tarasenko wrote: This is very surprising: the patch should have no effect on a sun4u machine. Er, no, it should. The primary vector by which I expect improvement is via not encoding dmmu.mmu_primary_context into the TB flags. I.e. ASI_DMMU, which sun4u certainly uses. The fact that the patch _also_ fixes a sun4v problem is secondary. r~
[Qemu-devel] [PULL 07/20] target-arm: Implement missing ACTLR registers
We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
ACTLR_EL3, for consistency.
Since we don't currently have any CPUs that need the EL2/EL3
versions to reset to non-zero values, implement as RAZ/WI.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1438281398-18746-5-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f6119be..97ca86a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3936,13 +3936,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
-ARMCPRegInfo auxcr = {
-.name = ACTLR_EL1, .state = ARM_CP_STATE_BOTH,
-.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
-.access = PL1_RW, .type = ARM_CP_CONST,
-.resetvalue = cpu-reset_auxcr
+ARMCPRegInfo auxcr_reginfo[] = {
+{ .name = ACTLR_EL1, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST,
+ .resetvalue = cpu-reset_auxcr },
+{ .name = ACTLR_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+{ .name = ACTLR_EL3, .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
+ .access = PL3_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+REGINFO_SENTINEL
};
-define_one_arm_cp_reg(cpu, auxcr);
+define_arm_cp_regs(cpu, auxcr_reginfo);
}
if (arm_feature(env, ARM_FEATURE_CBAR)) {
--
1.9.1
[Qemu-devel] [PULL 18/20] target-arm: Implement missing EL2 TLBI operations
Implement the missing TLBI operations that exist only
if EL2 is implemented.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1439548879-1972-5-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c8d07d9..6c38d66 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2591,6 +2591,16 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
}
}
+static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
+{
+CPUState *other_cs;
+
+CPU_FOREACH(other_cs) {
+tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
+}
+}
+
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -3146,10 +3156,22 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
.type = ARM_CP_NO_RAW, .access = PL2_W,
.writefn = tlbi_aa64_vae2_write },
+{ .name = TLBI_VALE2, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae2_write },
+{ .name = TLBI_ALLE2IS, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_alle2is_write },
{ .name = TLBI_VAE2IS, .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
.type = ARM_CP_NO_RAW, .access = PL2_W,
.writefn = tlbi_aa64_vae2is_write },
+{ .name = TLBI_VALE2IS, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_vae2is_write },
#ifndef CONFIG_USER_ONLY
/* Unlike the other EL2-related AT operations, these must
* UNDEF from EL3 if EL2 is not implemented, which is why we
--
1.9.1
[Qemu-devel] [PULL 01/20] xlnx-zynqmp: Connect the four OCM banks
From: Alistair Francis alistair.fran...@xilinx.com
The Xilinx EP108 has four separate OCM banks which are located
adjacent to each other. This patch adds the four banks to
the ZynqMP SoC.
Signed-off-by: Alistair Francis alistair.fran...@xilinx.com
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
afa6ba31163a5d541a0bef4b0dc11f2597e0c495.1436813543.git.alistair.fran...@xilinx.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm/xlnx-zynqmp.c | 15 +++
include/hw/arm/xlnx-zynqmp.h | 6 ++
2 files changed, 21 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 62ef4ceb..388baef 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -101,6 +101,21 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
qemu_irq gic_spi[GIC_NUM_SPI_INTR];
Error *err = NULL;
+/* Create the four OCM banks */
+for (i = 0; i XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
+char *ocm_name = g_strdup_printf(zynqmp.ocm_ram_bank_%d, i);
+
+memory_region_init_ram(s-ocm_ram[i], NULL, ocm_name,
+ XLNX_ZYNQMP_OCM_RAM_SIZE, error_abort);
+vmstate_register_ram_global(s-ocm_ram[i]);
+memory_region_add_subregion(get_system_memory(),
+XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
+i * XLNX_ZYNQMP_OCM_RAM_SIZE,
+s-ocm_ram[i]);
+
+g_free(ocm_name);
+}
+
qdev_prop_set_uint32(DEVICE(s-gic), num-irq, GIC_NUM_SPI_INTR + 32);
qdev_prop_set_uint32(DEVICE(s-gic), revision, 2);
qdev_prop_set_uint32(DEVICE(s-gic), num-cpu, XLNX_ZYNQMP_NUM_APU_CPUS);
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index c379632..6ccb57b 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -32,6 +32,10 @@
#define XLNX_ZYNQMP_NUM_GEMS 4
#define XLNX_ZYNQMP_NUM_UARTS 2
+#define XLNX_ZYNQMP_NUM_OCM_BANKS 4
+#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC
+#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x1
+
#define XLNX_ZYNQMP_GIC_REGIONS 2
/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
@@ -52,6 +56,8 @@ typedef struct XlnxZynqMPState {
ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
GICState gic;
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
+MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
+
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
--
1.9.1
[Qemu-devel] [PULL 02/20] MAINTAINERS: Update Xilinx Maintainership
From: Alistair Francis alistair.fran...@xilinx.com Peter C is leaving Xilinx, so update the maintainer list to point to Alistair and Edgar from Xilinx and Peter's personal email address. Signed-off-by: Alistair Francis alistair.fran...@xilinx.com Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com Message-id: 54b4c070452bac05aa3a9c1d75899bc097fef831.1436486024.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell peter.mayd...@linaro.org --- MAINTAINERS | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a059d5d..d0268f9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -349,7 +349,8 @@ S: Maintained F: hw/*/versatile* Xilinx Zynq -M: Peter Crosthwaite peter.crosthwa...@xilinx.com +M: Alistair Francis alistair.fran...@xilinx.com +M: Peter Crosthwaite crosthwaite.pe...@gmail.com S: Maintained F: hw/arm/xilinx_zynq.c F: hw/misc/zynq_slcr.c @@ -405,7 +406,7 @@ S: Maintained F: hw/microblaze/petalogix_s3adsp1800_mmu.c petalogix_ml605 -M: Peter Crosthwaite peter.crosthwa...@xilinx.com +M: Edgar E. Iglesias edgar.igles...@gmail.com S: Maintained F: hw/microblaze/petalogix_ml605_mmu.c @@ -685,10 +686,17 @@ S: Orphan F: hw/scsi/lsi53c895a.c SSI -M: Peter Crosthwaite peter.crosthwa...@xilinx.com +M: Peter Crosthwaite crosthwaite.pe...@gmail.com S: Maintained F: hw/ssi/* F: hw/block/m25p80.c +X: hw/ssi/xilinx_* + +Xilinx SPI +M: Alistair Francis alistair.fran...@xilinx.com +M: Peter Crosthwaite crosthwaite.pe...@gmail.com +S: Maintained +F: hw/ssi/xilinx_* USB M: Gerd Hoffmann kra...@redhat.com @@ -777,8 +785,9 @@ F: hw/scsi/megasas.c F: hw/scsi/mfi.h Xilinx EDK -M: Peter Crosthwaite peter.crosthwa...@xilinx.com M: Edgar E. Iglesias edgar.igles...@gmail.com +M: Alistair Francis alistair.fran...@xilinx.com +M: Peter Crosthwaite crosthwaite.pe...@gmail.com S: Maintained F: hw/*/xilinx_* F: include/hw/xilinx.h @@ -880,7 +889,7 @@ F: include/hw/cpu/icc_bus.h F: hw/cpu/icc_bus.c Device Tree -M: Peter Crosthwaite peter.crosthwa...@xilinx.com +M: Peter Crosthwaite crosthwaite.pe...@gmail.com M: Alexander Graf ag...@suse.de S: Maintained F: device_tree.[ch] -- 1.9.1
[Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations on IPAs
Implement the AArch64 TLBI operations which take an intermediate
physical address and invalidate stage 2 translations.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1439548879-1972-7-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 00ecda9..7df1f06 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2709,6 +2709,45 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
}
}
+static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
+{
+/* Invalidate by IPA. This has to invalidate any structures that
+ * contain only stage 2 translation information, but does not need
+ * to apply to structures that contain combined stage 1 and stage 2
+ * translation information.
+ * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
+ */
+ARMCPU *cpu = arm_env_get_cpu(env);
+CPUState *cs = CPU(cpu);
+uint64_t pageaddr;
+
+if (!arm_feature(env, ARM_FEATURE_EL2) || !(env-cp15.scr_el3 SCR_NS)) {
+return;
+}
+
+pageaddr = sextract64(value 12, 0, 48);
+
+tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
+}
+
+static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+CPUState *other_cs;
+uint64_t pageaddr;
+
+if (!arm_feature(env, ARM_FEATURE_EL2) || !(env-cp15.scr_el3 SCR_NS)) {
+return;
+}
+
+pageaddr = sextract64(value 12, 0, 48);
+
+CPU_FOREACH(other_cs) {
+tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
+}
+}
+
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* We don't implement EL2, so the only control on DC ZVA is the
@@ -2889,6 +2928,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
.access = PL1_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1_write },
+{ .name = TLBI_IPAS2E1IS, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_ipas2e1is_write },
+{ .name = TLBI_IPAS2LE1IS, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_ipas2e1is_write },
{ .name = TLBI_ALLE1IS, .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -2897,6 +2944,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_alle1is_write },
+{ .name = TLBI_IPAS2E1, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_ipas2e1_write },
+{ .name = TLBI_IPAS2LE1, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_ipas2e1_write },
{ .name = TLBI_ALLE1, .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
--
1.9.1
[Qemu-devel] [PULL 00/18] target-arm queue
Here's the ARM queue. I know I have a pile of backed-up code review to do, but I wanted to get these patches out rather than accumulating a fifty-patch queue... This is v2: only change is to drop the two smbios patches. thanks -- PMM The following changes since commit 34a4450434f1a5daee06fca223afcbb9c8f1ee24: Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150824' into staging (2015-08-25 13:34:57 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150825-1 for you to fetch changes up to cea66e91212164e02ad1d245c2371f7e8eb59e7f: target-arm: Implement AArch64 TLBI operations on IPAs (2015-08-25 16:18:33 +0100) target-arm queue: * add missing EL2/EL3 TLBI operations * add missing EL2/EL3 ATS operations * add missing EL2/EL3 registers * update Xilinx MAINTAINERS info * Xilinx: connect the four OCM banks Alistair Francis (3): xlnx-zynqmp: Connect the four OCM banks MAINTAINERS: Update Xilinx Maintainership MAINTAINERS: Add ZynqMP to MAINTAINERS file Peter Maydell (15): target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers target-arm: Implement missing AMAIR registers target-arm: Implement missing AFSR registers target-arm: Implement missing ACTLR registers target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations target-arm: Wire up AArch64 EL2 and EL3 address translation ops target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 target-arm: Enable the AArch32 ATS12NSO ops target-arm: Implement AArch32 ATS1H* operations cputlb: Add functions for flushing TLB for a single MMU index target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch target-arm: Implement missing EL2 TLBI operations target-arm: Implement missing EL3 TLB invalidate operations target-arm: Implement AArch64 TLBI operations on IPAs MAINTAINERS | 27 ++- cputlb.c | 97 + hw/arm/xlnx-zynqmp.c | 15 ++ include/exec/exec-all.h | 47 + include/hw/arm/xlnx-zynqmp.h | 6 + target-arm/cpu.h | 3 + target-arm/helper.c | 489 ++- target-arm/op_helper.c | 8 + 8 files changed, 629 insertions(+), 63 deletions(-)
Re: [Qemu-devel] [ARM SMBIOS V4 PATCH 1/2] smbios: add smbios 3.0 support
On Tue, Aug 25, 2015 at 04:17:42PM +0100, Peter Maydell wrote:
On 13 August 2015 at 18:09, Wei Huang w...@redhat.com wrote:
This patch adds support for SMBIOS 3.0 entry point. When caller invokes
smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
smbios_get_tables() will return the entry point table in right format.
-/* SMBIOS entry point (anchor).
- * BIOS must place this at a 16-bit-aligned address between 0xf and
0xf.
+/* SMBIOS entry point
+ * BIOS must place this at a 16-bit-aligned address between 0xf
+ * and 0xf.
*/
-struct smbios_entry_point {
+struct smbios_21_entry_point {
uint8_t anchor_string[4];
uint8_t checksum;
uint8_t length;
@@ -58,6 +52,25 @@ struct smbios_entry_point {
uint8_t smbios_bcd_revision;
} QEMU_PACKED;
This breaks 'make check' for x86, because tests/bios-tables-test.c
still uses 'struct smbios_entry_point' and no longer compiles
if this patch is applied.
Urgh.
I'm removing these two patches from my target-arm queue.
Fair enough.
Wei - is there actually any particular point in renaming this
structure? In all versions of the specification before 3.0, this was
only known as the smbios entry point. Only with the introduction of
SMBIOS 3.0 this was retrospectively renamed.
(And personally, I find that renaming a bit counterintuitive, since it
is still a valid 32-bit entry point in SMBIOS3, and was the only entry
point up until and including SMBIOS 2.8.)
/
Leif
[Qemu-devel] [PULL 10/20] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
Some coprocessor register access functions need to be able
to report trap to EL3 with an 'uncategorized' syndrome;
add the necessary CPAccessResult enum and handling for it.
I don't currently know of any registers that need to trap
to EL2 with the 'uncategorized' syndrome, but adding the
_EL2 enum as well is trivial and fills in what would
otherwise be an odd gap in the handling.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1437751263-21913-4-git-send-email-peter.mayd...@linaro.org
---
target-arm/cpu.h | 3 +++
target-arm/op_helper.c | 8
2 files changed, 11 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2e680da..31825d3 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1284,6 +1284,9 @@ typedef enum CPAccessResult {
/* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
CP_ACCESS_TRAP_EL2 = 3,
CP_ACCESS_TRAP_EL3 = 4,
+/* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
+CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
+CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
} CPAccessResult;
/* Access functions for coprocessor registers. These cannot fail and
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 663c05d..1425a1d 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -444,6 +444,14 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void
*rip, uint32_t syndrome)
target_el = exception_target_el(env);
syndrome = syn_uncategorized();
break;
+case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
+target_el = 2;
+syndrome = syn_uncategorized();
+break;
+case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
+target_el = 3;
+syndrome = syn_uncategorized();
+break;
default:
g_assert_not_reached();
}
--
1.9.1
[Qemu-devel] [PULL 09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops
Wire up the AArch64 EL2 and EL3 address translation operations
(AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some
errors in the ats_write64() function in previously unused code
that would have done the wrong kind of lookup for accesses from
EL3 when SCR.NS==0.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1437751263-21913-3-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 43 +--
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 86d0baf..8603660 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1844,6 +1844,14 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
+static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+if (arm_current_el(env) == 3 !(env-cp15.scr_el3 SCR_NS)) {
+return CP_ACCESS_TRAP;
+}
+return CP_ACCESS_OK;
+}
+
static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -1871,10 +1879,10 @@ static void ats_write64(CPUARMState *env, const
ARMCPRegInfo *ri,
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
break;
case 4: /* AT S12E1R, AT S12E1W */
-mmu_idx = ARMMMUIdx_S12NSE1;
+mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
break;
case 6: /* AT S12E0R, AT S12E0W */
-mmu_idx = ARMMMUIdx_S12NSE0;
+mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
break;
default:
g_assert_not_reached();
@@ -2746,6 +2754,25 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = AT_S1E0W, .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
.access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+{ .name = AT_S12E1R, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 4,
+ .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+{ .name = AT_S12E1W, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+{ .name = AT_S12E0R, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
+ .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+{ .name = AT_S12E0W, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 7,
+ .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+/* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
+{ .name = AT_S1E3R, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
+ .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+{ .name = AT_S1E3W, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
+ .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
#endif
/* TLB invalidate last level of translation table walk */
{ .name = TLBIMVALIS, .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
@@ -3021,6 +3048,18 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.type = ARM_CP_NO_RAW, .access = PL2_W,
.writefn = tlbi_aa64_vaa_write },
#ifndef CONFIG_USER_ONLY
+/* Unlike the other EL2-related AT operations, these must
+ * UNDEF from EL3 if EL2 is not implemented, which is why we
+ * define them here rather than with the rest of the AT ops.
+ */
+{ .name = AT_S1E2R, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
+ .access = PL2_W, .accessfn = at_s1e2_access,
+ .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+{ .name = AT_S1E2W, .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
+ .access = PL2_W, .accessfn = at_s1e2_access,
+ .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
{ .name = CNTHCTL_EL2, .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
/* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
--
1.9.1
Re: [Qemu-devel] [PATCH] qdev-monitor.c: Add device id generation
On Aug 25, 2015, at 8:42 AM, Markus Armbruster wrote:
My other reply is about design issues. This one is about the actual
code. Until we get rough consensus on the former, the latter doesn't
really matter, but here goes anyway.
Eric Blake ebl...@redhat.com writes:
On 08/24/2015 12:53 PM, Programmingkid wrote:
Add device ID generation to each device if an ID isn't given.
Signed-off-by: John Arbuckle programmingk...@gmail.com
---
This patch can be tested by adding adding usb devices using the monitor.
Start QEMU with the -usb option. Then go to the monitor and type
device_add usb-mouse. The ID of the device will be set to a number.
Since QEMU will not allow an user to add a device with an ID set to a
number, there is no chance for ID collisions.
qdev-monitor.c | 24 ++--
1 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/qdev-monitor.c b/qdev-monitor.c
index f9e2d62..98267c4 100644
--- a/qdev-monitor.c
+++ b/qdev-monitor.c
@@ -26,6 +26,10 @@
#include qapi/qmp/qerror.h
#include qemu/config-file.h
#include qemu/error-report.h
+#include math.h
+
+/* USB's max number of devices is 127. This number is 3 digits long. */
+#define MAX_NUM_DIGITS_FOR_USB_ID 3
This limit makes no sense to me.
The limit is used to decide how many characters the device_id string is going
to have.
Three digits would be 0 to 999 device ID's would be supported. I can't imagine
anyone spending the time to add that many devices.
/*
* Aliases were a bad idea from the start. Let's keep them
@@ -574,17 +578,25 @@ DeviceState *qdev_device_add(QemuOpts *opts, Error
**errp)
id = qemu_opts_id(opts);
if (id) {
dev-id = id;
+} else { /* create an id for a device if none is provided */
+static int device_id_count;
+
+/* Add one for '\0' character */
+char *device_id = (char *) malloc(sizeof(char) *
+MAX_NUM_DIGITS_FOR_USB_ID + 1);
+sprintf(device_id, %d, device_id_count++);
g_strdup_printf() is a lot nicer about avoiding the risk of arbitrary
overflow...
+dev-id = (const char *) device_id;
+
+/* if device_id_count = 10^MAX_NUM_DIGITS_FOR_USB_ID */
+if (device_id_count = pow(10, MAX_NUM_DIGITS_FOR_USB_ID)) {
+printf(Warning: Maximum number of device ID's
generated!\n\a);
+printf(Time for you to make your own device ID's.\n);
besides, printf() is probably the wrong way to do error reporting, and
we don't use \a BEL sequences anywhere else in qemu code.
+}
}
When device_id_count reaches the limit, you warn. Next time around, you
overrun the buffer. Not good.
I could change it so next time around, only the warning is displayed.
Eric is right, g_strdup_printf() is easier and safer.
If you say so. I have never heard of it myself.
I'd make the count 64 bits, so wrapping becomes vanishingly unlikely.
That big of a number seems unreasonably big. I can see the advantage of
using such a big number. Can QEMU even handle that many devices?
if (dev-id) {
This if would now be a dead check if your patch is applied.
object_property_add_child(qdev_get_peripheral(), dev-id,
OBJECT(dev), NULL);
-} else {
-static int anon_count;
-gchar *name = g_strdup_printf(device[%d], anon_count++);
-object_property_add_child(qdev_get_peripheral_anon(), name,
- OBJECT(dev), NULL);
-g_free(name);
}
It looks like your goal was to move this code earlier, but you changed
enough aspects of it that I'm not sure what the right fix should be.
Drop the conditional, it's both useless and confusing after your patch.
Ok.
I'm thinking I will wait until the other maintainers and whoever else is
interested,
say how they feel on the subject of generated ID's for devices before making
a new patch.
Re: [Qemu-devel] [PATCH v2 07/18] nvdimm: reserve address range for NVDIMM
On Fri, Aug 14, 2015 at 10:52:00PM +0800, Xiao Guangrong wrote:
NVDIMM reserves all the free range above 4G to do:
- Persistent Memory (PMEM) mapping
- implement NVDIMM ACPI device _DSM method
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
hw/i386/pc.c | 12 ++--
hw/mem/nvdimm/pc-nvdimm.c | 13 +
include/hw/mem/pc-nvdimm.h | 1 +
3 files changed, 24 insertions(+), 2 deletions(-)
CCing Igor for memory hotplug-related changes.
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7661ea9..41af6ea 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -64,6 +64,7 @@
#include hw/pci/pci_host.h
#include acpi-build.h
#include hw/mem/pc-dimm.h
+#include hw/mem/pc-nvdimm.h
#include qapi/visitor.h
#include qapi-visit.h
@@ -1302,6 +1303,7 @@ FWCfgState *pc_memory_init(MachineState *machine,
MemoryRegion *ram_below_4g, *ram_above_4g;
FWCfgState *fw_cfg;
PCMachineState *pcms = PC_MACHINE(machine);
+ram_addr_t offset;
assert(machine-ram_size == below_4g_mem_size + above_4g_mem_size);
@@ -1339,6 +1341,8 @@ FWCfgState *pc_memory_init(MachineState *machine,
exit(EXIT_FAILURE);
}
+offset = 0x1ULL + above_4g_mem_size;
+
/* initialize hotplug memory address space */
if (guest_info-has_reserved_memory
(machine-ram_size machine-maxram_size)) {
@@ -1358,8 +1362,7 @@ FWCfgState *pc_memory_init(MachineState *machine,
exit(EXIT_FAILURE);
}
-pcms-hotplug_memory.base =
-ROUND_UP(0x1ULL + above_4g_mem_size, 1ULL 30);
+pcms-hotplug_memory.base = ROUND_UP(offset, 1ULL 30);
if (pcms-enforce_aligned_dimm) {
/* size hotplug region assuming 1G page max alignment per slot */
@@ -1377,8 +1380,13 @@ FWCfgState *pc_memory_init(MachineState *machine,
hotplug-memory, hotplug_mem_size);
memory_region_add_subregion(system_memory, pcms-hotplug_memory.base,
pcms-hotplug_memory.mr);
+
+offset = pcms-hotplug_memory.base + hotplug_mem_size;
}
+ /* all the space left above 4G is reserved for NVDIMM. */
+pc_nvdimm_reserve_range(offset);
+
/* Initialize PC system firmware */
pc_system_firmware_init(rom_memory, guest_info-isapc_ram_fw);
diff --git a/hw/mem/nvdimm/pc-nvdimm.c b/hw/mem/nvdimm/pc-nvdimm.c
index a53d235..7a270a8 100644
--- a/hw/mem/nvdimm/pc-nvdimm.c
+++ b/hw/mem/nvdimm/pc-nvdimm.c
@@ -24,6 +24,19 @@
#include hw/mem/pc-nvdimm.h
+#define PAGE_SIZE (1UL 12)
+
+static struct nvdimms_info {
+ram_addr_t current_addr;
+} nvdimms_info;
+
+/* the address range [offset, ~0ULL) is reserved for NVDIMM. */
+void pc_nvdimm_reserve_range(ram_addr_t offset)
+{
+offset = ROUND_UP(offset, PAGE_SIZE);
+nvdimms_info.current_addr = offset;
+}
+
static char *get_file(Object *obj, Error **errp)
{
PCNVDIMMDevice *nvdimm = PC_NVDIMM(obj);
diff --git a/include/hw/mem/pc-nvdimm.h b/include/hw/mem/pc-nvdimm.h
index 51152b8..8601e9b 100644
--- a/include/hw/mem/pc-nvdimm.h
+++ b/include/hw/mem/pc-nvdimm.h
@@ -28,4 +28,5 @@ typedef struct PCNVDIMMDevice {
#define PC_NVDIMM(obj) \
OBJECT_CHECK(PCNVDIMMDevice, (obj), TYPE_PC_NVDIMM)
+void pc_nvdimm_reserve_range(ram_addr_t offset);
#endif
--
2.4.3
--
To unsubscribe from this list: send the line unsubscribe kvm in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [Qemu-devel] [ARM SMBIOS V4 PATCH 1/2] smbios: add smbios 3.0 support
On 25 August 2015 at 16:59, Wei Huang w...@redhat.com wrote: On 08/25/2015 10:29 AM, Leif Lindholm wrote: Wei - is there actually any particular point in renaming this structure? In all versions of the specification before 3.0, this was only known as the smbios entry point. Only with the introduction of SMBIOS 3.0 this was retrospectively renamed. I can take this suggestion, with clear comment in header file so nobody will get confused. Peter, please let me know if you object. I don't object (though the opinion of the qemu smbios/acpi folk is probably more important than mine). Please make sure you test the x86 platform has not been broken by this change (preferably more thoroughly than just running 'make check'...). thanks -- PMM
Re: [Qemu-devel] [PATCH v2 13/18] nvdimm: build namespace config data
On Fri, Aug 14, 2015 at 10:52:06PM +0800, Xiao Guangrong wrote:
+#ifdef NVDIMM_DEBUG
+#define nvdebug(fmt, ...) fprintf(stderr, nvdimm: fmt, ## __VA_ARGS__)
+#else
+#define nvdebug(...)
+#endif
The following allows the compiler to check format strings and syntax
check the argument expressions:
#define NVDIMM_DEBUG 0 /* set to 1 for debug output */
#define nvdebug(fmt, ...) \
if (NVDIMM_DEBUG) { \
fprintf(stderr, nvdimm: fmt, ## __VA_ARGS__); \
}
This approach avoids bitrot (e.g. debug format string arguments have
become outdated).
Re: [Qemu-devel] [PATCH] target-sparc: Store mmu index in TB flags
On Tue, Aug 25, 2015 at 4:25 PM, Richard Henderson r...@twiddle.net wrote: On 08/24/2015 11:44 PM, Artyom Tarasenko wrote: This is very surprising: the patch should have no effect on a sun4u machine. Er, no, it should. The primary vector by which I expect improvement is via not encoding dmmu.mmu_primary_context into the TB flags. I.e. ASI_DMMU, which sun4u certainly uses. The fact that the patch _also_ fixes a sun4v problem is secondary. Sorry, my bad, I haven't noticed that. Applied it on top of the tcg-indirect branch, but see no measurable impact: my reference g++ run still takes ~ 17 minutes. Artyom -- Regards, Artyom Tarasenko SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
Re: [Qemu-devel] [PATCH 07/12] qga: fill default options in main()
Quoting Marc-André Lureau (2015-07-01 06:47:42)
Fill all default options during main(). This is a preparation patch
to allow to dump the configuration.
Signed-off-by: Marc-André Lureau marcandre.lur...@gmail.com
Reviewed-by: Michael Roth mdr...@linux.vnet.ibm.com
---
qga/main.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/qga/main.c b/qga/main.c
index b965f61..5575637 100644
--- a/qga/main.c
+++ b/qga/main.c
@@ -658,23 +658,6 @@ static gboolean channel_init(GAState *s, const gchar
*method, const gchar *path)
{
GAChannelMethod channel_method;
-if (method == NULL) {
-method = virtio-serial;
-}
-
-if (path == NULL) {
-if (strcmp(method, virtio-serial) == 0 ) {
-/* try the default path for the virtio-serial port */
-path = QGA_VIRTIO_PATH_DEFAULT;
-} else if (strcmp(method, isa-serial) == 0){
-/* try the default path for the serial port - COM1 */
-path = QGA_SERIAL_PATH_DEFAULT;
-} else {
-g_critical(must specify a path for this channel);
-return false;
-}
-}
-
if (strcmp(method, virtio-serial) == 0) {
s-virtio = true; /* virtio requires special handling in some cases
*/
channel_method = GA_CHANNEL_VIRTIO_SERIAL;
@@ -1076,6 +1059,23 @@ int main(int argc, char **argv)
state_dir = g_strdup(dfl_pathnames.state_dir);
}
+if (method == NULL) {
+method = g_strdup(virtio-serial);
+}
+
+if (device_path == NULL) {
+if (strcmp(method, virtio-serial) == 0) {
+/* try the default path for the virtio-serial port */
+device_path = g_strdup(QGA_VIRTIO_PATH_DEFAULT);
+} else if (strcmp(method, isa-serial) == 0) {
+/* try the default path for the serial port - COM1 */
+device_path = g_strdup(QGA_SERIAL_PATH_DEFAULT);
+} else {
+g_critical(must specify a path for this channel);
+goto out_bad;
+}
+}
+
#ifdef _WIN32
/* On win32 the state directory is application specific (be it the
default
* or a user override). We got past the command line parsing; let's
create
--
2.4.3
Re: [Qemu-devel] [PATCH 04/12] qga: rename 'path' to 'device_path'
Quoting Marc-André Lureau (2015-07-01 06:47:39)
'path' is already a global function, rename the variable since it's
going to be in global scope in a later patch.
Signed-off-by: Marc-André Lureau marcandre.lur...@gmail.com
I think I'd prefer something like 'channel_path' since we support
sockets as well. Looks good otherwise.
---
qga/main.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/qga/main.c b/qga/main.c
index 0c455f8..1c81575 100644
--- a/qga/main.c
+++ b/qga/main.c
@@ -944,7 +944,7 @@ static GList *split_list(gchar *str, const gchar
separator)
int main(int argc, char **argv)
{
const char *sopt = hVvdm:p:l:f:F::b:s:t:;
-const char *method = NULL, *path = NULL;
+const char *method = NULL, *device_path = NULL;
const char *log_filepath = NULL;
const char *pid_filepath;
#ifdef CONFIG_FSFREEZE
@@ -990,7 +990,7 @@ int main(int argc, char **argv)
method = optarg;
break;
case 'p':
-path = optarg;
+device_path = optarg;
break;
case 'l':
log_filepath = optarg;
@@ -1040,7 +1040,8 @@ int main(int argc, char **argv)
if (ga_install_vss_provider()) {
exit(EXIT_FAILURE);
}
-if (ga_install_service(path, log_filepath, fixed_state_dir))
{
+if (ga_install_service(device_path, log_filepath,
+ fixed_state_dir)) {
exit(EXIT_FAILURE);
}
exit(EXIT_SUCCESS);
@@ -1185,7 +1186,7 @@ int main(int argc, char **argv)
#endif
s-main_loop = g_main_loop_new(NULL, false);
-if (!channel_init(ga_state, method, path)) {
+if (!channel_init(ga_state, method, device_path)) {
g_critical(failed to initialize guest agent channel);
goto out_bad;
}
--
2.4.3
[Qemu-devel] [PATCH v2 3/8] s390x: Enable new s390-storage-keys device
From: Jason J. Herne jjhe...@linux.vnet.ibm.com
s390 guest initialization is modified to make use of new s390-storage-keys
device. Old code that globally allocated storage key array is removed.
The new device enables storage key access for kvm guests.
Cache storage key QOM objects in frequently used helper functions to avoid a
performance hit every time we use one of these functions.
Reviewed-by: Cornelia Huck cornelia.h...@de.ibm.com
Reviewed-by: Thomas Huth th...@linux.vnet.ibm.com
Reviewed-by: David Hildenbrand d...@linux.vnet.ibm.com
Signed-off-by: Jason J. Herne jjhe...@linux.vnet.ibm.com
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
---
hw/s390x/s390-virtio-ccw.c | 8
hw/s390x/s390-virtio.c | 11 +--
hw/s390x/s390-virtio.h | 2 +-
target-s390x/cpu.h | 2 --
target-s390x/mem_helper.c | 46 --
target-s390x/mmu_helper.c | 28 +++-
trace-events | 4
7 files changed, 77 insertions(+), 24 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 71df282..0a057ae 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -19,6 +19,7 @@
#include virtio-ccw.h
#include qemu/config-file.h
#include s390-pci-bus.h
+#include hw/s390x/storage-keys.h
#define TYPE_S390_CCW_MACHINE s390-ccw-machine
@@ -105,7 +106,6 @@ static void ccw_init(MachineState *machine)
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
sclpMemoryHotplugDev *mhd = init_sclp_memory_hotplug_dev();
-uint8_t *storage_keys;
int ret;
VirtualCssBus *css_bus;
DeviceState *dev;
@@ -179,11 +179,11 @@ static void ccw_init(MachineState *machine)
mhd-standby_mem_size = standby_mem_size;
}
-/* allocate storage keys */
-storage_keys = g_malloc0(my_ram_size / TARGET_PAGE_SIZE);
+/* Initialize storage key device */
+s390_skeys_init();
/* init CPUs */
-s390_init_cpus(machine-cpu_model, storage_keys);
+s390_init_cpus(machine-cpu_model);
if (kvm_enabled()) {
kvm_s390_enable_css_support(s390_cpu_addr2state(0));
diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c
index 1284e77..6cc6b5d 100644
--- a/hw/s390x/s390-virtio.c
+++ b/hw/s390x/s390-virtio.c
@@ -38,6 +38,7 @@
#include hw/s390x/sclp.h
#include hw/s390x/s390_flic.h
#include hw/s390x/s390-virtio.h
+#include hw/s390x/storage-keys.h
#include cpu.h
//#define DEBUG_S390
@@ -164,7 +165,7 @@ void s390_init_ipl_dev(const char *kernel_filename,
qdev_init_nofail(dev);
}
-void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys)
+void s390_init_cpus(const char *cpu_model)
{
int i;
@@ -184,7 +185,6 @@ void s390_init_cpus(const char *cpu_model, uint8_t
*storage_keys)
ipi_states[i] = cpu;
cs-halted = 1;
cs-exception_index = EXCP_HLT;
-cpu-env.storage_keys = storage_keys;
}
}
@@ -264,7 +264,6 @@ static void s390_init(MachineState *machine)
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
int increment_size = 20;
-uint8_t *storage_keys;
void *virtio_region;
hwaddr virtio_region_len;
hwaddr virtio_region_start;
@@ -306,11 +305,11 @@ static void s390_init(MachineState *machine)
cpu_physical_memory_unmap(virtio_region, virtio_region_len, 1,
virtio_region_len);
-/* allocate storage keys */
-storage_keys = g_malloc0(my_ram_size / TARGET_PAGE_SIZE);
+/* Initialize storage key device */
+s390_skeys_init();
/* init CPUs */
-s390_init_cpus(machine-cpu_model, storage_keys);
+s390_init_cpus(machine-cpu_model);
/* Create VirtIO network adapters */
s390_create_virtio_net((BusState *)s390_bus, virtio-net-s390);
diff --git a/hw/s390x/s390-virtio.h b/hw/s390x/s390-virtio.h
index c847853..cf68796 100644
--- a/hw/s390x/s390-virtio.h
+++ b/hw/s390x/s390-virtio.h
@@ -19,7 +19,7 @@
typedef int (*s390_virtio_fn)(const uint64_t *args);
void s390_register_virtio_hypercall(uint64_t code, s390_virtio_fn fn);
-void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys);
+void s390_init_cpus(const char *cpu_model);
void s390_init_ipl_dev(const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 63aebf4..b650890 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -143,8 +143,6 @@ typedef struct CPUS390XState {
uint32_t cpu_num;
uint32_t machine_type;
-uint8_t *storage_keys;
-
uint64_t tod_offset;
uint64_t tod_basetime;
QEMUTimer *tod_timer;
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 6f8bd79..84bf198 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@
[Qemu-devel] [PATCH v2 4/8] s390x: Dump storage keys qmp command
From: Jason J. Herne jjhe...@linux.vnet.ibm.com
Provide a dump-skeys qmp command to allow the end user to dump storage
keys. This is useful for debugging problems with guest storage key support
within Qemu and for guest operating system developers.
Reviewed-by: Thomas Huth th...@linux.vnet.ibm.com
Reviewed-by: David Hildenbrand d...@linux.vnet.ibm.com
Signed-off-by: Jason J. Herne jjhe...@linux.vnet.ibm.com
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
---
hw/s390x/s390-skeys.c | 97 +++
monitor.c | 7
qapi-schema.json | 13 +++
qmp-commands.hx | 25 +
4 files changed, 142 insertions(+)
diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c
index 77c42ff..ebf6a54 100644
--- a/hw/s390x/s390-skeys.c
+++ b/hw/s390x/s390-skeys.c
@@ -10,9 +10,12 @@
*/
#include hw/boards.h
+#include qmp-commands.h
#include hw/s390x/storage-keys.h
#include qemu/error-report.h
+#define S390_SKEYS_BUFFER_SIZE 131072 /* Room for 128k storage keys */
+
S390SKeysState *s390_get_skeys_device(void)
{
S390SKeysState *ss;
@@ -38,6 +41,100 @@ void s390_skeys_init(void)
qdev_init_nofail(DEVICE(obj));
}
+static void write_keys(QEMUFile *f, uint8_t *keys, uint64_t startgfn,
+ uint64_t count, Error **errp)
+{
+uint64_t curpage = startgfn;
+uint64_t maxpage = curpage + count - 1;
+const char *fmt = page=%03 PRIx64 : key(%d) = ACC=%X, FP=%d, REF=%d,
+ ch=%d, reserved=%d\n;
+char *buf = g_try_malloc(128);
+int len;
+
+if (!buf) {
+error_setg(errp, Out of memory);
+return;
+}
+
+for (; curpage = maxpage; curpage++) {
+uint8_t acc = (*keys 0xF0) 4;
+int fp = (*keys 0x08);
+int ref = (*keys 0x04);
+int ch = (*keys 0x02);
+int res = (*keys 0x01);
+
+len = snprintf(buf, 128, fmt, curpage,
+ *keys, acc, fp, ref, ch, res);
+qemu_put_buffer(f, (uint8_t *)buf, len);
+keys++;
+}
+
+g_free(buf);
+}
+
+void qmp_dump_skeys(const char *filename, Error **errp)
+{
+S390SKeysState *ss = s390_get_skeys_device();
+S390SKeysClass *skeyclass = S390_SKEYS_GET_CLASS(ss);
+const uint64_t total_count = ram_size / TARGET_PAGE_SIZE;
+uint64_t handled_count = 0, cur_count;
+Error *lerr = NULL;
+vaddr cur_gfn = 0;
+uint8_t *buf;
+int ret;
+QEMUFile *f;
+
+/* Quick check to see if guest is using storage keys*/
+if (!skeyclass-skeys_enabled(ss)) {
+error_setg(lerr, This guest is not using storage keys.
+ Nothing to dump.);
+error_propagate(errp, lerr);
+return;
+}
+
+f = qemu_fopen(filename, wb);
+if (!f) {
+error_setg(lerr, Could not open file);
+error_propagate(errp, lerr);
+return;
+}
+
+buf = g_try_malloc(S390_SKEYS_BUFFER_SIZE);
+if (!buf) {
+error_setg(lerr, Could not allocate memory);
+error_propagate(errp, lerr);
+goto out;
+}
+
+/* we'll only dump initial memory for now */
+while (handled_count total_count) {
+/* Calculate how many keys to ask for handle overflow case */
+cur_count = MIN(total_count - handled_count, S390_SKEYS_BUFFER_SIZE);
+
+ret = skeyclass-get_skeys(ss, cur_gfn, cur_count, buf);
+if (ret 0) {
+error_setg(lerr, get_keys error %d, ret);
+error_propagate(errp, lerr);
+goto out_free;
+}
+
+/* write keys to stream */
+write_keys(f, buf, cur_gfn, cur_count, lerr);
+if (lerr) {
+error_propagate(errp, lerr);
+goto out_free;
+}
+
+cur_gfn += cur_count;
+handled_count += cur_count;
+}
+
+out_free:
+g_free(buf);
+out:
+qemu_fclose(f);
+}
+
static void qemu_s390_skeys_init(Object *obj)
{
QEMUS390SKeysState *skeys = QEMU_S390_SKEYS(obj);
diff --git a/monitor.c b/monitor.c
index fc32f12..daa3d98 100644
--- a/monitor.c
+++ b/monitor.c
@@ -5361,3 +5361,10 @@ void qmp_rtc_reset_reinjection(Error **errp)
error_setg(errp, QERR_FEATURE_DISABLED, rtc-reset-reinjection);
}
#endif
+
+#ifndef TARGET_S390X
+void qmp_dump_skeys(const char *filename, Error **errp)
+{
+error_setg(errp, QERR_FEATURE_DISABLED, dump-skeys);
+}
+#endif
diff --git a/qapi-schema.json b/qapi-schema.json
index 4342a08..1213b4e 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -2058,6 +2058,19 @@
'returns': 'DumpGuestMemoryCapability' }
##
+# @dump-skeys
+#
+# Dump guest's storage keys. @filename: the path to the file to dump to.
+# This command is only supported on s390 architecture.
+#
+# Returns: nothing on success
+#
+# Since: 2.5
+##
+{ 'command': 'dump-skeys',
+ 'data': { 'filename': 'str' } }
+
+##
# @netdev_add:
#
# Add a network backend.
diff --git a/qmp-commands.hx b/qmp-commands.hx
index
[Qemu-devel] [PATCH v2 8/8] s390x: Disable storage key migration on old machine type
From: Jason J. Herne jjhe...@linux.vnet.ibm.com
This code disables storage key migration when an older machine type is
specified.
Reviewed-by: David Hildenbrand d...@linux.vnet.ibm.com
Signed-off-by: Jason J. Herne jjhe...@linux.vnet.ibm.com
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
---
hw/s390x/s390-skeys.c | 33 ++---
hw/s390x/s390-virtio-ccw.c | 12
include/hw/s390x/storage-keys.h | 1 +
3 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c
index 9d4a79d..392d547 100644
--- a/hw/s390x/s390-skeys.c
+++ b/hw/s390x/s390-skeys.c
@@ -363,12 +363,39 @@ static int s390_storage_keys_load(QEMUFile *f, void
*opaque, int version_id)
return ret;
}
-static void s390_skeys_instance_init(Object *obj)
+static inline bool s390_skeys_get_migration_enabled(Object *obj, Error **errp)
+{
+S390SKeysState *ss = S390_SKEYS(obj);
+
+return ss-migration_enabled;
+}
+
+static inline void s390_skeys_set_migration_enabled(Object *obj, bool value,
+Error **errp)
{
S390SKeysState *ss = S390_SKEYS(obj);
-register_savevm(NULL, TYPE_S390_SKEYS, 0, 1, s390_storage_keys_save,
-s390_storage_keys_load, ss);
+/* Prevent double registration of savevm handler */
+if (ss-migration_enabled == value) {
+return;
+}
+
+ss-migration_enabled = value;
+
+if (ss-migration_enabled) {
+register_savevm(NULL, TYPE_S390_SKEYS, 0, 1, s390_storage_keys_save,
+s390_storage_keys_load, ss);
+} else {
+unregister_savevm(DEVICE(ss), TYPE_S390_SKEYS, ss);
+}
+}
+
+static void s390_skeys_instance_init(Object *obj)
+{
+object_property_add_bool(obj, migration-enabled,
+ s390_skeys_get_migration_enabled,
+ s390_skeys_set_migration_enabled, NULL);
+object_property_set_bool(obj, true, migration-enabled, NULL);
}
static void s390_skeys_class_init(ObjectClass *oc, void *data)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 0a057ae..e2a26e9 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -282,12 +282,24 @@ static const TypeInfo ccw_machine_info = {
},
};
+#define CCW_COMPAT_2_4 \
+{\
+.driver = TYPE_S390_SKEYS,\
+.property = migration-enabled,\
+.value= off,\
+},
+
static void ccw_machine_2_4_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+static GlobalProperty compat_props[] = {
+CCW_COMPAT_2_4
+{ /* end of list */ }
+};
mc-name = s390-ccw-virtio-2.4;
mc-desc = VirtIO-ccw based S390 machine v2.4;
+mc-compat_props = compat_props;
}
static const TypeInfo ccw_machine_2_4_info = {
diff --git a/include/hw/s390x/storage-keys.h b/include/hw/s390x/storage-keys.h
index 18e08d2..72b850c 100644
--- a/include/hw/s390x/storage-keys.h
+++ b/include/hw/s390x/storage-keys.h
@@ -21,6 +21,7 @@
typedef struct S390SKeysState {
DeviceState parent_obj;
+bool migration_enabled;
} S390SKeysState;
--
2.5.0
Re: [Qemu-devel] [PATCH] q35: Remove old machine versions
On Mon, Aug 24, 2015 at 11:54:48AM +0200, Markus Armbruster wrote: John Snow js...@redhat.com writes: On 08/19/2015 02:55 AM, Dr. David Alan Gilbert wrote: * Eduardo Habkost (ehabk...@redhat.com) wrote: Migration with q35 was not possible before commit 04329029a8c539eb5f75dcb6d8b016f0c53a031a, because q35 unconditionally creates an ich9-ahci device, that was marked as unmigratable. So all q35 machines before pc-q35-2.4 were unmigratable, and there's no point in keeping compatibility code for them. Remove all old pc-q35 machine classes and keep only pc-q35-2.4. But doesn't that mean that anyone who has a machine configured with one of those machine types will suddenly find it wont start? Dave To some extent, all versions of this board prior to 2.4 should be considered unsupported and we should discourage their use anyway. If you really want, I suppose we could just alias them to 2.4 ... I'd very much prefer an honest won't start over a silent change of the machine type. If we really want to bend over backwards for existing uses of these machine types, we could make them error out with use pc-q35-2.5 instead. Since I don't think they exist outside testing, I wouldn't bother. Agreed, we should be reporting a hard error for any machine types we have deleted. Or if we care about smooth upgrade path then we shouldn't be deleting them in the first place. Silently changing the user's requested machine type into a different machine type is violating the semantics of stable machine types. Regards, Daniel -- |: http://berrange.com -o-http://www.flickr.com/photos/dberrange/ :| |: http://libvirt.org -o- http://virt-manager.org :| |: http://autobuild.org -o- http://search.cpan.org/~danberr/ :| |: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
Re: [Qemu-devel] [PATCH 03/12] qga: move string split in seperate function
Quoting Marc-André Lureau (2015-07-01 06:47:38)
The function is going to be reused in a later patch.
Signed-off-by: Marc-André Lureau marcandre.lur...@gmail.com
Reviewed-by: Michael Roth mdr...@linux.vnet.ibm.com
---
qga/main.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/qga/main.c b/qga/main.c
index af93992..0c455f8 100644
--- a/qga/main.c
+++ b/qga/main.c
@@ -921,6 +921,26 @@ static void ga_print_cmd(QmpCommand *cmd, void *opaque)
printf(%s\n, qmp_command_name(cmd));
}
+static GList *split_list(gchar *str, const gchar separator)
+{
+GList *list = NULL;
+int i, j, len;
+
+for (j = 0, i = 0, len = strlen(str); i len; i++) {
+if (str[i] == separator) {
+str[i] = 0;
+list = g_list_append(list, str[j]);
+j = i + 1;
+}
+}
+
+if (j i) {
+list = g_list_append(list, str[j]);
+}
+
+return list;
+}
+
int main(int argc, char **argv)
{
const char *sopt = hVvdm:p:l:f:F::b:s:t:;
@@ -953,7 +973,7 @@ int main(int argc, char **argv)
{ statedir, 1, NULL, 't' },
{ NULL, 0, NULL, 0 }
};
-int opt_ind = 0, ch, daemonize = 0, i, j, len;
+int opt_ind = 0, ch, daemonize = 0;
GLogLevelFlags log_level = G_LOG_LEVEL_ERROR | G_LOG_LEVEL_CRITICAL;
GList *blacklist = NULL;
GAState *s;
@@ -1001,16 +1021,7 @@ int main(int argc, char **argv)
qmp_for_each_command(ga_print_cmd, NULL);
exit(EXIT_SUCCESS);
}
-for (j = 0, i = 0, len = strlen(optarg); i len; i++) {
-if (optarg[i] == ',') {
-optarg[i] = 0;
-blacklist = g_list_append(blacklist, optarg[j]);
-j = i + 1;
-}
-}
-if (j i) {
-blacklist = g_list_append(blacklist, optarg[j]);
-}
+blacklist = g_list_concat(blacklist, split_list(optarg, ','));
break;
}
#ifdef _WIN32
--
2.4.3
Re: [Qemu-devel] [PULL 00/18] target-arm queue
On 25 August 2015 at 16:23, Peter Maydell peter.mayd...@linaro.org wrote: Here's the ARM queue. I know I have a pile of backed-up code review to do, but I wanted to get these patches out rather than accumulating a fifty-patch queue... This is v2: only change is to drop the two smbios patches. v2 applied to master. -- PMM
[Qemu-devel] Created virtio-vsock wiki page
I have created a wiki page for virtio-vsock. It links to my git repos and the draft virtio specification: http://qemu-project.org/Features/VirtioVsock I'll expand and update it over the coming days and weeks. Please let me know if you'd like to see specific information on there (e.g. step-by-step build QEMU invocation guide). Stefan
Re: [Qemu-devel] [PATCH] q35: Remove old machine versions
On 08/25/2015 05:42 AM, Michael S. Tsirkin wrote: On Wed, Aug 19, 2015 at 09:30:20AM -0700, Eduardo Habkost wrote: On Wed, Aug 19, 2015 at 10:55:26AM +0100, Dr. David Alan Gilbert wrote: * Eduardo Habkost (ehabk...@redhat.com) wrote: Migration with q35 was not possible before commit 04329029a8c539eb5f75dcb6d8b016f0c53a031a, because q35 unconditionally creates an ich9-ahci device, that was marked as unmigratable. So all q35 machines before pc-q35-2.4 were unmigratable, and there's no point in keeping compatibility code for them. Remove all old pc-q35 machine classes and keep only pc-q35-2.4. But doesn't that mean that anyone who has a machine configured with one of those machine types will suddenly find it wont start? Yes, and they will have to update their configuration to use pc-q35-2.4 or newer. That seems easily avoidable: just make pc-q35-X alias pc-q35-2.4 for X 2.4. Both Marcel and Markus would prefer it to fail outright instead of silently perform magic, in response to my suggesting the same thing. -- Eduardo
Re: [Qemu-devel] [PATCH v2 14/18] nvdimm: support NFIT_CMD_IMPLEMENTED function
On Fri, Aug 14, 2015 at 10:52:07PM +0800, Xiao Guangrong wrote:
@@ -306,6 +354,18 @@ struct dsm_buffer {
static ram_addr_t dsm_addr;
static size_t dsm_size;
+struct cmd_out_implemented {
QEMU coding style uses typedef struct {} CamelCase. Please follow this
convention in all user-defined structs (see ./CODING_STYLE).
static void dsm_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
+struct MemoryRegion *dsm_ram_mr = opaque;
+struct dsm_buffer *dsm;
+struct dsm_out *out;
+void *buf;
+
assert(val == NOTIFY_VALUE);
The guest should not be able to cause an abort(3). If val !=
NOTIFY_VALUE we can do nvdebug() and then return.
+
+buf = memory_region_get_ram_ptr(dsm_ram_mr);
+dsm = buf;
+out = buf;
+
+le32_to_cpus(dsm-handle);
+le32_to_cpus(dsm-arg1);
+le32_to_cpus(dsm-arg2);
Can SMP guests modify DSM RAM while this thread is running?
We must avoid race conditions. It's probably better to copy in data
before byte-swapping or checking input values.
Re: [Qemu-devel] [PATCH v2 00/18] implement vNVDIMM
On Fri, Aug 14, 2015 at 10:51:53PM +0800, Xiao Guangrong wrote: Changlog: - Use litten endian for DSM method, thanks for Stefan's suggestion - introduce a new parameter, @configdata, if it's false, Qemu will build a static and readonly namespace in memory and use it serveing for DSM GET_CONFIG_SIZE/GET_CONFIG_DATA requests. In this case, no reserved region is needed at the end of the @file, it is good for the user who want to pass whole nvdimm device and make its data completely be visible to guest - divide the source code into separated files and add maintain info I have skipped ACPI patches because I'm not very familiar with that area. Have you thought about live migration? Are the contents of the NVDIMM migrated since they are registered as a RAM region? Stefan
Re: [Qemu-devel] [RFC PATCH v0 1/3] pc-dimm: Add a field to PCDIMMDevice to mark device deletion state
On Mon, Aug 24, 2015 at 09:30:35PM -0500, Michael Roth wrote: Quoting Bharata B Rao (2015-08-19 01:56:09) Add a field to PCDIMMDevice to note that the device has been marked for removal. This will be used by PowerPC memory hotplug code to honour the LMB removal requests of only those LMBs that belong to PCDIMMDevice that has been marked for removal. This will be set from -unplug() handler. Why not track the delete pending state in the DRC? We have an awaiting_release flag there for similar purpose. Ah yes, that should be possible. Will drop this patch in the next iteration. Regards, Bharata.
Re: [Qemu-devel] [PATCH 5/6] virtio-pci: introduce pio notification capability for modern device
On 08/25/2015 07:48 PM, Michael S. Tsirkin wrote: On Fri, Aug 21, 2015 at 05:05:49PM +0800, Jason Wang wrote: We used to use mmio for notification. This could be slow on some arch (e.g on x86 without EPT). So this patch introduces pio bar and a pio notification cap for modern device. This ability is enabled through property modern-pio-notify for virtio pci devices and was disabled by default. Management can enable when it thinks it was needed. Benchmarks shows almost no obvious difference with legacy device. Thanks Wenli Quan wq...@redhat.com for the benchmarking. Cc: Michael S. Tsirkin m...@redhat.com Signed-off-by: Jason Wang jasow...@redhat.com I don't really care much about non-EPT hosts, but if you propose a patch to optimize them, it should be accompanied by numbers showing the performance difference. According to the test, PIO is a little bit faster than fast mmio in some specific TCP_RR case: modern device fast mmio vs modern device pio: TCP_RR: size/session/+transaction rate%/+cpu%/-+per cpu%/ 64/1/[+1.5646%]/+5.6604%/-4.3415%/ 64/25/+0.3003%/-0.4517%/+0.7486%/ ... 256/1/[+1.0046%]/[-6.5238%]/[+7.0673%]/ So the improvement is almost as much as previous patch.
[Qemu-devel] [FIX PATCH] spapr_rtas: Prevent QEMU crash during hotplug without a prior device_add
If drmgr is used in the guest to hotplug a device before a device_add
has been issued via the QEMU monitor, QEMU segfaults in configure_connector
call. This occurs due to accessing of NULL FDT which otherwise would have
been created and associated with the DRC during device_add command.
Check for NULL FDT and return failure from configure_connector call.
Signed-off-by: Bharata B Rao bhar...@linux.vnet.ibm.com
Cc: Michael Roth mdr...@linux.vnet.ibm.com
---
Not fully sure if RTAS_OUT_HW_ERROR is the right error code here. Should
we be using RTAS_OUT_NOT_SUPPORTED instead ?
hw/ppc/spapr_rtas.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index e99e25f..3be8eec 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -522,6 +522,12 @@ static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
fdt = drck-get_fdt(drc, NULL);
+if (!fdt) {
+DPRINTF(rtas_ibm_configure_connector: Missing FDT for DRC index:
%xh\n,
+drc_index);
+rc = RTAS_OUT_HW_ERROR;
+goto out;
+}
ccs = spapr_ccs_find(spapr, drc_index);
if (!ccs) {
--
2.1.0
Re: [Qemu-devel] [RFC 2/4] hw/i386: Introduce AMD IOMMU
Also, am not sure what HATS, GATS and sizes of virtual addresses(for
both guest and host) I should be using.
On Tue, Aug 25, 2015 at 10:41 AM, David kiarie davidkiar...@gmail.com wrote:
On Tue, Aug 25, 2015 at 10:31 AM, Valentine Sinitsyn
valentine.sinit...@gmail.com wrote:
On 25.08.2015 12:25, David kiarie wrote:
On Tue, Aug 25, 2015 at 9:39 AM, Valentine Sinitsyn
valentine.sinit...@gmail.com wrote:
Hi,
On 25.08.2015 04:19, David Kiarie wrote:
From: David davidkiar...@gmail.com
Add AMD IOMMU emulation to Qemu. This is a very basic AMD IOMMU
emulation that only does translation and some basic Event logging.
Guest translation enables nested PCI passthrough
Signed-off-by: David Kiarie davidkiar...@gmail.com
---
hw/i386/Makefile.objs | 1 +
hw/i386/amd_iommu.c | 993
++
hw/i386/amd_iommu.h | 298 +++
3 files changed, 1292 insertions(+)
create mode 100644 hw/i386/amd_iommu.c
create mode 100644 hw/i386/amd_iommu.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index ebd1015..2bae11c 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -3,6 +3,7 @@ obj-y += multiboot.o
obj-y += pc.o pc_piix.o pc_q35.o
obj-y += pc_sysfw.o
obj-y += intel_iommu.o
+obj-y += amd_iommu.o
obj-$(CONFIG_XEN) += ../xenpv/ xen/
obj-y += kvmvapic.o
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
new file mode 100644
index 000..a3a0b20
--- /dev/null
+++ b/hw/i386/amd_iommu.c
@@ -0,0 +1,993 @@
+/*
+ * QEMU emulation of an AMD IOMMU (AMD-Vi)
+ *
+ * Copyright (C) 2011 Eduard - Gabriel Munteanu
+ * Copyright (C) 2015 David Kiarie, davidkiar...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ *
+ */
+#include hw/i386/amd_iommu.h
+
+#define PCI_EXT_CAP_ID_PASID 0x1B
+#define PCI_EXT_CAP_ID_PRI 0x13
+
+#define PCI_SLOT(devfn) (((devfn) 3) 0x1f)
+#define PCI_FUNC(devfn) ((devfn) 0x07)
+
+#define MAX_VA_ADDR (64UL 5)
+#define MAX_PH_ADDR (48UL 8)
+#define MAX_GVA_ADDR (64UL 15)
+
+//#define DEBUG_AMD_IOMMU
+#ifdef DEBUG_AMD_IOMMU
+enum {
+DEBUG_GENERAL, DEBUG_CAPAB, DEBUG_MMIO, DEBUG_ELOG,
+DEBUG_CACHE, DEBUG_COMMAND, DEBUG_MMU
+};
+
+#define IOMMU_DBGBIT(x) (1 DEBUG_##x)
+static int iommu_dbgflags = IOMMU_DBGBIT(GENERAL) | IOMMU_DBGBIT(MMU) |
IOMMU_DBGBIT(MMIO);
+//| IOMMU_DBGBIT(CAPAB) | IOMMU_DBGBIT(ELOG) | IOMMU_DBGBIT(CACHE) |
IOMMU_DBGBIT(COMMAND);
+
+#define IOMMU_DPRINTF(what, fmt, ...) do { \
+if (iommu_dbgflags IOMMU_DBGBIT(what)) { \
+fprintf(stderr, (amd-iommu)%s: fmt \n, __func__, \
+## __VA_ARGS__); } \
+} while (0)
+#else
+#define IOMMU_DPRINTF(what, fmt, ...) do {} while (0)
+#endif
+
+/* helper functions - FIXME - provide for reading one byte */
+static uint16_t amd_iommu_readw(AMDIOMMUState *s, hwaddr addr)
+{
+return lduw_le_p(s-mmior[addr]);
+}
+
+static uint32_t amd_iommu_readl(AMDIOMMUState *s, hwaddr addr)
+{
+return ldl_le_p(s-mmior[addr]);
+}
+
+static uint64_t amd_iommu_readq(AMDIOMMUState *s, hwaddr addr)
+{
+return ldq_le_p(s-mmior[addr]);
+}
+
+static void amd_iommu_writew(AMDIOMMUState *s, hwaddr addr, uint16_t
val)
+{
+stw_le_p(s-mmior[addr], val);
+}
+
+static void amd_iommu_writel(AMDIOMMUState *s, hwaddr addr, uint32_t
val)
+{
+stl_le_p(s-mmior[addr], val);
+}
+
+static void amd_iommu_writeq(AMDIOMMUState *s, hwaddr addr, uint64_t
val)
+{
+stq_le_p(s-mmior[addr], val);
+}
+
+/* execute a completion wait command */
+static void amd_iommu_completion_wait(AMDIOMMUState *s, uint8_t *cmd)
+{
+unsigned int addr;
+
+/* completion store */
+if(cmd[0] COM_COMPLETION_STORE_MASK){
+addr = le64_to_cpu(*(uint64_t*)cmd) COM_STORE_ADDRESS_MASK;
+if(dma_memory_write(address_space_memory, addr, cmd + 8, 8)){
+IOMMU_DPRINTF(ELOG, error: fail to write at address
0%xPRIx64, addr);
+}
+
+}
+
+/* set completion interrupt */
When I was experimenting with a real IOMMU, it all looked like if both
COM_COMPLETION_STORE_MASK and COM_COMPLETION_BIT are set in the command,
only an interrupt is generated. Could someone comment on this?
Which bit do you mean by COM_COMPLETION_BIT ?Do
Re: [Qemu-devel] [PATCH RFC v3 30/32] qapi: New QMP command query-schema for QMP schema introspection
Eric Blake ebl...@redhat.com writes:
On 08/24/2015 10:55 AM, Markus Armbruster wrote:
Our motivation for dropping nested structs was to avoid burning the
'name': {} struct member syntax on a trivial and rarely used
convenience, and instead make it available for a way to specify member
attributes beyond name and type.
Is there a chance we want to define simple union cases with attributes
beyond tag value and type?
You may have a valid point there. It's hard to predict the future, but
leaving dictionary open for future use is the most extensible approach.
But in the patches I'm currently working on, I had only been adding
support for anonymous types for the branches of flat unions; I
intentionally left simple unions to REQUIRE a type name for the branches
(because of the way we create a wrapper type around the single data
member for introspection purposes).
I asked only about simple unions, but my question actually applies to
any kind of union. In fact, we could decide to reserve the {} syntax
for extensions in the longhand syntactical form, and still burn it on
convenience in shorthand, sugared forms.
I think we have a better chance to answer that question after we clean
non-simple unions.
Well, my proposed cleanup was figuring out a way to explicitly specify
that for a given enum value, we add no additional members to the wire
struct. But there is a possible alternative syntax for that:
{ 'union': 'Union', 'base': 'Base', 'discriminator': 'type',
'data': { 'branch1': 'AdditionalMembers',
'branch2': null } }
which uses 'null' in place of '{}' for the explicitly empty case, while
still requiring a type name for all other branches.
Let's revisit this once we've figured out how to clean up union syntax.
I still think that
requiring a user to explicitly list all branches of a union is a nice
fail-safe (if the enum is extended, we are then reminded to update the
union to match) that we don't currently have.
Missing case reminders are obviously useful for code switching over an
enumeration. They're less useful for data. A forgotten case in code
compiles fine, then fails (often catastrophically) at run time. A
forgotten case in data simply won't compile (assuming a statically
checked language).
Both Abort and ChardevDummy exist only because you need a type to
declare a simple union case. I'd like to explore cleaning up the
convoluted union syntax first. If we then still have a need for
empty structs, we can consider optimizing them.
And that's where my patches were headed - by allowing a dict instead of
a type name for the branches of a flat union, the syntax for flat unions
becomes simpler, and allows us to sanely represent a
no-additional-members variant without needing 'Abort' as an empty type.
Empty cases in flat unions are not a problem: simply don't mention the
tag value.
But that's opposite of the direction I want to move, where we require
all branches to be listed, but have a clean way to document the branches
that add no additional members to the variant object.
Let's figure out how to clean up union syntax first, and how to do empty
cases second.
I'd like to explore doing unions in schema syntax the way we represent
them internally and in introspection. Basically get rid of the need to
inherit the common members from a base nonsense.
I've already posted patches that would allow:
{ 'union': 'Union', 'base': { ... }, 'discriminator': 'type',
'data': { ... } }
that is, allowing the base fields to be specified inline as an anonymous
struct rather than having to create a one-off named struct for that task.
https://lists.gnu.org/archive/html/qemu-devel/2015-08/msg02346.html
In my opinion, the whole 'base' business is a hack to inject additional
common members into a union. If I remember correctly, Kevin did that
just to keep his flat union work minimally invasive. Considering what
it took us to do introspection the not minimally invasive way, I can't
fault him for taking a shortcut.
In my recent KVM Forum talk, I showed the QAPI schema and introspection
value for SchemaInfo. The former is a flat union with a struct base,
i.e. two types connected by a (non-trivial) inheritance relation. The
latter is simpler: a single, straightforward variant record. That's
what I'd like to have in the schema, too.
https://events.linuxfoundation.org/sites/events/files/slides/armbru-qemu-introspection.pdf
But there's still the question of whether we want to always tie the
union branches to an explicitly named enum, or whether it is nice to
preserve the current simple union semantics that an implicit enum is
created to cover all branches when an explicit enum type is not named.
Conversely, I still want to get to the point that even a simple union
can optionally document that it reuses an existing enum (along with the
corresponding qapi-generator enforced rules
Re: [Qemu-devel] [PATCH] q35: Remove old machine versions
On 08/24/2015 12:54 PM, Markus Armbruster wrote: John Snow js...@redhat.com writes: On 08/19/2015 02:55 AM, Dr. David Alan Gilbert wrote: * Eduardo Habkost (ehabk...@redhat.com) wrote: Migration with q35 was not possible before commit 04329029a8c539eb5f75dcb6d8b016f0c53a031a, because q35 unconditionally creates an ich9-ahci device, that was marked as unmigratable. So all q35 machines before pc-q35-2.4 were unmigratable, and there's no point in keeping compatibility code for them. Remove all old pc-q35 machine classes and keep only pc-q35-2.4. But doesn't that mean that anyone who has a machine configured with one of those machine types will suddenly find it wont start? Dave To some extent, all versions of this board prior to 2.4 should be considered unsupported and we should discourage their use anyway. If you really want, I suppose we could just alias them to 2.4 ... I'd very much prefer an honest won't start over a silent change of the machine type. +1 Thanks, Marcel If we really want to bend over backwards for existing uses of these machine types, we could make them error out with use pc-q35-2.5 instead. Since I don't think they exist outside testing, I wouldn't bother.
Re: [Qemu-devel] [RFC 2/4] hw/i386: Introduce AMD IOMMU
On Tue, Aug 25, 2015 at 9:39 AM, Valentine Sinitsyn
valentine.sinit...@gmail.com wrote:
Hi,
On 25.08.2015 04:19, David Kiarie wrote:
From: David davidkiar...@gmail.com
Add AMD IOMMU emulation to Qemu. This is a very basic AMD IOMMU
emulation that only does translation and some basic Event logging.
Guest translation enables nested PCI passthrough
Signed-off-by: David Kiarie davidkiar...@gmail.com
---
hw/i386/Makefile.objs | 1 +
hw/i386/amd_iommu.c | 993
++
hw/i386/amd_iommu.h | 298 +++
3 files changed, 1292 insertions(+)
create mode 100644 hw/i386/amd_iommu.c
create mode 100644 hw/i386/amd_iommu.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index ebd1015..2bae11c 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -3,6 +3,7 @@ obj-y += multiboot.o
obj-y += pc.o pc_piix.o pc_q35.o
obj-y += pc_sysfw.o
obj-y += intel_iommu.o
+obj-y += amd_iommu.o
obj-$(CONFIG_XEN) += ../xenpv/ xen/
obj-y += kvmvapic.o
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
new file mode 100644
index 000..a3a0b20
--- /dev/null
+++ b/hw/i386/amd_iommu.c
@@ -0,0 +1,993 @@
+/*
+ * QEMU emulation of an AMD IOMMU (AMD-Vi)
+ *
+ * Copyright (C) 2011 Eduard - Gabriel Munteanu
+ * Copyright (C) 2015 David Kiarie, davidkiar...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ *
+ */
+#include hw/i386/amd_iommu.h
+
+#define PCI_EXT_CAP_ID_PASID 0x1B
+#define PCI_EXT_CAP_ID_PRI 0x13
+
+#define PCI_SLOT(devfn) (((devfn) 3) 0x1f)
+#define PCI_FUNC(devfn) ((devfn) 0x07)
+
+#define MAX_VA_ADDR (64UL 5)
+#define MAX_PH_ADDR (48UL 8)
+#define MAX_GVA_ADDR (64UL 15)
+
+//#define DEBUG_AMD_IOMMU
+#ifdef DEBUG_AMD_IOMMU
+enum {
+DEBUG_GENERAL, DEBUG_CAPAB, DEBUG_MMIO, DEBUG_ELOG,
+DEBUG_CACHE, DEBUG_COMMAND, DEBUG_MMU
+};
+
+#define IOMMU_DBGBIT(x) (1 DEBUG_##x)
+static int iommu_dbgflags = IOMMU_DBGBIT(GENERAL) | IOMMU_DBGBIT(MMU) |
IOMMU_DBGBIT(MMIO);
+//| IOMMU_DBGBIT(CAPAB) | IOMMU_DBGBIT(ELOG) | IOMMU_DBGBIT(CACHE) |
IOMMU_DBGBIT(COMMAND);
+
+#define IOMMU_DPRINTF(what, fmt, ...) do { \
+if (iommu_dbgflags IOMMU_DBGBIT(what)) { \
+fprintf(stderr, (amd-iommu)%s: fmt \n, __func__, \
+## __VA_ARGS__); } \
+} while (0)
+#else
+#define IOMMU_DPRINTF(what, fmt, ...) do {} while (0)
+#endif
+
+/* helper functions - FIXME - provide for reading one byte */
+static uint16_t amd_iommu_readw(AMDIOMMUState *s, hwaddr addr)
+{
+return lduw_le_p(s-mmior[addr]);
+}
+
+static uint32_t amd_iommu_readl(AMDIOMMUState *s, hwaddr addr)
+{
+return ldl_le_p(s-mmior[addr]);
+}
+
+static uint64_t amd_iommu_readq(AMDIOMMUState *s, hwaddr addr)
+{
+return ldq_le_p(s-mmior[addr]);
+}
+
+static void amd_iommu_writew(AMDIOMMUState *s, hwaddr addr, uint16_t val)
+{
+stw_le_p(s-mmior[addr], val);
+}
+
+static void amd_iommu_writel(AMDIOMMUState *s, hwaddr addr, uint32_t val)
+{
+stl_le_p(s-mmior[addr], val);
+}
+
+static void amd_iommu_writeq(AMDIOMMUState *s, hwaddr addr, uint64_t val)
+{
+stq_le_p(s-mmior[addr], val);
+}
+
+/* execute a completion wait command */
+static void amd_iommu_completion_wait(AMDIOMMUState *s, uint8_t *cmd)
+{
+unsigned int addr;
+
+/* completion store */
+if(cmd[0] COM_COMPLETION_STORE_MASK){
+addr = le64_to_cpu(*(uint64_t*)cmd) COM_STORE_ADDRESS_MASK;
+if(dma_memory_write(address_space_memory, addr, cmd + 8, 8)){
+IOMMU_DPRINTF(ELOG, error: fail to write at address
0%xPRIx64, addr);
+}
+
+}
+
+/* set completion interrupt */
When I was experimenting with a real IOMMU, it all looked like if both
COM_COMPLETION_STORE_MASK and COM_COMPLETION_BIT are set in the command,
only an interrupt is generated. Could someone comment on this?
Which bit do you mean by COM_COMPLETION_BIT ?Do you mean
'COM_COMPLETION_INTR ? If yes, when would such a scenario occur ?
I have checked on from the spec, I can't find anything worthwhile and
I don't any of us is running an IOMMU - except you, so I guess you
should tell us what to do...
+if (cmd[0] COM_COMPLETION_INTR){
+s-mmior[MMIO_STATUS] |=
[Qemu-devel] [Bug 1488363] [NEW] qemu 2.4.0 hangs using vfio for pci passthrough of graphics card
Public bug reported: 2.3.0 (manjaro distro package) works fine. 2.4.0 (manjaro or the arch vanilla one) hangs on the SeaBIOS screen when saying Press F12 for boot menu. All tested with the same hardware, OS, command and configuration. It also starts without the GPU passed through, even with the USB passed through. I am using the latest SeaBIOS 1.8.2. The release notes say: VFIO Support for resetting AMD Bonaire and Hawaii GPUs Platform device passthrough support for Calxeda xgmac devices So maybe something there broke it. I am using the arch qemu 2.4.0 PKGBUILD (modified to have make -j8 and removed iscsi, gluster, ceph, etc.), which uses vanilla sources and no patches. https://projects.archlinux.org/svntogit/packages.git/tree/trunk?h=packages/qemu I am not using a frontend. I am using a script I wrote that generates the command below. Guest OS here would be 64 bit windows 7, but it didn't start so that's not relevant. Also a Manjaro Linux VM won't start. CPU is AMD FX-8150; board is Gigabyte GA-990FXA-UD5 (990FX chipset). full command line (without the \ after each line) is: qemu-system-x86_64 -enable-kvm -M q35 -m 3584 -cpu host -boot c -smp 7,sockets=1,cores=7,threads=1 -vga none -device ioh3420,bus=pcie.0,addr=1c.0,port=1,chassis=1,id=root.1 -device vfio-pci,host=04:00.0,bus=root.1,multifunction=on,x-vga=on,addr=0.0,romfile=Sapphire.R7260X.1024.131106.rom -device vfio-pci,host=00:14.2,bus=pcie.0 -device vfio-pci,host=00:16.0,bus=root.1 -device vfio-pci,host=00:16.2,bus=root.1 -usb -device ahci,bus=pcie.0,id=ahci -drive file=/dev/data/vm1,id=disk1,format=raw,if=virtio,index=0,media=disk,discard=on -drive media=cdrom,id=cdrom,index=5,media=cdrom -netdev type=tap,id=net0,ifname=tap-vm1 -device virtio-net-pci,netdev=net0,mac=00:01:02:03:04:05 -monitor stdio -boot menu=on $ lspci -nn | grep -E 04:00.0|00:14.2|00:16.0|00:16.2 00:14.2 Audio device [0403]: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia (Intel HDA) [1002:4383] (rev 40) 00:16.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] 00:16.2 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] 04:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Bonaire XTX [Radeon R7 260X] [1002:6658] Also I have this one that also hangs: 05:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Juniper XT [Radeon HD 6770] [1002:68ba] ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1488363 Title: qemu 2.4.0 hangs using vfio for pci passthrough of graphics card Status in QEMU: New Bug description: 2.3.0 (manjaro distro package) works fine. 2.4.0 (manjaro or the arch vanilla one) hangs on the SeaBIOS screen when saying Press F12 for boot menu. All tested with the same hardware, OS, command and configuration. It also starts without the GPU passed through, even with the USB passed through. I am using the latest SeaBIOS 1.8.2. The release notes say: VFIO Support for resetting AMD Bonaire and Hawaii GPUs Platform device passthrough support for Calxeda xgmac devices So maybe something there broke it. I am using the arch qemu 2.4.0 PKGBUILD (modified to have make -j8 and removed iscsi, gluster, ceph, etc.), which uses vanilla sources and no patches. https://projects.archlinux.org/svntogit/packages.git/tree/trunk?h=packages/qemu I am not using a frontend. I am using a script I wrote that generates the command below. Guest OS here would be 64 bit windows 7, but it didn't start so that's not relevant. Also a Manjaro Linux VM won't start. CPU is AMD FX-8150; board is Gigabyte GA-990FXA-UD5 (990FX chipset). full command line (without the \ after each line) is: qemu-system-x86_64 -enable-kvm -M q35 -m 3584 -cpu host -boot c -smp 7,sockets=1,cores=7,threads=1 -vga none -device ioh3420,bus=pcie.0,addr=1c.0,port=1,chassis=1,id=root.1 -device vfio-pci,host=04:00.0,bus=root.1,multifunction=on,x-vga=on,addr=0.0,romfile=Sapphire.R7260X.1024.131106.rom -device vfio-pci,host=00:14.2,bus=pcie.0 -device vfio-pci,host=00:16.0,bus=root.1 -device vfio-pci,host=00:16.2,bus=root.1 -usb -device ahci,bus=pcie.0,id=ahci -drive file=/dev/data/vm1,id=disk1,format=raw,if=virtio,index=0,media=disk,discard=on -drive media=cdrom,id=cdrom,index=5,media=cdrom -netdev type=tap,id=net0,ifname=tap-vm1 -device virtio-net-pci,netdev=net0,mac=00:01:02:03:04:05 -monitor stdio -boot menu=on $ lspci -nn | grep -E 04:00.0|00:14.2|00:16.0|00:16.2 00:14.2 Audio
Re: [Qemu-devel] [RFC 2/4] hw/i386: Introduce AMD IOMMU
On Tue, Aug 25, 2015 at 10:31 AM, Valentine Sinitsyn
valentine.sinit...@gmail.com wrote:
On 25.08.2015 12:25, David kiarie wrote:
On Tue, Aug 25, 2015 at 9:39 AM, Valentine Sinitsyn
valentine.sinit...@gmail.com wrote:
Hi,
On 25.08.2015 04:19, David Kiarie wrote:
From: David davidkiar...@gmail.com
Add AMD IOMMU emulation to Qemu. This is a very basic AMD IOMMU
emulation that only does translation and some basic Event logging.
Guest translation enables nested PCI passthrough
Signed-off-by: David Kiarie davidkiar...@gmail.com
---
hw/i386/Makefile.objs | 1 +
hw/i386/amd_iommu.c | 993
++
hw/i386/amd_iommu.h | 298 +++
3 files changed, 1292 insertions(+)
create mode 100644 hw/i386/amd_iommu.c
create mode 100644 hw/i386/amd_iommu.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index ebd1015..2bae11c 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -3,6 +3,7 @@ obj-y += multiboot.o
obj-y += pc.o pc_piix.o pc_q35.o
obj-y += pc_sysfw.o
obj-y += intel_iommu.o
+obj-y += amd_iommu.o
obj-$(CONFIG_XEN) += ../xenpv/ xen/
obj-y += kvmvapic.o
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
new file mode 100644
index 000..a3a0b20
--- /dev/null
+++ b/hw/i386/amd_iommu.c
@@ -0,0 +1,993 @@
+/*
+ * QEMU emulation of an AMD IOMMU (AMD-Vi)
+ *
+ * Copyright (C) 2011 Eduard - Gabriel Munteanu
+ * Copyright (C) 2015 David Kiarie, davidkiar...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ *
+ */
+#include hw/i386/amd_iommu.h
+
+#define PCI_EXT_CAP_ID_PASID 0x1B
+#define PCI_EXT_CAP_ID_PRI 0x13
+
+#define PCI_SLOT(devfn) (((devfn) 3) 0x1f)
+#define PCI_FUNC(devfn) ((devfn) 0x07)
+
+#define MAX_VA_ADDR (64UL 5)
+#define MAX_PH_ADDR (48UL 8)
+#define MAX_GVA_ADDR (64UL 15)
+
+//#define DEBUG_AMD_IOMMU
+#ifdef DEBUG_AMD_IOMMU
+enum {
+DEBUG_GENERAL, DEBUG_CAPAB, DEBUG_MMIO, DEBUG_ELOG,
+DEBUG_CACHE, DEBUG_COMMAND, DEBUG_MMU
+};
+
+#define IOMMU_DBGBIT(x) (1 DEBUG_##x)
+static int iommu_dbgflags = IOMMU_DBGBIT(GENERAL) | IOMMU_DBGBIT(MMU) |
IOMMU_DBGBIT(MMIO);
+//| IOMMU_DBGBIT(CAPAB) | IOMMU_DBGBIT(ELOG) | IOMMU_DBGBIT(CACHE) |
IOMMU_DBGBIT(COMMAND);
+
+#define IOMMU_DPRINTF(what, fmt, ...) do { \
+if (iommu_dbgflags IOMMU_DBGBIT(what)) { \
+fprintf(stderr, (amd-iommu)%s: fmt \n, __func__, \
+## __VA_ARGS__); } \
+} while (0)
+#else
+#define IOMMU_DPRINTF(what, fmt, ...) do {} while (0)
+#endif
+
+/* helper functions - FIXME - provide for reading one byte */
+static uint16_t amd_iommu_readw(AMDIOMMUState *s, hwaddr addr)
+{
+return lduw_le_p(s-mmior[addr]);
+}
+
+static uint32_t amd_iommu_readl(AMDIOMMUState *s, hwaddr addr)
+{
+return ldl_le_p(s-mmior[addr]);
+}
+
+static uint64_t amd_iommu_readq(AMDIOMMUState *s, hwaddr addr)
+{
+return ldq_le_p(s-mmior[addr]);
+}
+
+static void amd_iommu_writew(AMDIOMMUState *s, hwaddr addr, uint16_t
val)
+{
+stw_le_p(s-mmior[addr], val);
+}
+
+static void amd_iommu_writel(AMDIOMMUState *s, hwaddr addr, uint32_t
val)
+{
+stl_le_p(s-mmior[addr], val);
+}
+
+static void amd_iommu_writeq(AMDIOMMUState *s, hwaddr addr, uint64_t
val)
+{
+stq_le_p(s-mmior[addr], val);
+}
+
+/* execute a completion wait command */
+static void amd_iommu_completion_wait(AMDIOMMUState *s, uint8_t *cmd)
+{
+unsigned int addr;
+
+/* completion store */
+if(cmd[0] COM_COMPLETION_STORE_MASK){
+addr = le64_to_cpu(*(uint64_t*)cmd) COM_STORE_ADDRESS_MASK;
+if(dma_memory_write(address_space_memory, addr, cmd + 8, 8)){
+IOMMU_DPRINTF(ELOG, error: fail to write at address
0%xPRIx64, addr);
+}
+
+}
+
+/* set completion interrupt */
When I was experimenting with a real IOMMU, it all looked like if both
COM_COMPLETION_STORE_MASK and COM_COMPLETION_BIT are set in the command,
only an interrupt is generated. Could someone comment on this?
Which bit do you mean by COM_COMPLETION_BIT ?Do you mean
'COM_COMPLETION_INTR ? If yes, when would such a scenario occur ?
I was referring to COM_COMPLETION_INTR, sorry for the typo.
I have checked on from the spec, I can't find
Re: [Qemu-devel] [PATCH] target-sparc: Store mmu index in TB flags
Am 25.08.2015 um 08:44 schrieb Artyom Tarasenko: your patch gives the worst result in stream benchmark but nearly the best in pugixml compile times and prime.c runtime every tried patch or branch nearly halfs the speed of the stream benchmark comapred to qemu-git-master This is very surprising: the patch should have no effect on a sun4u machine. Have you applied it to the master or some other branch? Have you pulled the master branch recently? Maybe there was another change affecting the performance? i've completely removed my git qemu folder and freshly cloned the qemu-master, applied the patch and rechecked if applied - and these are my numbers i always remove my qemu-master (i always use master, other branch or clean master + patch) and build completely and im always using the same settings, remadisk etc. for compilation and benchmarking and its not realy surprising - there are ~5 people in the talk - each with different ideas where the slowness comes from and all use different or non formalized bechmark-suits (like your combination or my 3 tests) - each test i've made seems to give wired or suprising results - so my conclusion is: no one realy knows what it is and where it comes from - and as long as there is no equal benchmark-suite (for example NetBSD + the 3 tests) it will go on to be surprising or wired when i post results Example: at first it was - your RAM is full, your system is swapping, your harddisk is slow etc. talks with Artyom Tarasenko, Aurelien Jarno and some others - none of these are a problem - i've got more then enough RAM and CPU power in my host and free in the guest, and using a ramdisk for the image make IO less noisy Aurelien Jarno said it could be the 32bit userland in the my debian 7.8 SPARC64 system - and showed numbers with prime.c that proves it i've rechecked that and came to the same results and switched over to NetBSD SPARC64 (a pure 64bit system) that make prime.c the fastest but that does not realy reduce the pugixml compile times (my host needs 3sek, NetBSD takes ~3minutes, building cmake need ~10 hours or longer) then someone said it could be IO - so i put the NetBSD image on a ramdisk - helped a little then Karel Gardas got the idea that the compilation process is primary memory bound - so asked me to use the stream-benchmark - i've posting results on every change and i still don't know if the numbers im getting from the benchmark are relevant in any way (no one realy replies to them) - but they seems to be very relevant then i've tested the branch from tgc-indirect branch - prime.c get a little better, stream get slower the last patch from Richard Henderson gives still unclear results - prime.c get a little better, stream get the slowest the next thing i will do is a complete script based qemu-compilation and benchmark run in my NetBSD image - then the human-factor is down to 0% and the only source of suprising/wired results is my host-hardware is threre any interest in my NetBSD image (or the installation process)? (to have a change to get to similar results in the differences) should i add some other tests? what is usualy in use for performance tests? still no answer on that question im ready and happy to compile/run all your got/want :)
Re: [Qemu-devel] [kvm-s390] qemu-system-s390x: cannot use stdio by multiple character devices
Hi Christian:
Test case 068(qemu/tests/qemu-iotests/068, which is for loading a saved
VM state from a qcow2 image)
was broken because s390-virtio-ccw uses the new bootloader of
s390-ccw.img, instead of s390-zipl.rom.
1. qemu-img create -f qcow2 scratch/t.qcow2 64M
2. [root@r17lp42 qemu-iotests]# ../../s390x-softmmu/qemu-system-s390x
-nodefaults -nographic -monitor stdio -serial none -hda scratch/t.qcow2
QEMU 2.3.94 monitor - type 'help' for more information
(qemu) [root@r17lp42 qemu-iotests]#
3. I can get error message from s390-ccw.img as below,
Using guessed DASD geometry.
Using ECKD scheme (block size 4096),
CDL
! No zIPL section in IPL2 record. !
in qemu/pc-bios/s390-ccw/bootmap.c
213 static void ipl_eckd_cdl(void)
214 {
215 XEckdMbr *mbr;
216 Ipl2 *ipl2 = (void *)sec;
217 IplVolumeLabel *vlbl = (void *)sec;
218 block_number_t block_nr;
219
220 /* we have just read the block #0 and recognized it as IPL1 */
*221 sclp_print(CDL\n);*
222
223 memset(sec, FREE_SPACE_FILLER, sizeof(sec));
224 read_block(1, ipl2, Cannot read IPL2 record at block 1);
225
226 mbr = ipl2-u.x.mbr;
227 IPL_assert(magic_match(mbr, ZIPL_MAGIC), *No zIPL section in IPL2
record.*);
We may have two solutions,
1. providing a very small linux image(assuming name is t.qcow2) for s390x which can
be IPLed, via s390x-softmmu/qemu-system-s390x
-nodefaults -nographic -monitor stdio -serial none -hda scratch/t.qcow2
2. disable test case 068 for s390x
What's your opinion? thanks
On 08/20/2015 10:57 PM, Alexander Graf wrote:
On 20.08.15 01:20, tu bo wrote:
Hi Alex:
Ping you again just in case you did not get my mail :-)
On 08/13/2015 03:52 PM, tu bo wrote:
Hi Alex:
I added one disk device for test case 068(qemu/tests/qemu-iotests/068,
which is for for loading a saved VM state from a qcow2 image ),
and got the same problem for s390-virtio-ccw. Below is my steps:
1. qemu-img create -f qcow2 scratch/t.qcow2 64M
2. [root@r17lp42 qemu-iotests]# ../../s390x-softmmu/qemu-system-s390x
-nodefaults -nographic -monitor stdio -serial none -hda scratch/t.qcow2
QEMU 2.3.94 monitor - type 'help' for more information
(qemu) [root@r17lp42 qemu-iotests]#
For s390-virtio, test result is as expected
1. qemu-img create -f qcow2 scratch/t.qcow2 64M
2. [root@r17lp42 qemu-iotests]# qemu-system-s390x -nodefaults
-nographic -monitor stdio -serial none -hda scratch/t.qcow2
QEMU 2.3.50 monitor - type 'help' for more information
(qemu) info roms
addr=9000 size=0x000ce8 mem=ram
name=/usr/share/qemu/s390-zipl.rom
(qemu) savevm 0
(qemu)
(qemu) quit
3.[root@r17lp42 qemu-iotests]# qemu-system-s390x -nodefaults
-nographic -monitor stdio -serial none -hda scratch/t.qcow2 -loadvm 0
QEMU 2.3.50 monitor - type 'help' for more information
(qemu)
For x86-64, test result is as expected,
1. [gavin@oc646435 qemu-iotests]$ qemu-img create -f qcow2
scratch/t.qcow2 64M
2. [gavin@oc646435 qemu-iotests]$
../../x86_64-softmmu/qemu-system-x86_64 -nodefaults -nographic
-monitor stdio -serial none -hda scratch/t.qcow2
QEMU 2.3.94 monitor - type 'help' for more information
(qemu) info roms
fw=genroms/kvmvapic.bin size=0x002400 name=kvmvapic.bin
addr=fffc size=0x04 mem=rom name=bios-256k.bin
/rom@etc/acpi/tables size=0x20 name=etc/acpi/tables
/rom@etc/table-loader size=0x001000 name=etc/table-loader
/rom@etc/acpi/rsdp size=0x24 name=etc/acpi/rsdp
(qemu) savevm 0
(qemu)
3. [gavin@oc646435 qemu-iotests]$
../../x86_64-softmmu/qemu-system-x86_64 -nodefaults -nographic
-monitor stdio -serial none -hda scratch/t.qcow2 -loadvm 0
QEMU 2.3.94 monitor - type 'help' for more information
(qemu)
Could you share me why s390-virtio-ccw has different behavior with
s390-virtio x86_64 for this scenario? thanks
Because the s390 folks at IBM thought it'd be cool to emit a panic
(read: shut down) in the ccw bootloader when there is a problem? ;)
If this breaks test cases for you, please coordinate with Christian
Borntraeger and Eugene Dvurechenski whether it makes sense to change it.
Alex
Re: [Qemu-devel] QEMU produces invalid JSON due to locale-dependent code
On Tue 25 Aug 2015 09:54:42 AM CEST, Markus Armbruster wrote: Switching back to C locale whenever some unwanted locale-dependency breaks the code is problematic, because it involves finding all the places that break, iteratively (euphemism for we debug one breakage after the other, adding temporary locale switches as we go). I'd feel much better about confining GTK in its own thread, and setting only that thread's locale. FWIW GTK+ is not thread safe, all GTK+ code must run in the same thread, so that should already be happening. I assume however that it's the same thread that runs the monitor, so that might not be a solution in the end. Berto
Re: [Qemu-devel] [PATCH 10/10] machine: Set MachineClass::name automatically
On 08/21/2015 12:54 AM, Eduardo Habkost wrote:
Now all TYPE_MACHINE subclasses use MACHINE_TYPE_NAME to generate the
class name. So instead of requiring each subclass to set
MachineClass::name manually, we can now set it automatically at the
TYPE_MACHINE class_base_init() function.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
hw/arm/vexpress.c | 2 --
hw/arm/virt.c | 1 -
hw/core/machine.c | 3 +++
hw/ppc/mac_newworld.c | 1 -
hw/ppc/spapr.c | 4
hw/s390x/s390-virtio.c | 1 -
vl.c | 1 -
7 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index a86979d..55aed2b 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -758,7 +758,6 @@ static void vexpress_a9_class_init(ObjectClass *oc, void
*data)
MachineClass *mc = MACHINE_CLASS(oc);
VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
-mc-name = TYPE_VEXPRESS_A9_MACHINE;
mc-desc = ARM Versatile Express for Cortex-A9;
vmc-daughterboard = a9_daughterboard;;
@@ -769,7 +768,6 @@ static void vexpress_a15_class_init(ObjectClass *oc, void
*data)
MachineClass *mc = MACHINE_CLASS(oc);
VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
-mc-name = TYPE_VEXPRESS_A15_MACHINE;
mc-desc = ARM Versatile Express for Cortex-A15;
vmc-daughterboard = a15_daughterboard;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 5ba4b80..af985f6 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -960,7 +960,6 @@ static void virt_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
-mc-name = VIRT_MACHINE_NAME;
mc-desc = ARM Virtual Machine,
mc-init = machvirt_init;
mc-max_cpus = 8;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index e50c4b7..a889d7a 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -305,8 +305,11 @@ static void machine_class_init(ObjectClass *oc, void *data)
static void machine_class_base_init(ObjectClass *oc, void *data)
{
if (!object_class_is_abstract(oc)) {
+MachineClass *mc = MACHINE_CLASS(oc);
const char *cname = object_class_get_name(oc);
assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
+mc-name = g_strndup(cname,
+strlen(cname) - strlen(TYPE_MACHINE_SUFFIX));
}
}
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index a6b8209..70e7431 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -508,7 +508,6 @@ static void core99_machine_class_init(ObjectClass *oc, void
*data)
{
MachineClass *mc = MACHINE_CLASS(oc);
-mc-name = mac99;
mc-desc = Mac99 based PowerMAC;
mc-init = ppc_core99_init;
mc-max_cpus = MAX_CPUS;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 012b6ed..05926a3 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1919,7 +1919,6 @@ static void spapr_machine_2_1_class_init(ObjectClass *oc,
void *data)
{ /* end of list */ }
};
-mc-name = pseries-2.1;
mc-desc = pSeries Logical Partition (PAPR compliant) v2.1;
mc-compat_props = compat_props;
}
@@ -1939,7 +1938,6 @@ static void spapr_machine_2_2_class_init(ObjectClass *oc,
void *data)
};
MachineClass *mc = MACHINE_CLASS(oc);
-mc-name = pseries-2.2;
mc-desc = pSeries Logical Partition (PAPR compliant) v2.2;
mc-compat_props = compat_props;
}
@@ -1959,7 +1957,6 @@ static void spapr_machine_2_3_class_init(ObjectClass *oc,
void *data)
};
MachineClass *mc = MACHINE_CLASS(oc);
-mc-name = pseries-2.3;
mc-desc = pSeries Logical Partition (PAPR compliant) v2.3;
mc-compat_props = compat_props;
}
@@ -1975,7 +1972,6 @@ static void spapr_machine_2_4_class_init(ObjectClass *oc,
void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
-mc-name = pseries-2.4;
mc-desc = pSeries Logical Partition (PAPR compliant) v2.4;
mc-alias = pseries;
mc-is_default = 1;
diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c
index 43d6ccb..35c0ce2 100644
--- a/hw/s390x/s390-virtio.c
+++ b/hw/s390x/s390-virtio.c
@@ -334,7 +334,6 @@ static void s390_machine_class_init(ObjectClass *oc, void
*data)
MachineClass *mc = MACHINE_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
-mc-name = S390_MACHINE;
mc-alias = s390;
mc-desc = VirtIO based S390 machine;
mc-init = s390_init;
diff --git a/vl.c b/vl.c
index b7ddfeb..870ee48 100644
--- a/vl.c
+++ b/vl.c
@@ -1432,7 +1432,6 @@ static void qemu_machine_class_init(ObjectClass *oc, void
*data)
{
MachineClass *mc = MACHINE_CLASS(oc);
QEMUMachine *qm = data;
-mc-name = qm-name;
mc-desc = qm-desc;
mc-init = qm-init;
mc-kvm_type = qm-kvm_type;
Nice!
Please forget the possible stupid question, but what happens with
*all* other machine types? Why don't we have to remove the name
assignment from the other machine
Re: [Qemu-devel] [PATCH 01/10] machine: MACHINE_TYPE_NAME macro
On 08/21/2015 12:54 AM, Eduardo Habkost wrote:
The macro will be useful to ensure the machine class names follow the
right format to make machine class lookup by class name work correctly.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
include/hw/boards.h | 6 ++
vl.c| 2 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 3f84afd..178517c 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -40,6 +40,12 @@ void memory_region_allocate_system_memory(MemoryRegion *mr,
Object *owner,
int qemu_register_machine(QEMUMachine *m);
#define TYPE_MACHINE_SUFFIX -machine
+
+/* Machine class name that needs to be used for class-name-based machine
+ * type lookup to work.
+ */
+#define MACHINE_TYPE_NAME(machinename) (machinename TYPE_MACHINE_SUFFIX)
+
#define TYPE_MACHINE machine
#undef MACHINE /* BSD defines it and QEMU does not use it */
#define MACHINE(obj) \
diff --git a/vl.c b/vl.c
index 584ca88..b7ddfeb 100644
--- a/vl.c
+++ b/vl.c
@@ -1447,7 +1447,7 @@ static void qemu_machine_class_init(ObjectClass *oc, void
*data)
int qemu_register_machine(QEMUMachine *m)
{
-char *name = g_strconcat(m-name, TYPE_MACHINE_SUFFIX, NULL);
+char *name = g_strdup_printf(MACHINE_TYPE_NAME(%s), m-name);
TypeInfo ti = {
.name = name,
.parent = TYPE_MACHINE,
Reviewed-by: Marcel Apfelbaum mar...@redhat.com
Thanks,
Marcel
Re: [Qemu-devel] [PATCH 09/10] machine: Ensure all TYPE_MACHINE subclasses have the right suffix
On 08/21/2015 12:54 AM, Eduardo Habkost wrote:
Now that all non-abstract TYPE_MACHINE subclasses have the -machine
suffix, add an assert to ensure this will be always true.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
hw/core/machine.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index ac4654e..e50c4b7 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -302,6 +302,14 @@ static void machine_class_init(ObjectClass *oc, void *data)
mc-default_ram_size = 128 * M_BYTE;
}
+static void machine_class_base_init(ObjectClass *oc, void *data)
+{
+if (!object_class_is_abstract(oc)) {
+const char *cname = object_class_get_name(oc);
+assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
+}
+}
+
static void machine_initfn(Object *obj)
{
MachineState *ms = MACHINE(obj);
@@ -472,6 +480,7 @@ static const TypeInfo machine_info = {
.abstract = true,
.class_size = sizeof(MachineClass),
.class_init= machine_class_init,
+.class_base_init = machine_class_base_init,
.instance_size = sizeof(MachineState),
.instance_init = machine_initfn,
.instance_finalize = machine_finalize,
Reviewed-by: Marcel Apfelbaum mar...@redhat.com
Thanks,
Marcel
