[Qemu-devel] [Bug 1588328] Re: Qemu 2.6 Solaris 9 Sparc Segmentation Fault

Hi Mark, I compared the cksum provided and the dvd cksum that i did, seems to match. I did try out Solaris 8 too. It seems to work fine with sun formatted hda disk. I did try removing the -hda for solaris 9, the problem still persist. I shall find if i can get another solaris 9 image source to

Re: [Qemu-devel] [PATCH v6 08/22] raw-posix: Add image locking support

On Fri, 06/03 16:49, Fam Zheng wrote: > +static > +int raw_reopen_downgrade(BDRVReopenState *state, > + RawReopenOperation op, > + BdrvLockfCmd old_lock, > + BdrvLockfCmd new_lock, > + Error **errp) >

Re: [Qemu-devel] [PATCH] iotests: 095: Clean up QEMU before showing image info

On Fri, 06/03 16:52, Max Reitz wrote: > On 03.06.2016 11:07, Fam Zheng wrote: > > Somehow in my locking series, I missed this case where concurrent access > > to an image is performed, perhaps we can remove this case independently. > > The patch itself is good, but this commit message will not

[Qemu-devel] [PATCH 7/5] block: Refactor zero_beyond_eof hack in bdrv_aligned_preadv()

Reindent code so that later removal of zero_beyond_eof doesn't interfere as much with upcoming changes to the normal path. Patch viewed best with 'git diff -b'. Signed-off-by: Eric Blake --- block/io.c | 74 +++--- 1

[Qemu-devel] [PATCH 6/5] block: Fix harmless off-by-one in bdrv_aligned_preadv()

If the amount of data to read ends exactly on the total size of the bs, then we were wasting time creating a local qiov to read the data in preparation for what would normally be appending zeroes beyond the end, even though this corner case has nothing further to do. Signed-off-by: Eric Blake

[Qemu-devel] [PATCH] target-*: dfilter support for in_asm

The arm target was handled by 06486077, but other targets were ignored. This handles all the rest which actually support disassembly (that is, skipping moxie and tilegx). Signed-off-by: Richard Henderson --- target-alpha/translate.c | 3 ++- target-cris/translate.c

Re: [Qemu-devel] [PATCH 5/5] qcow2: Implement .bdrv_co_pwritev

On 06/03/2016 11:21 AM, Kevin Wolf wrote: > This changes qcow2 to implement the byte-based .bdrv_co_pwritev > interface rather than the sector-based old one. > Subject line consistency: 2/5 has trailing (), this one does not. I prefer 2/5. > As preallocation uses the same allocation function as

Re: [Qemu-devel] [PATCH v2 0/8] virtio-blk: multiqueue support

On Thu, Jun 02, 2016 at 05:19:41PM -0700, Stefan Hajnoczi wrote: > On Mon, May 30, 2016 at 06:25:58PM -0700, Stefan Hajnoczi wrote: > > v2: > > * Simplify s->rq live migration [Paolo] > > * Use more efficient bitmap ops for batch notification [Paolo] > > * Fix perf regression due to batch

Re: [Qemu-devel] [PATCH 5/5] block: Move request_alignment into BlockLimit

On 06/03/2016 11:49 AM, Eric Blake wrote: > On 06/03/2016 11:03 AM, Eric Blake wrote: >> It makes more sense to have ALL block size limit constraints >> in the same struct. Improve the documentation while at it. >> >> Note that bdrv_refresh_limits() has to keep things alive across >> a memset()

Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier

On 03/06/16 23:43, Peter Maydell wrote: > On 3 June 2016 at 20:49, Sergey Fedorov wrote: >> I'm not so sure about acq/rel flags. Is there any architecture which has >> explicit acq/rel barriers? I suppose acq/rel memory access instructions >> are always load-link and

[Qemu-devel] [RFC v3 19/19] cpu-exec: remove tb_lock from the hot-path

Lock contention in the hot path of moving between existing patched TranslationBlocks is the main drag on MTTCG performance. This patch pushes the tb_lock() usage down to the two places that really need it: - code generation (tb_gen_code) - jump patching (tb_add_jump) The rest of the code

[Qemu-devel] [RFC v3 16/19] tcg: move locking for tb_invalidate_phys_page_range up

While we previously assumed an existing memory lock protected the page look up in the MTTCG SoftMMU case the memory lock is provided by the tb_lock. As a result we push the taking of this lock up the call tree. This requires a slightly different entry for the SoftMMU and user-mode cases from

Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier

On 3 June 2016 at 20:49, Sergey Fedorov wrote: > I'm not so sure about acq/rel flags. Is there any architecture which has > explicit acq/rel barriers? I suppose acq/rel memory access instructions > are always load-link and store-conditional and thus rely on exclusive >

[Qemu-devel] [RFC v3 14/19] tcg: remove global exit_request

The only remaining use of the global exit_request flag is now to ensure we exit the run_loop when we first start to process pending work. This is just as easily done by setting the first_cpu->exit_request flag. We lightly re-factor the main vCPU thread to ensure cpu->exit_requests cause us to

[Qemu-devel] [RFC v3 15/19] tcg: drop global lock during TCG code execution

This finally allows TCG to benefit from the iothread introduction: Drop the global mutex while running pure TCG CPU code. Reacquire the lock when entering MMIO or PIO emulation, or when leaving the TCG loop. We have to revert a few optimization for the current TCG threading model, namely kicking

[Qemu-devel] [RFC v3 18/19] tcg: Ensure safe TB lookup out of 'tb_lock'

From: Sergey Fedorov First, ensure atomicity of CPU's 'tb_jmp_cache' access by: * using atomic_read() to look up a TB when not holding 'tb_lock'; * using atomic_write() to remove a TB from each CPU's local cache on TB invalidation. Second, add some memory barriers to

[Qemu-devel] [RFC v3 11/19] tcg: add options for enabling MTTCG

From: KONRAD Frederic We know there will be cases where MTTCG won't work until additional work is done in the front/back ends to support. It will however be useful to be able to turn it on. As a result MTTCG will default to off unless the combination is supported.

[Qemu-devel] [RFC v3 08/19] tcg: protect TBContext with tb_lock.

From: KONRAD Frederic This protects TBContext with tb_lock to make tb_* thread safe. We can still have issue with tb_flush in case of multithread TCG: another CPU can be executing code during a flush. This can be fixed later by making all other TCG thread exiting

[Qemu-devel] [RFC v3 10/19] tcg: cpus rm tcg_exec_all()

In preparation for multi-threaded TCG we remove tcg_exec_all and move all the CPU cycling into the main thread function. When MTTCG is enabled we shall use a separate thread function which only handles one vCPU. Signed-off-by: Alex Bennée --- v2 - update timer calls to

[Qemu-devel] [RFC v3 17/19] tcg: enable thread-per-vCPU

There are a number of changes that occur at the same time here: - tb_lock is no longer a NOP for SoftMMU The tb_lock protects both translation and memory map structures. The debug assert is updated to reflect this. - introduce a single vCPU qemu_tcg_cpu_thread_fn One of these is

[Qemu-devel] [RFC v3 09/19] target-arm/arm-powerctl: wake up sleeping CPUs

Testing with Alexander's bare metal syncronisation tests fails in MTTCG leaving one CPU spinning forever waiting for the second CPU to wake up. We simply need to kick the vCPU once we have processed the PSCI power on call. As the power control API is for system emulation only as is the

[Qemu-devel] [RFC v3 04/19] docs: new design document multi-thread-tcg.txt (DRAFTING)

This is a current DRAFT of a design proposal for upgrading TCG emulation to take advantage of modern CPUs by running a thread-per-CPU. The document goes through the various areas of the code affected by such a change and proposes design requirements for each part of the solution. It has been

[Qemu-devel] [RFC v3 13/19] tcg: rename tcg_current_cpu to tcg_current_rr_cpu

..and make the definition local to cpus. In preparation for MTTCG the concept of a global tcg_current_cpu will no longer make sense. However we still need to keep track of it in the single-threaded case to be able to exit quickly when required. qemu_cpu_kick_no_halt() moves and becomes

[Qemu-devel] [RFC v3 06/19] tcg: comment on which functions have to be called with tb_lock held

From: Paolo Bonzini softmmu requires more functions to be thread-safe, because translation blocks can be invalidated from e.g. notdirty callbacks. Probably the same holds for user-mode emulation, it's just that no one has ever tried to produce a coherent locking there.

[Qemu-devel] [RFC v3 03/19] translate-all: add DEBUG_LOCKING asserts

This adds asserts to check the locking on the various translation engines structures. There are two sets of structures that are protected by locks. The first the l1map and PageDesc structures used to track which translation blocks are associated with which physical addresses. In user-mode this is

[Qemu-devel] [RFC v3 12/19] tcg: add kick timer for single-threaded vCPU emulation

Currently we rely on the side effect of the main loop grabbing the iothread_mutex to give any long running basic block chains a kick to ensure the next vCPU is scheduled. As this code is being re-factored and rationalised we now do it explicitly here. Signed-off-by: Alex Bennée

[Qemu-devel] [RFC v3 05/19] exec: add assert_debug_safe and notes on debug structures

The debug structures are different from many of the other shared ones as they are modified from two places: - architectural debug registers - the gdb stub The first is usually in the context of vCPU currently running so modifications are safe. The second is generally only changed while the

[Qemu-devel] [RFC v3 00/19] Base enabling patches for MTTCG

This is the third iteration of the RFC patch set which aims to provide the basic framework for MTTCG. There have been some considerable changes since the last extensive review (thanks to all the reviewers). - many updates to docs/multi-thread-tcg.txt design document - added assertions for

[Qemu-devel] [RFC v3 01/19] cpus: make all_vcpus_paused() return bool

Signed-off-by: Alex Bennée Reviewed-by: Sergey Fedorov --- v3 - add r-b tags --- cpus.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cpus.c b/cpus.c index 665f9bb..c404dd7 100644 --- a/cpus.c +++ b/cpus.c @@

[Qemu-devel] [RFC v3 02/19] translate_all: DEBUG_FLUSH -> DEBUG_TB_FLUSH

Make the debug define consistent with the others. The flush operation is all about invalidating TranslationBlocks on flush events. Also fix up the commenting on the other DEBUG for the benefit of checkpatch. Signed-off-by: Alex Bennée --- translate-all.c | 8 1

[Qemu-devel] [RFC v3 07/19] translate-all: Add assert_memory_lock annotations

This adds calls to the assert_memory_lock for all public APIs which are documented as holding the mmap_lock for user-mode. Signed-off-by: Alex Bennée --- linux-user/elfload.c | 4 translate-all.c | 20 2 files changed, 24 insertions(+)

Re: [Qemu-devel] [PATCH v2] blockdev: clean up error handling in do_open_tray

On 06/03/2016 01:39 PM, Colin Lord wrote: > Returns negative error codes and accompanying error messages in cases where > the device has no tray or the tray is locked and isn't forced open. This > extra information should result in better flexibility in functions that > call do_open_tray. > >

Re: [Qemu-devel] [PATCH 5/5] qcow2: Implement .bdrv_co_pwritev

On 06/03/2016 11:21 AM, Kevin Wolf wrote: > This changes qcow2 to implement the byte-based .bdrv_co_pwritev > interface rather than the sector-based old one. > > As preallocation uses the same allocation function as normal writes, and > the interface of that function needs to be changed, it is

Re: [Qemu-devel] [PATCH v2] blockdev: clean up error handling in do_open_tray

Am 03.06.2016 um 21:39 hat Colin Lord geschrieben: > Returns negative error codes and accompanying error messages in cases where > the device has no tray or the tray is locked and isn't forced open. This > extra information should result in better flexibility in functions that > call do_open_tray.

Re: [Qemu-devel] [PATCH RFC 0/8] cpus: make "-cpu cpux, features" global properties

On Fri, Jun 03, 2016 at 08:36:21AM +0200, David Hildenbrand wrote: > > On Thu, Jun 02, 2016 at 10:44:49PM +0200, David Hildenbrand wrote: > > > > Current CLI option -cpu cpux,features serves as template > > > > for all created cpus of type: cpux. However QEMU parses > > > > "features" every time

Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier

On 03/06/16 21:27, Pranith Kumar wrote: > On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson wrote: >> > >> > Hum. That does seem helpful-ish. But I'm not certain how helpful it is to >> > complicate the helper functions even further. >> > >> > What if we have

Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier

On 03/06/16 21:30, Pranith Kumar wrote: > On Thu, Jun 2, 2016 at 9:08 PM, Richard Henderson wrote: >> On 06/02/2016 02:37 PM, Sergey Fedorov wrote: >>> >>> It would give us three TCG operations for each memory operation instead >>> of one. But then we might like to combine these

Re: [Qemu-devel] [PATCH 4/5] qcow2: Use bytes instead of sectors for QCowL2Meta

On 06/03/2016 11:21 AM, Kevin Wolf wrote: > In preparation for implementing .bdrv_co_pwritev in qcow2. > > Signed-off-by: Kevin Wolf > --- > block/qcow2-cluster.c | 32 > block/qcow2.h | 13 +++-- > 2 files changed, 15

[Qemu-devel] [PATCH v2] blockdev: clean up error handling in do_open_tray

Returns negative error codes and accompanying error messages in cases where the device has no tray or the tray is locked and isn't forced open. This extra information should result in better flexibility in functions that call do_open_tray. Signed-off-by: Colin Lord --- v2: fix

Re: [Qemu-devel] [PATCH RFC 4/8] target-i386: cpu: consolidate calls of object_property_parse() in x86_cpu_parse_featurestr

On Fri, Jun 03, 2016 at 11:37:49AM +0200, Igor Mammedov wrote: > On Fri, 3 Jun 2016 09:30:09 +0200 > Peter Krempa wrote: > > > On Thu, Jun 02, 2016 at 18:31:04 +0200, Igor Mammedov wrote: > > > On Thu, 2 Jun 2016 17:05:06 +0200 > > > Peter Krempa wrote:

Re: [Qemu-devel] [PATCH 3/5] qcow2: Make copy_sectors() byte based

On 06/03/2016 11:21 AM, Kevin Wolf wrote: > This will allow copy on write operations where the overwritten part of > the cluster is not aligned to sector boundaries. > > Signed-off-by: Kevin Wolf > --- > block/qcow2-cluster.c | 37 + > 1

Re: [Qemu-devel] [PATCH RFC 1/8] target-i386: cpu: move features logic that requires CPUState to realize time

On Fri, Jun 03, 2016 at 12:13:18PM +0200, Igor Mammedov wrote: > On Thu, 2 Jun 2016 14:34:27 -0300 > Eduardo Habkost wrote: > > > On Thu, Jun 02, 2016 at 06:56:55PM +0200, Igor Mammedov wrote: > > > On Thu, 2 Jun 2016 11:38:26 -0300 > > > Eduardo Habkost

Re: [Qemu-devel] [RFC v1 05/12] atomic: introduce cmpxchg_bool

On 06/03/2016 01:12 PM, Alex Bennée wrote: >>> +#define atomic_bool_cmpxchg(ptr, old, new) \ >>> +({ \ >>> +typeof(*ptr) _old = (old), _new = (new);\ >>> +bool r;

Re: [Qemu-devel] [PATCH 2/5] qcow2: Implement .bdrv_co_preadv()

On 06/03/2016 11:21 AM, Kevin Wolf wrote: > Reading from qcow2 images is now byte granularity. > > Most of the affected code in qcow2 actually gets simpler with this > change. The only exception is encryption, which is fixed on 512 bytes > blocks; in order to keep this working,

Re: [Qemu-devel] [PATCH] blockdev: fix error handling in do_open_tray

Am 03.06.2016 um 20:20 hat cl...@redhat.com geschrieben: > From: Colin Lord > > Returns negative error codes and accompanying error messages in cases where > the device has no tray or the tray is locked and isn't forced open. This > extra information should result in better

Re: [Qemu-devel] [RFC v1 05/12] atomic: introduce cmpxchg_bool

Sergey Fedorov writes: > On 15/04/16 17:23, Alex Bennée wrote: >> diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h >> index 5dba7db..94e7110 100644 >> --- a/include/qemu/atomic.h >> +++ b/include/qemu/atomic.h >> @@ -123,6 +123,16 @@ >> _old;

Re: [Qemu-devel] [PATCH] blockdev: fix error handling in do_open_tray

On 06/03/2016 12:20 PM, cl...@redhat.com wrote: > From: Colin Lord You may want to update your ~/.gitconfig to set sendemail.from to list your name in the same manner in which you add S-o-b. (Not strictly a problem, as 'git am' does the right thing either way, but it will

[Qemu-devel] [PATCH v8 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

From: Aleksandar Markovic New set of helpers for handling nan2008-syle versions of instructions .., for Mips R6. All involved instructions have float operand and integer result. Their core functionality is implemented via

[Qemu-devel] [PATCH v8 3/9] softfloat: For Mips only, correct default NaN values

From: Aleksandar Markovic Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct default NaN values (in their 16-, 32-, and 64-bit flavors). For more info, see [1], page 84, Table 6.3 "Value Supplied When a New Quiet NaN Is Created", and

[Qemu-devel] [PATCH v8 6/9] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA

From: Aleksandar Markovic Function msa_reset() is updated so that flag snan_bit_is_one is properly set to 0. By applying this patch, a number of incorrect MSA behaviors that require IEEE 754-2008 compliance will be fixed. Those are behaviors that (up to the

[Qemu-devel] [PATCH v8 7/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>

From: Aleksandar Markovic Updated handling of instructions .. Note that legacy (pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore, any NaN operand causes signaling invalid operation), while abs2008 ones are non-arithmetic, always

[Qemu-devel] [PATCH v8 9/9] target-mips: Implement FCR31's R/W bitmask and related functionalities

From: Aleksandar Markovic This patch implements read and write access rules for Mips floating point control and status register (FCR31). The change can be divided into following parts: - Add fields that will keep FCR31's R/W bitmask in procesor definitions and

[Qemu-devel] [PATCH v8 2/9] softfloat: Clean code format in fpu/softfloat-specialize.h

From: Aleksandar Markovic fpu/softfloat-specialize.h is the most critical file in SoftFloat library, since it handles numerous differences between platforms in relation to floating point arithmetics. This patch makes the code in this file more consistent

[Qemu-devel] [PATCH v8 5/9] linux-user: Update preprocessor constants for Mips-specific e_flags bits

From: Aleksandar Markovic Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added, and the format of the surrounding code segment adjusted. Signed-off-by: Thomas Schwinge Signed-off-by: Maciej W. Rozycki

[Qemu-devel] [PATCH v8 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

From: Aleksandar Markovic This patch modifies SoftFloat library so that it can be configured in run-time in relation to the meaning of signaling NaN bit, while, at the same time, strictly preserving its behavior on all existing platforms. Background: In

[Qemu-devel] [PATCH v8 4/9] softfloat: For Mips only, correct order in pickNaNMulAdd()

From: Aleksandar Markovic Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct the order of argument comparisons in pickNaNMulAdd(). For more info, see [1], page 53, section "3.5.3 NaN Propagation". [1] "MIPS Architecture for Programmers

[Qemu-devel] [PATCH v8 0/9] IEEE 754-2008 support for Mips

From: Aleksandar Markovic v8 - fixed mail recipients v7 - preprocesor constants for FCR31 bits removed - cleanup items in CFC1 and CTC1 handling removed - initialization of snan_bit_is_one for main FP unit moved from patch 6 to patch 9 - an instance

Re: [Qemu-devel] [PATCH v2 0/4] xlnx-zynqmp: Fix various issues with KVM runs

On 25 May 2016 at 11:52, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > This series fixes a bunch of issues with KVM runs using the ZynqMP > machine. > > When using KVM, we don't have support for TrustZone, the RPU subsystem > with

Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier

On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson wrote: > > Hum. That does seem helpful-ish. But I'm not certain how helpful it is to > complicate the helper functions even further. > > What if we have tcg_canonicalize_memop (or some such) split off the barriers > into

Re: [Qemu-devel] [PATCH] hw/arm/virt: Reject gic-version=host for non-KVM

On 26 May 2016 at 15:31, Cole Robinson wrote: > If you try to gic-version=host with TCG on a KVM aarch64 host, > qemu segfaults, since host requires KVM APIs. > > Explicitly reject gic-version=host if KVM is not enabled > > https://bugzilla.redhat.com/show_bug.cgi?id=1339977

Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier

On Thu, Jun 2, 2016 at 9:08 PM, Richard Henderson wrote: > On 06/02/2016 02:37 PM, Sergey Fedorov wrote: >> >> >> It would give us three TCG operations for each memory operation instead >> of one. But then we might like to combine these barrier operations back >> with memory

Re: [Qemu-devel] [PATCH v2] i2c: add aspeed i2c controller

On 31 May 2016 at 15:18, Cédric Le Goater wrote: > The Aspeed AST2400 integrates a set of 14 I2C/SMBus bus controllers > directly connected to the APB bus. They can be programmed as master or > slave but the propopsed model only supports the master mode. > > On the TODO list, we

Re: [Qemu-devel] [PULL 04/16] Makefile: Rules for docker testing

On Fri, Jun 03, 2016 at 09:23:28AM +0800, Fam Zheng wrote: > On Thu, 06/02 16:13, Eduardo Habkost wrote: > > On Wed, Jun 01, 2016 at 05:45:12PM +0800, Fam Zheng wrote: > > [...] > > > + > > > +CUR_TIME := $(shell date +%Y-%m-%d-%H.%M.%S.) > > > +# Makes the definition constant after the first

Re: [Qemu-devel] [PATCH 0/6] Drop the qemu_char_get_next_serial function

On 25 May 2016 at 11:58, xiaoqiang zhao wrote: > This patch series's main idea is to drop the use of > qemu_char_get_next_serial. patches 1-5 QOM'ify the related > device model and the affected board code. Most of them > are arm related. The patch 6 get rid of the function

[Qemu-devel] [PATCH] blockdev: fix error handling in do_open_tray

From: Colin Lord Returns negative error codes and accompanying error messages in cases where the device has no tray or the tray is locked and isn't forced open. This extra information should result in better flexibility in functions that call do_open_tray. Signed-off-by: Colin

[Qemu-devel] [PATCH v7 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit

From: Aleksandar Markovic This patch modifies SoftFloat library so that it can be configured in run-time in relation to the meaning of signaling NaN bit, while, at the same time, strictly preserving its behavior on all existing platforms. Background: In

[Qemu-devel] [PATCH v7 0/9] IEEE 754-2008 support for Mips

From: Aleksandar Markovic v7 - preprocesor constants for FCR31 bits removed - cleanup items in CFC1 and CTC1 handling removed - initialization of snan_bit_is_one for main FP unit moved from patch 6 to patch 9 - an instance of "!" corrected to "~"

Re: [Qemu-devel] [PATCH 16/16] hbitmap: Use DIV_ROUND_UP

On 05/31/2016 12:36 PM, Laurent Vivier wrote: > Replace (((n) + (d) - 1) /(d)) by DIV_ROUND_UP(n,d). > > This patch is the result of coccinelle script > scripts/coccinelle/round.cocci > > CC: Paolo Bonzini > Signed-off-by: Laurent Vivier > --- >

[Qemu-devel] [Bug 1568356] Re: ERROR:ui/sdl2-2d.c:120:sdl2_2d_switch:

Hi T, i can confirm the patch is working . sdl2 switch screen is fixed . i had been tested it on 2.5.1 and is ok. I think will be better add this in the qemu git next step sdl gl ;-) Many thanks Luigi -- You received this bug notification because you are a member of qemu- devel-ml, which is

Re: [Qemu-devel] [PATCH] hw/intc/gic: RAZ/WI non-sec access to sec interrupts

On 26 May 2016 at 15:45, Jens Wiklander wrote: > Treat non-secure accesses to registers and bits in registers of secure > interrupts as RAZ/WI. > > Signed-off-by: Jens Wiklander > --- > hw/intc/arm_gic.c | 68 >

Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode

On 06/03/2016 05:47 PM, Mark Cave-Ayland wrote: > On 03/06/16 15:14, Mark Cave-Ayland wrote: > >> On 03/06/16 15:06, Cedric Le Goater wrote: >> >>> On 06/03/2016 04:00 PM, Cédric Le Goater wrote: Hello Mark, On 06/03/2016 03:52 PM, Mark Cave-Ayland wrote: > On 03/06/16 13:11,

Re: [Qemu-devel] [PATCH 5/5] block: Move request_alignment into BlockLimit

On 06/03/2016 11:03 AM, Eric Blake wrote: > It makes more sense to have ALL block size limit constraints > in the same struct. Improve the documentation while at it. > > Note that bdrv_refresh_limits() has to keep things alive across > a memset() of BlockLimits. > > Signed-off-by: Eric Blake

Re: [Qemu-devel] [PATCH v6 08/15] qdist: add module to represent frequency distributions of data

On 03/06/16 20:29, Sergey Fedorov wrote: > On 03/06/16 20:22, Emilio G. Cota wrote: >> On Sat, May 28, 2016 at 21:15:06 +0300, Sergey Fedorov wrote: >>> On 25/05/16 04:13, Emilio G. Cota wrote: >>> (snip) +double qdist_avg(const struct qdist *dist) +{ +unsigned long count;

Re: [Qemu-devel] [PATCH 1/5] qcow2: Work with bytes in qcow2_get_cluster_offset()

On 06/03/2016 11:21 AM, Kevin Wolf wrote: > This patch changes the units that qcow2_get_cluster_offset() uses > internally, without touching the interface just yet. This will be done > in another patch. > > Signed-off-by: Kevin Wolf > --- > block/qcow2-cluster.c | 43

Re: [Qemu-devel] [PULL 04/16] Makefile: Rules for docker testing

On Fri, Jun 03, 2016 at 09:23:28AM +0800, Fam Zheng wrote: > On Thu, 06/02 16:13, Eduardo Habkost wrote: > > On Wed, Jun 01, 2016 at 05:45:12PM +0800, Fam Zheng wrote: > > [...] > > > + > > > +CUR_TIME := $(shell date +%Y-%m-%d-%H.%M.%S.) > > > +# Makes the definition constant after the first

[Qemu-devel] [PATCH 2/5] qcow2: Implement .bdrv_co_preadv()

Reading from qcow2 images is now byte granularity. Most of the affected code in qcow2 actually gets simpler with this change. The only exception is encryption, which is fixed on 512 bytes blocks; in order to keep this working, bs->request_alignment is set for encrypted images. Signed-off-by:

Re: [Qemu-devel] [PATCH v6 08/15] qdist: add module to represent frequency distributions of data

On 03/06/16 20:22, Emilio G. Cota wrote: > On Sat, May 28, 2016 at 21:15:06 +0300, Sergey Fedorov wrote: >> On 25/05/16 04:13, Emilio G. Cota wrote: >> (snip) >>> +double qdist_avg(const struct qdist *dist) >>> +{ >>> +unsigned long count; >>> +size_t i; >>> +double ret = 0; >>> + >>>

[Qemu-devel] [PATCH 3/5] qcow2: Make copy_sectors() byte based

This will allow copy on write operations where the overwritten part of the cluster is not aligned to sector boundaries. Signed-off-by: Kevin Wolf --- block/qcow2-cluster.c | 37 + 1 file changed, 17 insertions(+), 20 deletions(-) diff --git

Re: [Qemu-devel] [QEMU PATCH v2] target-i386: Add Skylake-Client CPU model

On Fri, Jun 03, 2016 at 11:50:14AM +0800, Xiao Guangrong wrote: > > > On 05/23/2016 09:46 PM, Paolo Bonzini wrote: > > > > > > On 20/05/2016 23:39, Eduardo Habkost wrote: > > > Introduce Skylake-Client CPU model, which inherits the features > > > from Broadwell and supports some additional

[Qemu-devel] [PATCH 5/5] qcow2: Implement .bdrv_co_pwritev

This changes qcow2 to implement the byte-based .bdrv_co_pwritev interface rather than the sector-based old one. As preallocation uses the same allocation function as normal writes, and the interface of that function needs to be changed, it is converted in the same patch. Signed-off-by: Kevin

[Qemu-devel] [PATCH 1/5] qcow2: Work with bytes in qcow2_get_cluster_offset()

This patch changes the units that qcow2_get_cluster_offset() uses internally, without touching the interface just yet. This will be done in another patch. Signed-off-by: Kevin Wolf --- block/qcow2-cluster.c | 43 ++- 1 file changed, 22

Re: [Qemu-devel] [PATCH v6 08/15] qdist: add module to represent frequency distributions of data

On Sat, May 28, 2016 at 21:15:06 +0300, Sergey Fedorov wrote: > On 25/05/16 04:13, Emilio G. Cota wrote: > (snip) > > +double qdist_avg(const struct qdist *dist) > > +{ > > +unsigned long count; > > +size_t i; > > +double ret = 0; > > + > > +count = qdist_sample_count(dist); > > +

[Qemu-devel] [PATCH 0/5] qcow2: Implement .bdrv_co_preadv/pwritev

This series converts qcow2 to the byte-based I/O interfaces. This simplifies the code by removing many unit conversions, and in the unlikely case of actual unaligned requests, it even makes the driver work more efficiently by avoiding read-modify-write. Kevin Wolf (5): qcow2: Work with bytes in

[Qemu-devel] [PATCH 4/5] qcow2: Use bytes instead of sectors for QCowL2Meta

In preparation for implementing .bdrv_co_pwritev in qcow2. Signed-off-by: Kevin Wolf --- block/qcow2-cluster.c | 32 block/qcow2.h | 13 +++-- 2 files changed, 15 insertions(+), 30 deletions(-) diff --git

[Qemu-devel] [PATCH] target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation

Address size is 40-bit for the AArch32 stage 2 translation, and t0sz can be negative (from -8 to 7), so we need to adjust it to use the existing TTBR selecting logic. Signed-off-by: Sergey Sorokin --- target-arm/helper.c | 38 ++ 1 file

Re: [Qemu-devel] [QEMU RFC PATCH v3 4/6] Migration: migrate QTAILQ

On 06/02/2016 08:01 AM, Sascha Silbe wrote: > Dear Jianjun, > > Jianjun Duan writes: > > [include/migration/vmstate.h] >> @@ -185,6 +185,8 @@ enum VMStateFlags { >> * to determine the number of entries in the array. Only valid in >> * combination with one

Re: [Qemu-devel] Bug in ppc/BookE wait instruction

On 03/06/16 16:45, Jakub Horak wrote: (Added David as PPC maintainer and qemu-ppc mailing list) > Hello, > I think there's a bug in "wait" instruction code generator for PowerPC > architecture. It doesn't make sense to store a non-initialized register. > > Best regards, > Jakub Horak > > >

[Qemu-devel] [PATCH 2/5] block: Honor flags during bdrv_aligned_preadv()

Not that we pass any flags during reads yet, but we may want to support BDRV_REQ_FUA on reads in the future. So don't throw away the input flags. Signed-off-by: Eric Blake --- block/io.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/block/io.c

[Qemu-devel] [PATCH 1/5] block: Tighter assertions on bdrv_aligned_preadv()

Make sure everything is aligned to the passed-in alignment, not just sectors. Also makes sure that the computation of max_nb_sectors later in the function will not divide by zero, by guaranteeing align is at least a sector. Signed-off-by: Eric Blake --- block/io.c | 5 +++--

[Qemu-devel] [PATCH 0/5] Byte-based block limits

BlockLimits is currently an ugly mix of byte limits vs. sector limits. Unify it. Fix some bugs I found in bdrv_aligned_preadv() while at it. Probably conflicts with Kevin's ongoing work to migrate bdrv_aligned_preadv() to be byte-based, but I found this handy before tackling conversion of

[Qemu-devel] [PATCH 5/5] block: Move request_alignment into BlockLimit

It makes more sense to have ALL block size limit constraints in the same struct. Improve the documentation while at it. Note that bdrv_refresh_limits() has to keep things alive across a memset() of BlockLimits. Signed-off-by: Eric Blake --- include/block/block_int.h | 12

[Qemu-devel] [PATCH 3/5] block: Switch transfer length bounds to byte-based

Sector-based limits are awkward to think about; in our on-going quest to move to byte-based interfaces, convert max_transfer_length and opt_transfer_length. Rename them (dropping the _length suffix) so that the compiler will help us catch the change in semantics across any rebased code. Improve

[Qemu-devel] [PATCH 4/5] block: Switch discard length bounds to byte-based

Sector-based limits are awkward to think about; in our on-going quest to move to byte-based interfaces, convert max_discard and discard_alignment. Rename them, using 'pdiscard' as an aid to track which remaining discard interfaces need conversion, and so that the compiler will help us catch the

Re: [Qemu-devel] [PATCH qemu v17 12/12] spapr_iommu, vfio, memory: Notify IOMMU about starting/stopping listening

On Wed, 1 Jun 2016 18:57:43 +1000 Alexey Kardashevskiy wrote: > The sPAPR TCE tables manage 2 copies when VFIO is using an IOMMU - > a guest view of the table and a hardware TCE table. If there is no VFIO > presense in the address space, then just the guest view is used, if >

Re: [Qemu-devel] [PATCH 2/2] arm/virt: Mark pcie controller node as dma-coherent

> -Original Message- > From: Qemu-devel > [mailto:qemu-devel-bounces+mihai.caraman=freescale@nongnu.org] On Behalf > Of Peter Maydell > Sent: Thursday, June 02, 2016 3:33 PM > To: Bogdan Purcareata > Cc: QEMU Developers ; Peter

Re: [Qemu-devel] [PATCH qemu v17 10/12] vfio/spapr: Create DMA window dynamically (SPAPR IOMMU v2)

On Wed, 1 Jun 2016 18:57:41 +1000 Alexey Kardashevskiy wrote: > New VFIO_SPAPR_TCE_v2_IOMMU type supports dynamic DMA window management. > This adds ability to VFIO common code to dynamically allocate/remove > DMA windows in the host kernel when new VFIO container is

Re: [Qemu-devel] [RFC v1 05/12] atomic: introduce cmpxchg_bool

On 15/04/16 17:23, Alex Bennée wrote: > diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h > index 5dba7db..94e7110 100644 > --- a/include/qemu/atomic.h > +++ b/include/qemu/atomic.h > @@ -123,6 +123,16 @@ > _old; \ >

Re: [Qemu-devel] [PATCH 2/2] arm/virt: Mark pcie controller node as dma-coherent

-Original Message- From: Alexander Graf [mailto:ag...@suse.de] Sent: Friday, June 03, 2016 6:26 PM To: Mihai Claudiu Caraman ; Peter Maydell > Cc: Bogdan Purcareata ; QEMU Developers > ;

Re: [Qemu-devel] [PATCH qemu v17 09/12] vfio: Add host side DMA window capabilities

On Wed, 1 Jun 2016 18:57:40 +1000 Alexey Kardashevskiy wrote: > There are going to be multiple IOMMUs per a container. This moves > the single host IOMMU parameter set to a list of VFIOHostDMAWindow. > > This should cause no behavioral change and will be used later by > the

Re: [Qemu-devel] [PATCH v2 10/13] raw-posix: Convert to bdrv_co_pwrite_zeroes()

Am 01.06.2016 um 23:10 hat Eric Blake geschrieben: > Another step on our continuing quest to switch to byte-based > interfaces. > > Signed-off-by: Eric Blake > --- > block/raw-posix.c | 34 +- > trace-events | 2 +- > 2 files changed, 18

  1   2   3   4   >