Re: [Qemu-devel] [RFC v2 22/32] vhost+postcopy: Add vhost waker

[Peter Xu]

On Thu, Aug 24, 2017 at 08:27:20PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert" 
> 
> Register a waker function in vhost-user code to be notified when
> pages arrive or requests to previously mapped pages get requested.
> 
> Signed-off-by: Dr. David Alan Gilbert 
> ---
>  hw/virtio/trace-events |  3 +++
>  hw/virtio/vhost-user.c | 26 ++
>  2 files changed, 29 insertions(+)
> 
> diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
> index f7d4b831fe..adebf6dc6b 100644
> --- a/hw/virtio/trace-events
> +++ b/hw/virtio/trace-events
> @@ -7,6 +7,9 @@ vhost_user_postcopy_fault_handler_found(int i, uint64_t 
> region_offset, uint64_t
>  vhost_user_postcopy_listen(void) ""
>  vhost_user_set_mem_table_postcopy(uint64_t client_addr, uint64_t qhva, int 
> reply_i, int region_i) "client:0x%"PRIx64" for hva: 0x%"PRIx64" reply %d 
> region %d"
>  vhost_user_set_mem_table_withfd(int index, const char *name, uint64_t 
> memory_size, uint64_t guest_phys_addr, uint64_t userspace_addr, uint64_t 
> offset) "%d:%s: size:0x%"PRIx64" GPA:0x%"PRIx64" QVA/userspace:0x%"PRIx64" RB 
> offset:0x%"PRIx64
> +vhost_user_postcopy_waker(const char *rb, uint64_t rb_offset) "%s + 
> 0x%"PRIx64
> +vhost_user_postcopy_waker_found(uint64_t client_addr) "0x%"PRIx64
> +vhost_user_postcopy_waker_nomatch(const char *rb, uint64_t rb_offset) "%s + 
> 0x%"PRIx64
>  
>  # hw/virtio/virtio.c
>  virtqueue_alloc_element(void *elem, size_t sz, unsigned in_num, unsigned 
> out_num) "elem %p size %zd in_num %u out_num %u"
> diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
> index 2897ff70b3..3bff33a1a6 100644
> --- a/hw/virtio/vhost-user.c
> +++ b/hw/virtio/vhost-user.c
> @@ -847,6 +847,31 @@ static int vhost_user_postcopy_fault_handler(struct 
> PostCopyFD *pcfd,
>  return -1;
>  }
>  
> +static int vhost_user_postcopy_waker(struct PostCopyFD *pcfd, RAMBlock *rb,
> + uint64_t offset)
> +{
> +struct vhost_dev *dev = pcfd->data;
> +struct vhost_user *u = dev->opaque;
> +int i;
> +
> +trace_vhost_user_postcopy_waker(qemu_ram_get_idstr(rb), offset);
> +/* Translate the offset into an address in the clients address space */
> +for (i = 0; i < MIN(dev->mem->nregions, u->region_rb_len); i++) {
> +if (u->region_rb[i] == rb &&
> +offset >= u->region_rb_offset[i] &&
> +offset < (u->region_rb_offset[i] +
> +  dev->mem->regions[i].memory_size)) {

Just curious: checks against offset should only be for safety, right?
Is there valid case that even rb is correct but the offset gets out of
the range of that RAMBlock?

> +uint64_t client_addr = (offset - u->region_rb_offset[i]) +
> +   u->postcopy_client_bases[i];
> +trace_vhost_user_postcopy_waker_found(client_addr);
> +return postcopy_wake_shared(pcfd, client_addr, rb);
> +}
> +}
> +
> +trace_vhost_user_postcopy_waker_nomatch(qemu_ram_get_idstr(rb), offset);
> +return 0;
> +}
> +
>  /*
>   * Called at the start of an inbound postcopy on reception of the
>   * 'advise' command.
> @@ -892,6 +917,7 @@ static int vhost_user_postcopy_advise(struct vhost_dev 
> *dev, Error **errp)
>  u->postcopy_fd.fd = ufd;
>  u->postcopy_fd.data = dev;
>  u->postcopy_fd.handler = vhost_user_postcopy_fault_handler;
> +u->postcopy_fd.waker = vhost_user_postcopy_waker;
>  u->postcopy_fd.idstr = "vhost-user"; /* Need to find unique name */
>  postcopy_register_shared_ufd(>postcopy_fd);
>  return 0;
> -- 
> 2.13.5
> 

-- 
Peter Xu

Re: [Qemu-devel] [RFC for-2.10 1/3] pci/pcie: Make a consistent helper for switching PCI/PCIe "hybrid" devices

[David Gibson]

On Tue, Aug 29, 2017 at 11:12:36AM -0300, Eduardo Habkost wrote:
> On Tue, Aug 29, 2017 at 09:42:39PM +1000, David Gibson wrote:
> > On Wed, Apr 26, 2017 at 06:23:58PM +0300, Michael S. Tsirkin wrote:
> > > On Tue, Mar 28, 2017 at 01:16:49PM +1100, David Gibson wrote:
> > > > virtio-pci and XHCI are "hybrid" devices in the sense that they can 
> > > > present
> > > > themselves as either PCIe or plain PCI devices depending on the machine
> > > > and bus they're connected to.
> > > > 
> > > > For virtio-pci to present as PCIe it requires that it's connected to a 
> > > > PCIe
> > > > bus and that it's not a root bus - this is to ensure that the device is
> > > > connected via a PCIe root port or downstream port rather than being a
> > > > integrated endpoint.  Some guests (Windows in particular AIUI) don't 
> > > > really
> > > > cope with PCIe integrated endpoints.
> > > > 
> > > > For XHCI it only checks that the bus is PCIe, but that probably means it
> > > > would cause problems if attached as an integrated devices directly to a
> > > > PCIe root bus.
> > > > 
> > > > This patch makes the test consistent between XHCI and virtio-pci, and
> > > > clarifies things by having them both use a new 'pci_allow_hybrid_pcie()'
> > > > helper which performs the same check as virtio-pci.
> > > > 
> > > > Signed-off-by: David Gibson 
> > > > ---
> > > >  hw/pci/pci.c   | 7 +++
> > > >  hw/usb/hcd-xhci.c  | 2 +-
> > > >  hw/virtio/virtio-pci.c | 3 +--
> > > >  include/hw/pci/pci.h   | 1 +
> > > >  4 files changed, 10 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> > > > index bd8043c..779787b 100644
> > > > --- a/hw/pci/pci.c
> > > > +++ b/hw/pci/pci.c
> > > > @@ -390,6 +390,13 @@ bool pci_bus_is_root(PCIBus *bus)
> > > >  return PCI_BUS_GET_CLASS(bus)->is_root(bus);
> > > >  }
> > > >  
> > > > +bool pci_allow_hybrid_pcie(PCIDevice *pci_dev)
> > > > +{
> > > > +PCIBus *bus = pci_dev->bus;
> > > > +
> > > > +return pci_bus_is_express(bus) && !pci_bus_is_root(bus);
> > > > +}
> > > > +
> > > >  void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState 
> > > > *parent,
> > > >   const char *name,
> > > >   MemoryRegion *address_space_mem,
> > > 
> > > I'd prefer pci_allow_hybrid_pci_pcie.
> > 
> > Ok, I've made that change for the next spin (aimed at 2.11, obviously).
> 
> I'm a bit confused by the naming: by looking at the function
> name, I don't know if "allow hybrid" means "this bus+device can
> (also) work as Conventional PCI" or "this bus+device can (also)
> work as PCI Express".

Neither, actually.  It means "should this device, which is capable of
both PCI and PCIe operation, operate as PCIe in this context".  It's
only expected to be called by devices which support both modes of
operation.

I have yet to think of a succinct name which conveys that :(.

> What about just naming it pci_allow_pcie() or
> pci_bus_allow_pcie()?  It looks like the function doesn't care if
> the device is hybrid or PCIe-only: it's only checking if the
> device can work as PCIe on that bus.  It's up to the device to
> decide if it should switch to Conventional PCI or report an error
> if the function returns false.

Hmm.. that would mean changing *every* existing PCIe device to call
this, which I don't think I want to do.

Also it's _not* really saying if a device can operate as PCIe.  AIUI,
a device _can_ operate as PCIe on a root bus (without a port) although
it's unusual.  Integrated PCIe devices would do so, IIUC.  For that
matter I believe current devices which only support PCIe mode will
also operate in PCIe mode on a root bus right now; but doing so
without inserting a root port might make guests unhappy, at least on
PC.

> 
> > 
> > > 
> > > > diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
> > > > index f0af852..a7ff4fd 100644
> > > > --- a/hw/usb/hcd-xhci.c
> > > > +++ b/hw/usb/hcd-xhci.c
> > > > @@ -3619,7 +3619,7 @@ static void usb_xhci_realize(struct PCIDevice 
> > > > *dev, Error **errp)
> > > >   
> > > > PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
> > > >   >mem);
> > > >  
> > > > -if (pci_bus_is_express(dev->bus) ||
> > > > +if (pci_allow_hybrid_pcie(dev) ||
> > > >  xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
> > > >  ret = pcie_endpoint_cap_init(dev, 0xa0);
> > > >  assert(ret >= 0);
> > > 
> > > This seems to change the behaviour for xhci on a root bus - what
> > > am I missing?
> > 
> > Nothing.  I didn't consider the backwards compat implications; I'll
> > fix it for the next spin.
> > 
> 
> 
> 

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [RFC v2 17/32] vhost+postcopy: Stash RAMBlock and offset

[Peter Xu]

On Thu, Aug 24, 2017 at 08:27:15PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert" 
> 
> Stash the RAMBlock and offset for later use looking up
> addresses.
> 
> Signed-off-by: Dr. David Alan Gilbert 
> ---
>  hw/virtio/trace-events |  1 +
>  hw/virtio/vhost-user.c | 30 ++
>  2 files changed, 31 insertions(+)
> 
> diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
> index 63fd4a79cf..5067dee19b 100644
> --- a/hw/virtio/trace-events
> +++ b/hw/virtio/trace-events
> @@ -3,6 +3,7 @@
>  # hw/virtio/vhost-user.c
>  vhost_user_postcopy_listen(void) ""
>  vhost_user_set_mem_table_postcopy(uint64_t client_addr, uint64_t qhva, int 
> reply_i, int region_i) "client:0x%"PRIx64" for hva: 0x%"PRIx64" reply %d 
> region %d"
> +vhost_user_set_mem_table_withfd(int index, const char *name, uint64_t 
> memory_size, uint64_t guest_phys_addr, uint64_t userspace_addr, uint64_t 
> offset) "%d:%s: size:0x%"PRIx64" GPA:0x%"PRIx64" QVA/userspace:0x%"PRIx64" RB 
> offset:0x%"PRIx64
>  
>  # hw/virtio/virtio.c
>  virtqueue_alloc_element(void *elem, size_t sz, unsigned in_num, unsigned 
> out_num) "elem %p size %zd in_num %u out_num %u"
> diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
> index 2e4eb0864a..fbe2743298 100644
> --- a/hw/virtio/vhost-user.c
> +++ b/hw/virtio/vhost-user.c
> @@ -135,6 +135,14 @@ struct vhost_user {
>  NotifierWithReturn postcopy_notifier;
>  struct PostCopyFD  postcopy_fd;
>  uint64_t   postcopy_client_bases[VHOST_MEMORY_MAX_NREGIONS];
> +/* Length of the region_rb and region_rb_offset arrays */
> +size_t region_rb_len;
> +/* RAMBlock associated with a given region */
> +RAMBlock **region_rb;
> +/* The offset from the start of the RAMBlock to the start of the
> + * vhost region.
> + */
> +ram_addr_t*region_rb_offset;
>  };
>  
>  static bool ioeventfd_enabled(void)
> @@ -319,6 +327,17 @@ static int vhost_user_set_mem_table(struct vhost_dev 
> *dev,
>  msg.flags |= VHOST_USER_NEED_REPLY_MASK;
>  }
>  
> +if (u->region_rb_len < dev->mem->nregions) {
> +u->region_rb = g_renew(RAMBlock*, u->region_rb, dev->mem->nregions);
> +u->region_rb_offset = g_renew(ram_addr_t, u->region_rb_offset,
> +  dev->mem->nregions);
> +memset(&(u->region_rb[u->region_rb_len]), '\0',
> +   sizeof(RAMBlock *) * (dev->mem->nregions - u->region_rb_len));
> +memset(&(u->region_rb_offset[u->region_rb_len]), '\0',
> +   sizeof(ram_addr_t) * (dev->mem->nregions - u->region_rb_len));
> +u->region_rb_len = dev->mem->nregions;
> +}
> +
>  for (i = 0; i < dev->mem->nregions; ++i) {
>  struct vhost_memory_region *reg = dev->mem->regions + i;
>  ram_addr_t offset;
> @@ -327,8 +346,14 @@ static int vhost_user_set_mem_table(struct vhost_dev 
> *dev,
>  assert((uintptr_t)reg->userspace_addr == reg->userspace_addr);
>  mr = memory_region_from_host((void *)(uintptr_t)reg->userspace_addr,
>   );
> +u->region_rb_offset[i] = offset;
> +u->region_rb[i] = mr->ram_block;

Do we need to record these info even if fd <= 0?

>  fd = memory_region_get_fd(mr);
>  if (fd > 0) {
> +trace_vhost_user_set_mem_table_withfd(fd_num, mr->name,
> +  reg->memory_size,
> +  reg->guest_phys_addr,
> +  reg->userspace_addr, 
> offset);
>  msg.payload.memory.regions[fd_num].userspace_addr = 
> reg->userspace_addr;
>  msg.payload.memory.regions[fd_num].memory_size  = 
> reg->memory_size;
>  msg.payload.memory.regions[fd_num].guest_phys_addr = 
> reg->guest_phys_addr;
> @@ -992,6 +1017,11 @@ static int vhost_user_cleanup(struct vhost_dev *dev)
>  close(u->slave_fd);
>  u->slave_fd = -1;
>  }
> +g_free(u->region_rb);
> +u->region_rb = NULL;
> +g_free(u->region_rb_offset);
> +u->region_rb_offset = NULL;
> +u->region_rb_len = 0;
>  g_free(u);
>  dev->opaque = 0;
>  
> -- 
> 2.13.5
> 

-- 
Peter Xu

Re: [Qemu-devel] [RFC v2 19/32] vhost+postcopy: Resolve client address

[Peter Xu]

On Thu, Aug 24, 2017 at 08:27:17PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert" 
> 
> Resolve fault addresses read off the clients UFD into RAMBlock
> and offset, and call back to the postcopy code to ask for the page.
> 
> Signed-off-by: Dr. David Alan Gilbert 
> ---
>  hw/virtio/trace-events |  3 +++
>  hw/virtio/vhost-user.c | 30 +-
>  2 files changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
> index 5067dee19b..f7d4b831fe 100644
> --- a/hw/virtio/trace-events
> +++ b/hw/virtio/trace-events
> @@ -1,6 +1,9 @@
>  # See docs/devel/tracing.txt for syntax documentation.
>  
>  # hw/virtio/vhost-user.c
> +vhost_user_postcopy_fault_handler(const char *name, uint64_t fault_address, 
> int nregions) "%s: @0x%"PRIx64" nregions:%d"
> +vhost_user_postcopy_fault_handler_loop(int i, uint64_t client_base, uint64_t 
> size) "%d: client 0x%"PRIx64" +0x%"PRIx64
> +vhost_user_postcopy_fault_handler_found(int i, uint64_t region_offset, 
> uint64_t rb_offset) "%d: region_offset: 0x%"PRIx64" rb_offset:0x%"PRIx64
>  vhost_user_postcopy_listen(void) ""
>  vhost_user_set_mem_table_postcopy(uint64_t client_addr, uint64_t qhva, int 
> reply_i, int region_i) "client:0x%"PRIx64" for hva: 0x%"PRIx64" reply %d 
> region %d"
>  vhost_user_set_mem_table_withfd(int index, const char *name, uint64_t 
> memory_size, uint64_t guest_phys_addr, uint64_t userspace_addr, uint64_t 
> offset) "%d:%s: size:0x%"PRIx64" GPA:0x%"PRIx64" QVA/userspace:0x%"PRIx64" RB 
> offset:0x%"PRIx64
> diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
> index fbe2743298..2897ff70b3 100644
> --- a/hw/virtio/vhost-user.c
> +++ b/hw/virtio/vhost-user.c
> @@ -816,7 +816,35 @@ out:
>  static int vhost_user_postcopy_fault_handler(struct PostCopyFD *pcfd,
>   void *ufd)
>  {
> -return 0;
> +struct vhost_dev *dev = pcfd->data;
> +struct vhost_user *u = dev->opaque;
> +struct uffd_msg *msg = ufd;
> +uint64_t faultaddr = msg->arg.pagefault.address;
> +RAMBlock *rb = NULL;
> +uint64_t rb_offset;
> +int i;
> +
> +trace_vhost_user_postcopy_fault_handler(pcfd->idstr, faultaddr,
> +dev->mem->nregions);
> +for (i = 0; i < MIN(dev->mem->nregions, u->region_rb_len); i++) {

Should dev->mem->nregions always the same as u->region_rb_len?

> +trace_vhost_user_postcopy_fault_handler_loop(i,
> +u->postcopy_client_bases[i], 
> dev->mem->regions[i].memory_size);
> +if (faultaddr >= u->postcopy_client_bases[i]) {
> +/* Ofset of the fault address in the vhost region */
> +uint64_t region_offset = faultaddr - u->postcopy_client_bases[i];
> +if (region_offset <= dev->mem->regions[i].memory_size) {

Should be "<" rather than "<="?  Say:

Region 1: [0, 1M), size 1M
Region 2: [1M, 2M), size 1M

Looks like otherwise faultaddr=1M will fall into region 1, while it
should be region 2?

> +rb_offset = region_offset + u->region_rb_offset[i];
> +trace_vhost_user_postcopy_fault_handler_found(i,
> +region_offset, rb_offset);
> +rb = u->region_rb[i];

Nit: this "rb" might be avoided if only used once.

> +return postcopy_request_shared_page(pcfd, rb, faultaddr,
> +rb_offset);
> +}
> +}
> +}
> +error_report("%s: Failed to find region for fault %" PRIx64,
> + __func__, faultaddr);
> +return -1;
>  }
>  
>  /*
> -- 
> 2.13.5
> 

-- 
Peter Xu

Re: [Qemu-devel] [PATCH v4 1/1] PPC: KVM: Support machine option to set VSMT mode

[David Gibson]

On Fri, Aug 18, 2017 at 03:50:22PM +1000, Sam Bobroff wrote:
> KVM now allows writing to KVM_CAP_PPC_SMT which has previously been
> read only. Doing so causes KVM to act, for that VM, as if the host's
> SMT mode was the given value. This is particularly important on Power
> 9 systems because their default value is 1, but they are able to
> support values up to 8.
> 
> This patch introduces a way to control this capability via a new
> machine property called VSMT ("Virtual SMT"). If the value is not set
> on the command line a default is chosen that is, when possible,
> compatible with legacy systems.
> 
> Note that the intialization of KVM_CAP_PPC_SMT has changed slightly
> because it has changed (in KVM) from a global capability to a
> VM-specific one. This won't cause a problem on older KVMs because VM
> capabilities fall back to global ones.
> 
> Signed-off-by: Sam Bobroff 

There are some things that could be tweaked, but I see no reason they
can't be done as followups.

Applied to ppc-for-2.11.

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH v2 0/3] QEMU Backup Tool

[Fam Zheng]

On Tue, 08/29 22:13, Ishani Chugh wrote:
> This patch series is intended to introduce QEMU Backup tool.
> qemu-backup will be a command-line tool for performing full and
> incremental disk backups on running VMs. It is intended as a
> reference implementation for management stack and backup developers
> to see QEMU's backup features in action.
> This patch series contains three patches,
>1) QEMU Backup command line tool.
>2) Test for full backup.
>3) Manpage for the tool.

Looks good in general. I've left small suggestions. Thanks for working on this
tool!

Fam

> 
> Ishani Chugh (3):
>   backup: QEMU Backup Tool
>   Test for full Backup
>   Add manpage for QEMU Backup Tool
> 
>  Makefile|  14 +-
>  contrib/backup/qemu-backup.py   | 335 
> 
>  contrib/backup/qemu-backup.texi | 144 +
>  tests/qemu-iotests/191  |  86 +++
>  tests/qemu-iotests/191.out  |  35 +
>  tests/qemu-iotests/group|   2 +
>  6 files changed, 612 insertions(+), 4 deletions(-)
>  create mode 100644 contrib/backup/qemu-backup.py
>  create mode 100644 contrib/backup/qemu-backup.texi
>  create mode 100755 tests/qemu-iotests/191
>  create mode 100644 tests/qemu-iotests/191.out
> 
> -- 
> 2.7.4
> 
> 

Re: [Qemu-devel] [PATCH v2 3/3] Add manpage for QEMU Backup Tool

[Fam Zheng]

On Tue, 08/29 22:13, Ishani Chugh wrote:
> qemu-backup will be a command-line tool for performing full and
> incremental disk backups on running VMs. It is intended as a
> reference implementation for management stack and backup developers
> to see QEMU's backup features in action. The following commit is an

Please don't say "the following commit" in a commit message to refer to "this
commit", because it sounds like the next commit.

> initial implementation of manpage listing the commands which the
> backup tool will support. The manpage wil be build along with other

s/wil/will/
s/build/built/

> docs when configure is provided with --enable-docs flag in the
> location contrib/backup in build directory.
> 
> 
> Signed-off-by: Ishani Chugh 
> ---
>  Makefile|  14 ++--
>  contrib/backup/qemu-backup.texi | 144 
> 
>  2 files changed, 154 insertions(+), 4 deletions(-)
>  create mode 100644 contrib/backup/qemu-backup.texi
> 
> diff --git a/Makefile b/Makefile
> index 81447b1..ba1574d 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -209,6 +209,7 @@ ifdef BUILD_DOCS
>  DOCS=qemu-doc.html qemu-doc.txt qemu.1 qemu-img.1 qemu-nbd.8 qemu-ga.8
>  DOCS+=docs/interop/qemu-qmp-ref.html docs/interop/qemu-qmp-ref.txt 
> docs/interop/qemu-qmp-ref.7
>  DOCS+=docs/interop/qemu-ga-ref.html docs/interop/qemu-ga-ref.txt 
> docs/interop/qemu-ga-ref.7
> +DOCS+=contrib/backup/qemu-backup.html contrib/backup/qemu-backup.txt
>  ifdef CONFIG_VIRTFS
>  DOCS+=fsdev/virtfs-proxy-helper.1
>  endif
> @@ -508,6 +509,8 @@ VERSION ?= $(shell cat VERSION)
>  
>  dist: qemu-$(VERSION).tar.bz2
>  
> +qemu-backup.8: contrib/backup/qemu-backup.texi
> +
>  qemu-%.tar.bz2:
>   $(SRC_PATH)/scripts/make-release "$(SRC_PATH)" "$(patsubst 
> qemu-%.tar.bz2,%,$@)"
>  
> @@ -719,16 +722,19 @@ fsdev/virtfs-proxy-helper.1: 
> fsdev/virtfs-proxy-helper.texi
>  qemu-nbd.8: qemu-nbd.texi qemu-option-trace.texi
>  qemu-ga.8: qemu-ga.texi
>  
> -html: qemu-doc.html docs/interop/qemu-qmp-ref.html 
> docs/interop/qemu-ga-ref.html
> -info: qemu-doc.info docs/interop/qemu-qmp-ref.info 
> docs/interop/qemu-ga-ref.info
> -pdf: qemu-doc.pdf docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf
> -txt: qemu-doc.txt docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt
> +html: qemu-doc.html docs/interop/qemu-qmp-ref.html 
> docs/interop/qemu-ga-ref.html contrib/backup/qemu-backup.html
> +info: qemu-doc.info docs/interop/qemu-qmp-ref.info 
> docs/interop/qemu-ga-ref.info contrib/backup/qemu-backup.info
> +pdf: qemu-doc.pdf docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf 
> contrib/backup/qemu-backup.pdf
> +txt: qemu-doc.txt docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt 
> contrib/backup/qemu-backup.txt
>  
>  qemu-doc.html qemu-doc.info qemu-doc.pdf qemu-doc.txt: \
>   qemu-img.texi qemu-nbd.texi qemu-options.texi qemu-option-trace.texi \
>   qemu-monitor.texi qemu-img-cmds.texi qemu-ga.texi \
>   qemu-monitor-info.texi
>  
> +contrib/backup/qemu-backup.html contrib/backup/qemu-backup.pdf 
> contrib/backup/qemu-backup.txt contrib/backup/qemu-backup.info: \
> + contrib/backup/qemu-backup.texi
> +
>  docs/interop/qemu-ga-ref.dvi docs/interop/qemu-ga-ref.html \
>  docs/interop/qemu-ga-ref.info docs/interop/qemu-ga-ref.pdf \
>  docs/interop/qemu-ga-ref.txt docs/interop/qemu-ga-ref.7: \
> diff --git a/contrib/backup/qemu-backup.texi b/contrib/backup/qemu-backup.texi
> new file mode 100644
> index 000..68e7231
> --- /dev/null
> +++ b/contrib/backup/qemu-backup.texi
> @@ -0,0 +1,144 @@
> +\input texinfo
> +@setfilename qemu-backup
> +
> +@documentlanguage en
> +@documentencoding UTF-8
> +
> +@settitle QEMU Backup Tool
> +@copying
> +
> +Copyright @copyright{} 2017 The QEMU Project developers
> +@end copying
> +@ifinfo
> +@direntry
> +* QEMU: (QEMU-backup).Man page for QEMU Backup Tool.
> +@end direntry
> +@end ifinfo
> +@iftex
> +@titlepage
> +@sp 7
> +@center @titlefont{QEMU Backup Tool}
> +@sp 1
> +@sp 3
> +@end titlepage
> +@end iftex
> +@ifnottex
> +@node Top
> +@top Short Sample
> +
> +@menu
> +* Name::
> +* Synopsis::
> +* List of Commands::
> +* Command Parameters::
> +* Command Descriptions::
> +* License::
> +@end menu
> +
> +@end ifnottex
> +
> +@node Name
> +@chapter Name
> +
> +QEMU disk backup tool.
> +
> +@node Synopsis
> +@chapter Synopsis
> +
> +qemu-backup command [command options].
> +
> +@node  List of Commands
> +@chapter  List of Commands
> +@itemize
> +@item qemu-backup guest add --guest guestname --qmp socketpath
> +@item qemu-backup guest list
> +@item qemu-backup drive add --id driveid --guest guestname --target target
> +@item qemu-backup drive add --all --guest guestname --target target
> +@item qemu-backup drive list --guest guestname
> +@item qemu-backup backup [--inc] --guest guestname
> +@item qemu-backup restore --guest guestname
> +@item qemu-backup guest remove --guest 

Re: [Qemu-devel] [PATCH v2 1/3] backup: QEMU Backup Tool

[Fam Zheng]

On Tue, 08/29 22:13, Ishani Chugh wrote:
> +class BackupTool(object):
> +"""BackupTool Class"""
> +def __init__(self, config_file=os.path.expanduser('~') +
> + '/.config/qemu/qemu-backup-config'):
> +if "QEMU_BACKUP_CONFIG" in os.environ:
> +self.config_file = os.environ["QEMU_BACKUP_CONFIG"]
> +else:
> +self.config_file = config_file
> +try:
> +if not os.path.isdir(os.path.dirname(self.config_file)):
> +os.makedirs(os.path.dirname(self.config_file))
> +except:
> +print("Cannot create config directory", file=sys.stderr)
> +sys.exit(1)
> +self.config = configparser.ConfigParser()
> +self.config.read(self.config_file)

I suggest adding versioning to the config file, so that a future update to this
tool can make an incompatible change without breaking older tool:

[general]
version=0.1

[guest_1]
...

[guest_2]
...

And only continue if the version is known.

Fam

Re: [Qemu-devel] [PATCH v2 1/3] backup: QEMU Backup Tool

[Fam Zheng]

On Tue, 08/29 22:13, Ishani Chugh wrote:
> +def _restore(self, guest_name):
> +"""
> +Prints Steps to perform restore operation
> +"""
> +if guest_name not in self.config.sections():
> +print("Cannot find specified guest", file=sys.stderr)
> +sys.exit(1)
> +
> +self.verify_guest_running(guest_name)
> +connection = QEMUMonitorProtocol(
> + self.get_socket_address(
> + self.config[guest_name]['qmp']))
> +connection.connect()
> +print("To perform restore:")
> +print("Shut down guest")
> +for key in self.config[guest_name]:
> +if key.startswith("drive_"):
> +drive = key[len('drive_'):]
> +target = self.config[guest_name][key]
> +cmd = {'execute': 'query-block'}
> +returned_json = connection.cmd_obj(cmd)
> +device_present = False
> +for device in returned_json['return']:
> +if device['device'] == drive:
> +device_present = True
> +location = device['inserted']['image']['filename']
> +print("Replace " + location + " By " + target)

Maybe just

print("qemu-img convert " + location + " " + target)

which is almost ready to copy into a command line? (You or the user needs
take care of quoting and escaping to handle the special characters, if any.)

> +
> +if not device_present:
> +print("No such drive in guest", file=sys.stderr)
> +sys.exit(1)
> +

Fam

Re: [Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC

[Philippe Mathieu-Daudé]

Hi Subbaraya,

On 08/28/2017 01:38 PM, Subbaraya Sundeep wrote:

Smartfusion2 SoC has hardened Microcontroller subsystem
and flash based FPGA fabric. This patch adds support for
Microcontroller subsystem in the SoC.

Signed-off-by: Subbaraya Sundeep 
---
  default-configs/arm-softmmu.mak |   1 +
  hw/arm/Makefile.objs|   1 +
  hw/arm/msf2-soc.c   | 215 
  include/hw/arm/msf2-soc.h   |  66 
  4 files changed, 283 insertions(+)
  create mode 100644 hw/arm/msf2-soc.c
  create mode 100644 include/hw/arm/msf2-soc.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index bbdd3c1..5059d13 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -129,3 +129,4 @@ CONFIG_ACPI=y
  CONFIG_SMBIOS=y
  CONFIG_ASPEED_SOC=y
  CONFIG_GPIO_KEY=y
+CONFIG_MSF2=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index a2e56ec..df36a03 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
  obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
  obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
  obj-$(CONFIG_MPS2) += mps2.o
+obj-$(CONFIG_MSF2) += msf2-soc.o
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
new file mode 100644
index 000..276eec5
--- /dev/null
+++ b/hw/arm/msf2-soc.c
@@ -0,0 +1,215 @@
+/*
+ * SmartFusion2 SoC emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "hw/char/serial.h"
+#include "hw/boards.h"
+#include "sysemu/block-backend.h"
+#include "qemu/cutils.h"
+#include "hw/arm/msf2-soc.h"
+
+#define MSF2_TIMER_BASE   0x40004000
+#define MSF2_SYSREG_BASE  0x40038000
+
+#define ENVM_BASE_ADDRESS 0x6000
+
+#define SRAM_BASE_ADDRESS 0x2000
+
+#define MSF2_ENVM_SIZE(512 * K_BYTE)
+#define MSF2_ESRAM_SIZE   (64 * K_BYTE)


Eventually you should name those _SIZE_MAX.

I miscorrected you in v4, 64kB is true with SECDED disabled, else the 
SoC is designed for 80kB. Not a big deal, we can add a "SECDED not 
supported" warning later.

Can you add a comment about it?


+
+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x4000 , 0x4001 };
+
+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
+static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
+
+static void m2sxxx_soc_initfn(Object *obj)
+{
+MSF2State *s = MSF2_SOC(obj);
+int i;
+
+object_initialize(>armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
+qdev_set_parent_bus(DEVICE(>armv7m), sysbus_get_default());
+
+object_initialize(>sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
+qdev_set_parent_bus(DEVICE(>sysreg), sysbus_get_default());
+
+object_initialize(>timer, sizeof(s->timer), TYPE_MSS_TIMER);
+qdev_set_parent_bus(DEVICE(>timer), sysbus_get_default());
+


What about the UARTs?


+for (i = 0; i < MSF2_NUM_SPIS; i++) {
+object_initialize(>spi[i], sizeof(s->spi[i]),
+  TYPE_MSS_SPI);
+qdev_set_parent_bus(DEVICE(>spi[i]), sysbus_get_default());
+}
+}
+
+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+MSF2State *s = MSF2_SOC(dev_soc);
+DeviceState *dev, *armv7m;
+SysBusDevice *busdev;
+Error *err = NULL;
+int i;
+
+MemoryRegion *system_memory = get_system_memory();
+MemoryRegion *nvm = g_new(MemoryRegion, 1);
+MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
+MemoryRegion *sram = g_new(MemoryRegion, 1);
+
+memory_region_init_ram(nvm, NULL, "MSF2.eNVM", 

Re: [Qemu-devel] [PATCH 6/9] AHCI: Replace DPRINTF with trace-events

[Philippe Mathieu-Daudé]

[...]

+# hw/ide/ahci.c
+ahci_port_read(void *s, int port, int offset, uint32_t ret)
"ahci(%p)[%d]: port read @ 0x%x: 0x%08x"
+ahci_irq_raise(void *s) "ahci(%p): raise irq"
+ahci_irq_lower(void *s) "ahci(%p): lower irq"
+ahci_check_irq(void *s, uint32_t old, uint32_t new) "ahci(%p): check
irq 0x%08x --> 0x%08x"
+
+ahci_port_write(void *s, int port, int offset, uint32_t val)
"ahci(%p)[%d]: port write @ 0x%x: 0x%08x"
+ahci_mem_read_32(void *s, uint64_t addr, uint32_t val) "ahci(%p): mem
read @ 0x%"PRIx64": 0x%08x"


can you use same format than ahci_mem_read()?

"ahci(%p): read%u @ 0x%"PRIx64": 0x%08x"


+ahci_mem_read(void *s, unsigned size, uint64_t addr, uint64_t val)
"ahci(%p): read%u @ 0x%"PRIx64": 0x%016"PRIx64
+ahci_mem_write(void *s, unsigned size, uint64_t addr, uint64_t val)
"ahci(%p): write%u @ 0x%"PRIx64": 0x%016"PRIx64
+ahci_mem_write_unknown(void *s, uint64_t addr) "ahci(%p): write to
unknown register 0x%"PRIx64


report the value written, eventually:

"ahci(%p): write%u @ 0x%"PRIx64": 0x%016"PRIx64" UNKNOWN"



Not necessary here; it's reported by the more generic
trace_ahci_mem_write which gets all of the writes no matter where they
go. In this case, too, the write is actually ignored and doesn't wind up
going anywhere ...

... but I suppose it wouldn't hurt to know what that value would have
been. If we enable just this trace that will probably help illuminate
what the errant write is.


+ahci_set_signature(void *s, int port, uint8_t nsector, uint8_t
sector, uint8_t lcyl, uint8_t hcyl, uint32_t sig) "ahci(%p)[%d]: set
signature sector:0x%02x nsector:0x%02x lcyl:0x%02x hcyl:0x%02x
(cumulatively: 0x%08x)"
+ahci_reset_port(void *s, int port) "ahci(%p)[%d]: reset port"


could be generic:

ahci_port(void *s, int port) "ahci(%p)[%d]: %s"

then

trace_ahci_port(s, port, "reset port");



I don't disagree, just more trepidation on what that means for the trace
events which are otherwise all named exactly for the functions that call
them.

Also, the problem with combining these sorts of traces becomes one with
the DPRINTF we're replacing: you can't target individual sections of
code anymore, and you either turn on "ahci_port" or off.


Oh I did not think of that, good point.



If there is a better suggestion for avoiding the ahci(%p)[%d]: pattern
here over and over and over and over again I'd happily take it.

Stefan?

[...snip...]


+ahci_reset(void *s) "ahci(%p): HBA reset"
+allwinner_ahci_mem_read(void *s, void *a, uint64_t addr, uint64_t
val, unsigned size) "ahci(%p): read a=%p addr=0x%"HWADDR_PRIx"
val=0x%"PRIx64", size=%d"


is AllwinnerAHCIState useful?



Only as far as it happens to be the argument to this function; of course
AHCIState is the real prize, but we have to fish it out of
AllwinnerAHCIState first.


I'd rather use directly trace_ahci_mem_read(s, size, addr, val)

+allwinner_ahci_mem_write(void *s, void *a, uint64_t addr, uint64_t

val, unsigned size) "ahci(%p): write a=%p addr=0x%"HWADDR_PRIx"
val=0x%"PRIx64", size=%d"


and trace_ahci_mem_write(s, size, addr, val)

Regards,

Phil.

Re: [Qemu-devel] [PATCH 4/8] tcg: Add operations for host vectors

[Philippe Mathieu-Daudé]

On 08/17/2017 08:01 PM, Richard Henderson wrote:

Nothing uses or implements them yet.

Signed-off-by: Richard Henderson 


Reviewed-by: Philippe Mathieu-Daudé 


---
  tcg/tcg-opc.h | 89 +++
  tcg/tcg.h | 24 
  2 files changed, 113 insertions(+)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 956fb1e9f3..9162125fac 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -206,6 +206,95 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
  
  #undef TLADDR_ARGS

  #undef DATA64_ARGS
+
+/* Host integer vector operations.  */
+/* These opcodes are required whenever the base vector size is enabled.  */
+
+DEF(mov_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_v64))
+DEF(mov_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(mov_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_v256))
+
+DEF(movi_v64, 1, 0, 1, IMPL(TCG_TARGET_HAS_v64))
+DEF(movi_v128, 1, 0, 1, IMPL(TCG_TARGET_HAS_v128))
+DEF(movi_v256, 1, 0, 1, IMPL(TCG_TARGET_HAS_v256))
+
+DEF(ld_v64, 1, 1, 1, IMPL(TCG_TARGET_HAS_v64))
+DEF(ld_v128, 1, 1, 1, IMPL(TCG_TARGET_HAS_v128))
+DEF(ld_v256, 1, 1, 1, IMPL(TCG_TARGET_HAS_v256))
+
+DEF(st_v64, 0, 2, 1, IMPL(TCG_TARGET_HAS_v64))
+DEF(st_v128, 0, 2, 1, IMPL(TCG_TARGET_HAS_v128))
+DEF(st_v256, 0, 2, 1, IMPL(TCG_TARGET_HAS_v256))
+
+DEF(and_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))
+DEF(and_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(and_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+
+DEF(or_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))
+DEF(or_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(or_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+
+DEF(xor_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))
+DEF(xor_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(xor_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+
+DEF(add8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))
+DEF(add16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))
+DEF(add32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))
+
+DEF(add8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(add16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(add32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(add64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+
+DEF(add8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+DEF(add16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+DEF(add32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+DEF(add64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+
+DEF(sub8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))
+DEF(sub16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))
+DEF(sub32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))
+
+DEF(sub8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(sub16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(sub32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+DEF(sub64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))
+
+DEF(sub8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+DEF(sub16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+DEF(sub32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+DEF(sub64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))
+
+/* These opcodes are optional.
+   All element counts must be supported if any are.  */
+
+DEF(not_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v64))
+DEF(not_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v128))
+DEF(not_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v256))
+
+DEF(andc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v64))
+DEF(andc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v128))
+DEF(andc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v256))
+
+DEF(orc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v64))
+DEF(orc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v128))
+DEF(orc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v256))
+
+DEF(neg8_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64))
+DEF(neg16_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64))
+DEF(neg32_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64))
+
+DEF(neg8_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128))
+DEF(neg16_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128))
+DEF(neg32_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128))
+DEF(neg64_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128))
+
+DEF(neg8_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256))
+DEF(neg16_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256))
+DEF(neg32_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256))
+DEF(neg64_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256))
+
  #undef IMPL
  #undef IMPL64
  #undef DEF
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 1277caed3d..b9e15da13b 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -166,6 +166,30 @@ typedef uint64_t TCGRegSet;
  #define TCG_TARGET_HAS_rem_i64  0
  #endif
  
+#ifndef TCG_TARGET_HAS_v64

+#define TCG_TARGET_HAS_v64  0
+#define TCG_TARGET_HAS_andc_v64 0
+#define TCG_TARGET_HAS_orc_v64  0
+#define TCG_TARGET_HAS_not_v64  0
+#define TCG_TARGET_HAS_neg_v64  0
+#endif
+
+#ifndef TCG_TARGET_HAS_v128
+#define TCG_TARGET_HAS_v128 0
+#define TCG_TARGET_HAS_andc_v1280
+#define TCG_TARGET_HAS_orc_v128 0
+#define TCG_TARGET_HAS_not_v128 0
+#define TCG_TARGET_HAS_neg_v128 0
+#endif
+
+#ifndef TCG_TARGET_HAS_v256
+#define TCG_TARGET_HAS_v256 

Re: [Qemu-devel] [Qemu devel v7 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit

[Philippe Mathieu-Daudé]

Hi Subbaraya,

On 08/28/2017 01:38 PM, Subbaraya Sundeep wrote:

Emulated Emcraft's Smartfusion2 System On Module starter
kit.

Signed-off-by: Subbaraya Sundeep 
---
  hw/arm/Makefile.objs |  2 +-
  hw/arm/msf2-som.c| 94 
  2 files changed, 95 insertions(+), 1 deletion(-)
  create mode 100644 hw/arm/msf2-som.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index df36a03..e81a7dc 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -19,4 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
  obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
  obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
  obj-$(CONFIG_MPS2) += mps2.o
-obj-$(CONFIG_MSF2) += msf2-soc.o
+obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
new file mode 100644
index 000..fd89ba9
--- /dev/null
+++ b/hw/arm/msf2-som.c
@@ -0,0 +1,94 @@
+/*
+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "qemu/cutils.h"
+#include "hw/arm/msf2-soc.h"
+
+#define DDR_BASE_ADDRESS  0xA000
+#define DDR_SIZE  (64 * M_BYTE)
+
+#define M2S010_ENVM_SIZE  (256 * K_BYTE)
+#define M2S010_ESRAM_SIZE (64 * K_BYTE)
+
+static void emcraft_sf2_init(MachineState *machine)


Since Emcraft can produce an upgraded SF2 SoC based on a different MCU, 
I prefer you rename it:


static void emcraft_sf2_s2s010_init(MachineState *machine)


+{
+DeviceState *dev;
+DeviceState *spi_flash;
+MSF2State *soc;
+DriveInfo *dinfo = drive_get_next(IF_MTD);
+qemu_irq cs_line;
+SSIBus *spi_bus;
+MemoryRegion *sysmem = get_system_memory();
+MemoryRegion *ddr = g_new(MemoryRegion, 1);
+
+memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
+   _fatal);
+memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
+
+dev = qdev_create(NULL, TYPE_MSF2_SOC);
+qdev_prop_set_string(dev, "part-name", "M2S010");
+qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
+qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
+
+/*
+ * CPU clock and peripheral clocks(APB0, APB1)are configurable
+ * in Libero. CPU clock is divided by APB0 and APB1 divisors for
+ * peripherals. Emcraft's SoM kit comes with these settings by default.
+ */
+qdev_prop_set_uint32(dev, "m3clk", 142 * 100);
+qdev_prop_set_uint32(dev, "apb0div", 2);
+qdev_prop_set_uint32(dev, "apb1div", 2);
+
+object_property_set_bool(OBJECT(dev), true, "realized", _fatal);
+
+soc = MSF2_SOC(dev);
+
+/* Attach SPI flash to SPI0 controller */
+spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
+spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
+qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
+if (dinfo) {
+qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
+_fatal);
+}
+qdev_init_nofail(spi_flash);
+cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
+sysbus_connect_irq(SYS_BUS_DEVICE(>spi[0]), 1, cs_line);
+
+armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+   soc->envm_size);
+}
+
+static void emcraft_sf2_machine_init(MachineClass *mc)
+{
+mc->desc = "SmartFusion2 SOM kit from Emcraft";


mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";


+mc->init = emcraft_sf2_init;


mc->init = emcraft_sf2_s2s010_init;


+}
+
+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)


Good work :)

With the changes:
Reviewed-by: Philippe Mathieu-Daudé 

Re: [Qemu-devel] [PATCH v2 7/9] AHCI: Rework IRQ constants

[Philippe Mathieu-Daudé]

On 08/29/2017 05:49 PM, John Snow wrote:

Create a new enum so that we can name the IRQ bits, which will make debugging
them a little nicer if we can print them out. Not handled in this patch, but
this will make it possible to get a nice debug printf detailing exactly which
status bits are set, as it can be multiple at any given time.

As a consequence of this patch, it is no longer possible to set multiple IRQ
codes at once, but nothing was utilizing this ability anyway.

Signed-off-by: John Snow 
---
  hw/ide/ahci.c  | 49 ++---
  hw/ide/ahci_internal.h | 44 +++-
  hw/ide/trace-events|  2 +-
  3 files changed, 74 insertions(+), 21 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index c60a000..a0a4dd6 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -56,6 +56,27 @@ static bool ahci_map_fis_address(AHCIDevice *ad);
  static void ahci_unmap_clb_address(AHCIDevice *ad);
  static void ahci_unmap_fis_address(AHCIDevice *ad);
  
+static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__END] = {

+[AHCI_PORT_IRQ_BIT_DHRS] = "DHRS",
+[AHCI_PORT_IRQ_BIT_PSS]  = "PSS",
+[AHCI_PORT_IRQ_BIT_DSS]  = "DSS",
+[AHCI_PORT_IRQ_BIT_SDBS] = "SDBS",
+[AHCI_PORT_IRQ_BIT_UFS]  = "UFS",
+[AHCI_PORT_IRQ_BIT_DPS]  = "DPS",
+[AHCI_PORT_IRQ_BIT_PCS]  = "PCS",
+[AHCI_PORT_IRQ_BIT_DMPS] = "DMPS",
+[8 ... 21]   = "RESERVED",
+[AHCI_PORT_IRQ_BIT_PRCS] = "PRCS",
+[AHCI_PORT_IRQ_BIT_IPMS] = "IPMS",
+[AHCI_PORT_IRQ_BIT_OFS]  = "OFS",
+[25] = "RESERVED",
+[AHCI_PORT_IRQ_BIT_INFS] = "INFS",
+[AHCI_PORT_IRQ_BIT_IFS]  = "IFS",
+[AHCI_PORT_IRQ_BIT_HBDS] = "HBDS",
+[AHCI_PORT_IRQ_BIT_HBFS] = "HBFS",
+[AHCI_PORT_IRQ_BIT_TFES] = "TFES",
+[AHCI_PORT_IRQ_BIT_CPDS] = "CPDS"
+};
  
  static uint32_t  ahci_port_read(AHCIState *s, int port, int offset)

  {
@@ -170,12 +191,18 @@ static void ahci_check_irq(AHCIState *s)
  }
  
  static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,

- int irq_type)
+ enum AHCIPortIRQ irqbit)
  {
-DPRINTF(d->port_no, "trigger irq %#x -> %x\n",
-irq_type, d->port_regs.irq_mask & irq_type);
+g_assert(irqbit >= 0 && irqbit < 32);


I still think this assert is superfluous, anyway (and having hard time 
reading C99 statement before declarations - I need to grow):


Reviewed-by: Philippe Mathieu-Daudé 


+uint32_t irq = 1U << irqbit;
+uint32_t irqstat = d->port_regs.irq_stat | irq;
  
-d->port_regs.irq_stat |= irq_type;

+trace_ahci_trigger_irq(s, d->port_no,
+   AHCIPortIRQ_lookup[irqbit], irq,
+   d->port_regs.irq_stat, irqstat,
+   irqstat & d->port_regs.irq_mask);
+
+d->port_regs.irq_stat = irqstat;
  ahci_check_irq(s);
  }
  
@@ -718,7 +745,7 @@ static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs)
  
  /* Trigger IRQ if interrupt bit is set (which currently, it always is) */

  if (sdb_fis->flags & 0x40) {
-ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS);
+ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS);
  }
  }
  
@@ -761,10 +788,10 @@ static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len)

  ad->port.ifs[0].status;
  
  if (pio_fis[2] & ERR_STAT) {

-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
  }
  
-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS);

+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);
  }
  
  static bool ahci_write_fis_d2h(AHCIDevice *ad)

@@ -804,10 +831,10 @@ static bool ahci_write_fis_d2h(AHCIDevice *ad)
  ad->port.ifs[0].status;
  
  if (d2h_fis[2] & ERR_STAT) {

-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
  }
  
-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);

+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS);
  return true;
  }
  
@@ -1082,7 +1109,7 @@ static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,

   "is smaller than the requested size (0x%zx)",
   ncq_tfs->sglist.size, size);
  ncq_err(ncq_tfs);
-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW);
+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS);
  return;
  } else if (ncq_tfs->sglist.size != size) {
  trace_process_ncq_command_large(s, port, tag,
@@ -1225,7 +1252,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t 
slot)
  trace_handle_cmd_badfis(s, port);
  return -1;
  } else if (cmd_len != 0x80) {
-ahci_trigger_irq(s, >dev[port], PORT_IRQ_HBUS_ERR);
+ahci_trigger_irq(s, >dev[port], AHCI_PORT_IRQ_BIT_HBFS);

Re: [Qemu-devel] [PATCH 7/9] AHCI: Rework IRQ constants

[Philippe Mathieu-Daudé]

On 08/08/2017 03:33 PM, John Snow wrote:

Create a new enum so that we can name the IRQ bits, which will make
debugging
them a little nicer if we can print them out. Not handled in this
patch, but
this will make it possible to get a nice debug printf detailing
exactly which
status bits are set, as it can be multiple at any given time.

As a consequence of this patch, it is no longer possible to set
multiple IRQ
codes at once, but nothing was utilizing this ability anyway.

Signed-off-by: John Snow 
---
   hw/ide/ahci.c  | 49
++---
   hw/ide/ahci_internal.h | 44
+++-
   hw/ide/trace-events|  2 +-
   3 files changed, 74 insertions(+), 21 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index d5acceb..c5a9b69 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -56,6 +56,27 @@ static bool ahci_map_fis_address(AHCIDevice *ad);
   static void ahci_unmap_clb_address(AHCIDevice *ad);
   static void ahci_unmap_fis_address(AHCIDevice *ad);
   +static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__END] = {
+[AHCI_PORT_IRQ_BIT_DHRS] = "DHRS",
+[AHCI_PORT_IRQ_BIT_PSS]  = "PSS",
+[AHCI_PORT_IRQ_BIT_DSS]  = "DSS",
+[AHCI_PORT_IRQ_BIT_SDBS] = "SDBS",
+[AHCI_PORT_IRQ_BIT_UFS]  = "UFS",
+[AHCI_PORT_IRQ_BIT_DPS]  = "DPS",
+[AHCI_PORT_IRQ_BIT_PCS]  = "PCS",
+[AHCI_PORT_IRQ_BIT_DMPS] = "DMPS",
+[8 ... 21]   = "RESERVED",
+[AHCI_PORT_IRQ_BIT_PRCS] = "PRCS",
+[AHCI_PORT_IRQ_BIT_IPMS] = "IPMS",
+[AHCI_PORT_IRQ_BIT_OFS]  = "OFS",
+[25] = "RESERVED",
+[AHCI_PORT_IRQ_BIT_INFS] = "INFS",
+[AHCI_PORT_IRQ_BIT_IFS]  = "IFS",
+[AHCI_PORT_IRQ_BIT_HBDS] = "HBDS",
+[AHCI_PORT_IRQ_BIT_HBFS] = "HBFS",
+[AHCI_PORT_IRQ_BIT_TFES] = "TFES",
+[AHCI_PORT_IRQ_BIT_CPDS] = "CPDS"
+};
 static uint32_t  ahci_port_read(AHCIState *s, int port, int offset)
   {
@@ -170,12 +191,18 @@ static void ahci_check_irq(AHCIState *s)
   }
 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
- int irq_type)
+ enum AHCIPortIRQ irqbit)
   {
-DPRINTF(d->port_no, "trigger irq %#x -> %x\n",
-irq_type, d->port_regs.irq_mask & irq_type);
+g_assert(irqbit >= 0 && irqbit < 32);


Since you now use an enum this check is no more necessary.



You can actually still pass in a wrong value if you wanted to. This is
to prevent old-style IRQ masks from getting passed in by accident.


No accident :) This is now an enum, also:

hw/ide$ git grep ahci_trigger_irq
ahci.c:764:ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS);
ahci.c:807:ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
ahci.c:810:ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);
ahci.c:850:ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
ahci.c:853:ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS);
ahci.c:1128:ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS);
ahci.c:1276:ahci_trigger_irq(s, >dev[port], 
AHCI_PORT_IRQ_BIT_HBFS);


You only use enum values, not any cast.




However ...


+uint32_t irq = 1U << irqbit;
+uint32_t irqstat = d->port_regs.irq_stat | irq;
   -d->port_regs.irq_stat |= irq_type;
+trace_ahci_trigger_irq(s, d->port_no,
+   AHCIPortIRQ_lookup[irqbit], irq,
+   d->port_regs.irq_stat, irqstat,
+   irqstat & d->port_regs.irq_mask);
+


Why not keep using masked irqs, and iterate over AHCI_PORT_IRQ__END
bits? Something like:

 if (TRACE_AHCI_IRQ_ENABLED) {
 int irqbit;
 for (irqbit = 0; irqbit < AHCI_PORT_IRQ__END; irqbit++) {
 if (irqmask & BIT(irqbit)) {
 trace_ahci_trigger_irq(s, d->port_no, ...



Would rather not iterate like that for the IRQ path. Generally no place
in the codebase needs to raise more than one IRQ type at a time, so why
bother allowing it?


Indeed.

Re: [Qemu-devel] [PATCH 1/8] tcg: Add generic vector infrastructure and ops for add/sub/logic

[Philippe Mathieu-Daudé]

Hi Richard,

I can't find anything to say about this patch... Hardcore stuff.
Some part could be more a bit more verbose but after a while focusing it 
makes sens.

I wonder how long it took you to write this :) "roughly 2h"

On 08/17/2017 08:01 PM, Richard Henderson wrote:

Signed-off-by: Richard Henderson 


Hoping I didn't miss anything:

Reviewed-by: Philippe Mathieu-Daudé 


---
  Makefile.target|   5 +-
  tcg/tcg-op-gvec.h  |  88 ++
  tcg/tcg-runtime.h  |  16 ++
  tcg/tcg-op-gvec.c  | 443 +
  tcg/tcg-runtime-gvec.c | 199 ++
  5 files changed, 749 insertions(+), 2 deletions(-)
  create mode 100644 tcg/tcg-op-gvec.h
  create mode 100644 tcg/tcg-op-gvec.c
  create mode 100644 tcg/tcg-runtime-gvec.c

diff --git a/Makefile.target b/Makefile.target
index 7f42c45db8..9ae3e904f7 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -93,8 +93,9 @@ all: $(PROGS) stap
  # cpu emulator library
  obj-y += exec.o
  obj-y += accel/
-obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o
-obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/tcg-runtime.o
+obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-common.o tcg/optimize.o
+obj-$(CONFIG_TCG) += tcg/tcg-op.o tcg/tcg-op-gvec.o
+obj-$(CONFIG_TCG) += tcg/tcg-runtime.o tcg/tcg-runtime-gvec.o
  obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o
  obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o
  obj-y += fpu/softfloat.o
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
new file mode 100644
index 00..10db3599a5
--- /dev/null
+++ b/tcg/tcg-op-gvec.h
@@ -0,0 +1,88 @@
+/*
+ *  Generic vector operation expansion
+ *
+ *  Copyright (c) 2017 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+/*
+ * "Generic" vectors.  All operands are given as offsets from ENV,
+ * and therefore cannot also be allocated via tcg_global_mem_new_*.
+ * OPSZ is the byte size of the vector upon which the operation is performed.
+ * CLSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.
+ *
+ * All sizes must be 8 or any multiple of 16.
+ * When OPSZ is 8, the alignment may be 8, otherwise must be 16.
+ * Operands may completely, but not partially, overlap.
+ */
+
+/* Fundamental operation expanders.  These are exposed to the front ends
+   so that target-specific SIMD operations can be handled similarly to
+   the standard SIMD operations.  */
+
+typedef struct {
+/* "Small" sizes: expand inline as a 64-bit or 32-bit lane.
+   Generally only one of these will be non-NULL.  */
+void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
+void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
+/* Similarly, but load up a constant and re-use across lanes.  */
+void (*fni8x)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64);
+uint64_t extra_value;
+/* Larger sizes: expand out-of-line helper w/size descriptor.  */
+void (*fno)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+} GVecGen3;
+
+void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+uint32_t opsz, uint32_t clsz, const GVecGen3 *);
+
+#define DEF_GVEC_2(X) \
+void tcg_gen_gvec_##X(uint32_t dofs, uint32_t aofs, uint32_t bofs, \
+  uint32_t opsz, uint32_t clsz)
+
+DEF_GVEC_2(add8);
+DEF_GVEC_2(add16);
+DEF_GVEC_2(add32);
+DEF_GVEC_2(add64);
+
+DEF_GVEC_2(sub8);
+DEF_GVEC_2(sub16);
+DEF_GVEC_2(sub32);
+DEF_GVEC_2(sub64);
+
+DEF_GVEC_2(and8);
+DEF_GVEC_2(or8);
+DEF_GVEC_2(xor8);
+DEF_GVEC_2(andc8);
+DEF_GVEC_2(orc8);
+
+#undef DEF_GVEC_2
+
+/*
+ * 64-bit vector operations.  Use these when the register has been
+ * allocated with tcg_global_mem_new_i64.  OPSZ = CLSZ = 8.
+ */
+
+#define DEF_VEC8_2(X) \
+void tcg_gen_vec8_##X(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+
+DEF_VEC8_2(add8);
+DEF_VEC8_2(add16);
+DEF_VEC8_2(add32);
+
+DEF_VEC8_2(sub8);
+DEF_VEC8_2(sub16);
+DEF_VEC8_2(sub32);
+
+#undef DEF_VEC8_2
diff --git a/tcg/tcg-runtime.h b/tcg/tcg-runtime.h
index c41d38a557..f8d07090f8 100644
--- a/tcg/tcg-runtime.h
+++ b/tcg/tcg-runtime.h
@@ -134,3 +134,19 @@ GEN_ATOMIC_HELPERS(xor_fetch)
  GEN_ATOMIC_HELPERS(xchg)
  
  #undef GEN_ATOMIC_HELPERS

+
+DEF_HELPER_FLAGS_4(gvec_add8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

Re: [Qemu-devel] [PATCH v2 5/9] IDE: replace DEBUG_AIO with trace events

[Philippe Mathieu-Daudé]

Hi John,

On 08/29/2017 05:49 PM, John Snow wrote:

Signed-off-by: John Snow 
---
  hw/ide/atapi.c|  5 +
  hw/ide/core.c | 17 ++---
  hw/ide/trace-events   |  3 +++
  include/hw/ide/internal.h |  6 --
  4 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c
index 37fa699..b8fc51e 100644
--- a/hw/ide/atapi.c
+++ b/hw/ide/atapi.c
@@ -416,10 +416,7 @@ static void ide_atapi_cmd_read_dma_cb(void *opaque, int 
ret)
  s->io_buffer_size = n * 2048;
  data_offset = 0;
  }
-#ifdef DEBUG_AIO
-printf("aio_read_cd: lba=%u n=%d\n", s->lba, n);
-#endif
-
+trace_ide_atapi_cmd_read_dma_cb_aio(s, s->lba, n);
  s->bus->dma->iov.iov_base = (void *)(s->io_buffer + data_offset);
  s->bus->dma->iov.iov_len = n * ATAPI_SECTOR_SIZE;
  qemu_iovec_init_external(>bus->dma->qiov, >bus->dma->iov, 1);
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 82a19b1..a1c90e9 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -58,6 +58,13 @@ static const int smart_attributes[][12] = {
  { 190,  0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
  };
  
+const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT] = {

+[IDE_DMA_READ] = "DMA READ",
+[IDE_DMA_WRITE] = "DMA WRITE",
+[IDE_DMA_TRIM] = "DMA TRIM",
+[IDE_DMA_ATAPI] = "DMA ATAPI"
+};
+
  static void ide_dummy_transfer_stop(IDEState *s);
  
  static void padstr(char *str, const char *src, int len)

@@ -860,10 +867,8 @@ static void ide_dma_cb(void *opaque, int ret)
  goto eot;
  }
  
-#ifdef DEBUG_AIO

-printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
-   sector_num, n, s->dma_cmd);
-#endif
+trace_ide_dma_cb(s, sector_num, n,
+ IDE_DMA_CMD_lookup[s->dma_cmd]);
  
  if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&

  !ide_sect_range_ok(s, sector_num, n)) {
@@ -2391,9 +2396,7 @@ void ide_bus_reset(IDEBus *bus)
  
  /* pending async DMA */

  if (bus->dma->aiocb) {
-#ifdef DEBUG_AIO
-printf("aio_cancel\n");
-#endif
+trace_ide_bus_reset_aio();
  blk_aio_cancel(bus->dma->aiocb);
  bus->dma->aiocb = NULL;
  }
diff --git a/hw/ide/trace-events b/hw/ide/trace-events
index 8c79a6c..cc8949c 100644
--- a/hw/ide/trace-events
+++ b/hw/ide/trace-events
@@ -18,6 +18,8 @@ ide_cancel_dma_sync_remaining(void) "draining all remaining 
requests"
  ide_sector_read(int64_t sector_num, int nsectors) "sector=%"PRId64" 
nsectors=%d"
  ide_sector_write(int64_t sector_num, int nsectors) "sector=%"PRId64" 
nsectors=%d"
  ide_reset(void *s) "IDEstate %p"
+ide_bus_reset_aio(void) "aio_cancel"
+ide_dma_cb(void *s, int64_t sector_num, int n, const char *dma) "IDEState %p; 
sector_num=%"PRId64" n=%d cmd=%s"
  
  # BMDMA HBAs:
  
@@ -51,5 +53,6 @@ ide_atapi_cmd_reply_end_new(void *s, int status) "IDEState: %p; new transfer sta

  ide_atapi_cmd_check_status(void *s) "IDEState: %p"
  ide_atapi_cmd_read(void *s, const char *method, int lba, int nb_sectors) 
"IDEState: %p; read %s: LBA=%d nb_sectors=%d"
  ide_atapi_cmd(void *s, uint8_t cmd) "IDEState: %p; cmd: 0x%02x"
+ide_atapi_cmd_read_dma_cb_aio(void *s, int lba, int n) "IDEState: %p; aio read: 
lba=%d n=%d"
  # Warning: Verbose
  ide_atapi_cmd_packet(void *s, uint16_t limit, const char *packet) "IDEState: %p; 
limit=0x%x packet: %s"
diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
index 74efe8a..db9fde0 100644
--- a/include/hw/ide/internal.h
+++ b/include/hw/ide/internal.h
@@ -14,7 +14,6 @@
  #include "block/scsi.h"
  
  /* debug IDE devices */

-//#define DEBUG_AIO
  #define USE_DMA_CDROM
  
  typedef struct IDEBus IDEBus;

@@ -333,12 +332,15 @@ struct unreported_events {
  };
  
  enum ide_dma_cmd {

-IDE_DMA_READ,
+IDE_DMA_READ = 0,
  IDE_DMA_WRITE,
  IDE_DMA_TRIM,
  IDE_DMA_ATAPI,
+IDE_DMA__COUNT
  };
  
+extern const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT];


I recommend you to avoid this declaring extern const array with size, I 
remember some compilers (old GCC?) ignoring array size in extern. Eric 
will correct me!


It is much safer to use a getter:

const char *IDE_DMA_CMD_lookup(enum ide_dma_cmd cmd)
{
static const char *IDE_DMA_CMD_name[IDE_DMA__COUNT] = {
[IDE_DMA_READ] = "DMA READ",
[IDE_DMA_WRITE] = "DMA WRITE",
[IDE_DMA_TRIM] = "DMA TRIM",
[IDE_DMA_ATAPI] = "DMA ATAPI"
};

return IDE_DMA_CMD_name[cmd];
};

If you agree:
Reviewed-by: Philippe Mathieu-Daudé 


+
  #define ide_cmd_is_read(s) \
((s)->dma_cmd == IDE_DMA_READ)
  

Re: [Qemu-devel] [PATCH 1/8] tcg/s390: Fully convert tcg_target_op_def

[Philippe Mathieu-Daudé]

On 08/29/2017 05:47 PM, Richard Henderson wrote:

From: Richard Henderson 

Use a switch instead of searching a table.

Signed-off-by: Richard Henderson 


Reviewed-by: Philippe Mathieu-Daudé 


---
  tcg/s390/tcg-target.inc.c | 278 +-
  1 file changed, 154 insertions(+), 124 deletions(-)

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 5d7083e90c..d34649eb13 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -2246,134 +2246,164 @@ static inline void tcg_out_op(TCGContext *s, 
TCGOpcode opc,
  }
  }
  
-static const TCGTargetOpDef s390_op_defs[] = {

-{ INDEX_op_exit_tb, { } },
-{ INDEX_op_goto_tb, { } },
-{ INDEX_op_br, { } },
-{ INDEX_op_goto_ptr, { "r" } },
-
-{ INDEX_op_ld8u_i32, { "r", "r" } },
-{ INDEX_op_ld8s_i32, { "r", "r" } },
-{ INDEX_op_ld16u_i32, { "r", "r" } },
-{ INDEX_op_ld16s_i32, { "r", "r" } },
-{ INDEX_op_ld_i32, { "r", "r" } },
-{ INDEX_op_st8_i32, { "r", "r" } },
-{ INDEX_op_st16_i32, { "r", "r" } },
-{ INDEX_op_st_i32, { "r", "r" } },
-
-{ INDEX_op_add_i32, { "r", "r", "ri" } },
-{ INDEX_op_sub_i32, { "r", "0", "ri" } },
-{ INDEX_op_mul_i32, { "r", "0", "rK" } },
-
-{ INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } },
-{ INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } },
-
-{ INDEX_op_and_i32, { "r", "0", "ri" } },
-{ INDEX_op_or_i32, { "r", "0", "rO" } },
-{ INDEX_op_xor_i32, { "r", "0", "rX" } },
-
-{ INDEX_op_neg_i32, { "r", "r" } },
-
-{ INDEX_op_shl_i32, { "r", "0", "ri" } },
-{ INDEX_op_shr_i32, { "r", "0", "ri" } },
-{ INDEX_op_sar_i32, { "r", "0", "ri" } },
-
-{ INDEX_op_rotl_i32, { "r", "r", "ri" } },
-{ INDEX_op_rotr_i32, { "r", "r", "ri" } },
-
-{ INDEX_op_ext8s_i32, { "r", "r" } },
-{ INDEX_op_ext8u_i32, { "r", "r" } },
-{ INDEX_op_ext16s_i32, { "r", "r" } },
-{ INDEX_op_ext16u_i32, { "r", "r" } },
-
-{ INDEX_op_bswap16_i32, { "r", "r" } },
-{ INDEX_op_bswap32_i32, { "r", "r" } },
-
-{ INDEX_op_add2_i32, { "r", "r", "0", "1", "rA", "r" } },
-{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "rA", "r" } },
-
-{ INDEX_op_brcond_i32, { "r", "rC" } },
-{ INDEX_op_setcond_i32, { "r", "r", "rC" } },
-{ INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } },
-{ INDEX_op_deposit_i32, { "r", "rZ", "r" } },
-{ INDEX_op_extract_i32, { "r", "r" } },
-
-{ INDEX_op_qemu_ld_i32, { "r", "L" } },
-{ INDEX_op_qemu_ld_i64, { "r", "L" } },
-{ INDEX_op_qemu_st_i32, { "L", "L" } },
-{ INDEX_op_qemu_st_i64, { "L", "L" } },
-
-{ INDEX_op_ld8u_i64, { "r", "r" } },
-{ INDEX_op_ld8s_i64, { "r", "r" } },
-{ INDEX_op_ld16u_i64, { "r", "r" } },
-{ INDEX_op_ld16s_i64, { "r", "r" } },
-{ INDEX_op_ld32u_i64, { "r", "r" } },
-{ INDEX_op_ld32s_i64, { "r", "r" } },
-{ INDEX_op_ld_i64, { "r", "r" } },
-
-{ INDEX_op_st8_i64, { "r", "r" } },
-{ INDEX_op_st16_i64, { "r", "r" } },
-{ INDEX_op_st32_i64, { "r", "r" } },
-{ INDEX_op_st_i64, { "r", "r" } },
-
-{ INDEX_op_add_i64, { "r", "r", "ri" } },
-{ INDEX_op_sub_i64, { "r", "0", "ri" } },
-{ INDEX_op_mul_i64, { "r", "0", "rK" } },
-
-{ INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } },
-{ INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } },
-{ INDEX_op_mulu2_i64, { "b", "a", "0", "r" } },
-
-{ INDEX_op_and_i64, { "r", "0", "ri" } },
-{ INDEX_op_or_i64, { "r", "0", "rO" } },
-{ INDEX_op_xor_i64, { "r", "0", "rX" } },
-
-{ INDEX_op_neg_i64, { "r", "r" } },
-
-{ INDEX_op_shl_i64, { "r", "r", "ri" } },
-{ INDEX_op_shr_i64, { "r", "r", "ri" } },
-{ INDEX_op_sar_i64, { "r", "r", "ri" } },
-
-{ INDEX_op_rotl_i64, { "r", "r", "ri" } },
-{ INDEX_op_rotr_i64, { "r", "r", "ri" } },
-
-{ INDEX_op_ext8s_i64, { "r", "r" } },
-{ INDEX_op_ext8u_i64, { "r", "r" } },
-{ INDEX_op_ext16s_i64, { "r", "r" } },
-{ INDEX_op_ext16u_i64, { "r", "r" } },
-{ INDEX_op_ext32s_i64, { "r", "r" } },
-{ INDEX_op_ext32u_i64, { "r", "r" } },
-
-{ INDEX_op_ext_i32_i64, { "r", "r" } },
-{ INDEX_op_extu_i32_i64, { "r", "r" } },
-
-{ INDEX_op_bswap16_i64, { "r", "r" } },
-{ INDEX_op_bswap32_i64, { "r", "r" } },
-{ INDEX_op_bswap64_i64, { "r", "r" } },
-
-{ INDEX_op_clz_i64, { "r", "r", "ri" } },
-
-{ INDEX_op_add2_i64, { "r", "r", "0", "1", "rA", "r" } },
-{ INDEX_op_sub2_i64, { "r", "r", "0", "1", "rA", "r" } },
-
-{ INDEX_op_brcond_i64, { "r", "rC" } },
-{ INDEX_op_setcond_i64, { "r", "r", "rC" } },
-{ INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
-{ INDEX_op_deposit_i64, { "r", "0", "r" } },
-{ INDEX_op_extract_i64, { "r", "r" } },
-
-{ INDEX_op_mb, { } },
-{ -1 },
-};
-
  static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
  {
-int i, n = ARRAY_SIZE(s390_op_defs);
+static const 

Re: [Qemu-devel] [PATCH] oslib-posix: Print errors before aborting on qemu_alloc_stack()

[Philippe Mathieu-Daudé]

On 08/29/2017 06:20 PM, Eduardo Habkost wrote:

If QEMU is running on a system that's out of memory and mmap()
fails, QEMU aborts with no error message at all, making it hard
to debug the reason for the failure.

Add perror() calls that will print error information before
aborting.

Signed-off-by: Eduardo Habkost 


Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 


---
  util/oslib-posix.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index cacf0ef..80086c5 100644
--- a/util/oslib-posix.c
+++ b/util/oslib-posix.c
@@ -530,6 +530,7 @@ void *qemu_alloc_stack(size_t *sz)
  ptr = mmap(NULL, *sz, PROT_READ | PROT_WRITE,
 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
  if (ptr == MAP_FAILED) {
+perror("failed to allocate memory for stack");
  abort();
  }
  
@@ -544,6 +545,7 @@ void *qemu_alloc_stack(size_t *sz)

  guardpage = ptr;
  #endif
  if (mprotect(guardpage, pagesz, PROT_NONE) != 0) {
+perror("failed to set up stack guard page");
  abort();
  }
  

Re: [Qemu-devel] [PATCH v4 03/10] tests: Add vm test lib

[Fam Zheng]

On Tue, 08/29 14:34, Philippe Mathieu-Daudé wrote:
> > +self._args = [ \
> > +"-nodefaults", "-m", "2G",
> > +"-cpu", "host",
> > +"-netdev", "user,id=vnet,hostfwd=:0.0.0.0:0-:22",
> > +"-device", "virtio-net-pci,netdev=vnet",
> > +"-vnc", ":0,to=20",
> > +"-serial", "file:%s" % os.path.join(self._tmpdir, 
> > "serial.out")]
> > +if vcpus:
> > +self._args += ["-smp", str(vcpus)]
> 
> What about enabling mttcg which isn't default?
> 
> self._args += ["--accel", "tcg,thread=multi"]

Any specific reason to enable it? I think it is not available on older QEMU.

> 
> > +if os.access("/dev/kvm", os.R_OK | os.W_OK):
> > +self._args += ["-enable-kvm"]
> > +else:
> > +logging.info("KVM not available, not using -enable-kvm")
> > +self._data_args = []
> [...]

Fam

Re: [Qemu-devel] [PATCH v4 06/10] tests: Add NetBSD image

[Fam Zheng]

On Tue, 08/29 18:47, Philippe Mathieu-Daudé wrote:
> Hi Fam,
> 
> On 08/29/2017 09:09 AM, Philippe Mathieu-Daudé wrote:
> [...]>> +if __name__ == "__main__":
> > > +    sys.exit(basevm.main(NetBSDVM))
> > 
> > This one is failing:
> > 
> > DEBUG:root:ssh_cmd: ssh -q -o StrictHostKeyChecking=no -o
> > UserKnownHostsFile=/dev/null -o ConnectTimeout=1 -p 34091 -i
> > /tmp/qemu-vm-59XYOj/id_rsa qemu@127.0.0.1
> >      set -e;
> >      cd $(mktemp -d /var/tmp/qemu-test.XX);
> >      tar -xf /dev/rld1a;
> >      ./configure --python=python2.7 ;
> >      gmake -j4;
> >      gmake check;
> > 
> > ...
> >    CC  bt-host.o
> >    CC  bt-vhci.o
> >    CC  dma-helpers.o
> >    CC  vl.o
> >    CC  tpm.o
> > In file included from vl.c:72:0:
> > /var/tmp/qemu-test.ht0XHU/include/hw/loader.h:4:29: fatal error:
> > hw/nvram/fw_cfg.h: No such file or directory
> >   #include "hw/nvram/fw_cfg.h"
> >   ^
> > compilation terminated.
> > /var/tmp/qemu-test.ht0XHU/rules.mak:66: recipe for target 'vl.o' failed
> > gmake: *** [vl.o] Error 1
> > gmake: *** Waiting for unfinished jobs
> > tests/vm/Makefile.include:32: recipe for target 'vm-build-netbsd' failed
> > make: *** [vm-build-netbsd] Error 3
> 
> Probably false alarm, this seems to be an ENOMEM host error.
> 
> I later got:
> 
>   CHK version_gen.h
> Makefile:342: recipe for target 'subdir-dtc' failed
> gmake[1]: *** No rule to make target 'dtc/libfdt/fdt.h', needed by
> 'libfdt/fdt.o'.  Stop.
> gmake: *** [subdir-dtc] Error 2
> gmake: *** Waiting for unfinished jobs
> 
> which I solved running "gmake -C dtc" after ./configure but I'm not sure it
> is necessary or can come from my tree, this testing is veeery slow and
> mostly kill my laptop, I ended wondering on what kind of hardware you
> developed this series without going crazy nut :S

Not too beefy, just a Lenovo W541 laptop with i7-4810. To save you from being
killed again, maybe we should reduce the default -smp to nr_cores / 2?

Fam

Re: [Qemu-devel] [PATCH v4 03/10] tests: Add vm test lib

[Fam Zheng]

On Tue, 08/29 09:15, Philippe Mathieu-Daudé wrote:
> > +self._args = [ \
> > +"-nodefaults", "-m", "2G",
> > +"-cpu", "host",
> > +"-netdev", "user,id=vnet,hostfwd=:0.0.0.0:0-:22",
> 
> Testing with debian/unstable:
> 
> $ make vm-build-netbsd V=1
> ./tests/vm/netbsd  --debug   --image "tests/vm/netbsd.img" --build-qemu .
> DEBUG:root:Creating archive /tmp/qemu-vm-PxfXNv/data-3a52c.tar for data dir:
> .
> DEBUG:root:QEMU args: -nodefaults -m 2G -cpu host -netdev
> user,id=vnet,hostfwd=:0.0.0.0:0-:22 -device virtio-net-pci,netdev=vnet -vnc
> :0,to=20 -serial file:/tmp/qemu-vm-PxfXNv/serial.out -smp 4 -enable-kvm
> -device VGA -drive
> file=tests/vm/netbsd.img,snapshot=on,if=none,id=drive0,cache=writeback
> -device virtio-blk,drive=drive0,bootindex=0 -drive 
> file=/tmp/qemu-vm-PxfXNv/data-3a52c.tar,if=none,id=data-3a52c,cache=writeback,format=raw
> -device virtio-blk,drive=data-3a52c,serial=data-3a52c,bootindex=1
> Failed to prepare guest environment

Can you please look into the stderr of the QEMU command line to see what
arguments went wrong? (I hope the qemu.py improvement patches on the list can
give a better error message in such cases.)

Fam

Re: [Qemu-devel] [PATCH v4 03/10] tests: Add vm test lib

[Fam Zheng]

On Tue, 08/29 13:11, Daniel P. Berrange wrote:
> On Tue, Aug 29, 2017 at 09:06:48AM -0300, Philippe Mathieu-Daudé wrote:
> > Hi Fam,
> > 
> > On 08/28/2017 02:47 PM, Fam Zheng wrote:
> > > This is the common code to implement a "VM test" to
> > > 
> > >1) Download and initialize a pre-defined VM that has necessary
> > >dependencies to build QEMU and SSH access.
> > > 
> > >2) Archive $SRC_PATH to a .tar file.
> > > 
> > >3) Boot the VM, and pass the source tar file to the guest.
> > > 
> > >4) SSH into the VM, untar the source tarball, build from the source.
> > > 
> > > Signed-off-by: Fam Zheng 
> > > ---
> > >   tests/vm/basevm.py | 287 
> > > +
> > >   1 file changed, 287 insertions(+)
> > >   create mode 100755 tests/vm/basevm.py
> > > 
> > > diff --git a/tests/vm/basevm.py b/tests/vm/basevm.py
> > > new file mode 100755
> > > index 00..d0095c5332
> > > --- /dev/null
> > > +++ b/tests/vm/basevm.py
> 
> > > +def add_source_dir(self, data_dir):
> > > +name = "data-" + hashlib.sha1(data_dir).hexdigest()[:5]
> > > +tarfile = os.path.join(self._tmpdir, name + ".tar")
> > > +logging.debug("Creating archive %s for data dir: %s", tarfile, 
> > > data_dir)
> > > +if subprocess.call("type gtar", stdout=self._devnull,
> > > +   stderr=self._devnull, shell=True) == 0:
> > > +tar_cmd = "gtar"
> > > +else:
> > > +tar_cmd = "tar"
> > > +subprocess.check_call([tar_cmd,
> > > +   "--exclude-vcs",
> > > +   "--exclude=tests/vm/*.img",
> > > +   "--exclude=tests/vm/*.img.*",
> > > +   "--exclude=*.d",
> > > +   "--exclude=*.o",
> > > +   "--exclude=docker-src.*",
> > > +   "-cf", tarfile, '.'], cwd=data_dir,
> > 
> > I'm not happy with this command :/
> > My distrib uses tmpfs for /tmp and suddently the whole X window became
> > irresponsive until this script failing after filling 8G of /tmp and swap:
> > 
> > ...
> > DEBUG:root:Creating archive /tmp/qemu-vm-F7CY9O/data-3a52c.tar for data dir:
> > .
> > tar: /tmp/qemu-vm-F7CY9O/data-3a52c.tar: Wrote only 4096 of 10240 bytes
> > tar: Error is not recoverable: exiting now
> > Failed to prepare guest environment
> > 
> > Then I figured out my workdir is full of testing stuff, debug images,
> > firmwares, coredumps, etc.
> > 
> > I'll think of another way.
> 
> Yeah, /tmp should never be used for anything which has significant
> size. Could go for /var/tmp instead, but IMHO just use the QEMU build
> dir, as is done for (almost) all other build & test artifacts and
> thus avoid any global dirs.

Thanks, I'll fix it. Using current dir would be fine.

Fam

> 
> 
> Regards,
> Daniel
> -- 
> |: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
> |: https://libvirt.org -o-https://fstop138.berrange.com :|
> |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PATCH for-2.11 4/6] ppc: replace inter-function cyclic dependency/recurssion with 2 simple lookups

[David Gibson]

On Fri, Aug 25, 2017 at 09:34:32AM +0200, Igor Mammedov wrote:
> On Fri, 25 Aug 2017 14:12:08 +1000
> David Gibson  wrote:
> 
> > On Thu, Aug 24, 2017 at 10:21:49AM +0200, Igor Mammedov wrote:
> > > previous patches cleaned up cpu model/alias naming which
> > > allows to simplify cpu model/alias to cpu type lookup a bit
> > > byt removing recurssion and dependency of ppc_cpu_class_by_name() /
> > > ppc_cpu_class_by_alias() on each other.
> > > Besides of simplifying code it reduces it by ~15LOC.
> > > 
> > > Signed-off-by: Igor Mammedov   
> > 
> > Urm.. I think this is probably good.  But I'm having a little trouble
> > convincing myself this really has the same effect as before.
> It's hard to wrap brain around current cyclic recursion and
> how to 2 simple linear lookups could replace it.

I noticed :)

> By itself this patch won't work, it depends on 2-3/6 for
> normalized cpu type names and recursion-less alias table.
> 
> The only change in behavior here is that it does alias
> translation first and only then cpu_model to type translation.

I've had a closer look and convinced myself of that now.

Reviewed-by: David Gibson 

I'm sorry, I've lost track of these patches a bit, since I wasn't
originally expecting to queue them.  I can't actually remember if
there were any comments needing a respin.

Regardless, can you resend the series (including my R-bs) and I'll
queue it for 2.11.

> 
> > 
> > > ---
> > >  target/ppc/translate_init.c | 43 
> > > +--
> > >  1 file changed, 13 insertions(+), 30 deletions(-)
> > > 
> > > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> > > index 0325226..f1a559d 100644
> > > --- a/target/ppc/translate_init.c
> > > +++ b/target/ppc/translate_init.c
> > > @@ -10176,22 +10176,6 @@ PowerPCCPUClass 
> > > *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
> > >  return pcc;
> > >  }
> > >  
> > > -static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
> > > -{
> > > -ObjectClass *oc = (ObjectClass *)a;
> > > -const char *name = b;
> > > -PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> > > -
> > > -if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 
> > > &&
> > > -ppc_cpu_is_valid(pcc) &&
> > > -strcmp(object_class_get_name(oc) + strlen(name),
> > > -   POWERPC_CPU_TYPE_SUFFIX) == 0) {
> > > -return 0;
> > > -}
> > > -return -1;
> > > -}
> > > -
> > > -
> > >  static ObjectClass *ppc_cpu_class_by_name(const char *name);
> > >  
> > >  static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
> > > @@ -10216,8 +10200,8 @@ static ObjectClass 
> > > *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
> > >  
> > >  static ObjectClass *ppc_cpu_class_by_name(const char *name)
> > >  {
> > > -GSList *list, *item;
> > > -ObjectClass *ret = NULL;
> > > +char *cpu_model, *typename;
> > > +ObjectClass *oc;
> > >  const char *p;
> > >  int i, len;
> > >  
> > > @@ -10238,21 +10222,20 @@ static ObjectClass *ppc_cpu_class_by_name(const 
> > > char *name)
> > >  }
> > >  }
> > >  
> > > -list = object_class_get_list(TYPE_POWERPC_CPU, false);
> > > -item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
> > > -if (item != NULL) {
> > > -ret = OBJECT_CLASS(item->data);
> > > +cpu_model = g_ascii_strup(name, -1);
> > > +p = ppc_cpu_lookup_alias(cpu_model);
> > > +if (p) {
> > > +g_free(cpu_model);
> > > +cpu_model = g_strdup(p);
> > >  }
> > > -g_slist_free(list);
> > >  
> > > -if (ret) {
> > > -return ret;
> > > -}
> > > +typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
> > > +oc = object_class_by_name(typename);
> > > +g_free(typename);
> > > +g_free(cpu_model);
> > >  
> > > -for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
> > > -if (strcasecmp(ppc_cpu_aliases[i].alias, name) == 0) {
> > > -return ppc_cpu_class_by_alias(_cpu_aliases[i]);
> > > -}
> > > +if (oc && ppc_cpu_is_valid(POWERPC_CPU_CLASS(oc))) {
> > > +return oc;
> > >  }
> > >  
> > >  return NULL;  
> > 
> 

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH for-2.11] tests: Fix broken ivshmem-server-msi/-irq tests

[David Gibson]

On Tue, Aug 29, 2017 at 08:13:36PM +0200, Thomas Huth wrote:
> Broken with commit b4ba67d9a7025 ("libqos: Change PCI accessors to take
> opaque BAR handle") a while ago, but nobody noticed since the tests are
> only run in SPEED=slow mode: The msix_pba_bar is not correctly initialized
> anymore if bir_pba has the same value as bir_table. With this fix,
> "make check SPEED=slow" should work fine again.
> 
> Fixes: b4ba67d9a702507793c2724e56f98e9b0f7be02b
> Signed-off-by: Thomas Huth 

Reviewed-by: David Gibson 

> ---
>  tests/libqos/pci.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c
> index 2dcdead..28d576c 100644
> --- a/tests/libqos/pci.c
> +++ b/tests/libqos/pci.c
> @@ -120,6 +120,8 @@ void qpci_msix_enable(QPCIDevice *dev)
>  bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
>  if (bir_pba != bir_table) {
>  dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL);
> +} else {
> +dev->msix_pba_bar = dev->msix_table_bar;
>  }
>  dev->msix_pba_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
>  
> @@ -138,8 +140,11 @@ void qpci_msix_disable(QPCIDevice *dev)
>  qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
>  val & 
> ~PCI_MSIX_FLAGS_ENABLE);
>  
> +if (dev->msix_pba_bar.addr != dev->msix_table_bar.addr) {
> +qpci_iounmap(dev, dev->msix_pba_bar);
> +}
>  qpci_iounmap(dev, dev->msix_table_bar);
> -qpci_iounmap(dev, dev->msix_pba_bar);
> +
>  dev->msix_enabled = 0;
>  dev->msix_table_off = 0;
>  dev->msix_pba_off = 0;

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [Qemu-ppc] [PATCH for-2.11 v2] hw/ppc: CAS reset on early device hotplug

[David Gibson]

On Tue, Aug 29, 2017 at 05:54:28PM -0300, Daniel Henrique Barboza wrote:
> 
> 
> On 08/29/2017 04:23 AM, David Gibson wrote:
> > On Fri, Aug 25, 2017 at 06:11:18PM -0300, Daniel Henrique Barboza wrote:
> > > v2:
> > > - rebased with ppc-for-2.11
> > > - function 'spapr_cas_completed' dropped
> > > - function 'spapr_drc_needed' made public and it's now used inside
> > >'spapr_hotplugged_dev_before_cas'
> > > - 'spapr_drc_needed' was changed to support the migration of logical
> > >DRCs with devs attached in UNUSED state
> > > - new function: 'spapr_clear_pending_events'. This function is used
> > >inside ppc_spapr_reset to reset the pending_events QTAILQ
> > Thanks for the followup, unfortunately there is still an important bug
> > left, see comments on the patch itself.
> > 
> > At a higher level, though, looking at the event reset code made me
> > think of a possible even simpler solution to this problem.
> > 
> > The queue of events (both hotplug and epow) is already in a simple
> > internal form that's independent of the two delivery mechanisms.  The
> > only difference is what event source triggers the interrupt.  This
> > explains why an extra hotplug event after the CAS "unstuck" the queue.
> > 
> > AFAICT, a spurious interrupts here should be harmless - the kernel
> > will just check the queue and find nothing there.
> > 
> > So, it should be sufficient to, after CAS, pulse the hotplug queue
> > interrupt if the hotplug queue is negotiated.
> > 
> This is something I've tried in my first attempts at this problem, before
> sending the first patch in which I blocked hotplug before CAS. Back then,
> the problem was that the kernel panics with sig 11 (acess of bad area) when
> receiving the pulse after CAS.

Huh.

> I've investigated it a bit today and it seems that it still the case. Firing
> an IRQ right
> after CAS breaks the kernel. In fact, if you time a regular CPU hotplug
> right after
> CAS you'll get the same sig 11 kernel ooops. It looks like there is a time
> window after
> CAS that the kernel can't handle the hotplug process and pulsing the hotplug
> queue in this window breaks the guest. I've tried some hacks such as pulsing
> the queue
> in the first 'event_scan' call made by the guest, but apparently it is still
> too early.
> 
> I've sent an email to the linuxppc-dev mailing list talking about this
> behavior
> and asking if there is a reliable way to know when  we can safely pulse the
> hotplug
> queue. Meanwhile, I'll keep working in the v3 respin of this patch in case
> this
> solution of pulsing the hotplug queue ends up being not feasible.

Right.  As Ben's reply says that definitely looks like a guest kernel
bug.  But, it's in enough kernels in the wild that we really need to
work around it anyway.  I think the reset-at-CAS approach is our best
bet to accomplish that at this stage.

Note that the clear-queue-at-reset preliminary cleanup will be
valuable even if we end up not needing the rest of the reset at CAS
stuff.

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH V4 0/3] Optimize COLO-compare performance

[Jason Wang]

On 2017年08月29日 18:45, Fam Zheng wrote:

On Tue, 08/29 17:01, Jason Wang wrote:


On 2017年08月22日 15:16, no-re...@patchew.org wrote:

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1503305719-2512-1-git-send-email-zhangchen.f...@cn.fujitsu.com
Subject: [Qemu-devel] [PATCH V4 0/3] Optimize COLO-compare performance

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
  echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
  if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; 
then
  failed=1
  echo
  fi
  n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
37052358b5 net/colo-compare.c: Fix comments and scheme
46824a6565 net/colo-compare.c: Adjust net queue pop order for performance
acea048383 net/colo-compare.c: Optimize unpredictable tcp options comparison

=== OUTPUT BEGIN ===
Checking PATCH 1/3: net/colo-compare.c: Optimize unpredictable tcp options 
comparison...
Checking PATCH 2/3: net/colo-compare.c: Adjust net queue pop order for 
performance...
Checking PATCH 3/3: net/colo-compare.c: Fix comments and scheme...
ERROR: space prohibited after that '-' (ctx:WxW)
#18: FILE: net/colo-compare.c:47:
+  |   conn list   + - >  conn + --- >  conn + -- > ...
   ^

ERROR: space prohibited after that '-' (ctx:OxW)
#18: FILE: net/colo-compare.c:47:
+  |   conn list   + - >  conn + --- >  conn + -- > ...
 ^

ERROR: space required one side of that '--' (ctx:WxW)
#18: FILE: net/colo-compare.c:47:
+  |   conn list   + - >  conn + --- >  conn + -- > ...
 ^

total: 3 errors, 0 warnings, 40 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-de...@freelists.org

Fam, this looks like a false positive since it was actually an ascii graph
inside a comment?


Yes, let's just ignore this report.

Fam


Thanks.

I've queued this series.

Re: [Qemu-devel] [PATCH] spapr: Add ibm, processor-storage-keys property to CPU DT node

[David Gibson]

On Tue, Aug 29, 2017 at 09:31:07AM -0700, Ram Pai wrote:
> On Tue, Aug 29, 2017 at 11:40:30AM +1000, David Gibson wrote:
> > On Mon, Aug 28, 2017 at 10:53:56AM -0700, Ram Pai wrote:
> > > On Thu, Aug 24, 2017 at 12:54:48PM +1000, Paul Mackerras wrote:
> > > > 
> > > > We could either have two u16 fields for the number of keys for data
> > > > and instruction, or we could have a u32 field for the number of keys
> > > > and a separate bit in the flags field to indicate that instruction
> > > > keys are supported.  Which would be preferable?
> > > 
> > > the second choice is more confusion-proof; to me atleast.
> > > 
> > > The first choice gives a illusion that there are 'x' number of data keys
> > > and 'y' number of instruction keys; which is not exactly true.
> > 
> > Ah.. can you elaborate?
> 
> On power8 and power9, there are only 32 keys, each key can be configured to
> disable data-access and instruction-access.  The first choice, will
> report 32 keys for data-access and 32 keys for instruction-access. To a
> casual on-looker it gives an impresssion that there are 32 keys for
> data-access and 32 keys for instruction-access; 64 keys in total. And
> that is what I think can be the cause for confusion.

Ah, I see.

Paul, sorry, I hadn't realized the above when I said I preferred
separate values for data and instr keys.  In view of the above, I
change my preference to a single # of keys and a flag that they can be
used for instructions.

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH] qom: Remove unused errp parameter from can_be_deleted()

[Gonglei (Arei)]

> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Wednesday, August 30, 2017 6:04 AM
> To: qemu-devel@nongnu.org
> Cc: Gonglei (Arei); Paolo Bonzini; Igor Mammedov; Andreas Färber; Lin Ma
> Subject: [PATCH] qom: Remove unused errp parameter from can_be_deleted()
> 
> The errp argument is ignored by all implementations of the
> method, and user_creatable_del() would break if any
> implementation set an error (because it calls error_setg(errp) if
> the function returns false).  Remove the unused parameter.
> 
> Signed-off-by: Eduardo Habkost 
> ---
>  include/qom/object_interfaces.h | 5 ++---
>  backends/cryptodev.c| 2 +-
>  backends/hostmem.c  | 2 +-
>  qom/object_interfaces.c | 6 +++---
>  4 files changed, 7 insertions(+), 8 deletions(-)
> 

Reviewed-by: Gonglei 

[Qemu-devel] [Bug 1713825] [NEW] Booting Windows 2016 with qxl video crashes qemu

[Maciej Piechotka]

Public bug reported:

launched from libvirt.

qemu version: 2.9.0
host: Linux  4.9.34-gentoo #1 SMP Sat Jul 29 13:28:43 PDT 2017 x86_64 
Intel(R) Core(TM) i7-3930K CPU @ 3.20GHz GenuineIntel GNU/Linux
guest: Windows 2016 64 bit

Thread 28 (Thread 0x7f0e2edff700 (LWP 29860)):
#0  __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:51
set = {__val = {18446744067266837079, 139698892694944, 139699853745096, 
139700858749789, 4222451712, 139694281220640, 139694281220741, 139694281220640, 
139694281220640, 139694281220810, 
139694281220940, 139694281220640, 139694281220940, 0, 0, 0}}
pid = 
tid = 
#1  0x7f0ea40b644a in __GI_abort () at abort.c:89
save_stage = 2
act = {__sigaction_handler = {sa_handler = 0x7f0e2edfe5c0, sa_sigaction 
= 0x7f0e2edfe5c0}, sa_mask = {__val = {139694281219872, 139698106269697, 
139698892695344, 4, 2676511744, 0, 139698892695144, 0, 
  139698892694912, 1, 4737316546111099904, 139700859888720, 
4737316546111099904, 139700862161824, 139700911349760, 94211934977482}}, 
sa_flags = 416, 
  sa_restorer = 0x55af6ceb0500 <__PRETTY_FUNCTION__.36381>}
sigs = {__val = {32, 0 }}
#2  0x7f0ea40abab6 in __assert_fail_base (fmt=, 
assertion=assertion@entry=0x55af6ceafdca "offset < qxl->vga.vram_size", 
file=file@entry=0x55af6ceaeaa0 
"/var/tmp/portage/app-emulation/qemu-2.9.0-r2/work/qemu-2.9.0/hw/display/qxl.c",
 line=line@entry=416, 
function=function@entry=0x55af6ceb0500 <__PRETTY_FUNCTION__.36381> 
"qxl_ram_set_dirty") at assert.c:92
str = 0x7f0d1c026220 "\340r\002\034\r\177"
total = 4096
#3  0x7f0ea40abb81 in __GI___assert_fail 
(assertion=assertion@entry=0x55af6ceafdca "offset < qxl->vga.vram_size", 
file=file@entry=0x55af6ceaeaa0 
"/var/tmp/portage/app-emulation/qemu-2.9.0-r2/work/qemu-2.9.0/hw/display/qxl.c",
 line=line@entry=416, 
function=function@entry=0x55af6ceb0500 <__PRETTY_FUNCTION__.36381> 
"qxl_ram_set_dirty") at assert.c:101
No locals.
#4  0x55af6cc58805 in qxl_ram_set_dirty (qxl=, 
ptr=) at 
/var/tmp/portage/app-emulation/qemu-2.9.0-r2/work/qemu-2.9.0/hw/display/qxl.c:416
base = 
offset = 
qxl = 
ptr = 
base = 
offset = 
#5  0x55af6cc5b9e2 in interface_release_resource (sin=0x55af71a91ed0, 
ext=...) at 
/var/tmp/portage/app-emulation/qemu-2.9.0-r2/work/qemu-2.9.0/hw/display/qxl.c:767
qxl = 0x55af71a91450
ring = 
item = 
id = 18446690739814400920
__func__ = "interface_release_resource"
#6  0x7f0ea510afa8 in red_drawable_unref (red_drawable=0x7f0d1c026120) at 
red-worker.c:101
No locals.
#7  0x7f0ea510b609 in red_drawable_unref (red_drawable=) at 
red-worker.c:104
No locals.
#8  0x7f0ea510eae9 in drawable_unref 
(drawable=drawable@entry=0x7f0e68285ac0) at display-channel.c:1438
display = 0x55af71dbd3c0
__FUNCTION__ = "drawable_unref"
#9  0x7f0ea51109f7 in draw_until (display=display@entry=0x55af71dbd3c0, 
surface=surface@entry=0x7f0e6828aae8, last=0x7f0e68285ac0) at 
display-channel.c:1637
container = 0x0
now = 0x7f0e68285ac0
#10 0x7f0ea510f93f in display_channel_draw (display=0x55af71dbd3c0, 
area=0x7f0e2edfe8e0, surface_id=) at display-channel.c:1729
surface = 0x7f0e6828aae8
last = 
__FUNCTION__ = "display_channel_draw"
__func__ = "display_channel_draw"

** Affects: qemu
 Importance: Undecided
 Status: New

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1713825

Title:
  Booting Windows 2016 with qxl video crashes qemu

Status in QEMU:
  New

Bug description:
  launched from libvirt.

  qemu version: 2.9.0
  host: Linux  4.9.34-gentoo #1 SMP Sat Jul 29 13:28:43 PDT 2017 
x86_64 Intel(R) Core(TM) i7-3930K CPU @ 3.20GHz GenuineIntel GNU/Linux
  guest: Windows 2016 64 bit

  Thread 28 (Thread 0x7f0e2edff700 (LWP 29860)):
  #0  __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:51
  set = {__val = {18446744067266837079, 139698892694944, 
139699853745096, 139700858749789, 4222451712, 139694281220640, 139694281220741, 
139694281220640, 139694281220640, 139694281220810, 
  139694281220940, 139694281220640, 139694281220940, 0, 0, 0}}
  pid = 
  tid = 
  #1  0x7f0ea40b644a in __GI_abort () at abort.c:89
  save_stage = 2
  act = {__sigaction_handler = {sa_handler = 0x7f0e2edfe5c0, 
sa_sigaction = 0x7f0e2edfe5c0}, sa_mask = {__val = {139694281219872, 
139698106269697, 139698892695344, 4, 2676511744, 0, 139698892695144, 0, 
139698892694912, 1, 4737316546111099904, 139700859888720, 
4737316546111099904, 139700862161824, 139700911349760, 94211934977482}}, 
sa_flags = 416, 
sa_restorer = 0x55af6ceb0500 <__PRETTY_FUNCTION__.36381>}
  sigs = {__val = {32, 0 }}
  #2  

Re: [Qemu-devel] [PATCH v2 9/9] AHCI: remove DPRINTF macro

[Philippe Mathieu-Daudé]

On 08/29/2017 05:49 PM, John Snow wrote:

Signed-off-by: John Snow 


Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 


---
  hw/ide/ahci.c | 9 -
  1 file changed, 9 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 2e75f9b..57bb59d 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -34,17 +34,8 @@
  #include "hw/ide/pci.h"
  #include "hw/ide/ahci_internal.h"
  
-#define DEBUG_AHCI 0

  #include "trace.h"
  
-#define DPRINTF(port, fmt, ...) \

-do { \
-if (DEBUG_AHCI) { \
-fprintf(stderr, "ahci: %s: [%d] ", __func__, port); \
-fprintf(stderr, fmt, ## __VA_ARGS__); \
-} \
-} while (0)
-
  static void check_cmd(AHCIState *s, int port);
  static int handle_cmd(AHCIState *s, int port, uint8_t slot);
  static void ahci_reset_port(AHCIState *s, int port);

Re: [Qemu-devel] [PATCH v2 6/9] AHCI: Replace DPRINTF with trace-events

[Philippe Mathieu-Daudé]

On 08/29/2017 05:49 PM, John Snow wrote:

There are a few hangers-on that will be dealt with individually
in forthcoming patches.

Signed-off-by: John Snow 


Reviewed-by: Philippe Mathieu-Daudé 


---
  hw/ide/ahci.c   | 157 +++-
  hw/ide/trace-events |  49 
  2 files changed, 117 insertions(+), 89 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 406a1b5..c60a000 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -35,6 +35,7 @@
  #include "hw/ide/ahci_internal.h"
  
  #define DEBUG_AHCI 0

+#include "trace.h"
  
  #define DPRINTF(port, fmt, ...) \

  do { \
@@ -114,9 +115,9 @@ static uint32_t  ahci_port_read(AHCIState *s, int port, int 
offset)
  default:
  val = 0;
  }
-DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
-return val;
  
+trace_ahci_port_read(s, port, offset, val);

+return val;
  }
  
  static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)

@@ -125,7 +126,7 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
  PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
 TYPE_PCI_DEVICE);
  
-DPRINTF(0, "raise irq\n");

+trace_ahci_irq_raise(s);
  
  if (pci_dev && msi_enabled(pci_dev)) {

  msi_notify(pci_dev, 0);
@@ -140,7 +141,7 @@ static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
  PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
 TYPE_PCI_DEVICE);
  
-DPRINTF(0, "lower irq\n");

+trace_ahci_irq_lower(s);
  
  if (!pci_dev || !msi_enabled(pci_dev)) {

  qemu_irq_lower(s->irq);
@@ -150,8 +151,7 @@ static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
  static void ahci_check_irq(AHCIState *s)
  {
  int i;
-
-DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus);
+uint32_t old_irq = s->control_regs.irqstatus;
  
  s->control_regs.irqstatus = 0;

  for (i = 0; i < s->ports; i++) {
@@ -160,7 +160,7 @@ static void ahci_check_irq(AHCIState *s)
  s->control_regs.irqstatus |= (1 << i);
  }
  }
-
+trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus);
  if (s->control_regs.irqstatus &&
  (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
  ahci_irq_raise(s, NULL);
@@ -240,7 +240,7 @@ static void  ahci_port_write(AHCIState *s, int port, int 
offset, uint32_t val)
  {
  AHCIPortRegs *pr = >dev[port].port_regs;
  
-DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);

+trace_ahci_port_write(s, port, offset, val);
  switch (offset) {
  case PORT_LST_ADDR:
  pr->lst_addr = val;
@@ -341,8 +341,6 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)
  val = s->control_regs.version;
  break;
  }
-
-DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val);
  } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
 (addr < (AHCI_PORT_REGS_START_ADDR +
  (s->ports * AHCI_PORT_ADDR_OFFSET_LEN {
@@ -350,6 +348,7 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)
   addr & AHCI_PORT_ADDR_OFFSET_MASK);
  }
  
+trace_ahci_mem_read_32(s, addr, val);

  return val;
  }
  
@@ -379,8 +378,7 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)

  val = (hi << 32 | lo) >> (ofst * 8);
  }
  
-DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",

-addr, val, size);
+trace_ahci_mem_read(opaque, size, addr, val);
  return val;
  }
  
@@ -390,8 +388,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr,

  {
  AHCIState *s = opaque;
  
-DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",

-addr, val, size);
+trace_ahci_mem_write(s, size, addr, val);
  
  /* Only aligned reads are allowed on AHCI */

  if (addr & 3) {
@@ -401,15 +398,12 @@ static void ahci_mem_write(void *opaque, hwaddr addr,
  }
  
  if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {

-DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, 
val);
-
  switch (addr) {
  case HOST_CAP: /* R/WO, RO */
  /* FIXME handle R/WO */
  break;
  case HOST_CTL: /* R/W */
  if (val & HOST_CTL_RESET) {
-DPRINTF(-1, "HBA Reset\n");
  ahci_reset(s);
  } else {
  s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
@@ -427,7 +421,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr,
  /* FIXME report write? */
  break;
  default:
-DPRINTF(-1, "write to unknown register 

Re: [Qemu-devel] [PATCH v2 3/9] IDE: add tracing for data ports

[Philippe Mathieu-Daudé]

On 08/29/2017 05:49 PM, John Snow wrote:

To be used sparingly, but still interesting in the case of small
firmwares designed to reproduce bugs in QEMU IDE.

Signed-off-by: John Snow 


Reviewed-by: Philippe Mathieu-Daudé 


---
  hw/ide/core.c   | 12 +++-
  hw/ide/trace-events |  5 +
  2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/hw/ide/core.c b/hw/ide/core.c
index cb250e6..82a19b1 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -2259,6 +2259,8 @@ void ide_data_writew(void *opaque, uint32_t addr, 
uint32_t val)
  IDEState *s = idebus_active_if(bus);
  uint8_t *p;
  
+trace_ide_data_writew(addr, val, bus, s);

+
  /* PIO data access allowed only when DRQ bit is set. The result of a write
   * during PIO out is indeterminate, just ignore it. */
  if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
@@ -2304,6 +2306,8 @@ uint32_t ide_data_readw(void *opaque, uint32_t addr)
  s->status &= ~DRQ_STAT;
  s->end_transfer_func(s);
  }
+
+trace_ide_data_readw(addr, ret, bus, s);
  return ret;
  }
  
@@ -2313,6 +2317,8 @@ void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)

  IDEState *s = idebus_active_if(bus);
  uint8_t *p;
  
+trace_ide_data_writel(addr, val, bus, s);

+
  /* PIO data access allowed only when DRQ bit is set. The result of a write
   * during PIO out is indeterminate, just ignore it. */
  if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
@@ -2343,7 +2349,8 @@ uint32_t ide_data_readl(void *opaque, uint32_t addr)
  /* PIO data access allowed only when DRQ bit is set. The result of a read
   * during PIO in is indeterminate, return 0 and don't move forward. */
  if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
-return 0;
+ret = 0;
+goto out;
  }
  
  p = s->data_ptr;

@@ -2358,6 +2365,9 @@ uint32_t ide_data_readl(void *opaque, uint32_t addr)
  s->status &= ~DRQ_STAT;
  s->end_transfer_func(s);
  }
+
+out:
+trace_ide_data_readl(addr, ret, bus, s);
  return ret;
  }
  
diff --git a/hw/ide/trace-events b/hw/ide/trace-events

index bff8f39..17bc6f1 100644
--- a/hw/ide/trace-events
+++ b/hw/ide/trace-events
@@ -6,6 +6,11 @@ ide_ioport_read(uint32_t addr, const char *reg, uint32_t val, 
void *bus, void *s
  ide_ioport_write(uint32_t addr, const char *reg, uint32_t val, void *bus, void *s) "IDE PIO wr @ 
0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState %p"
  ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s)   "IDE PIO rd @ 
0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p; IDEState %p"
  ide_cmd_write(uint32_t addr, uint32_t val, void *bus)  "IDE PIO wr @ 
0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus %p"
+# Warning: verbose
+ide_data_readw(uint32_t addr, uint32_t val, void *bus, void *s)"IDE PIO rd @ 
0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p; IDEState %p"
+ide_data_writew(uint32_t addr, uint32_t val, void *bus, void *s)   "IDE PIO wr @ 
0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p; IDEState %p"
+ide_data_readl(uint32_t addr, uint32_t val, void *bus, void *s)"IDE PIO rd @ 
0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState %p"
+ide_data_writel(uint32_t addr, uint32_t val, void *bus, void *s)   "IDE PIO wr @ 
0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState %p"
  # misc
  ide_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; state 
%p; cmd 0x%02x"
  ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffered 
request %p with -ECANCELED"

Re: [Qemu-devel] [PATCH 00/17] nbd client refactoring and fixing

[Eric Blake]

On 08/25/2017 05:10 PM, Eric Blake wrote:
> On 08/04/2017 10:14 AM, Vladimir Sementsov-Ogievskiy wrote:
>> A bit more refactoring and fixing before BLOCK_STATUS series.
>> I've tried to make individual patches simple enough, so there are
>> a lot of them.
>>
>> Vladimir Sementsov-Ogievskiy (17):
>>   nbd/client: fix nbd_opt_go
>>   nbd/client: refactor nbd_read_eof
>>   nbd/client: refactor nbd_receive_reply
>>   nbd/client: fix nbd_send_request to return int
>>   block/nbd-client: get rid of ssize_t
>>   block/nbd-client: fix nbd_read_reply_entry
>>   block/nbd-client: refactor request send/receive
>>   block/nbd-client: rename nbd_recv_coroutines_enter_all
>>   block/nbd-client: move nbd_co_receive_reply content into
>> nbd_co_request
>>   block/nbd-client: move nbd_coroutine_end content into nbd_co_request
>>   block/nbd-client: fix nbd_co_request: set s->reply.handle to 0 on
>> error
>>   block/nbd-client: refactor nbd_co_request
>>   block/nbd-client: refactor NBDClientSession.recv_coroutine
>>   block/nbd-client: exit reply-reading coroutine on incorrect handle
>>   block/nbd-client: refactor reading reply
>>   block/nbd-client: drop reply field from NBDClientSession
>>   block/nbd-client: always return EIO on and after the first io channel
>> error
> 
> I've pushed 1-5 and 7-10 onto my NBD staging branch for 2.11:
> 
>   git://repo.or.cz/qemu/ericb.git nbd

Correction - I've decided to take Stefan's patches first (since his
patch 1/3 was a bit more elegant at doing the same thing as your patch
10); that caused rebase conflicts for your patch 7 (which I simplified
by creating nbd_co_request as a wrapper rather than trying to inline its
parts), and my change to your patch 7 obsoletes the need for 9 or 10.  I
also placed your patch 8 before your patch 7 (if you don't like what I
changed on patch 7, it is now last in my NBD staging area, so I can more
easily drop it from my tree if you'd prefer to respin it differently).

> with a couple of changes squashed in as mentioned in individual patches;
> please double-check that it looks okay.  If so, then I will use that
> branch as the starting point for all NBD commits destined for 2.11,
> sending a pull request once the tree opens.
> 
> Patches 6 and 11 are somewhat subsumed by the work that went into 2.10,
> and the remaining patches are starting to cause enough conflicts that
> I'd prefer you complete the rebase of patches 12-17 and post a v2 on top
> of my staging branch.

These statements still hold; you'll need to rebase the rest of your
series on top of my tree.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



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Description: OpenPGP digital signature

[Qemu-devel] [PATCH 3/3] vfio/pci: Add NVIDIA GPUDirect Cliques support

[Alex Williamson]

NVIDIA has defined a specification for creating GPUDirect "cliques",
where devices with the same clique ID support direct peer-to-peer DMA.
When running on bare-metal, tools like NVIDIA's p2pBandwidthLatencyTest
(part of cuda-samples) determine which GPUs can support peer-to-peer
based on chipset and topology.  When running in a VM, these tools have
no visibility to the physical hardware support or topology.  This
option allows the user to specify hints via a vendor defined
capability.  For instance:

  






  

This enables two cliques.  The first is a singleton clique with ID 0,
for the first hostdev defined in the XML (note that since cliques
define peer-to-peer sets, singleton clique offer no benefit).  The
subsequent two hostdevs are both added to clique ID 1, indicating
peer-to-peer is possible between these devices.

QEMU only provides validation that the clique ID is valid and applied
to an NVIDIA graphics device, any validation that the resulting
cliques are functional and valid is the user's responsibility.  The
NVIDIA specification allows a 4-bit clique ID, thus valid values are
0-15.

Signed-off-by: Alex Williamson 
---
 hw/vfio/pci-quirks.c |  110 ++
 hw/vfio/pci.c|5 ++
 hw/vfio/pci.h|3 +
 3 files changed, 118 insertions(+)

diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index 40aaae76feb9..14291c2a16b2 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -14,6 +14,7 @@
 #include "qemu/error-report.h"
 #include "qemu/range.h"
 #include "qapi/error.h"
+#include "qapi/visitor.h"
 #include "hw/nvram/fw_cfg.h"
 #include "pci.h"
 #include "trace.h"
@@ -1850,7 +1851,116 @@ void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev)
 break;
 }
 }
+
+/*
+ * The NVIDIA GPUDirect P2P Vendor capability allows the user to specify
+ * devices as a member of a clique.  Devices within the same clique ID
+ * are capable of direct P2P.  It's the user's responsibility that this
+ * is correct.  The spec says that this may reside at any unused config
+ * offset, but reserves and recommends hypervisors place this at C8h.
+ * The spec also states that the hypervisor should place this capability
+ * at the end of the capability list, thus next is defined as 0h.
+ *
+ * +++++
+ * | sig 7:0 ('P')  |  vndr len (8h) |next (0h)   |   cap id (9h)  |
+ * +++++
+ * | rsvd 15:7(0h),id 6:3,ver 2:0(0h)|  sig 23:8 ('P2')|
+ * +-+-+
+ *
+ * https://lists.gnu.org/archive/html/qemu-devel/2017-08/pdfUda5iEpgOS.pdf
+ */
+static void get_nv_gpudirect_clique_id(Object *obj, Visitor *v,
+   const char *name, void *opaque,
+   Error **errp)
+{
+DeviceState *dev = DEVICE(obj);
+Property *prop = opaque;
+uint8_t *ptr = qdev_get_prop_ptr(dev, prop);
+
+visit_type_uint8(v, name, ptr, errp);
+}
+
+static void set_nv_gpudirect_clique_id(Object *obj, Visitor *v,
+   const char *name, void *opaque,
+   Error **errp)
+{
+DeviceState *dev = DEVICE(obj);
+Property *prop = opaque;
+uint8_t value, *ptr = qdev_get_prop_ptr(dev, prop);
+Error *local_err = NULL;
+
+if (dev->realized) {
+qdev_prop_set_after_realize(dev, name, errp);
+return;
+}
+
+visit_type_uint8(v, name, , _err);
+if (local_err) {
+error_propagate(errp, local_err);
+return;
+}
+
+if (value & ~0xF) {
+error_setg(errp, "Property %s: valid range 0-15", name);
+return;
+}
+
+*ptr = value;
+}
+
+const PropertyInfo qdev_prop_nv_gpudirect_clique = {
+.name = "uint4",
+.description = "NVIDIA GPUDirect Clique ID (0 - 15)",
+.get = get_nv_gpudirect_clique_id,
+.set = set_nv_gpudirect_clique_id,
+};
+
+static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp)
+{
+PCIDevice *pdev = >pdev;
+int ret, pos = 0xC8;
+
+if (vdev->nv_gpudirect_clique == 0xFF) {
+return 0;
+}
+
+if (!vfio_pci_is(vdev, PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID)) {
+error_setg(errp, "NVIDIA GPUDirect Clique ID: invalid device vendor");
+return -EINVAL;
+}
+
+if (pci_get_byte(pdev->config + PCI_CLASS_DEVICE + 1) !=
+PCI_BASE_CLASS_DISPLAY) {
+error_setg(errp, "NVIDIA GPUDirect Clique ID: unsupported PCI class");
+return -EINVAL;
+}
+
+ret = pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8, errp);
+if (ret < 0) {
+error_prepend(errp, "Failed to add NVIDIA GPUDirect cap: ");
+return ret;
+}
+
+memset(vdev->emulated_config_bits + pos, 0xFF, 8);
+pos += PCI_CAP_FLAGS;
+

[Qemu-devel] [PATCH 2/3] vfio/pci: Add virtual capabilities quirk infrastructure

[Alex Williamson]

If the hypervisor needs to add purely virtual capabilties, give us a
hook through quirks to do that.  Note that we determine the maximum
size for a capability based on the physical device, if we insert a
virtual capability, that can change.  Therefore if maximum size is
smaller after added virt capabilities, use that.

Signed-off-by: Alex Williamson 
---
 hw/vfio/pci-quirks.c |4 
 hw/vfio/pci.c|8 
 hw/vfio/pci.h|1 +
 3 files changed, 13 insertions(+)

diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index 349085ea12bc..40aaae76feb9 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -1850,3 +1850,7 @@ void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev)
 break;
 }
 }
+int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp)
+{
+return 0;
+}
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 916d365dfab3..bfeaaef22d00 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -1833,8 +1833,16 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t 
pos, Error **errp)
 pdev->config[PCI_CAPABILITY_LIST] = 0;
 vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff;
 vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
+
+ret = vfio_add_virt_caps(vdev, errp);
+if (ret) {
+return ret;
+}
 }
 
+/* Scale down size, esp in case virt caps were added above */
+size = MIN(size, vfio_std_cap_max_size(pdev, pos));
+
 /* Use emulated next pointer to allow dropping caps */
 pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff);
 
diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h
index a8366bb2a74a..958cee058b3b 100644
--- a/hw/vfio/pci.h
+++ b/hw/vfio/pci.h
@@ -160,6 +160,7 @@ void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr);
 void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr);
 void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr);
 void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev);
+int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp);
 
 int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp);
 

[Qemu-devel] [PATCH 0/3] vfio/pci: Add NVIDIA GPUDirect P2P clique support

[Alex Williamson]

NVIDIA has a specification for exposing a virtual vendor capability
which provides a hint to guest drivers as to which sets of GPUs can
support direct peer-to-peer DMA.  Devices with the same clique ID are
expected to support this.  The user can specify a clique ID for an
NVIDIA graphics device using the new vfio-pci x-nv-gpudirect-clique=
option, where valid clique IDs are a 4-bit integer.  It's entirely the
user's responsibility to specify sets of devices for which P2P works
correctly and provides some benefit.  This is only useful for DMA
between NVIDIA GPUs, therefore it's only useful to specify cliques
comprised of more than one GPU.  Furthermore, this does not enable DMA
between VMs, there is no change to VM DMA mapping, this only exposes
hints about existing DMA paths to the guest driver.  Thanks,

Alex

---

Alex Williamson (3):
  vfio/pci: Do not unwind on error
  vfio/pci: Add virtual capabilities quirk infrastructure
  vfio/pci: Add NVIDIA GPUDirect Cliques support


 hw/vfio/pci-quirks.c |  114 ++
 hw/vfio/pci.c|   17 +++
 hw/vfio/pci.h|4 ++
 3 files changed, 133 insertions(+), 2 deletions(-)

[Qemu-devel] [PATCH 1/3] vfio/pci: Do not unwind on error

[Alex Williamson]

If vfio_add_std_cap() errors then going to out prepends irrelevant
errors for capabilities we haven't attempted to add as we unwind our
recursive stack.  Just return error.

Fixes: 7ef165b9a8d9 ("vfio/pci: Pass an error object to vfio_add_capabilities")
Signed-off-by: Alex Williamson 
---
 hw/vfio/pci.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 31e1edf44745..916d365dfab3 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -1826,7 +1826,7 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t 
pos, Error **errp)
 if (next) {
 ret = vfio_add_std_cap(vdev, next, errp);
 if (ret) {
-goto out;
+return ret;
 }
 } else {
 /* Begin the rebuild, use QEMU emulated list bits */
@@ -1862,7 +1862,7 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t 
pos, Error **errp)
 ret = pci_add_capability(pdev, cap_id, pos, size, errp);
 break;
 }
-out:
+
 if (ret < 0) {
 error_prepend(errp,
   "failed to add PCI capability 0x%x[0x%x]@0x%x: ",

[Qemu-devel] [PATCH] qom: Remove unused errp parameter from can_be_deleted()

[Eduardo Habkost]

The errp argument is ignored by all implementations of the
method, and user_creatable_del() would break if any
implementation set an error (because it calls error_setg(errp) if
the function returns false).  Remove the unused parameter.

Signed-off-by: Eduardo Habkost 
---
 include/qom/object_interfaces.h | 5 ++---
 backends/cryptodev.c| 2 +-
 backends/hostmem.c  | 2 +-
 qom/object_interfaces.c | 6 +++---
 4 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/include/qom/object_interfaces.h b/include/qom/object_interfaces.h
index fdd7603..d63c1c2 100644
--- a/include/qom/object_interfaces.h
+++ b/include/qom/object_interfaces.h
@@ -51,7 +51,7 @@ typedef struct UserCreatableClass {
 
 /*  */
 void (*complete)(UserCreatable *uc, Error **errp);
-bool (*can_be_deleted)(UserCreatable *uc, Error **errp);
+bool (*can_be_deleted)(UserCreatable *uc);
 } UserCreatableClass;
 
 /**
@@ -68,12 +68,11 @@ void user_creatable_complete(Object *obj, Error **errp);
 /**
  * user_creatable_can_be_deleted:
  * @uc: the object whose can_be_deleted() method is called if implemented
- * @errp: if an error occurs, a pointer to an area to store the error
  *
  * Wrapper to call can_be_deleted() method if one of types it's inherited
  * from implements USER_CREATABLE interface.
  */
-bool user_creatable_can_be_deleted(UserCreatable *uc, Error **errp);
+bool user_creatable_can_be_deleted(UserCreatable *uc);
 
 /**
  * user_creatable_add_type:
diff --git a/backends/cryptodev.c b/backends/cryptodev.c
index 1764c17..67edfa5 100644
--- a/backends/cryptodev.c
+++ b/backends/cryptodev.c
@@ -215,7 +215,7 @@ bool cryptodev_backend_is_ready(CryptoDevBackend *backend)
 }
 
 static bool
-cryptodev_backend_can_be_deleted(UserCreatable *uc, Error **errp)
+cryptodev_backend_can_be_deleted(UserCreatable *uc)
 {
 return !cryptodev_backend_is_used(CRYPTODEV_BACKEND(uc));
 }
diff --git a/backends/hostmem.c b/backends/hostmem.c
index 4606b73..34550b9 100644
--- a/backends/hostmem.c
+++ b/backends/hostmem.c
@@ -342,7 +342,7 @@ out:
 }
 
 static bool
-host_memory_backend_can_be_deleted(UserCreatable *uc, Error **errp)
+host_memory_backend_can_be_deleted(UserCreatable *uc)
 {
 if (host_memory_backend_is_mapped(MEMORY_BACKEND(uc))) {
 return false;
diff --git a/qom/object_interfaces.c b/qom/object_interfaces.c
index ff27e06..3bb8959 100644
--- a/qom/object_interfaces.c
+++ b/qom/object_interfaces.c
@@ -23,13 +23,13 @@ void user_creatable_complete(Object *obj, Error **errp)
 }
 }
 
-bool user_creatable_can_be_deleted(UserCreatable *uc, Error **errp)
+bool user_creatable_can_be_deleted(UserCreatable *uc)
 {
 
 UserCreatableClass *ucc = USER_CREATABLE_GET_CLASS(uc);
 
 if (ucc->can_be_deleted) {
-return ucc->can_be_deleted(uc, errp);
+return ucc->can_be_deleted(uc);
 } else {
 return true;
 }
@@ -178,7 +178,7 @@ void user_creatable_del(const char *id, Error **errp)
 return;
 }
 
-if (!user_creatable_can_be_deleted(USER_CREATABLE(obj), errp)) {
+if (!user_creatable_can_be_deleted(USER_CREATABLE(obj))) {
 error_setg(errp, "object '%s' is in use, can not be deleted", id);
 return;
 }
-- 
2.9.4

Re: [Qemu-devel] [Qemu devel v7 PATCH 1/5] msf2: Add Smartfusion2 System timer

[Alistair Francis]

On Mon, Aug 28, 2017 at 10:32 PM, sundeep subbaraya
 wrote:
> Hi Alistair,
>
> On Tue, Aug 29, 2017 at 3:23 AM, Alistair Francis 
> wrote:
>>
>> On Mon, Aug 28, 2017 at 9:37 AM, Subbaraya Sundeep
>>  wrote:
>> > Modelled System Timer in Microsemi's Smartfusion2 Soc.
>> > Timer has two 32bit down counters and two interrupts.
>> >
>> > Signed-off-by: Subbaraya Sundeep 
>>
>> I had already reviewed this patch in v6. As long as you have made all
>> of the changes mentioned their you can add my reviewed-by to the next
>> version (as long as there are no other significant changes).
>>
>> Can you please ensure you do add and keep reviewed-by tags, it's a
>> pain to have to do it multiple times.
>
>
> Sorry I was not aware that I can add reviewed by tag myself and send.

You can't just add them, but if someone has reviewded your patch you
should keep it on that patch.

> I will add your reviewed by since I fixed all your comments.
> Do I need to send another version v8 with your Reviewed-by ?

No it's ok. I'll have a look at the other patches. When you do send a
new version just include them then.

Thanks,
Alistair

>
> Thanks,
> Sundeep
>
>>
>>
>> Thanks,
>> Alistair
>>
>> > ---
>> >  hw/timer/Makefile.objs   |   1 +
>> >  hw/timer/mss-timer.c | 289
>> > +++
>> >  include/hw/timer/mss-timer.h |  64 ++
>> >  3 files changed, 354 insertions(+)
>> >  create mode 100644 hw/timer/mss-timer.c
>> >  create mode 100644 include/hw/timer/mss-timer.h
>> >
>> > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
>> > index 15cce1c..8c19eac 100644
>> > --- a/hw/timer/Makefile.objs
>> > +++ b/hw/timer/Makefile.objs
>> > @@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
>> >
>> >  common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
>> >  common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
>> > +common-obj-$(CONFIG_MSF2) += mss-timer.o
>> > diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
>> > new file mode 100644
>> > index 000..60f1213
>> > --- /dev/null
>> > +++ b/hw/timer/mss-timer.c
>> > @@ -0,0 +1,289 @@
>> > +/*
>> > + * Block model of System timer present in
>> > + * Microsemi's SmartFusion2 and SmartFusion SoCs.
>> > + *
>> > + * Copyright (c) 2017 Subbaraya Sundeep .
>> > + *
>> > + * Permission is hereby granted, free of charge, to any person
>> > obtaining a copy
>> > + * of this software and associated documentation files (the
>> > "Software"), to deal
>> > + * in the Software without restriction, including without limitation
>> > the rights
>> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> > sell
>> > + * copies of the Software, and to permit persons to whom the Software
>> > is
>> > + * furnished to do so, subject to the following conditions:
>> > + *
>> > + * The above copyright notice and this permission notice shall be
>> > included in
>> > + * all copies or substantial portions of the Software.
>> > + *
>> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> > EXPRESS OR
>> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> > MERCHANTABILITY,
>> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> > SHALL
>> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> > OTHER
>> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> > ARISING FROM,
>> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> > DEALINGS IN
>> > + * THE SOFTWARE.
>> > + */
>> > +
>> > +#include "qemu/osdep.h"
>> > +#include "qemu/main-loop.h"
>> > +#include "qemu/log.h"
>> > +#include "hw/timer/mss-timer.h"
>> > +
>> > +#ifndef MSS_TIMER_ERR_DEBUG
>> > +#define MSS_TIMER_ERR_DEBUG  0
>> > +#endif
>> > +
>> > +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> > +if (MSS_TIMER_ERR_DEBUG >= lvl) { \
>> > +qemu_log("%s: " fmt "\n", __func__, ## args); \
>> > +} \
>> > +} while (0);
>> > +
>> > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> > +
>> > +#define R_TIM_VAL 0
>> > +#define R_TIM_LOADVAL 1
>> > +#define R_TIM_BGLOADVAL   2
>> > +#define R_TIM_CTRL3
>> > +#define R_TIM_RIS 4
>> > +#define R_TIM_MIS 5
>> > +
>> > +#define TIMER_CTRL_ENBL (1 << 0)
>> > +#define TIMER_CTRL_ONESHOT  (1 << 1)
>> > +#define TIMER_CTRL_INTR (1 << 2)
>> > +#define TIMER_RIS_ACK   (1 << 0)
>> > +#define TIMER_RST_CLR   (1 << 6)
>> > +#define TIMER_MODE  (1 << 0)
>> > +
>> > +static void timer_update_irq(struct Msf2Timer *st)
>> > +{
>> > +bool isr, ier;
>> > +
>> > +isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
>> > +ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
>> > +qemu_set_irq(st->irq, (ier && isr));
>> > +}
>> > +
>> > +static void timer_update(struct Msf2Timer *st)
>> > +{
>> > +

Re: [Qemu-devel] [PATCH v2 0/3] nbd-client: enter read_reply_co during init to avoid crash

[Eric Blake]

On 08/29/2017 07:27 AM, Stefan Hajnoczi wrote:
> v2:
>  * Rewrote Patch 1 following Paolo's suggestion [Paolo]
> 
> See Patch 1 for the segfault fix.  Patches 2 & 3 add qemu-iotests coverage.
> 
> This is a rare crash that we'll probably only see in testing.  It only seems 
> to
> happen with UNIX domain sockets.
> 
> Stefan Hajnoczi (3):
>   nbd-client: avoid read_reply_co entry if send failed
>   qemu-iotests: improve nbd-fault-injector.py startup protocol
>   qemu-iotests: test NBD over UNIX domain sockets in 083

Thanks; I'm including this series in my NBD tree, and will send a pull
request once 2.11 opens up.

> 
>  block/nbd-client.c   |  25 ++
>  tests/qemu-iotests/083   | 138 ++---
>  tests/qemu-iotests/083.out   | 145 
> +++
>  tests/qemu-iotests/common.filter |   4 +-
>  tests/qemu-iotests/nbd-fault-injector.py |   4 +
>  5 files changed, 228 insertions(+), 88 deletions(-)
> 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



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Re: [Qemu-devel] [PATCH v4 06/10] tests: Add NetBSD image

[Philippe Mathieu-Daudé]

Hi Fam,

On 08/29/2017 09:09 AM, Philippe Mathieu-Daudé wrote:
[...]>> +if __name__ == "__main__":

+    sys.exit(basevm.main(NetBSDVM))


This one is failing:

DEBUG:root:ssh_cmd: ssh -q -o StrictHostKeyChecking=no -o 
UserKnownHostsFile=/dev/null -o ConnectTimeout=1 -p 34091 -i 
/tmp/qemu-vm-59XYOj/id_rsa qemu@127.0.0.1

     set -e;
     cd $(mktemp -d /var/tmp/qemu-test.XX);
     tar -xf /dev/rld1a;
     ./configure --python=python2.7 ;
     gmake -j4;
     gmake check;

...
   CC  bt-host.o
   CC  bt-vhci.o
   CC  dma-helpers.o
   CC  vl.o
   CC  tpm.o
In file included from vl.c:72:0:
/var/tmp/qemu-test.ht0XHU/include/hw/loader.h:4:29: fatal error: 
hw/nvram/fw_cfg.h: No such file or directory

  #include "hw/nvram/fw_cfg.h"
  ^
compilation terminated.
/var/tmp/qemu-test.ht0XHU/rules.mak:66: recipe for target 'vl.o' failed
gmake: *** [vl.o] Error 1
gmake: *** Waiting for unfinished jobs
tests/vm/Makefile.include:32: recipe for target 'vm-build-netbsd' failed
make: *** [vm-build-netbsd] Error 3


Probably false alarm, this seems to be an ENOMEM host error.

I later got:

CHK version_gen.h
Makefile:342: recipe for target 'subdir-dtc' failed
gmake[1]: *** No rule to make target 'dtc/libfdt/fdt.h', needed by 
'libfdt/fdt.o'.  Stop.

gmake: *** [subdir-dtc] Error 2
gmake: *** Waiting for unfinished jobs

which I solved running "gmake -C dtc" after ./configure but I'm not sure 
it is necessary or can come from my tree, this testing is veeery 
slow and mostly kill my laptop, I ended wondering on what kind of 
hardware you developed this series without going crazy nut :S

[Qemu-devel] [PATCH] fixup! hostmem-file: Add "discard-data" option

[Eduardo Habkost]

On Tue, Aug 29, 2017 at 10:12:58AM -0300, Eduardo Habkost wrote:
> On Tue, Aug 29, 2017 at 12:13:45PM +0100, Daniel P. Berrange wrote:
> > On Thu, Aug 24, 2017 at 04:23:15PM -0300, Eduardo Habkost wrote:
[...]
> > > @@ -4172,6 +4172,9 @@ the path to either a shared memory or huge page 
> > > filesystem mount.
> > >  The @option{share} boolean option determines whether the memory
> > >  region is marked as private to QEMU, or shared. The latter allows
> > >  a co-operating external process to access the QEMU memory region.
> > > +Setting the @option{discard-data} boolean option to @var{on}
> > > +indicates that file contents can be destroyed when QEMU exits,
> > > +to avoid unnecessarily flushing data to the backing file.
> > 
> > We should note that this only works if QEMU shuts down normally. If QEMU
> > is aggressively killed (SIGKILL) or aborts for some reason, then we'll
> > never get a chance to invoke madvise(), so presumably the kernel will
> > still flush the data
> 
> Good point.  I tried to not give any guarantees by saying
> "contents _can_ be destroyed", but users may still have different
> expectations.
> 
> I will change it to:
> 
>   Setting the @option{discard-data} boolean option to @var{on}
>   indicates that file contents can be destroyed when QEMU exits,
>   to avoid unnecessarily flushing data to the backing file.  Note
>   that @option{discard-data} is only an optimization, and QEMU
>   might not discard file contents if it aborts unexpectedly or is
>   terminated using SIGKILL.

Fixup patch:

Signed-off-by: Eduardo Habkost 
---
 qemu-options.hx | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/qemu-options.hx b/qemu-options.hx
index ad985e4..de9a18a 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -4174,7 +4174,10 @@ region is marked as private to QEMU, or shared. The 
latter allows
 a co-operating external process to access the QEMU memory region.
 Setting the @option{discard-data} boolean option to @var{on}
 indicates that file contents can be destroyed when QEMU exits,
-to avoid unnecessarily flushing data to the backing file.
+to avoid unnecessarily flushing data to the backing file.  Note
+that @option{discard-data} is only an optimization, and QEMU
+might not discard file contents if it aborts unexpectedly or is
+terminated using SIGKILL.
 
 @item -object rng-random,id=@var{id},filename=@var{/dev/random}
 
-- 
2.9.4

Re: [Qemu-devel] [PULL 7/9] checkpatch: check trace-events code style

[Alex Williamson]

On Tue,  1 Aug 2017 14:16:16 +0100
Stefan Hajnoczi  wrote:

> From: Vladimir Sementsov-Ogievskiy 
> 
> According to CODING_STYLE, check that in trace-events:
> 1. hex numbers are prefixed with '0x'
> 2. '#' flag of printf is not used
> 3. The exclusion from 1. are period-separated groups of numbers
> 
> Signed-off-by: Vladimir Sementsov-Ogievskiy 
> Reviewed-by: Stefan Hajnoczi 
> Message-id: 20170731160135.12101-4-vsement...@virtuozzo.com
> Signed-off-by: Stefan Hajnoczi 
> ---
>  scripts/checkpatch.pl | 19 +++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
> index 4e91122813..fa478074b8 100755
> --- a/scripts/checkpatch.pl
> +++ b/scripts/checkpatch.pl
> @@ -1337,6 +1337,25 @@ sub process {
>   $rpt_cleaners = 1;
>   }
>  
> +# checks for trace-events files
> + if ($realfile =~ /trace-events$/ && $line =~ /^\+/) {
> + if ($rawline =~ /%[-+ 0]*#/) {
> + ERROR("Don't use '#' flag of printf format 
> ('%#') in " .
> +   "trace-events, use '0x' prefix instead\n" 
> . $herecurr);
> + } else {
> + my $hex =
> + qr/%[-+ 
> *.0-9]*([hljztL]|ll|hh)?(x|X|"\s*PRI[xX][^"]*"?)/;
> +
> + # don't consider groups splitted by [.:/ ], 
> like 2A.20:12ab
> + my $tmpline = $rawline =~ s/($hex[.:\/ 
> ])+$hex//gr;
> +
> + if ($tmpline =~ /(? + ERROR("Hex numbers must be prefixed 
> with '0x'\n" .
> +   $herecurr);
> + }
> + }
> + }
> +
>  # check we are in a valid source file if not then ignore this hunk
>   next if ($realfile !~ /\.(h|c|cpp|s|S|pl|py|sh)$/);
>  

This broke checkpatch.pl for me:

Bareword found where operator expected at ./scripts/checkpatch.pl line 1350, 
near "s/($hex[.:\/ ])+$hex//gr"
syntax error at ./scripts/checkpatch.pl line 1350, near "s/($hex[.:\/ 
])+$hex//gr"
Execution of ./scripts/checkpatch.pl aborted due to compilation errors.

$ perl -v

This is perl, v5.10.1 (*) built for x86_64-linux-thread-multi

Re: [Qemu-devel] [PATCH v2 6/7] throttle: Make burst_length 64bit and add range checks

[Eric Blake]

On 08/24/2017 08:24 AM, Alberto Garcia wrote:
> LeakyBucket.burst_length is defined as an unsigned integer but the
> code never checks for overflows and it only makes sure that the value
> is not 0.
> 
> In practice this means that the user can set something like
> throttling.iops-total-max-length=4294967300 despite being larger than
> UINT_MAX and the final value after casting to unsigned int will be 4.
> 
> This patch changes the data type to uint64_t. This does not increase
> the storage size of LeakyBucket, and allows us to assign the value
> directly from qemu_opt_get_number() or BlockIOThrottle and then do the
> checks directly in throttle_is_valid().
> 
> The value of burst_length does not have a specific upper limit,
> but since the bucket size is defined by max * burst_length we have
> to prevent overflows. Instead of going for UINT64_MAX or something
> similar this patch reuses THROTTLE_VALUE_MAX, which allows I/O bursts
> of 1 GiB/s for 10 days in a row.
> 
> Signed-off-by: Alberto Garcia 
> ---
>  include/qemu/throttle.h | 2 +-
>  util/throttle.c | 5 +
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



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Re: [Qemu-devel] [PATCH v2 5/7] throttle: Make LeakyBucket.avg and LeakyBucket.max integer types

[Eric Blake]

On 08/24/2017 08:24 AM, Alberto Garcia wrote:
> Both the throttling limits set with the throttling.iops-* and
> throttling.bps-* options and their QMP equivalents defined in the
> BlockIOThrottle struct are integer values.
> 
> Those limits are also reported in the BlockDeviceInfo struct and they
> are integers there as well.
> 
> Therefore there's no reason to store them internally as double and do
> the conversion everytime we're setting or querying them, so this patch
> uses uint64_t for those types. Let's also use an unsigned type because
> we don't allow negative values anyway.
> 
> LeakyBucket.level and LeakyBucket.burst_level do however remain double
> because their value changes depending on the fraction of time elapsed
> since the previous I/O operation.
> 
> Signed-off-by: Alberto Garcia 
> ---
>  include/qemu/throttle.h | 4 ++--
>  tests/test-throttle.c   | 3 ++-
>  util/throttle.c | 7 +++
>  3 files changed, 7 insertions(+), 7 deletions(-)
> 

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



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Re: [Qemu-devel] [PATCH v2 3/7] throttle: Make throttle_is_valid() a bit less verbose

[Eric Blake]

On 08/24/2017 08:24 AM, Alberto Garcia wrote:
> Use a pointer to the bucket instead of repeating cfg->buckets[i] all
> the time. This makes the code more concise and will help us expand the
> checks later and save a few line breaks.
> 
> Signed-off-by: Alberto Garcia 
> ---
>  util/throttle.c | 15 +++
>  1 file changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/util/throttle.c b/util/throttle.c
> index 9a6bda813c..bde56fe3de 100644
> --- a/util/throttle.c
> +++ b/util/throttle.c
> @@ -324,32 +324,31 @@ bool throttle_is_valid(ThrottleConfig *cfg, Error 
> **errp)
>  }
>  
>  for (i = 0; i < BUCKETS_COUNT; i++) {
> -if (cfg->buckets[i].avg < 0 ||
> -cfg->buckets[i].max < 0 ||
> -cfg->buckets[i].avg > THROTTLE_VALUE_MAX ||
> -cfg->buckets[i].max > THROTTLE_VALUE_MAX) {
> +LeakyBucket *bkt = >buckets[i];
> +if (bkt->avg < 0 || bkt->max < 0 ||

Up to the maintainer, but I'd include a blank line between declarations
and code.

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



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Re: [Qemu-devel] [PATCH v2 2/7] throttle: Update the throttle_fix_bucket() documentation

[Eric Blake]

On 08/24/2017 08:24 AM, Alberto Garcia wrote:
> The way the throttling algorithm works is that requests start being
> throttled once the bucket level exceeds the burst limit. When we get
> there the bucket leaks at the level set by the user (bkt->avg), and
> that leak rate is what prevents guest I/O from exceeding the desired
> limit.
> 
> If we don't allow bursts (i.e. bkt->max == 0) then we can start
> throttling requests immediately. The problem with keeping the
> threshold at 0 is that it only allows one request at a time, and as
> soon as there's a bit of I/O from the guest every other request will
> be throttled and performance will suffer considerably. That can even
> make the guest unable to reach the throttle limit if that limit is
> high enough, and that happens regardless of the block scheduler used
> by the guest.
> 
> Increasing that threshold gives flexibility to the guest, allowing it
> to perform short bursts of I/O before being throttled. Increasing the
> threshold too much does not make a difference in the long run (because
> it's the leak rate what defines the actual throughput) but it does
> allow the guest to perform longer initial bursts and exceed the
> throttle limit for a short while.
> 
> A burst value of bkt->avg / 10 allows the guest to perform 100ms'
> worth of I/O at the target rate without being throttled.
> 
> Signed-off-by: Alberto Garcia 
> ---
>  util/throttle.c | 11 +++
>  1 file changed, 3 insertions(+), 8 deletions(-)

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



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[Qemu-devel] [PATCH] oslib-posix: Print errors before aborting on qemu_alloc_stack()

[Eduardo Habkost]

If QEMU is running on a system that's out of memory and mmap()
fails, QEMU aborts with no error message at all, making it hard
to debug the reason for the failure.

Add perror() calls that will print error information before
aborting.

Signed-off-by: Eduardo Habkost 
---
 util/oslib-posix.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index cacf0ef..80086c5 100644
--- a/util/oslib-posix.c
+++ b/util/oslib-posix.c
@@ -530,6 +530,7 @@ void *qemu_alloc_stack(size_t *sz)
 ptr = mmap(NULL, *sz, PROT_READ | PROT_WRITE,
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 if (ptr == MAP_FAILED) {
+perror("failed to allocate memory for stack");
 abort();
 }
 
@@ -544,6 +545,7 @@ void *qemu_alloc_stack(size_t *sz)
 guardpage = ptr;
 #endif
 if (mprotect(guardpage, pagesz, PROT_NONE) != 0) {
+perror("failed to set up stack guard page");
 abort();
 }
 
-- 
2.9.4

Re: [Qemu-devel] [Qemu-block] [PATCH v3] qemu-iotests: Extend non-shared storage migration test (194)

[Eric Blake]

On 08/29/2017 12:42 PM, Stefan Hajnoczi wrote:
> On Tue, Aug 29, 2017 at 5:50 PM, Kashyap Chamarthy  
> wrote:
>> This is the follow-up patch that was discussed[*] as part of feedback to
>> qemu-iotest 194.
>>

>> Signed-off-by: Kashyap Chamarthy 
>> ---
>> Changes in v3:
>>  - Wait for migration to complete before issuing `block-job-cancel`
>>(StefanH)
>>  - Wait for the event BLOCK_JOB_COMPLETED on the source before stopping
>>the NBD server on the destination (StefanH)
>>
>> Changes in v2:
>>  - Check for both the events: MIGRATION and BLOCK_JOB_COMPLETED (EricB)
>> ---
>>  tests/qemu-iotests/194 | 23 +--
>>  tests/qemu-iotests/194.out | 11 ---
>>  2 files changed, 25 insertions(+), 9 deletions(-)
> 
> Reviewed-by: Stefan Hajnoczi 

Thanks; I've added this to my NBD queue (pull request to come shortly
after 2.11 release is finalized), since the test uses NBD.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



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Re: [Qemu-devel] [PATCH v4 11/43] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK

[Emilio G. Cota]

On Sun, Aug 27, 2017 at 18:15:50 -0400, Pranith Kumar wrote:
> Hi Emilio,
> 
> On Fri, Jul 21, 2017 at 1:59 AM, Emilio G. Cota  wrote:
> > This will enable us to decouple code translation from the value
> > of parallel_cpus at any given time. It will also help us minimize
> > TB flushes when generating code via EXCP_ATOMIC.
> >
> > Note that the declaration of parallel_cpus is brought to exec-all.h
> > to be able to define there the "curr_cflags" inline.
> >
> > Signed-off-by: Emilio G. Cota 
> 
> I was testing a winxp image today and I bisected a infinite loop to
> this commit. The loop happens both with and without mttcg, so I think
> it has got to do with something else.

Can you test the below? It lets me boot ubuntu, otherwise it reliably
chokes on a 'rep movsb' *very* early (doesn't even get to grub).

This discusson on v2 might be relevant (I added CF_COUNT_MASK as a
result of it, but it seems I have to revisit that):
  https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg06456.html

Anyway let me know if this fixes it for you. Thanks for testing!

Emilio

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 025fae0..8b2f233 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -326,7 +326,7 @@ struct TranslationBlock {
 #define CF_INVALID 0x8 /* TB is stale. Setters must acquire tb_lock */
 #define CF_PARALLEL0x10 /* Generate code for a parallel context */
 /* cflags' mask for hashing/comparison */
-#define CF_HASH_MASK (CF_COUNT_MASK | CF_PARALLEL)
+#define CF_HASH_MASK (CF_PARALLEL)

 /* Per-vCPU dynamic tracing state used to generate this TB */
 uint32_t trace_vcpu_dstate;

Re: [Qemu-devel] [PATCH v2 0/9] IDE: replace printfs with tracing

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20170829204934.9039-1-js...@redhat.com
Subject: [Qemu-devel] [PATCH v2 0/9] IDE: replace printfs with tracing
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]   patchew/20170829204934.9039-1-js...@redhat.com -> 
patchew/20170829204934.9039-1-js...@redhat.com
Switched to a new branch 'test'
317562672d AHCI: remove DPRINTF macro
5111f245b5 AHCI: pretty-print FIS to buffer instead of stderr
fd94464a09 AHCI: Rework IRQ constants
a2cbc7a1b9 AHCI: Replace DPRINTF with trace-events
7617a100a4 IDE: replace DEBUG_AIO with trace events
d0ab9d9ae8 ATAPI: Replace DEBUG_IDE_ATAPI with tracing events
ec07b9f487 IDE: add tracing for data ports
ad50ebd27b IDE: Add register hints to tracing
99af2ced97 IDE: replace DEBUG_IDE with tracing system

=== OUTPUT BEGIN ===
Checking PATCH 1/9: IDE: replace DEBUG_IDE with tracing system...
ERROR: spaces required around that '|' (ctx:VxV)
#143: FILE: hw/ide/core.c:1197:
+if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) {
^

total: 1 errors, 0 warnings, 337 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 2/9: IDE: Add register hints to tracing...
Checking PATCH 3/9: IDE: add tracing for data ports...
Checking PATCH 4/9: ATAPI: Replace DEBUG_IDE_ATAPI with tracing events...
Checking PATCH 5/9: IDE: replace DEBUG_AIO with trace events...
Checking PATCH 6/9: AHCI: Replace DPRINTF with trace-events...
ERROR: Hex numbers must be prefixed with '0x'
#540: FILE: hw/ide/trace-events:91:
+handle_reg_h2d_fis_pmp(void *s, int port, char b0, char b1, char b2) 
"ahci(%p)[%d]: Port Multiplier not supported, FIS: 0x%02x-%02x-%02x"

ERROR: Hex numbers must be prefixed with '0x'
#541: FILE: hw/ide/trace-events:92:
+handle_reg_h2d_fis_res(void *s, int port, char b0, char b1, char b2) 
"ahci(%p)[%d]: Reserved flags set in H2D Register FIS, FIS: 0x%02x-%02x-%02x"

ERROR: Hex numbers must be prefixed with '0x'
#547: FILE: hw/ide/trace-events:98:
+handle_cmd_unhandled_fis(void *s, int port, uint8_t b0, uint8_t b1, uint8_t 
b2) "ahci(%p)[%d]: unhandled FIS type. cmd_fis: 0x%02x-%02x-%02x"

total: 3 errors, 0 warnings, 496 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 7/9: AHCI: Rework IRQ constants...
Checking PATCH 8/9: AHCI: pretty-print FIS to buffer instead of stderr...
ERROR: Use g_assert or g_assert_not_reached
#35: FILE: hw/ide/ahci.c:658:
+g_assert_cmpint(cmd_len, <=, 0x100);

total: 1 errors, 0 warnings, 86 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 9/9: AHCI: remove DPRINTF macro...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-de...@freelists.org

Re: [Qemu-devel] [Qemu-ppc] [PATCH for-2.11 v2] hw/ppc: CAS reset on early device hotplug

[Daniel Henrique Barboza]

On 08/29/2017 04:23 AM, David Gibson wrote:

On Fri, Aug 25, 2017 at 06:11:18PM -0300, Daniel Henrique Barboza wrote:

v2:
- rebased with ppc-for-2.11
- function 'spapr_cas_completed' dropped
- function 'spapr_drc_needed' made public and it's now used inside
   'spapr_hotplugged_dev_before_cas'
- 'spapr_drc_needed' was changed to support the migration of logical
   DRCs with devs attached in UNUSED state
- new function: 'spapr_clear_pending_events'. This function is used
   inside ppc_spapr_reset to reset the pending_events QTAILQ

Thanks for the followup, unfortunately there is still an important bug
left, see comments on the patch itself.

At a higher level, though, looking at the event reset code made me
think of a possible even simpler solution to this problem.

The queue of events (both hotplug and epow) is already in a simple
internal form that's independent of the two delivery mechanisms.  The
only difference is what event source triggers the interrupt.  This
explains why an extra hotplug event after the CAS "unstuck" the queue.

AFAICT, a spurious interrupts here should be harmless - the kernel
will just check the queue and find nothing there.

So, it should be sufficient to, after CAS, pulse the hotplug queue
interrupt if the hotplug queue is negotiated.


This is something I've tried in my first attempts at this problem, before
sending the first patch in which I blocked hotplug before CAS. Back then,
the problem was that the kernel panics with sig 11 (acess of bad area) when
receiving the pulse after CAS.

I've investigated it a bit today and it seems that it still the case. 
Firing an IRQ right
after CAS breaks the kernel. In fact, if you time a regular CPU hotplug 
right after
CAS you'll get the same sig 11 kernel ooops. It looks like there is a 
time window after

CAS that the kernel can't handle the hotplug process and pulsing the hotplug
queue in this window breaks the guest. I've tried some hacks such as 
pulsing the queue
in the first 'event_scan' call made by the guest, but apparently it is 
still too early.


I've sent an email to the linuxppc-dev mailing list talking about this 
behavior
and asking if there is a reliable way to know when  we can safely pulse 
the hotplug
queue. Meanwhile, I'll keep working in the v3 respin of this patch in 
case this

solution of pulsing the hotplug queue ends up being not feasible.


Thanks,


Daniel

[Qemu-devel] [PATCH v2 6/9] AHCI: Replace DPRINTF with trace-events

[John Snow]

There are a few hangers-on that will be dealt with individually
in forthcoming patches.

Signed-off-by: John Snow 
---
 hw/ide/ahci.c   | 157 +++-
 hw/ide/trace-events |  49 
 2 files changed, 117 insertions(+), 89 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 406a1b5..c60a000 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -35,6 +35,7 @@
 #include "hw/ide/ahci_internal.h"
 
 #define DEBUG_AHCI 0
+#include "trace.h"
 
 #define DPRINTF(port, fmt, ...) \
 do { \
@@ -114,9 +115,9 @@ static uint32_t  ahci_port_read(AHCIState *s, int port, int 
offset)
 default:
 val = 0;
 }
-DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
-return val;
 
+trace_ahci_port_read(s, port, offset, val);
+return val;
 }
 
 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
@@ -125,7 +126,7 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
TYPE_PCI_DEVICE);
 
-DPRINTF(0, "raise irq\n");
+trace_ahci_irq_raise(s);
 
 if (pci_dev && msi_enabled(pci_dev)) {
 msi_notify(pci_dev, 0);
@@ -140,7 +141,7 @@ static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
TYPE_PCI_DEVICE);
 
-DPRINTF(0, "lower irq\n");
+trace_ahci_irq_lower(s);
 
 if (!pci_dev || !msi_enabled(pci_dev)) {
 qemu_irq_lower(s->irq);
@@ -150,8 +151,7 @@ static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
 static void ahci_check_irq(AHCIState *s)
 {
 int i;
-
-DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus);
+uint32_t old_irq = s->control_regs.irqstatus;
 
 s->control_regs.irqstatus = 0;
 for (i = 0; i < s->ports; i++) {
@@ -160,7 +160,7 @@ static void ahci_check_irq(AHCIState *s)
 s->control_regs.irqstatus |= (1 << i);
 }
 }
-
+trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus);
 if (s->control_regs.irqstatus &&
 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
 ahci_irq_raise(s, NULL);
@@ -240,7 +240,7 @@ static void  ahci_port_write(AHCIState *s, int port, int 
offset, uint32_t val)
 {
 AHCIPortRegs *pr = >dev[port].port_regs;
 
-DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
+trace_ahci_port_write(s, port, offset, val);
 switch (offset) {
 case PORT_LST_ADDR:
 pr->lst_addr = val;
@@ -341,8 +341,6 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)
 val = s->control_regs.version;
 break;
 }
-
-DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val);
 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
(addr < (AHCI_PORT_REGS_START_ADDR +
 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN {
@@ -350,6 +348,7 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)
  addr & AHCI_PORT_ADDR_OFFSET_MASK);
 }
 
+trace_ahci_mem_read_32(s, addr, val);
 return val;
 }
 
@@ -379,8 +378,7 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr, 
unsigned size)
 val = (hi << 32 | lo) >> (ofst * 8);
 }
 
-DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
-addr, val, size);
+trace_ahci_mem_read(opaque, size, addr, val);
 return val;
 }
 
@@ -390,8 +388,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr,
 {
 AHCIState *s = opaque;
 
-DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
-addr, val, size);
+trace_ahci_mem_write(s, size, addr, val);
 
 /* Only aligned reads are allowed on AHCI */
 if (addr & 3) {
@@ -401,15 +398,12 @@ static void ahci_mem_write(void *opaque, hwaddr addr,
 }
 
 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
-DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, 
val);
-
 switch (addr) {
 case HOST_CAP: /* R/WO, RO */
 /* FIXME handle R/WO */
 break;
 case HOST_CTL: /* R/W */
 if (val & HOST_CTL_RESET) {
-DPRINTF(-1, "HBA Reset\n");
 ahci_reset(s);
 } else {
 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
@@ -427,7 +421,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr,
 /* FIXME report write? */
 break;
 default:
-DPRINTF(-1, "write to unknown register 0x%x\n", 
(unsigned)addr);
+trace_ahci_mem_write_unknown(s, size, addr, val);
 }
 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
(addr < 

[Qemu-devel] [PATCH v2 8/9] AHCI: pretty-print FIS to buffer instead of stderr

[John Snow]

The current FIS printing routines dump the FIS to screen. adjust this
such that it dumps to buffer instead, then use this ability to have
FIS dump mechanisms via trace-events instead of compiled defines.

Signed-off-by: John Snow 
---
 hw/ide/ahci.c   | 54 +++--
 hw/ide/trace-events |  4 
 2 files changed, 48 insertions(+), 10 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index a0a4dd6..2e75f9b 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -644,20 +644,45 @@ static void ahci_reset_port(AHCIState *s, int port)
 ahci_init_d2h(d);
 }
 
-static void debug_print_fis(uint8_t *fis, int cmd_len)
+/* Buffer pretty output based on a raw FIS structure. */
+static void ahci_pretty_buffer_fis(uint8_t *fis, int cmd_len, char **out)
 {
-#if DEBUG_AHCI
+size_t bufsize;
+char *pbuf;
+char *pptr;
+size_t lines = DIV_ROUND_UP(cmd_len, 16);
+const char *preamble = "FIS:";
 int i;
 
-fprintf(stderr, "fis:");
+/* Total amount of memory to store FISes in HBA memory */
+g_assert_cmpint(cmd_len, <=, 0x100);
+g_assert(out);
+
+/* Printed like:
+ * FIS:\n
+ * 0x00: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee \n
+ * 0x10: ff \n
+ * \0
+ *
+ * Four bytes for the preamble, seven for each line prefix (including a
+ * newline to start a new line), three bytes for each source byte,
+ * a trailing newline and a terminal null byte.
+ */
+
+bufsize = strlen(preamble) + ((6 + 1) * lines) + (3 * cmd_len) + 1 + 1;
+pbuf = g_malloc(bufsize);
+pptr = pbuf;
+pptr += sprintf(pptr, "%s", preamble);
 for (i = 0; i < cmd_len; i++) {
 if ((i & 0xf) == 0) {
-fprintf(stderr, "\n%02x:",i);
+pptr += sprintf(pptr, "\n0x%02x: ", i);
 }
-fprintf(stderr, "%02x ",fis[i]);
+pptr += sprintf(pptr, "%02x ", fis[i]);
 }
-fprintf(stderr, "\n");
-#endif
+pptr += sprintf(pptr, "\n");
+pptr += 1; /* \0 */
+g_assert(pbuf + bufsize == pptr);
+*out = pbuf;
 }
 
 static bool ahci_map_fis_address(AHCIDevice *ad)
@@ -1201,7 +1226,12 @@ static void handle_reg_h2d_fis(AHCIState *s, int port,
  * table to ide_state->io_buffer */
 if (opts & AHCI_CMD_ATAPI) {
 memcpy(ide_state->io_buffer, _fis[AHCI_COMMAND_TABLE_ACMD], 0x10);
-debug_print_fis(ide_state->io_buffer, 0x10);
+if (TRACE_HANDLE_REG_H2D_FIS_DUMP_ENABLED) {
+char *pretty_fis;
+ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10, _fis);
+trace_handle_reg_h2d_fis_dump(s, port, pretty_fis);
+g_free(pretty_fis);
+}
 s->dev[port].done_atapi_packet = false;
 /* XXX send PIO setup FIS */
 }
@@ -1256,8 +1286,12 @@ static int handle_cmd(AHCIState *s, int port, uint8_t 
slot)
 trace_handle_cmd_badmap(s, port, cmd_len);
 goto out;
 }
-debug_print_fis(cmd_fis, 0x80);
-
+if (TRACE_HANDLE_CMD_FIS_DUMP_ENABLED) {
+char *pretty_fis;
+ahci_pretty_buffer_fis(cmd_fis, 0x80, _fis);
+trace_handle_cmd_fis_dump(s, port, pretty_fis);
+g_free(pretty_fis);
+}
 switch (cmd_fis[0]) {
 case SATA_FIS_TYPE_REGISTER_H2D:
 handle_reg_h2d_fis(s, port, slot, cmd_fis);
diff --git a/hw/ide/trace-events b/hw/ide/trace-events
index e15fd77..77ed3c1 100644
--- a/hw/ide/trace-events
+++ b/hw/ide/trace-events
@@ -105,3 +105,7 @@ ahci_cmd_done(void *s, int port) "ahci(%p)[%d]: cmd done"
 ahci_reset(void *s) "ahci(%p): HBA reset"
 allwinner_ahci_mem_read(void *s, void *a, uint64_t addr, uint64_t val, 
unsigned size) "ahci(%p): read a=%p addr=0x%"HWADDR_PRIx" val=0x%"PRIx64", 
size=%d"
 allwinner_ahci_mem_write(void *s, void *a, uint64_t addr, uint64_t val, 
unsigned size) "ahci(%p): write a=%p addr=0x%"HWADDR_PRIx" val=0x%"PRIx64", 
size=%d"
+
+# Warning: Verbose
+handle_reg_h2d_fis_dump(void *s, int port, char *fis) "ahci(%p)[%d]: %s"
+handle_cmd_fis_dump(void *s, int port, char *fis) "ahci(%p)[%d]: %s"
-- 
2.9.5

Re: [Qemu-devel] Persistent bitmaps for non-qcow2 formats

[John Snow]

On 08/29/2017 10:30 AM, Eric Blake wrote:
> On 08/28/2017 08:18 PM, John Snow wrote:
 We'd have to develop a new syntax for specifying these resources that
 can be stored in a qcow2 file,
>>>
>>> It's called the json-pseudo-protocol and was developed exactly for this.
>>>
>>
>> That's what I was hinting at for "or otherwise co-opt an existing
>> syntax" but I was unaware that it was intended for "exactly" this.
>>
>> Do we actually use it in any on-disk format, currently? qcow2 only lets
>> you specify simple filenames in the qcow2 metadata, right?
> 
> You can specify json-pseudo backing names both on the command line AND
> embedded in the qcow2 file itself (within the length limits imposed by
> the qcow2 header size).  Yes, this means it is already possible to
> create qcow2 files that can only be opened by qemu (or else teaching
> your alternative program how to parse qemu's json-pseudo-protocol).
> 
>>
or otherwise co-opt an existing syntax
 in-use by QEMU. This syntax would likely be useful only to QEMU, which
 would steer the qcow2 format in a direction not too useful by other
 emulators, and qcow2 is an open format, so we may want to avoid this.
>>>
>>> Storing a file name in the backing link field that cannot be interpreted
>>> by other programs is in my opinion still very much better than not
>>> storing any information whatsoever, because in the former case other
>>> programs can at least say "sorry, I have no idea what this means" (or
>>> maybe they can indeed interpret it, who knows), whereas in the latter
>>> they may not even know that the qcow2 image is incomplete.
>>>
>>
>> I don't disagree personally, but I seem to recall that Kevin was adamant
>> that the qcow2 bitmap extension should remain useful and semantically
>> meaningful to third parties, so I try to keep that in mind. Maybe I
>> should let him chime in instead of try to "concern troll" my own
>> suggestions into the ground.
> 
> We already have that situation today, but you are right to worry about
> whether making it even more prevalent is something we can try to minimize.
> 

Proposal distillate:

(1) Specify relationship on CLI, QCOW becomes a bitmap-child of any
arbitrary node.

Pros: Easy to implement
  Adds bitmap support to literally everything
Cons: Bitmap has no semantic link to data it describes
  Relationship must be re-specified every launch
  Max and Kevin are firmly NACK

(2) Raw file becomes a R/W backing file of the QCOW2, implemented as
either a bitmap-child or a more traditional backing file that can
additionally service writes

Pros: Easy to understand
  relationship between files exists outside of the QEMU process
  Adds bitmap support to just about everything that can be expressed
via JSON
Cons: All but necessitates QEMU-specific syntax in a qcow2 file
  Depending on implementation, possibly messy in bdrv_open
  Adding bitmaps to non-qcow2 files after open makes the launch CLI
invalid for future launches (Not any different to snapshots.)

(3) Add a raw-like mapping mode to QCOW2 instead, skipping the whole affair

Pros: Adds a nice, performant hybrid mode to qcow2
  Solves the problem of "bitmaps for raw" more or less
  Avoids bdrv_open() complications
  Avoids writing qemu-specific jargon in qcow2 files
Cons: Doesn't actually add arbitrary bitmaps to any file format
  Users are still gonna ask for bitmaps for other formats anyway



I think I like 2 or 3 -- or perhaps indeed two AND three. The qcow2-raw
mode sounds like something we ought to have anyway. I'll try to start an
RFC.

--js

Re: [Qemu-devel] [PATCH 0/8] tcg/s390 improvements

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20170829204759.6853-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PATCH 0/8] tcg/s390 improvements
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]patchew/20170829122745.14309-1-stefa...@redhat.com 
-> patchew/20170829122745.14309-1-stefa...@redhat.com
 * [new tag]   
patchew/20170829204759.6853-1-richard.hender...@linaro.org -> 
patchew/20170829204759.6853-1-richard.hender...@linaro.org
Switched to a new branch 'test'
efce52d267 tcg/s390: Use slbgr for setcond le and leu
35fae2aa5d tcg/s390: Use load-on-condition-2 facility
9ae14e93ab tcg/s390: Use distinct-operands facility
67d4b767e5 tcg/s390: Merge ori+xori facilities check to tcg_target_op_def
5a46cf248f tcg/s390: Merge add2i facilities check to tcg_target_op_def
f646646dd5 tcg/s390: Merge muli facilities check to tcg_target_op_def
c4698e87bb tcg/s390: Merge cmpi facilities check to tcg_target_op_def
4f75b31839 tcg/s390: Fully convert tcg_target_op_def

=== OUTPUT BEGIN ===
Checking PATCH 1/8: tcg/s390: Fully convert tcg_target_op_def...
Checking PATCH 2/8: tcg/s390: Merge cmpi facilities check to 
tcg_target_op_def...
ERROR: return is not a function, parentheses are not required
#104: FILE: tcg/s390/tcg-target.inc.c:2308:
+return (s390_facilities & FACILITY_EXT_IMM ? _ri : _rZ);

ERROR: return is not a function, parentheses are not required
#107: FILE: tcg/s390/tcg-target.inc.c:2310:
+return (s390_facilities & FACILITY_EXT_IMM ? _rC : _rZ);

ERROR: return is not a function, parentheses are not required
#122: FILE: tcg/s390/tcg-target.inc.c:2360:
+return (s390_facilities & FACILITY_EXT_IMM ? _c : _z);

ERROR: return is not a function, parentheses are not required
#134: FILE: tcg/s390/tcg-target.inc.c:2370:
+return (s390_facilities & FACILITY_EXT_IMM ? _c : _z);

total: 4 errors, 0 warnings, 118 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 3/8: tcg/s390: Merge muli facilities check to 
tcg_target_op_def...
ERROR: return is not a function, parentheses are not required
#87: FILE: tcg/s390/tcg-target.inc.c:2281:
+return (s390_facilities & FACILITY_GEN_INST_EXT ? _0_ri : _0_rI);

ERROR: return is not a function, parentheses are not required
#90: FILE: tcg/s390/tcg-target.inc.c:2283:
+return (s390_facilities & FACILITY_GEN_INST_EXT ? _0_rJ : _0_rI);

total: 2 errors, 0 warnings, 77 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 4/8: tcg/s390: Merge add2i facilities check to 
tcg_target_op_def...
ERROR: return is not a function, parentheses are not required
#84: FILE: tcg/s390/tcg-target.inc.c:2387:
+return (s390_facilities & FACILITY_EXT_IMM ? _ri : _r);

ERROR: return is not a function, parentheses are not required
#92: FILE: tcg/s390/tcg-target.inc.c:2390:
+return (s390_facilities & FACILITY_EXT_IMM ? _rA : _r);

total: 2 errors, 0 warnings, 77 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 5/8: tcg/s390: Merge ori+xori facilities check to 
tcg_target_op_def...
ERROR: return is not a function, parentheses are not required
#140: FILE: tcg/s390/tcg-target.inc.c:2229:
+return (s390_facilities & FACILITY_EXT_IMM

ERROR: return is not a function, parentheses are not required
#145: FILE: tcg/s390/tcg-target.inc.c:2233:
+return (s390_facilities & FACILITY_EXT_IMM

ERROR: return is not a function, parentheses are not required
#152: FILE: tcg/s390/tcg-target.inc.c:2240:
+return (s390_facilities & FACILITY_EXT_IMM

ERROR: return is not a function, parentheses are not required
#157: FILE: tcg/s390/tcg-target.inc.c:2244:
+return (s390_facilities & FACILITY_EXT_IMM

total: 4 errors, 0 warnings, 144 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 6/8: tcg/s390: Use distinct-operands facility...
ERROR: return is not a 

[Qemu-devel] [PATCH v2 4/9] ATAPI: Replace DEBUG_IDE_ATAPI with tracing events

[John Snow]

Goodbye, printfs.
Hello, fancy printfs.

Signed-off-by: John Snow 
---
 hw/ide/atapi.c| 64 +--
 hw/ide/trace-events   | 15 +++
 include/hw/ide/internal.h |  1 -
 3 files changed, 38 insertions(+), 42 deletions(-)

diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c
index fc1d19c..37fa699 100644
--- a/hw/ide/atapi.c
+++ b/hw/ide/atapi.c
@@ -27,6 +27,7 @@
 #include "hw/ide/internal.h"
 #include "hw/scsi/scsi.h"
 #include "sysemu/block-backend.h"
+#include "trace.h"
 
 #define ATAPI_SECTOR_BITS (2 + BDRV_SECTOR_BITS)
 #define ATAPI_SECTOR_SIZE (1 << ATAPI_SECTOR_BITS)
@@ -116,9 +117,7 @@ cd_read_sector_sync(IDEState *s)
 block_acct_start(blk_get_stats(s->blk), >acct,
  ATAPI_SECTOR_SIZE, BLOCK_ACCT_READ);
 
-#ifdef DEBUG_IDE_ATAPI
-printf("cd_read_sector_sync: lba=%d\n", s->lba);
-#endif
+trace_cd_read_sector_sync(s->lba);
 
 switch (s->cd_sector_size) {
 case 2048:
@@ -152,9 +151,7 @@ static void cd_read_sector_cb(void *opaque, int ret)
 {
 IDEState *s = opaque;
 
-#ifdef DEBUG_IDE_ATAPI
-printf("cd_read_sector_cb: lba=%d ret=%d\n", s->lba, ret);
-#endif
+trace_cd_read_sector_cb(s->lba, ret);
 
 if (ret < 0) {
 block_acct_failed(blk_get_stats(s->blk), >acct);
@@ -188,9 +185,7 @@ static int cd_read_sector(IDEState *s)
 s->iov.iov_len = ATAPI_SECTOR_SIZE;
 qemu_iovec_init_external(>qiov, >iov, 1);
 
-#ifdef DEBUG_IDE_ATAPI
-printf("cd_read_sector: lba=%d\n", s->lba);
-#endif
+trace_cd_read_sector(s->lba);
 
 block_acct_start(blk_get_stats(s->blk), >acct,
  ATAPI_SECTOR_SIZE, BLOCK_ACCT_READ);
@@ -213,9 +208,7 @@ void ide_atapi_cmd_ok(IDEState *s)
 
 void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
 {
-#ifdef DEBUG_IDE_ATAPI
-printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
-#endif
+trace_ide_atapi_cmd_error(s, sense_key, asc);
 s->error = sense_key << 4;
 s->status = READY_STAT | ERR_STAT;
 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
@@ -252,19 +245,14 @@ static uint16_t atapi_byte_count_limit(IDEState *s)
 void ide_atapi_cmd_reply_end(IDEState *s)
 {
 int byte_count_limit, size, ret;
-#ifdef DEBUG_IDE_ATAPI
-printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
-   s->packet_transfer_size,
-   s->elementary_transfer_size,
-   s->io_buffer_index);
-#endif
+trace_ide_atapi_cmd_reply_end(s, s->packet_transfer_size,
+  s->elementary_transfer_size,
+  s->io_buffer_index);
 if (s->packet_transfer_size <= 0) {
 /* end of transfer */
 ide_atapi_cmd_ok(s);
 ide_set_irq(s->bus);
-#ifdef DEBUG_IDE_ATAPI
-printf("end of transfer, status=0x%x\n", s->status);
-#endif
+trace_ide_atapi_cmd_reply_end_eot(s, s->status);
 } else {
 /* see if a new sector must be read */
 if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) {
@@ -300,9 +288,7 @@ void ide_atapi_cmd_reply_end(IDEState *s)
 /* a new transfer is needed */
 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
 byte_count_limit = atapi_byte_count_limit(s);
-#ifdef DEBUG_IDE_ATAPI
-printf("byte_count_limit=%d\n", byte_count_limit);
-#endif
+trace_ide_atapi_cmd_reply_end_bcl(s, byte_count_limit);
 size = s->packet_transfer_size;
 if (size > byte_count_limit) {
 /* byte count limit must be even if this case */
@@ -324,9 +310,7 @@ void ide_atapi_cmd_reply_end(IDEState *s)
 ide_transfer_start(s, s->io_buffer + s->io_buffer_index - size,
size, ide_atapi_cmd_reply_end);
 ide_set_irq(s->bus);
-#ifdef DEBUG_IDE_ATAPI
-printf("status=0x%x\n", s->status);
-#endif
+trace_ide_atapi_cmd_reply_end_new(s, s->status);
 }
 }
 }
@@ -368,9 +352,7 @@ static void ide_atapi_cmd_read_pio(IDEState *s, int lba, 
int nb_sectors,
 
 static void ide_atapi_cmd_check_status(IDEState *s)
 {
-#ifdef DEBUG_IDE_ATAPI
-printf("atapi_cmd_check_status\n");
-#endif
+trace_ide_atapi_cmd_check_status(s);
 s->error = MC_ERR | (UNIT_ATTENTION << 4);
 s->status = ERR_STAT;
 s->nsector = 0;
@@ -477,10 +459,8 @@ static void ide_atapi_cmd_read_dma(IDEState *s, int lba, 
int nb_sectors,
 static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors,
int sector_size)
 {
-#ifdef DEBUG_IDE_ATAPI
-printf("read %s: LBA=%d nb_sectors=%d\n", s->atapi_dma ? "dma" : "pio",
-lba, nb_sectors);
-#endif
+trace_ide_atapi_cmd_read(s, s->atapi_dma ? "dma" : "pio",
+ lba, nb_sectors);
 if (s->atapi_dma) {
 ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size);
 } else {
@@ -1330,16 +1310,18 @@ 

[Qemu-devel] [PATCH 7/8] tcg/s390: Use load-on-condition-2 facility

[Richard Henderson]

From: Richard Henderson 

This allows LOAD HALFWORD IMMEDIATE ON CONDITION,
eliminating one insn in some common cases.

Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target.h |  1 +
 tcg/s390/tcg-target.inc.c | 79 +--
 2 files changed, 63 insertions(+), 17 deletions(-)

diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 1b5eb22c26..81fc179459 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -59,6 +59,7 @@ typedef enum TCGReg {
 #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))
 #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
 #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND
+#define FACILITY_LOAD_ON_COND2(1ULL << (63 - 53))
 
 extern uint64_t s390_facilities;
 
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index a80b07db65..0de968fde2 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -122,6 +122,7 @@ typedef enum S390Opcode {
 RIE_CLGIJ   = 0xec7d,
 RIE_CLRJ= 0xec77,
 RIE_CRJ = 0xec76,
+RIE_LOCGHI  = 0xec46,
 RIE_RISBG   = 0xec55,
 
 RRE_AGR = 0xb908,
@@ -495,6 +496,13 @@ static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, 
TCGReg r1, int i2)
 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0x));
 }
 
+static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1,
+ int i2, int m3)
+{
+tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
+tcg_out32(s, (i2 << 16) | (op & 0xff));
+}
+
 static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
 {
 tcg_out16(s, op | (r1 << 4));
@@ -1063,7 +1071,20 @@ static void tgen_setcond(TCGContext *s, TCGType type, 
TCGCond cond,
  TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
 {
 int cc;
+bool have_loc;
 
+/* With LOC2, we can always emit the minimum 3 insns.  */
+if (s390_facilities & FACILITY_LOAD_ON_COND2) {
+/* Emit: d = 0, d = (cc ? 1 : d).  */
+cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
+tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
+tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc);
+return;
+}
+
+have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0;
+
+/* For HAVE_LOC, only the path through do_greater is smaller.  */
 switch (cond) {
 case TCG_COND_GTU:
 case TCG_COND_GT:
@@ -1076,6 +1097,9 @@ static void tgen_setcond(TCGContext *s, TCGType type, 
TCGCond cond,
 return;
 
 case TCG_COND_GEU:
+if (have_loc) {
+goto do_loc;
+}
 do_geu:
 /* We need "real" carry semantics, so use SUBTRACT LOGICAL
instead of COMPARE LOGICAL.  This may need an extra move.  */
@@ -1105,10 +1129,17 @@ static void tgen_setcond(TCGContext *s, TCGType type, 
TCGCond cond,
 return;
 
 case TCG_COND_LEU:
+if (have_loc) {
+goto do_loc;
+}
+/* fallthru */
 case TCG_COND_LTU:
 case TCG_COND_LT:
 /* Swap operands so that we can use GEU/GTU/GT.  */
 if (c2const) {
+if (have_loc) {
+goto do_loc;
+}
 tcg_out_movi(s, type, TCG_TMP0, c2);
 c2 = c1;
 c2const = 0;
@@ -1133,6 +1164,9 @@ static void tgen_setcond(TCGContext *s, TCGType type, 
TCGCond cond,
 break;
 
 case TCG_COND_EQ:
+if (have_loc) {
+goto do_loc;
+}
 /* X == 0 is X <= 0 is 0 >= X.  */
 if (c2const && c2 == 0) {
 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0);
@@ -1148,33 +1182,39 @@ static void tgen_setcond(TCGContext *s, TCGType type, 
TCGCond cond,
 }
 
 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
-if (s390_facilities & FACILITY_LOAD_ON_COND) {
-/* Emit: d = 0, t = 1, d = (cc ? t : d).  */
-tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
-tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
-tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
-} else {
-/* Emit: d = 1; if (cc) goto over; d = 0; over:  */
-tcg_out_movi(s, type, dest, 1);
-tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
-tcg_out_movi(s, type, dest, 0);
-}
+/* Emit: d = 1; if (cc) goto over; d = 0; over:  */
+tcg_out_movi(s, type, dest, 1);
+tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
+tcg_out_movi(s, type, dest, 0);
+return;
+
+ do_loc:
+cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
+/* Emit: d = 0, t = 1, d = (cc ? t : d).  */
+tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
+tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
+tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
 }
 
 static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
- TCGReg c1, TCGArg c2, int c2const, TCGReg r3)
+ TCGReg c1, TCGArg c2, int 

[Qemu-devel] [PATCH v2 7/9] AHCI: Rework IRQ constants

[John Snow]

Create a new enum so that we can name the IRQ bits, which will make debugging
them a little nicer if we can print them out. Not handled in this patch, but
this will make it possible to get a nice debug printf detailing exactly which
status bits are set, as it can be multiple at any given time.

As a consequence of this patch, it is no longer possible to set multiple IRQ
codes at once, but nothing was utilizing this ability anyway.

Signed-off-by: John Snow 
---
 hw/ide/ahci.c  | 49 ++---
 hw/ide/ahci_internal.h | 44 +++-
 hw/ide/trace-events|  2 +-
 3 files changed, 74 insertions(+), 21 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index c60a000..a0a4dd6 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -56,6 +56,27 @@ static bool ahci_map_fis_address(AHCIDevice *ad);
 static void ahci_unmap_clb_address(AHCIDevice *ad);
 static void ahci_unmap_fis_address(AHCIDevice *ad);
 
+static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__END] = {
+[AHCI_PORT_IRQ_BIT_DHRS] = "DHRS",
+[AHCI_PORT_IRQ_BIT_PSS]  = "PSS",
+[AHCI_PORT_IRQ_BIT_DSS]  = "DSS",
+[AHCI_PORT_IRQ_BIT_SDBS] = "SDBS",
+[AHCI_PORT_IRQ_BIT_UFS]  = "UFS",
+[AHCI_PORT_IRQ_BIT_DPS]  = "DPS",
+[AHCI_PORT_IRQ_BIT_PCS]  = "PCS",
+[AHCI_PORT_IRQ_BIT_DMPS] = "DMPS",
+[8 ... 21]   = "RESERVED",
+[AHCI_PORT_IRQ_BIT_PRCS] = "PRCS",
+[AHCI_PORT_IRQ_BIT_IPMS] = "IPMS",
+[AHCI_PORT_IRQ_BIT_OFS]  = "OFS",
+[25] = "RESERVED",
+[AHCI_PORT_IRQ_BIT_INFS] = "INFS",
+[AHCI_PORT_IRQ_BIT_IFS]  = "IFS",
+[AHCI_PORT_IRQ_BIT_HBDS] = "HBDS",
+[AHCI_PORT_IRQ_BIT_HBFS] = "HBFS",
+[AHCI_PORT_IRQ_BIT_TFES] = "TFES",
+[AHCI_PORT_IRQ_BIT_CPDS] = "CPDS"
+};
 
 static uint32_t  ahci_port_read(AHCIState *s, int port, int offset)
 {
@@ -170,12 +191,18 @@ static void ahci_check_irq(AHCIState *s)
 }
 
 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
- int irq_type)
+ enum AHCIPortIRQ irqbit)
 {
-DPRINTF(d->port_no, "trigger irq %#x -> %x\n",
-irq_type, d->port_regs.irq_mask & irq_type);
+g_assert(irqbit >= 0 && irqbit < 32);
+uint32_t irq = 1U << irqbit;
+uint32_t irqstat = d->port_regs.irq_stat | irq;
 
-d->port_regs.irq_stat |= irq_type;
+trace_ahci_trigger_irq(s, d->port_no,
+   AHCIPortIRQ_lookup[irqbit], irq,
+   d->port_regs.irq_stat, irqstat,
+   irqstat & d->port_regs.irq_mask);
+
+d->port_regs.irq_stat = irqstat;
 ahci_check_irq(s);
 }
 
@@ -718,7 +745,7 @@ static void ahci_write_fis_sdb(AHCIState *s, 
NCQTransferState *ncq_tfs)
 
 /* Trigger IRQ if interrupt bit is set (which currently, it always is) */
 if (sdb_fis->flags & 0x40) {
-ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS);
+ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS);
 }
 }
 
@@ -761,10 +788,10 @@ static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t 
len)
 ad->port.ifs[0].status;
 
 if (pio_fis[2] & ERR_STAT) {
-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
 }
 
-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS);
+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);
 }
 
 static bool ahci_write_fis_d2h(AHCIDevice *ad)
@@ -804,10 +831,10 @@ static bool ahci_write_fis_d2h(AHCIDevice *ad)
 ad->port.ifs[0].status;
 
 if (d2h_fis[2] & ERR_STAT) {
-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
 }
 
-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);
+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS);
 return true;
 }
 
@@ -1082,7 +1109,7 @@ static void process_ncq_command(AHCIState *s, int port, 
uint8_t *cmd_fis,
  "is smaller than the requested size (0x%zx)",
  ncq_tfs->sglist.size, size);
 ncq_err(ncq_tfs);
-ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW);
+ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS);
 return;
 } else if (ncq_tfs->sglist.size != size) {
 trace_process_ncq_command_large(s, port, tag,
@@ -1225,7 +1252,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t 
slot)
 trace_handle_cmd_badfis(s, port);
 return -1;
 } else if (cmd_len != 0x80) {
-ahci_trigger_irq(s, >dev[port], PORT_IRQ_HBUS_ERR);
+ahci_trigger_irq(s, >dev[port], AHCI_PORT_IRQ_BIT_HBFS);
 trace_handle_cmd_badmap(s, port, cmd_len);
 goto out;
 }
diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h
index 1e21169..7e67add 100644
--- a/hw/ide/ahci_internal.h
+++ b/hw/ide/ahci_internal.h
@@ -91,6 +91,31 @@
 #define PORT_CMD_ISSUE0x38 /* command 

[Qemu-devel] [PATCH v2 3/9] IDE: add tracing for data ports

[John Snow]

To be used sparingly, but still interesting in the case of small
firmwares designed to reproduce bugs in QEMU IDE.

Signed-off-by: John Snow 
---
 hw/ide/core.c   | 12 +++-
 hw/ide/trace-events |  5 +
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/hw/ide/core.c b/hw/ide/core.c
index cb250e6..82a19b1 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -2259,6 +2259,8 @@ void ide_data_writew(void *opaque, uint32_t addr, 
uint32_t val)
 IDEState *s = idebus_active_if(bus);
 uint8_t *p;
 
+trace_ide_data_writew(addr, val, bus, s);
+
 /* PIO data access allowed only when DRQ bit is set. The result of a write
  * during PIO out is indeterminate, just ignore it. */
 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
@@ -2304,6 +2306,8 @@ uint32_t ide_data_readw(void *opaque, uint32_t addr)
 s->status &= ~DRQ_STAT;
 s->end_transfer_func(s);
 }
+
+trace_ide_data_readw(addr, ret, bus, s);
 return ret;
 }
 
@@ -2313,6 +2317,8 @@ void ide_data_writel(void *opaque, uint32_t addr, 
uint32_t val)
 IDEState *s = idebus_active_if(bus);
 uint8_t *p;
 
+trace_ide_data_writel(addr, val, bus, s);
+
 /* PIO data access allowed only when DRQ bit is set. The result of a write
  * during PIO out is indeterminate, just ignore it. */
 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
@@ -2343,7 +2349,8 @@ uint32_t ide_data_readl(void *opaque, uint32_t addr)
 /* PIO data access allowed only when DRQ bit is set. The result of a read
  * during PIO in is indeterminate, return 0 and don't move forward. */
 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
-return 0;
+ret = 0;
+goto out;
 }
 
 p = s->data_ptr;
@@ -2358,6 +2365,9 @@ uint32_t ide_data_readl(void *opaque, uint32_t addr)
 s->status &= ~DRQ_STAT;
 s->end_transfer_func(s);
 }
+
+out:
+trace_ide_data_readl(addr, ret, bus, s);
 return ret;
 }
 
diff --git a/hw/ide/trace-events b/hw/ide/trace-events
index bff8f39..17bc6f1 100644
--- a/hw/ide/trace-events
+++ b/hw/ide/trace-events
@@ -6,6 +6,11 @@ ide_ioport_read(uint32_t addr, const char *reg, uint32_t val, 
void *bus, void *s
 ide_ioport_write(uint32_t addr, const char *reg, uint32_t val, void *bus, void 
*s) "IDE PIO wr @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState %p"
 ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s)   
"IDE PIO rd @ 0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p; IDEState 
%p"
 ide_cmd_write(uint32_t addr, uint32_t val, void *bus)  
"IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus %p"
+# Warning: verbose
+ide_data_readw(uint32_t addr, uint32_t val, void *bus, void *s)
"IDE PIO rd @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p; IDEState 
%p"
+ide_data_writew(uint32_t addr, uint32_t val, void *bus, void *s)   
"IDE PIO wr @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p; IDEState 
%p"
+ide_data_readl(uint32_t addr, uint32_t val, void *bus, void *s)
"IDE PIO rd @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState 
%p"
+ide_data_writel(uint32_t addr, uint32_t val, void *bus, void *s)   
"IDE PIO wr @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState 
%p"
 # misc
 ide_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; 
state %p; cmd 0x%02x"
 ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffered 
request %p with -ECANCELED"
-- 
2.9.5

[Qemu-devel] [PATCH v2 1/9] IDE: replace DEBUG_IDE with tracing system

[John Snow]

Remove the DEBUG_IDE preprocessor definition with something more
appropriately flexible, using the trace-events subsystem.

This will be less prone to bitrot and will more effectively allow
us to target just the functions we care about.

Signed-off-by: John Snow 
Reviewed-by: Eric Blake 
---
 Makefile.objs |  1 +
 hw/ide/cmd646.c   | 10 +++-
 hw/ide/core.c | 65 +++
 hw/ide/pci.c  | 17 -
 hw/ide/piix.c | 11 
 hw/ide/trace-events   | 35 +
 hw/ide/via.c  | 10 +++-
 include/hw/ide/internal.h |  1 -
 8 files changed, 80 insertions(+), 70 deletions(-)
 create mode 100644 hw/ide/trace-events

diff --git a/Makefile.objs b/Makefile.objs
index 24a4ea0..967c092 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -153,6 +153,7 @@ trace-events-subdirs += hw/acpi
 trace-events-subdirs += hw/arm
 trace-events-subdirs += hw/alpha
 trace-events-subdirs += hw/xen
+trace-events-subdirs += hw/ide
 trace-events-subdirs += ui
 trace-events-subdirs += audio
 trace-events-subdirs += net
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 9ebb8d4..86b2a8f 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -32,6 +32,7 @@
 #include "sysemu/dma.h"
 
 #include "hw/ide/pci.h"
+#include "trace.h"
 
 /* CMD646 specific */
 #define CFR0x50
@@ -195,9 +196,8 @@ static uint64_t bmdma_read(void *opaque, hwaddr addr,
 val = 0xff;
 break;
 }
-#ifdef DEBUG_IDE
-printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
-#endif
+
+trace_bmdma_read_cmd646(addr, val);
 return val;
 }
 
@@ -211,9 +211,7 @@ static void bmdma_write(void *opaque, hwaddr addr,
 return;
 }
 
-#ifdef DEBUG_IDE
-printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
-#endif
+trace_bmdma_write_cmd646(addr, val);
 switch(addr & 3) {
 case 0:
 bmdma_cmd_writeb(bm, val);
diff --git a/hw/ide/core.c b/hw/ide/core.c
index bea3953..31fd593 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -36,6 +36,7 @@
 #include "qemu/cutils.h"
 
 #include "hw/ide/internal.h"
+#include "trace.h"
 
 /* These values were based on a Seagate ST3500418AS but have been modified
to make more sense in QEMU */
@@ -656,10 +657,7 @@ void ide_cancel_dma_sync(IDEState *s)
  * write requests) pending and we can avoid to drain. */
 QLIST_FOREACH(req, >buffered_requests, list) {
 if (!req->orphaned) {
-#ifdef DEBUG_IDE
-printf("%s: invoking cb %p of buffered request %p with"
-   " -ECANCELED\n", __func__, req->original_cb, req);
-#endif
+trace_ide_cancel_dma_sync_buffered(req->original_cb, req);
 req->original_cb(req->original_opaque, -ECANCELED);
 }
 req->orphaned = true;
@@ -678,9 +676,7 @@ void ide_cancel_dma_sync(IDEState *s)
  * aio operation with preadv/pwritev.
  */
 if (s->bus->dma->aiocb) {
-#ifdef DEBUG_IDE
-printf("%s: draining all remaining requests", __func__);
-#endif
+trace_ide_cancel_dma_sync_remaining();
 blk_drain(s->blk);
 assert(s->bus->dma->aiocb == NULL);
 }
@@ -741,9 +737,7 @@ static void ide_sector_read(IDEState *s)
 n = s->req_nb_sectors;
 }
 
-#if defined(DEBUG_IDE)
-printf("sector=%" PRId64 "\n", sector_num);
-#endif
+trace_ide_sector_read(sector_num, n);
 
 if (!ide_sect_range_ok(s, sector_num, n)) {
 ide_rw_error(s);
@@ -1005,14 +999,14 @@ static void ide_sector_write(IDEState *s)
 
 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
 sector_num = ide_get_sector(s);
-#if defined(DEBUG_IDE)
-printf("sector=%" PRId64 "\n", sector_num);
-#endif
+
 n = s->nsector;
 if (n > s->req_nb_sectors) {
 n = s->req_nb_sectors;
 }
 
+trace_ide_sector_write(sector_num, n);
+
 if (!ide_sect_range_ok(s, sector_num, n)) {
 ide_rw_error(s);
 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
@@ -1194,18 +1188,17 @@ static void ide_clear_hob(IDEBus *bus)
 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 {
 IDEBus *bus = opaque;
+IDEState *s = idebus_active_if(bus);
+int reg_num = addr & 7;
 
-#ifdef DEBUG_IDE
-printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
-#endif
-
-addr &= 7;
+trace_ide_ioport_write(addr, val, bus, s);
 
 /* ignore writes to command block while busy with previous command */
-if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
+if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) {
 return;
+}
 
-switch(addr) {
+switch (reg_num) {
 case 0:
 break;
 case 1:
@@ -1261,9 +1254,7 @@ void ide_ioport_write(void *opaque, uint32_t addr, 
uint32_t val)
 
 static void ide_reset(IDEState *s)
 {
-#ifdef DEBUG_IDE
-printf("ide: reset\n");

[Qemu-devel] [PATCH 6/8] tcg/s390: Use distinct-operands facility

[Richard Henderson]

From: Richard Henderson 

This allows using a 3-operand insn form for some arithmetic,
logicals and shifts.

Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target.h |   1 +
 tcg/s390/tcg-target.inc.c | 118 +++---
 2 files changed, 91 insertions(+), 28 deletions(-)

diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 957f0c0afe..1b5eb22c26 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -58,6 +58,7 @@ typedef enum TCGReg {
 #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))
 #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))
 #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
+#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND
 
 extern uint64_t s390_facilities;
 
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 5414c9d879..a80b07db65 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -159,6 +159,16 @@ typedef enum S390Opcode {
 
 RRF_LOCR= 0xb9f2,
 RRF_LOCGR   = 0xb9e2,
+RRF_NRK = 0xb9f4,
+RRF_NGRK= 0xb9e4,
+RRF_ORK = 0xb9f6,
+RRF_OGRK= 0xb9e6,
+RRF_SRK = 0xb9f9,
+RRF_SGRK= 0xb9e9,
+RRF_SLRK= 0xb9fb,
+RRF_SLGRK   = 0xb9eb,
+RRF_XRK = 0xb9f7,
+RRF_XGRK= 0xb9e7,
 
 RR_AR   = 0x1a,
 RR_ALR  = 0x1e,
@@ -179,8 +189,11 @@ typedef enum S390Opcode {
 RSY_RLL = 0xeb1d,
 RSY_RLLG= 0xeb1c,
 RSY_SLLG= 0xeb0d,
+RSY_SLLK= 0xebdf,
 RSY_SRAG= 0xeb0a,
+RSY_SRAK= 0xebdc,
 RSY_SRLG= 0xeb0c,
+RSY_SRLK= 0xebde,
 
 RS_SLL  = 0x89,
 RS_SRA  = 0x8a,
@@ -1065,23 +1078,29 @@ static void tgen_setcond(TCGContext *s, TCGType type, 
TCGCond cond,
 case TCG_COND_GEU:
 do_geu:
 /* We need "real" carry semantics, so use SUBTRACT LOGICAL
-   instead of COMPARE LOGICAL.  This needs an extra move.  */
-tcg_out_mov(s, type, TCG_TMP0, c1);
+   instead of COMPARE LOGICAL.  This may need an extra move.  */
 if (c2const) {
-tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
+tcg_out_mov(s, type, TCG_TMP0, c1);
 if (type == TCG_TYPE_I32) {
 tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2);
 } else {
 tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2);
 }
+} else if (s390_facilities & FACILITY_DISTINCT_OPS) {
+if (type == TCG_TYPE_I32) {
+tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2);
+} else {
+tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2);
+}
 } else {
+tcg_out_mov(s, type, TCG_TMP0, c1);
 if (type == TCG_TYPE_I32) {
 tcg_out_insn(s, RR, SLR, TCG_TMP0, c2);
 } else {
 tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2);
 }
-tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
 }
+tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
 tcg_out_insn(s, RRE, ALCGR, dest, dest);
 return;
 
@@ -1648,7 +1667,7 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg 
data_reg, TCGReg addr_reg,
 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
 const TCGArg *args, const int *const_args)
 {
-S390Opcode op;
+S390Opcode op, op2;
 TCGArg a0, a1, a2;
 
 switch (opc) {
@@ -1753,29 +1772,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode 
opc,
 if (const_args[2]) {
 a2 = -a2;
 goto do_addi_32;
+} else if (a0 == a1) {
+tcg_out_insn(s, RR, SR, a0, a2);
+} else {
+tcg_out_insn(s, RRF, SRK, a0, a1, a2);
 }
-tcg_out_insn(s, RR, SR, args[0], args[2]);
 break;
 
 case INDEX_op_and_i32:
+a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
 if (const_args[2]) {
-tgen_andi(s, TCG_TYPE_I32, args[0], args[2]);
+tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+tgen_andi(s, TCG_TYPE_I32, a0, a2);
+} else if (a0 == a1) {
+tcg_out_insn(s, RR, NR, a0, a2);
 } else {
-tcg_out_insn(s, RR, NR, args[0], args[2]);
+tcg_out_insn(s, RRF, NRK, a0, a1, a2);
 }
 break;
 case INDEX_op_or_i32:
+a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
 if (const_args[2]) {
-tgen64_ori(s, args[0], args[2] & 0x);
+tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+tgen64_ori(s, a0, a2);
+} else if (a0 == a1) {
+tcg_out_insn(s, RR, OR, a0, a2);
 } else {
-tcg_out_insn(s, RR, OR, args[0], args[2]);
+tcg_out_insn(s, RRF, ORK, a0, a1, a2);
 }
 break;
 case INDEX_op_xor_i32:
+a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
 if (const_args[2]) {
-

[Qemu-devel] [PATCH v2 5/9] IDE: replace DEBUG_AIO with trace events

[John Snow]

Signed-off-by: John Snow 
---
 hw/ide/atapi.c|  5 +
 hw/ide/core.c | 17 ++---
 hw/ide/trace-events   |  3 +++
 include/hw/ide/internal.h |  6 --
 4 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c
index 37fa699..b8fc51e 100644
--- a/hw/ide/atapi.c
+++ b/hw/ide/atapi.c
@@ -416,10 +416,7 @@ static void ide_atapi_cmd_read_dma_cb(void *opaque, int 
ret)
 s->io_buffer_size = n * 2048;
 data_offset = 0;
 }
-#ifdef DEBUG_AIO
-printf("aio_read_cd: lba=%u n=%d\n", s->lba, n);
-#endif
-
+trace_ide_atapi_cmd_read_dma_cb_aio(s, s->lba, n);
 s->bus->dma->iov.iov_base = (void *)(s->io_buffer + data_offset);
 s->bus->dma->iov.iov_len = n * ATAPI_SECTOR_SIZE;
 qemu_iovec_init_external(>bus->dma->qiov, >bus->dma->iov, 1);
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 82a19b1..a1c90e9 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -58,6 +58,13 @@ static const int smart_attributes[][12] = {
 { 190,  0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
 };
 
+const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT] = {
+[IDE_DMA_READ] = "DMA READ",
+[IDE_DMA_WRITE] = "DMA WRITE",
+[IDE_DMA_TRIM] = "DMA TRIM",
+[IDE_DMA_ATAPI] = "DMA ATAPI"
+};
+
 static void ide_dummy_transfer_stop(IDEState *s);
 
 static void padstr(char *str, const char *src, int len)
@@ -860,10 +867,8 @@ static void ide_dma_cb(void *opaque, int ret)
 goto eot;
 }
 
-#ifdef DEBUG_AIO
-printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
-   sector_num, n, s->dma_cmd);
-#endif
+trace_ide_dma_cb(s, sector_num, n,
+ IDE_DMA_CMD_lookup[s->dma_cmd]);
 
 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
 !ide_sect_range_ok(s, sector_num, n)) {
@@ -2391,9 +2396,7 @@ void ide_bus_reset(IDEBus *bus)
 
 /* pending async DMA */
 if (bus->dma->aiocb) {
-#ifdef DEBUG_AIO
-printf("aio_cancel\n");
-#endif
+trace_ide_bus_reset_aio();
 blk_aio_cancel(bus->dma->aiocb);
 bus->dma->aiocb = NULL;
 }
diff --git a/hw/ide/trace-events b/hw/ide/trace-events
index 8c79a6c..cc8949c 100644
--- a/hw/ide/trace-events
+++ b/hw/ide/trace-events
@@ -18,6 +18,8 @@ ide_cancel_dma_sync_remaining(void) "draining all remaining 
requests"
 ide_sector_read(int64_t sector_num, int nsectors) "sector=%"PRId64" 
nsectors=%d"
 ide_sector_write(int64_t sector_num, int nsectors) "sector=%"PRId64" 
nsectors=%d"
 ide_reset(void *s) "IDEstate %p"
+ide_bus_reset_aio(void) "aio_cancel"
+ide_dma_cb(void *s, int64_t sector_num, int n, const char *dma) "IDEState %p; 
sector_num=%"PRId64" n=%d cmd=%s"
 
 # BMDMA HBAs:
 
@@ -51,5 +53,6 @@ ide_atapi_cmd_reply_end_new(void *s, int status) "IDEState: 
%p; new transfer sta
 ide_atapi_cmd_check_status(void *s) "IDEState: %p"
 ide_atapi_cmd_read(void *s, const char *method, int lba, int nb_sectors) 
"IDEState: %p; read %s: LBA=%d nb_sectors=%d"
 ide_atapi_cmd(void *s, uint8_t cmd) "IDEState: %p; cmd: 0x%02x"
+ide_atapi_cmd_read_dma_cb_aio(void *s, int lba, int n) "IDEState: %p; aio 
read: lba=%d n=%d"
 # Warning: Verbose
 ide_atapi_cmd_packet(void *s, uint16_t limit, const char *packet) "IDEState: 
%p; limit=0x%x packet: %s"
diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
index 74efe8a..db9fde0 100644
--- a/include/hw/ide/internal.h
+++ b/include/hw/ide/internal.h
@@ -14,7 +14,6 @@
 #include "block/scsi.h"
 
 /* debug IDE devices */
-//#define DEBUG_AIO
 #define USE_DMA_CDROM
 
 typedef struct IDEBus IDEBus;
@@ -333,12 +332,15 @@ struct unreported_events {
 };
 
 enum ide_dma_cmd {
-IDE_DMA_READ,
+IDE_DMA_READ = 0,
 IDE_DMA_WRITE,
 IDE_DMA_TRIM,
 IDE_DMA_ATAPI,
+IDE_DMA__COUNT
 };
 
+extern const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT];
+
 #define ide_cmd_is_read(s) \
((s)->dma_cmd == IDE_DMA_READ)
 
-- 
2.9.5

[Qemu-devel] [PATCH v2 9/9] AHCI: remove DPRINTF macro

[John Snow]

Signed-off-by: John Snow 
---
 hw/ide/ahci.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 2e75f9b..57bb59d 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -34,17 +34,8 @@
 #include "hw/ide/pci.h"
 #include "hw/ide/ahci_internal.h"
 
-#define DEBUG_AHCI 0
 #include "trace.h"
 
-#define DPRINTF(port, fmt, ...) \
-do { \
-if (DEBUG_AHCI) { \
-fprintf(stderr, "ahci: %s: [%d] ", __func__, port); \
-fprintf(stderr, fmt, ## __VA_ARGS__); \
-} \
-} while (0)
-
 static void check_cmd(AHCIState *s, int port);
 static int handle_cmd(AHCIState *s, int port, uint8_t slot);
 static void ahci_reset_port(AHCIState *s, int port);
-- 
2.9.5

[Qemu-devel] [PATCH v2 0/9] IDE: replace printfs with tracing

[John Snow]

Wherever possible, replace all printfs with proper tracing.
In most places I've tried to do a straight replacement, but
forthcoming patches may calibrate the tracing to be a little nicer.

For now, it's nice to just remove the all-or-nothing tracing.

For V2, I opted to leave in the nearly redundant tracers for now
with their individual names so that they can be targeted individually.

Key:
[] : patches are identical
[] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respectively

001/9:[0020] [FC] 'IDE: replace DEBUG_IDE with tracing system'
002/9:[0004] [FC] 'IDE: Add register hints to tracing'
003/9:[0005] [FC] 'IDE: add tracing for data ports'
004/9:[0004] [FC] 'ATAPI: Replace DEBUG_IDE_ATAPI with tracing events'
005/9:[0013] [FC] 'IDE: replace DEBUG_AIO with trace events'
006/9:[0007] [FC] 'AHCI: Replace DPRINTF with trace-events'
007/9:[] [--] 'AHCI: Rework IRQ constants'
008/9:[0001] [FC] 'AHCI: pretty-print FIS to buffer instead of stderr'
009/9:[] [--] 'AHCI: remove DPRINTF macro'

===
v2:
===

01: Rehabilitate commit message.
Fix switch () statement spacing. (Eric)
Adjust spacing in ide-tracing file to maintain columns.
Change filename orderings in trace-events. (Eric)
Fixed newline issue in trace-events. (Eric)

02: Context / Added R-B.

03: Added trace-events items to appropriate patch (removed from 04) (Eric)
Added a verbose warning for data tracers (Eric)

04: Shifted items to 03 (Eric)
Fixed newline issue (Eric)

05: Changed __END to __COUNT (Philippe)
Removed __BEGIN enumerator (Philippe)

06: Added more information to unknown write (Philippe)

08: Context (Entropy)

John Snow (9):
  IDE: replace DEBUG_IDE with tracing system
  IDE: Add register hints to tracing
  IDE: add tracing for data ports
  ATAPI: Replace DEBUG_IDE_ATAPI with tracing events
  IDE: replace DEBUG_AIO with trace events
  AHCI: Replace DPRINTF with trace-events
  AHCI: Rework IRQ constants
  AHCI: pretty-print FIS to buffer instead of stderr
  AHCI: remove DPRINTF macro

 Makefile.objs |   1 +
 hw/ide/ahci.c | 269 ++
 hw/ide/ahci_internal.h|  44 ++--
 hw/ide/atapi.c|  69 +---
 hw/ide/cmd646.c   |  10 +-
 hw/ide/core.c | 178 +++---
 hw/ide/pci.c  |  17 +--
 hw/ide/piix.c |  11 +-
 hw/ide/trace-events   | 111 +++
 hw/ide/via.c  |  10 +-
 include/hw/ide/internal.h |   8 +-
 11 files changed, 456 insertions(+), 272 deletions(-)
 create mode 100644 hw/ide/trace-events

-- 
2.9.5

[Qemu-devel] [PATCH 4/8] tcg/s390: Merge add2i facilities check to tcg_target_op_def

[Richard Henderson]

From: Richard Henderson 

Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target.inc.c | 38 ++
 1 file changed, 14 insertions(+), 24 deletions(-)

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index ff3f644f8e..6b08ccea6d 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -43,7 +43,7 @@
 #define TCG_CT_CONST_ORI   0x400
 #define TCG_CT_CONST_XORI  0x800
 #define TCG_CT_CONST_U31   0x1000
-#define TCG_CT_CONST_ADLI  0x2000
+#define TCG_CT_CONST_S33   0x2000
 #define TCG_CT_CONST_ZERO  0x4000
 
 /* Several places within the instruction set 0 means "no register"
@@ -387,7 +387,7 @@ static const char *target_parse_constraint(TCGArgConstraint 
*ct,
 tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
 break;
 case 'A':
-ct->ct |= TCG_CT_CONST_ADLI;
+ct->ct |= TCG_CT_CONST_S33;
 break;
 case 'I':
 ct->ct |= TCG_CT_CONST_S16;
@@ -478,20 +478,6 @@ static int tcg_match_xori(TCGType type, tcg_target_long 
val)
 return 1;
 }
 
-/* Immediates to be used with add2/sub2.  */
-
-static int tcg_match_add2i(TCGType type, tcg_target_long val)
-{
-if (s390_facilities & FACILITY_EXT_IMM) {
-if (type == TCG_TYPE_I32) {
-return 1;
-} else if (val >= -0xll && val <= 0xll) {
-return 1;
-}
-}
-return 0;
-}
-
 /* Test if a constant matches the constraint. */
 static int tcg_target_const_match(tcg_target_long val, TCGType type,
   const TCGArgConstraint *arg_ct)
@@ -511,8 +497,8 @@ static int tcg_target_const_match(tcg_target_long val, 
TCGType type,
 return val == (int16_t)val;
 } else if (ct & TCG_CT_CONST_S32) {
 return val == (int32_t)val;
-} else if (ct & TCG_CT_CONST_ADLI) {
-return tcg_match_add2i(type, val);
+} else if (ct & TCG_CT_CONST_S33) {
+return val >= -0xll && val <= 0xll;
 } else if (ct & TCG_CT_CONST_ORI) {
 return tcg_match_ori(type, val);
 } else if (ct & TCG_CT_CONST_XORI) {
@@ -2241,6 +2227,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
 static const TCGTargetOpDef r_0_rO = { .args_ct_str = { "r", "0", "rO" } };
 static const TCGTargetOpDef r_0_rX = { .args_ct_str = { "r", "0", "rX" } };
+static const TCGTargetOpDef a2_r
+= { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
+static const TCGTargetOpDef a2_ri
+= { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
+static const TCGTargetOpDef a2_rA
+= { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
 
 switch (op) {
 case INDEX_op_goto_ptr:
@@ -2389,15 +2381,13 @@ static const TCGTargetOpDef 
*tcg_target_op_def(TCGOpcode op)
 = { .args_ct_str = { "b", "a", "0", "r" } };
 return 
 }
+
 case INDEX_op_add2_i32:
-case INDEX_op_add2_i64:
 case INDEX_op_sub2_i32:
+return (s390_facilities & FACILITY_EXT_IMM ? _ri : _r);
+case INDEX_op_add2_i64:
 case INDEX_op_sub2_i64:
-{
-static const TCGTargetOpDef arith2
-= { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
-return 
-}
+return (s390_facilities & FACILITY_EXT_IMM ? _rA : _r);
 
 default:
 break;
-- 
2.13.5

[Qemu-devel] [PATCH 3/8] tcg/s390: Merge muli facilities check to tcg_target_op_def

[Richard Henderson]

From: Richard Henderson 

Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target.inc.c | 45 +
 1 file changed, 25 insertions(+), 20 deletions(-)

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index e075b4844a..ff3f644f8e 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -38,12 +38,13 @@
a 32-bit displacement here Just In Case.  */
 #define USE_LONG_BRANCHES 0
 
-#define TCG_CT_CONST_MULI  0x100
-#define TCG_CT_CONST_ORI   0x200
-#define TCG_CT_CONST_XORI  0x400
-#define TCG_CT_CONST_U31   0x800
-#define TCG_CT_CONST_ADLI  0x1000
-#define TCG_CT_CONST_ZERO  0x2000
+#define TCG_CT_CONST_S16   0x100
+#define TCG_CT_CONST_S32   0x200
+#define TCG_CT_CONST_ORI   0x400
+#define TCG_CT_CONST_XORI  0x800
+#define TCG_CT_CONST_U31   0x1000
+#define TCG_CT_CONST_ADLI  0x2000
+#define TCG_CT_CONST_ZERO  0x4000
 
 /* Several places within the instruction set 0 means "no register"
rather than TCG_REG_R0.  */
@@ -388,8 +389,11 @@ static const char 
*target_parse_constraint(TCGArgConstraint *ct,
 case 'A':
 ct->ct |= TCG_CT_CONST_ADLI;
 break;
-case 'K':
-ct->ct |= TCG_CT_CONST_MULI;
+case 'I':
+ct->ct |= TCG_CT_CONST_S16;
+break;
+case 'J':
+ct->ct |= TCG_CT_CONST_S32;
 break;
 case 'O':
 ct->ct |= TCG_CT_CONST_ORI;
@@ -503,16 +507,10 @@ static int tcg_target_const_match(tcg_target_long val, 
TCGType type,
 }
 
 /* The following are mutually exclusive.  */
-if (ct & TCG_CT_CONST_MULI) {
-/* Immediates that may be used with multiply.  If we have the
-   general-instruction-extensions, then we have MULTIPLY SINGLE
-   IMMEDIATE with a signed 32-bit, otherwise we have only
-   MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit.  */
-if (s390_facilities & FACILITY_GEN_INST_EXT) {
-return val == (int32_t)val;
-} else {
-return val == (int16_t)val;
-}
+if (ct & TCG_CT_CONST_S16) {
+return val == (int16_t)val;
+} else if (ct & TCG_CT_CONST_S32) {
+return val == (int32_t)val;
 } else if (ct & TCG_CT_CONST_ADLI) {
 return tcg_match_add2i(type, val);
 } else if (ct & TCG_CT_CONST_ORI) {
@@ -2239,7 +2237,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } };
 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
 static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
-static const TCGTargetOpDef r_0_rK = { .args_ct_str = { "r", "0", "rK" } };
+static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
+static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
 static const TCGTargetOpDef r_0_rO = { .args_ct_str = { "r", "0", "rO" } };
 static const TCGTargetOpDef r_0_rX = { .args_ct_str = { "r", "0", "rX" } };
 
@@ -2274,9 +2273,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 case INDEX_op_sub_i32:
 case INDEX_op_sub_i64:
 return _0_ri;
+
 case INDEX_op_mul_i32:
+/* If we have the general-instruction-extensions, then we have
+   MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
+   have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit.  */
+return (s390_facilities & FACILITY_GEN_INST_EXT ? _0_ri : _0_rI);
 case INDEX_op_mul_i64:
-return _0_rK;
+return (s390_facilities & FACILITY_GEN_INST_EXT ? _0_rJ : _0_rI);
+
 case INDEX_op_or_i32:
 case INDEX_op_or_i64:
 return _0_rO;
-- 
2.13.5

[Qemu-devel] [PATCH 5/8] tcg/s390: Merge ori+xori facilities check to tcg_target_op_def

[Richard Henderson]

From: Richard Henderson 

Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target.inc.c | 101 +++---
 1 file changed, 33 insertions(+), 68 deletions(-)

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 6b08ccea6d..5414c9d879 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -40,8 +40,8 @@
 
 #define TCG_CT_CONST_S16   0x100
 #define TCG_CT_CONST_S32   0x200
-#define TCG_CT_CONST_ORI   0x400
-#define TCG_CT_CONST_XORI  0x800
+#define TCG_CT_CONST_NN16  0x400
+#define TCG_CT_CONST_NN32  0x800
 #define TCG_CT_CONST_U31   0x1000
 #define TCG_CT_CONST_S33   0x2000
 #define TCG_CT_CONST_ZERO  0x4000
@@ -395,11 +395,11 @@ static const char 
*target_parse_constraint(TCGArgConstraint *ct,
 case 'J':
 ct->ct |= TCG_CT_CONST_S32;
 break;
-case 'O':
-ct->ct |= TCG_CT_CONST_ORI;
+case 'N':
+ct->ct |= TCG_CT_CONST_NN16;
 break;
-case 'X':
-ct->ct |= TCG_CT_CONST_XORI;
+case 'M':
+ct->ct |= TCG_CT_CONST_NN32;
 break;
 case 'C':
 /* ??? We have no insight here into whether the comparison is
@@ -424,60 +424,6 @@ static const char 
*target_parse_constraint(TCGArgConstraint *ct,
 return ct_str;
 }
 
-/* Immediates to be used with logical OR.  This is an optimization only,
-   since a full 64-bit immediate OR can always be performed with 4 sequential
-   OI[LH][LH] instructions.  What we're looking for is immediates that we
-   can load efficiently, and the immediate load plus the reg-reg OR is
-   smaller than the sequential OI's.  */
-
-static int tcg_match_ori(TCGType type, tcg_target_long val)
-{
-if (s390_facilities & FACILITY_EXT_IMM) {
-if (type == TCG_TYPE_I32) {
-/* All 32-bit ORs can be performed with 1 48-bit insn.  */
-return 1;
-}
-}
-
-/* Look for negative values.  These are best to load with LGHI.  */
-if (val < 0) {
-if (val == (int16_t)val) {
-return 0;
-}
-if (s390_facilities & FACILITY_EXT_IMM) {
-if (val == (int32_t)val) {
-return 0;
-}
-}
-}
-
-return 1;
-}
-
-/* Immediates to be used with logical XOR.  This is almost, but not quite,
-   only an optimization.  XOR with immediate is only supported with the
-   extended-immediate facility.  That said, there are a few patterns for
-   which it is better to load the value into a register first.  */
-
-static int tcg_match_xori(TCGType type, tcg_target_long val)
-{
-if ((s390_facilities & FACILITY_EXT_IMM) == 0) {
-return 0;
-}
-
-if (type == TCG_TYPE_I32) {
-/* All 32-bit XORs can be performed with 1 48-bit insn.  */
-return 1;
-}
-
-/* Look for negative values.  These are best to load with LGHI.  */
-if (val < 0 && val == (int32_t)val) {
-return 0;
-}
-
-return 1;
-}
-
 /* Test if a constant matches the constraint. */
 static int tcg_target_const_match(tcg_target_long val, TCGType type,
   const TCGArgConstraint *arg_ct)
@@ -499,10 +445,10 @@ static int tcg_target_const_match(tcg_target_long val, 
TCGType type,
 return val == (int32_t)val;
 } else if (ct & TCG_CT_CONST_S33) {
 return val >= -0xll && val <= 0xll;
-} else if (ct & TCG_CT_CONST_ORI) {
-return tcg_match_ori(type, val);
-} else if (ct & TCG_CT_CONST_XORI) {
-return tcg_match_xori(type, val);
+} else if (ct & TCG_CT_CONST_NN16) {
+return !(val < 0 && val == (int16_t)val);
+} else if (ct & TCG_CT_CONST_NN32) {
+return !(val < 0 && val == (int32_t)val);
 } else if (ct & TCG_CT_CONST_U31) {
 return val >= 0 && val <= 0x7fff;
 } else if (ct & TCG_CT_CONST_ZERO) {
@@ -,11 +2168,12 @@ static const TCGTargetOpDef 
*tcg_target_op_def(TCGOpcode op)
 static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } };
 static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } };
 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
 static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
 static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
 static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
-static const TCGTargetOpDef r_0_rO = { .args_ct_str = { "r", "0", "rO" } };
-static const TCGTargetOpDef r_0_rX = { .args_ct_str = { "r", "0", "rX" } };
+static const TCGTargetOpDef r_0_rN = { .args_ct_str = { "r", "0", "rN" } };
+static const TCGTargetOpDef r_0_rM = { .args_ct_str = { "r", "0", "rM" } };
 static const TCGTargetOpDef a2_r
 = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
 static const 

[Qemu-devel] [PATCH 8/8] tcg/s390: Use slbgr for setcond le and leu

[Richard Henderson]

From: Richard Henderson 

Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target.inc.c | 119 +-
 1 file changed, 43 insertions(+), 76 deletions(-)

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 0de968fde2..38b9e791ee 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -1084,11 +1084,20 @@ static void tgen_setcond(TCGContext *s, TCGType type, 
TCGCond cond,
 
 have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0;
 
-/* For HAVE_LOC, only the path through do_greater is smaller.  */
+/* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller.  */
+ restart:
 switch (cond) {
+case TCG_COND_NE:
+/* X != 0 is X > 0.  */
+if (c2const && c2 == 0) {
+cond = TCG_COND_GTU;
+} else {
+break;
+}
+/* fallthru */
+
 case TCG_COND_GTU:
 case TCG_COND_GT:
-do_greater:
 /* The result of a compare has CC=2 for GT and CC=3 unused.
ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit.  */
 tgen_cmp(s, type, cond, c1, c2, c2const, true);
@@ -1096,49 +1105,33 @@ static void tgen_setcond(TCGContext *s, TCGType type, 
TCGCond cond,
 tcg_out_insn(s, RRE, ALCGR, dest, dest);
 return;
 
-case TCG_COND_GEU:
-if (have_loc) {
-goto do_loc;
-}
-do_geu:
-/* We need "real" carry semantics, so use SUBTRACT LOGICAL
-   instead of COMPARE LOGICAL.  This may need an extra move.  */
-if (c2const) {
-tcg_out_mov(s, type, TCG_TMP0, c1);
-if (type == TCG_TYPE_I32) {
-tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2);
-} else {
-tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2);
-}
-} else if (s390_facilities & FACILITY_DISTINCT_OPS) {
-if (type == TCG_TYPE_I32) {
-tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2);
-} else {
-tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2);
-}
+case TCG_COND_EQ:
+/* X == 0 is X <= 0.  */
+if (c2const && c2 == 0) {
+cond = TCG_COND_LEU;
 } else {
-tcg_out_mov(s, type, TCG_TMP0, c1);
-if (type == TCG_TYPE_I32) {
-tcg_out_insn(s, RR, SLR, TCG_TMP0, c2);
-} else {
-tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2);
-}
+break;
 }
-tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
-tcg_out_insn(s, RRE, ALCGR, dest, dest);
-return;
+/* fallthru */
 
 case TCG_COND_LEU:
-if (have_loc) {
-goto do_loc;
-}
-/* fallthru */
+case TCG_COND_LE:
+/* As above, but we're looking for borrow, or !carry.
+   The second insn computes d - d - borrow, or -1 for true
+   and 0 for false.  So we must mask to 1 bit afterward.  */
+tgen_cmp(s, type, cond, c1, c2, c2const, true);
+tcg_out_insn(s, RRE, SLBGR, dest, dest);
+tgen_andi(s, type, dest, 1);
+return;
+
+case TCG_COND_GEU:
 case TCG_COND_LTU:
 case TCG_COND_LT:
-/* Swap operands so that we can use GEU/GTU/GT.  */
+case TCG_COND_GE:
+/* Swap operands so that we can use LEU/GTU/GT/LE.  */
 if (c2const) {
 if (have_loc) {
-goto do_loc;
+break;
 }
 tcg_out_movi(s, type, TCG_TMP0, c2);
 c2 = c1;
@@ -1149,51 +1142,25 @@ static void tgen_setcond(TCGContext *s, TCGType type, 
TCGCond cond,
 c1 = c2;
 c2 = t;
 }
-if (cond == TCG_COND_LEU) {
-goto do_geu;
-}
 cond = tcg_swap_cond(cond);
-goto do_greater;
-
-case TCG_COND_NE:
-/* X != 0 is X > 0.  */
-if (c2const && c2 == 0) {
-cond = TCG_COND_GTU;
-goto do_greater;
-}
-break;
-
-case TCG_COND_EQ:
-if (have_loc) {
-goto do_loc;
-}
-/* X == 0 is X <= 0 is 0 >= X.  */
-if (c2const && c2 == 0) {
-tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0);
-c2 = c1;
-c2const = 0;
-c1 = TCG_TMP0;
-goto do_geu;
-}
-break;
+goto restart;
 
 default:
-break;
+g_assert_not_reached();
 }
 
 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
-/* Emit: d = 1; if (cc) goto over; d = 0; over:  */
-tcg_out_movi(s, type, dest, 1);
-tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
-tcg_out_movi(s, type, dest, 0);
-return;
-
- do_loc:
-cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
-/* Emit: d = 0, t = 1, d = (cc ? t : d).  */
-tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
-tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);

[Qemu-devel] [PATCH v2 2/9] IDE: Add register hints to tracing

[John Snow]

Name the registers for tracing purposes.

Signed-off-by: John Snow 
Reviewed-by: Eric Blake 
---
 hw/ide/core.c   | 88 +
 hw/ide/trace-events |  8 ++---
 2 files changed, 72 insertions(+), 24 deletions(-)

diff --git a/hw/ide/core.c b/hw/ide/core.c
index 31fd593..cb250e6 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -1185,13 +1185,37 @@ static void ide_clear_hob(IDEBus *bus)
 bus->ifs[1].select &= ~(1 << 7);
 }
 
+/* IOport [W]rite [R]egisters */
+enum ATA_IOPORT_WR {
+ATA_IOPORT_WR_DATA = 0,
+ATA_IOPORT_WR_FEATURES = 1,
+ATA_IOPORT_WR_SECTOR_COUNT = 2,
+ATA_IOPORT_WR_SECTOR_NUMBER = 3,
+ATA_IOPORT_WR_CYLINDER_LOW = 4,
+ATA_IOPORT_WR_CYLINDER_HIGH = 5,
+ATA_IOPORT_WR_DEVICE_HEAD = 6,
+ATA_IOPORT_WR_COMMAND = 7,
+ATA_IOPORT_WR_NUM_REGISTERS,
+};
+
+const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {
+[ATA_IOPORT_WR_DATA] = "Data",
+[ATA_IOPORT_WR_FEATURES] = "Features",
+[ATA_IOPORT_WR_SECTOR_COUNT] = "Sector Count",
+[ATA_IOPORT_WR_SECTOR_NUMBER] = "Sector Number",
+[ATA_IOPORT_WR_CYLINDER_LOW] = "Cylinder Low",
+[ATA_IOPORT_WR_CYLINDER_HIGH] = "Cylinder High",
+[ATA_IOPORT_WR_DEVICE_HEAD] = "Device/Head",
+[ATA_IOPORT_WR_COMMAND] = "Command"
+};
+
 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 {
 IDEBus *bus = opaque;
 IDEState *s = idebus_active_if(bus);
 int reg_num = addr & 7;
 
-trace_ide_ioport_write(addr, val, bus, s);
+trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
 
 /* ignore writes to command block while busy with previous command */
 if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) {
@@ -1201,43 +1225,43 @@ void ide_ioport_write(void *opaque, uint32_t addr, 
uint32_t val)
 switch (reg_num) {
 case 0:
 break;
-case 1:
-   ide_clear_hob(bus);
+case ATA_IOPORT_WR_FEATURES:
+ide_clear_hob(bus);
 /* NOTE: data is written to the two drives */
-   bus->ifs[0].hob_feature = bus->ifs[0].feature;
-   bus->ifs[1].hob_feature = bus->ifs[1].feature;
+bus->ifs[0].hob_feature = bus->ifs[0].feature;
+bus->ifs[1].hob_feature = bus->ifs[1].feature;
 bus->ifs[0].feature = val;
 bus->ifs[1].feature = val;
 break;
-case 2:
+case ATA_IOPORT_WR_SECTOR_COUNT:
ide_clear_hob(bus);
bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
 bus->ifs[0].nsector = val;
 bus->ifs[1].nsector = val;
 break;
-case 3:
+case ATA_IOPORT_WR_SECTOR_NUMBER:
ide_clear_hob(bus);
bus->ifs[0].hob_sector = bus->ifs[0].sector;
bus->ifs[1].hob_sector = bus->ifs[1].sector;
 bus->ifs[0].sector = val;
 bus->ifs[1].sector = val;
 break;
-case 4:
+case ATA_IOPORT_WR_CYLINDER_LOW:
ide_clear_hob(bus);
bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
 bus->ifs[0].lcyl = val;
 bus->ifs[1].lcyl = val;
 break;
-case 5:
+case ATA_IOPORT_WR_CYLINDER_HIGH:
ide_clear_hob(bus);
bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
 bus->ifs[0].hcyl = val;
 bus->ifs[1].hcyl = val;
 break;
-case 6:
+case ATA_IOPORT_WR_DEVICE_HEAD:
/* FIXME: HOB readback uses bit 7 */
 bus->ifs[0].select = (val & ~0x10) | 0xa0;
 bus->ifs[1].select = (val | 0x10) | 0xa0;
@@ -1245,7 +1269,7 @@ void ide_ioport_write(void *opaque, uint32_t addr, 
uint32_t val)
 bus->unit = (val >> 4) & 1;
 break;
 default:
-case 7:
+case ATA_IOPORT_WR_COMMAND:
 /* command */
 ide_exec_cmd(bus, val);
 break;
@@ -2052,6 +2076,30 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
 }
 }
 
+/* IOport [R]ead [R]egisters */
+enum ATA_IOPORT_RR {
+ATA_IOPORT_RR_DATA = 0,
+ATA_IOPORT_RR_ERROR = 1,
+ATA_IOPORT_RR_SECTOR_COUNT = 2,
+ATA_IOPORT_RR_SECTOR_NUMBER = 3,
+ATA_IOPORT_RR_CYLINDER_LOW = 4,
+ATA_IOPORT_RR_CYLINDER_HIGH = 5,
+ATA_IOPORT_RR_DEVICE_HEAD = 6,
+ATA_IOPORT_RR_STATUS = 7,
+ATA_IOPORT_RR_NUM_REGISTERS,
+};
+
+const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {
+[ATA_IOPORT_RR_DATA] = "Data",
+[ATA_IOPORT_RR_ERROR] = "Error",
+[ATA_IOPORT_RR_SECTOR_COUNT] = "Sector Count",
+[ATA_IOPORT_RR_SECTOR_NUMBER] = "Sector Number",
+[ATA_IOPORT_RR_CYLINDER_LOW] = "Cylinder Low",
+[ATA_IOPORT_RR_CYLINDER_HIGH] = "Cylinder High",
+[ATA_IOPORT_RR_DEVICE_HEAD] = "Device/Head",
+[ATA_IOPORT_RR_STATUS] = "Status"
+};
+
 uint32_t ide_ioport_read(void *opaque, uint32_t addr)
 {
 IDEBus *bus = opaque;
@@ -2064,10 +2112,10 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)

[Qemu-devel] [PATCH 0/8] tcg/s390 improvements

[Richard Henderson]

This finally converts s390 to the tcg_target_op_def function, which
allows constraints to vary at runtime.  Once we have that, we can

(1) Perform some facilities checks once during startup instead of
every time we evaluate the constraint,
(2) Use the distinct-operands facility from z196.

In addition, two cleanups to the setcond expansion

(3) Use the load-on-condition-2 facility from z13,
(4) Use a smaller expansion for LE/LEU using SLBGR.

I wrote these after soft freeze and before I changed jobs, so it has
seen some testing.  Unfortunately, I no longer have access to s390
hardware, so I'd appreciate it if someone could re-test this rebase.


r~


Richard Henderson (8):
  tcg/s390: Fully convert tcg_target_op_def
  tcg/s390: Merge cmpi facilities check to tcg_target_op_def
  tcg/s390: Merge muli facilities check to tcg_target_op_def
  tcg/s390: Merge add2i facilities check to tcg_target_op_def
  tcg/s390: Merge ori+xori facilities check to tcg_target_op_def
  tcg/s390: Use distinct-operands facility
  tcg/s390: Use load-on-condition-2 facility
  tcg/s390: Use slbgr for setcond le and leu

 tcg/s390/tcg-target.h |   2 +
 tcg/s390/tcg-target.inc.c | 700 +-
 2 files changed, 380 insertions(+), 322 deletions(-)

-- 
2.13.5

[Qemu-devel] [PATCH 1/8] tcg/s390: Fully convert tcg_target_op_def

[Richard Henderson]

From: Richard Henderson 

Use a switch instead of searching a table.

Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target.inc.c | 278 +-
 1 file changed, 154 insertions(+), 124 deletions(-)

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 5d7083e90c..d34649eb13 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -2246,134 +2246,164 @@ static inline void tcg_out_op(TCGContext *s, 
TCGOpcode opc,
 }
 }
 
-static const TCGTargetOpDef s390_op_defs[] = {
-{ INDEX_op_exit_tb, { } },
-{ INDEX_op_goto_tb, { } },
-{ INDEX_op_br, { } },
-{ INDEX_op_goto_ptr, { "r" } },
-
-{ INDEX_op_ld8u_i32, { "r", "r" } },
-{ INDEX_op_ld8s_i32, { "r", "r" } },
-{ INDEX_op_ld16u_i32, { "r", "r" } },
-{ INDEX_op_ld16s_i32, { "r", "r" } },
-{ INDEX_op_ld_i32, { "r", "r" } },
-{ INDEX_op_st8_i32, { "r", "r" } },
-{ INDEX_op_st16_i32, { "r", "r" } },
-{ INDEX_op_st_i32, { "r", "r" } },
-
-{ INDEX_op_add_i32, { "r", "r", "ri" } },
-{ INDEX_op_sub_i32, { "r", "0", "ri" } },
-{ INDEX_op_mul_i32, { "r", "0", "rK" } },
-
-{ INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } },
-{ INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } },
-
-{ INDEX_op_and_i32, { "r", "0", "ri" } },
-{ INDEX_op_or_i32, { "r", "0", "rO" } },
-{ INDEX_op_xor_i32, { "r", "0", "rX" } },
-
-{ INDEX_op_neg_i32, { "r", "r" } },
-
-{ INDEX_op_shl_i32, { "r", "0", "ri" } },
-{ INDEX_op_shr_i32, { "r", "0", "ri" } },
-{ INDEX_op_sar_i32, { "r", "0", "ri" } },
-
-{ INDEX_op_rotl_i32, { "r", "r", "ri" } },
-{ INDEX_op_rotr_i32, { "r", "r", "ri" } },
-
-{ INDEX_op_ext8s_i32, { "r", "r" } },
-{ INDEX_op_ext8u_i32, { "r", "r" } },
-{ INDEX_op_ext16s_i32, { "r", "r" } },
-{ INDEX_op_ext16u_i32, { "r", "r" } },
-
-{ INDEX_op_bswap16_i32, { "r", "r" } },
-{ INDEX_op_bswap32_i32, { "r", "r" } },
-
-{ INDEX_op_add2_i32, { "r", "r", "0", "1", "rA", "r" } },
-{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "rA", "r" } },
-
-{ INDEX_op_brcond_i32, { "r", "rC" } },
-{ INDEX_op_setcond_i32, { "r", "r", "rC" } },
-{ INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } },
-{ INDEX_op_deposit_i32, { "r", "rZ", "r" } },
-{ INDEX_op_extract_i32, { "r", "r" } },
-
-{ INDEX_op_qemu_ld_i32, { "r", "L" } },
-{ INDEX_op_qemu_ld_i64, { "r", "L" } },
-{ INDEX_op_qemu_st_i32, { "L", "L" } },
-{ INDEX_op_qemu_st_i64, { "L", "L" } },
-
-{ INDEX_op_ld8u_i64, { "r", "r" } },
-{ INDEX_op_ld8s_i64, { "r", "r" } },
-{ INDEX_op_ld16u_i64, { "r", "r" } },
-{ INDEX_op_ld16s_i64, { "r", "r" } },
-{ INDEX_op_ld32u_i64, { "r", "r" } },
-{ INDEX_op_ld32s_i64, { "r", "r" } },
-{ INDEX_op_ld_i64, { "r", "r" } },
-
-{ INDEX_op_st8_i64, { "r", "r" } },
-{ INDEX_op_st16_i64, { "r", "r" } },
-{ INDEX_op_st32_i64, { "r", "r" } },
-{ INDEX_op_st_i64, { "r", "r" } },
-
-{ INDEX_op_add_i64, { "r", "r", "ri" } },
-{ INDEX_op_sub_i64, { "r", "0", "ri" } },
-{ INDEX_op_mul_i64, { "r", "0", "rK" } },
-
-{ INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } },
-{ INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } },
-{ INDEX_op_mulu2_i64, { "b", "a", "0", "r" } },
-
-{ INDEX_op_and_i64, { "r", "0", "ri" } },
-{ INDEX_op_or_i64, { "r", "0", "rO" } },
-{ INDEX_op_xor_i64, { "r", "0", "rX" } },
-
-{ INDEX_op_neg_i64, { "r", "r" } },
-
-{ INDEX_op_shl_i64, { "r", "r", "ri" } },
-{ INDEX_op_shr_i64, { "r", "r", "ri" } },
-{ INDEX_op_sar_i64, { "r", "r", "ri" } },
-
-{ INDEX_op_rotl_i64, { "r", "r", "ri" } },
-{ INDEX_op_rotr_i64, { "r", "r", "ri" } },
-
-{ INDEX_op_ext8s_i64, { "r", "r" } },
-{ INDEX_op_ext8u_i64, { "r", "r" } },
-{ INDEX_op_ext16s_i64, { "r", "r" } },
-{ INDEX_op_ext16u_i64, { "r", "r" } },
-{ INDEX_op_ext32s_i64, { "r", "r" } },
-{ INDEX_op_ext32u_i64, { "r", "r" } },
-
-{ INDEX_op_ext_i32_i64, { "r", "r" } },
-{ INDEX_op_extu_i32_i64, { "r", "r" } },
-
-{ INDEX_op_bswap16_i64, { "r", "r" } },
-{ INDEX_op_bswap32_i64, { "r", "r" } },
-{ INDEX_op_bswap64_i64, { "r", "r" } },
-
-{ INDEX_op_clz_i64, { "r", "r", "ri" } },
-
-{ INDEX_op_add2_i64, { "r", "r", "0", "1", "rA", "r" } },
-{ INDEX_op_sub2_i64, { "r", "r", "0", "1", "rA", "r" } },
-
-{ INDEX_op_brcond_i64, { "r", "rC" } },
-{ INDEX_op_setcond_i64, { "r", "r", "rC" } },
-{ INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } },
-{ INDEX_op_deposit_i64, { "r", "0", "r" } },
-{ INDEX_op_extract_i64, { "r", "r" } },
-
-{ INDEX_op_mb, { } },
-{ -1 },
-};
-
 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
 {
-int i, n = ARRAY_SIZE(s390_op_defs);
+static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+   

[Qemu-devel] [PATCH 2/8] tcg/s390: Merge cmpi facilities check to tcg_target_op_def

[Richard Henderson]

From: Richard Henderson 

Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target.inc.c | 68 +--
 1 file changed, 30 insertions(+), 38 deletions(-)

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index d34649eb13..e075b4844a 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -41,7 +41,7 @@
 #define TCG_CT_CONST_MULI  0x100
 #define TCG_CT_CONST_ORI   0x200
 #define TCG_CT_CONST_XORI  0x400
-#define TCG_CT_CONST_CMPI  0x800
+#define TCG_CT_CONST_U31   0x800
 #define TCG_CT_CONST_ADLI  0x1000
 #define TCG_CT_CONST_ZERO  0x2000
 
@@ -398,7 +398,18 @@ static const char 
*target_parse_constraint(TCGArgConstraint *ct,
 ct->ct |= TCG_CT_CONST_XORI;
 break;
 case 'C':
-ct->ct |= TCG_CT_CONST_CMPI;
+/* ??? We have no insight here into whether the comparison is
+   signed or unsigned.  The COMPARE IMMEDIATE insn uses a 32-bit
+   signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses
+   a 32-bit unsigned immediate.  If we were to use the (semi)
+   obvious "val == (int32_t)val" we would be enabling unsigned
+   comparisons vs very large numbers.  The only solution is to
+   take the intersection of the ranges.  */
+/* ??? Another possible solution is to simply lie and allow all
+   constants here and force the out-of-range values into a temp
+   register in tgen_cmp when we have knowledge of the actual
+   comparison code in use.  */
+ct->ct |= TCG_CT_CONST_U31;
 break;
 case 'Z':
 ct->ct |= TCG_CT_CONST_ZERO;
@@ -463,35 +474,6 @@ static int tcg_match_xori(TCGType type, tcg_target_long 
val)
 return 1;
 }
 
-/* Imediates to be used with comparisons.  */
-
-static int tcg_match_cmpi(TCGType type, tcg_target_long val)
-{
-if (s390_facilities & FACILITY_EXT_IMM) {
-/* The COMPARE IMMEDIATE instruction is available.  */
-if (type == TCG_TYPE_I32) {
-/* We have a 32-bit immediate and can compare against anything.  */
-return 1;
-} else {
-/* ??? We have no insight here into whether the comparison is
-   signed or unsigned.  The COMPARE IMMEDIATE insn uses a 32-bit
-   signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses
-   a 32-bit unsigned immediate.  If we were to use the (semi)
-   obvious "val == (int32_t)val" we would be enabling unsigned
-   comparisons vs very large numbers.  The only solution is to
-   take the intersection of the ranges.  */
-/* ??? Another possible solution is to simply lie and allow all
-   constants here and force the out-of-range values into a temp
-   register in tgen_cmp when we have knowledge of the actual
-   comparison code in use.  */
-return val >= 0 && val <= 0x7fff;
-}
-} else {
-/* Only the LOAD AND TEST instruction is available.  */
-return val == 0;
-}
-}
-
 /* Immediates to be used with add2/sub2.  */
 
 static int tcg_match_add2i(TCGType type, tcg_target_long val)
@@ -537,8 +519,8 @@ static int tcg_target_const_match(tcg_target_long val, 
TCGType type,
 return tcg_match_ori(type, val);
 } else if (ct & TCG_CT_CONST_XORI) {
 return tcg_match_xori(type, val);
-} else if (ct & TCG_CT_CONST_CMPI) {
-return tcg_match_cmpi(type, val);
+} else if (ct & TCG_CT_CONST_U31) {
+return val >= 0 && val <= 0x7fff;
 } else if (ct & TCG_CT_CONST_ZERO) {
 return val == 0;
 }
@@ -2252,7 +2234,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
 static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
+static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
 static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } };
+static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } };
 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
 static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
 static const TCGTargetOpDef r_0_rK = { .args_ct_str = { "r", "0", "rK" } };
@@ -2320,8 +2304,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 return _r_ri;
 
 case INDEX_op_brcond_i32:
+/* Without EXT_IMM, only the LOAD AND TEST insn is available.  */
+return (s390_facilities & FACILITY_EXT_IMM ? _ri : _rZ);
 case INDEX_op_brcond_i64:
-return _rC;
+return (s390_facilities & FACILITY_EXT_IMM ? _rC : _rZ);
 
 case INDEX_op_bswap16_i32:
 case INDEX_op_bswap16_i64:
@@ -2366,16 +2352,22 @@ static const 

Re: [Qemu-devel] [RFC PATCH 2/3] cpus-common: Cache allocated work items

[Paolo Bonzini]

Il 28 ago 2017 11:43 PM, "Pranith Kumar"  ha scritto:

On Mon, Aug 28, 2017 at 1:47 PM, Richard Henderson
 wrote:
> On 08/27/2017 08:53 PM, Pranith Kumar wrote:
>> Using heaptrack, I found that quite a few of our temporary allocations
>> are coming from allocating work items. Instead of doing this
>> continously, we can cache the allocated items and reuse them instead
>> of freeing them.
>>
>> This reduces the number of allocations by 25% (20 -> 15 for
>> ARM64 boot+shutdown test).
>>
>> Signed-off-by: Pranith Kumar 
>
> Why does this list need to record a "last" element?
> It would seem a simple lifo would be sufficient.
>
> (You would also be able to manage the list via cmpxchg without a separate
lock,
> but perhaps the difference between the two isn't measurable.)
>

Yes, seems like a better design choice. Will fix in next iteration.


More recent glibc will also have an efficient per-thread allocator, and
though I haven't yet benchmarked the newer glibc malloc, GSlice is slower
than at least both tcmalloc and jemalloc. Perhaps you could instead make
work items statically allocated?

Thanks,

Paolo


Thanks,
--
Pranith

Re: [Qemu-devel] Make NVME device "migratable" (savevm)

[Keith Busch]

On Tue, Aug 29, 2017 at 11:09:36AM +0100, Stefan Hajnoczi wrote:
> On Fri, Aug 25, 2017 at 11:39:30AM +0300, Sergei Dyshel wrote:
> > Hi all,
> > From what I understand, I can't "savevm" a VM that uses NVME device because
> > it has ".unmigratable = 1" in the code. What support must be implemented in
> > order to make it "migratable"?
> 
> CCing Keith Busch, the NVMe maintainer.

To make it migratable, you'll need implement the VMStateDescription to
save and restore the entire controller state, including all the queues.
It doesn't actually look like there's a much state to track compared to
other migratale devices, I just never got any time to write it out.

Re: [Qemu-devel] [PATCH 2/2] tests: Make acpid test compile

[Eric Blake]

On 08/28/2017 09:41 AM, Cédric Le Goater wrote:
> On 08/23/2017 01:53 PM, Dr. David Alan Gilbert wrote:
>> * Juan Quintela (quint...@redhat.com) wrote:
>>> Compiler gets confused with the size of the struct, so move form
>>> g_new0() to g_malloc0().
>>>
>>> I *think* that the problem is in gcc (or glib for that matter), but
>>> the documentation of the g_new0 states that 1sts first argument is an
>>> struct type, and uint32_t is not an struct type.
>>>
>>> Signed-off-by: Juan Quintela 
>>> ---

>>>  
>>>  /* get the addresses of the tables pointed by rsdt */
>>> -tables = g_new0(uint32_t, tables_nr);
>>> +tables = g_malloc0(sizeof(uint32_t) * tables_nr);
>>

> I fixed that one with :
> 
> @@ -40,7 +40,7 @@ static uint32_t acpi_find_vgia(void)
>  AcpiRsdpDescriptor rsdp_table;
>  uint32_t rsdt;
>  AcpiRsdtDescriptorRev1 rsdt_table;
> -int tables_nr;
> +uint32_t tables_nr;

I like this one better (multiplication in g_malloc0() makes me worry
about overflow; using unsigned math to avoid the problem is nicer).  Are
we going to see a v2 of this patch series?

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



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Re: [Qemu-devel] [Qemu-arm] [PATCH v3 0/2] virtio-iommu: VFIO integration

[Auger Eric]

Hi Linu,

On 29/08/2017 19:06, Linu Cherian wrote:
> Hi,
> 
> On Mon Aug 21, 2017 at 04:18:52PM +0530, Bharat Bhushan wrote:
>> This V3 version is mainly about rebasing on v3 version on Virtio-iommu device
>> framework from Eric Augur and addresing review comments.
>>
>> This patch series allows PCI pass-through using virtio-iommu.
>>   
>> This series is based on:
>>  - virtio-iommu specification written by Jean-Philippe Brucker
>>[RFC 0/3] virtio-iommu: a paravirtualized IOMMU,
>>  
>>  - virtio-iommu driver by Jean-Philippe Brucker
>>[RFC PATCH linux] iommu: Add virtio-iommu driver
>>  
>>  - virtio-iommu device emulation by Eric Augur.
>>[RFC v3 0/8] VIRTIO-IOMMU device
>>
>> PCI device pass-through and virtio-net-pci is tested with these changes 
>> using dma-ops
>>
> 
> Facing issues while trying to test with VFIO.
> 
> vfio_dma_map fails as below, 
> qemu-system-aarch64: vfio_dma_map(0x1ff0da0, 0xfdfc7000, 0x1000, 
> 0x79acc000) = -22 (Invalid argument)
> Very likely this seem to be an issue with map size. Kernel PAGE_SIZE 
> is 64k on my host and hence the map size for the physical SMMU also will
> start with 64k.
Most probably. I currently use 4KB on both host/guest.  Also the devices
I assign have BARs smaller than 64kB and this causes issue with DPDK.

> 
> Qemu source: https://github.com/eauger/qemu.git + this patch series
>  on branch v2.10.0-rc0-virtio-iommu-rfcv3
> Linux source: git://linux-arm.org/linux-jpb.git
>  on branch virtio-iommu/v0.1
> Any pointers ?
Looks good.
> 
> The other related questions i had,
> 1.  In, virtio_iommu_device_realize in qemu,
>s->config.page_sizes = TARGET_PAGE_MASK;
> 
>   Same is being taken as pgsize_bitmap in virtio_iommu guest kernel driver.
>   In, viommu_probe 
>   virtio_cread(vdev, struct virtio_iommu_config, page_sizes,
>  >pgsize_bitmap);
> 
>   Should s->config.page_sizes be initialized with page bitmap instead
>   of page mask ?
We currently support all page size bits greater or equal than the guest
page size
define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)

We evoked the problem you seem to face in
https://lists.gnu.org/archive/html/qemu-devel/2017-06/msg05308.html

and the temporary solution was to use TARGET_PAGE_MASK
> 
> 2. Should we not populate the supported page sizes based on  
>host kernel size and SMMU hardware capability rather than 
>based on the machine emulated on qemu? Atleast that makes
>sense for VFIO case.

I think Jean's proposal to address this issue is to enhance the PROBE
API. The driver would fetch for each device an accurate page_size_mask
that would characterize either the virtual iommu or the underlying
physical iommu. This would override the global page_size_mask. I think
the plan was to issue that for v0.5

Thanks

Eric
> 
>> This patch series does not implement RESV_MEM changes proposal by 
>> Jean-Philippe 
>> "https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg01796.html;
>>
>> v2->v3:
>>  - This series is based on "[RFC v3 0/8] VIRTIO-IOMMU device"
>>Which is based on top of v2.10-rc0 that 
>>  - Fixed issue with two PCI devices
>>  - Addressed review comments
>>
>> v1->v2:
>>   - Added trace events
>>   - removed vSMMU3 link in patch description
>>
>> Bharat Bhushan (2):
>>   target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route
>>   virtio-iommu: vfio integration with virtio-iommu
>>
>>  hw/virtio/trace-events   |   5 ++
>>  hw/virtio/virtio-iommu.c | 163 
>> +++
>>  include/hw/virtio/virtio-iommu.h |   6 ++
>>  target/arm/kvm.c |  27 +++
>>  target/arm/trace-events  |   3 +
>>  5 files changed, 204 insertions(+)
>>
>> -- 
>> 1.9.3
>>
>>
> 

Re: [Qemu-devel] [PATCH v2 1/3] nbd-client: avoid read_reply_co entry if send failed

[Eric Blake]

On 08/29/2017 07:27 AM, Stefan Hajnoczi wrote:
> The following segfault is encountered if the NBD server closes the UNIX
> domain socket immediately after negotiation:
> 

> 
> In the mean time blk_co_preadv() can be called and nbd_coroutine_end()
> calls aio_wake() on read_reply_co.  At this point in time
> read_reply_co's ctx isn't set because it has never been entered yet.
> 
> This patch simplifies the nbd_co_send_request() ->
> nbd_co_receive_reply() -> nbd_coroutine_end() lifecycle to just
> nbd_co_send_request() -> nbd_co_receive_reply().  The request is "ended"
> if an error occurs at any point.  Callers no longer have to invoke
> nbd_coroutine_end().

Vladimir's work also eliminated a separate call to nbd_coroutine_end.
There will be some interesting rebase issues to resolve between the two,
but I think we'll get there.

> 
> This cleanup also eliminates the segfault because we don't call
> aio_co_schedule() to wake up s->read_reply_co if sending the request
> failed.  It is only necessary to wake up s->read_reply_co if a reply was
> received.
> 
> Note this only happens with UNIX domain sockets on Linux.  It doesn't
> seem possible to reproduce this with TCP sockets.
> 
> Suggested-by: Paolo Bonzini 
> Signed-off-by: Stefan Hajnoczi 
> ---
>  block/nbd-client.c | 25 +
>  1 file changed, 9 insertions(+), 16 deletions(-)
> 

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



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Description: OpenPGP digital signature

Re: [Qemu-devel] [PATCH] s390-ccw: Fix alignment for CCW1

[Eric Farman]

On 08/29/2017 08:45 AM, Cornelia Huck wrote:

On Tue, 29 Aug 2017 08:39:27 -0400
Farhan Ali  wrote:


On 08/29/2017 08:04 AM, Cornelia Huck wrote:

On Mon, 28 Aug 2017 10:28:53 -0400
Farhan Ali  wrote:
  

On 08/28/2017 10:19 AM, Halil Pasic wrote:



On 08/28/2017 04:15 PM, Farhan Ali wrote:



On 08/28/2017 10:05 AM, Cornelia Huck wrote:

It's the alignment of the CCW which causes the problem.

The exact error message when starting the guest was:

! No virtio device found !

Since it worked for SCSI and CDL, and failed for LDL disks on that particular 
system, we are not really sure what caused the failure.
Debugging it further showed the CCW for LDL disks were not aligned at double 
word boundary.

This is really, really odd, as the low-level ccw code is the same for
any disk type...
  

Exactly!
  

Trying the test on a different system with LDL disks worked fine, with the 
aligned(8) fix.

Do you happen to have an old s390-ccw.img laying around in the test folder? 
QEMU might pick up
this one (e.g. when calling it without libvirt from the command line).
  

I explicitly mention the bios to use with '-bios' option and pick up the
latest bios. Without the aligned fix I see the error and with the fix it
works fine.

Wait, so the fix fixes it? Or am I confused now?
  


It fixes in my system and one other system we tried on. But fails on a system 
where this issue was first noticed.


This is very confusing. So you have tried -bios on the system
where the issue was first noticed and the issue still persists
despite of the fixed bios is specified?
  

Yes.

The system where the issue was first noticed, applying the fix for the
bios, fixes for:

1) CDL disks
2) SCSI disks

But fails for LDL disk.

On my system and one other system, the fix works for all the disk types,
CDL, SCSI and LDL and fixes the issue.


Are you using different toolchains on the failing and the working
systems? Does it work when you copy the bios from a working system? >>>
(Clutching at straws here...)
  


So yesterday we realized for the failing system, the bios wasn't being
built on that system rather it was being built on a different system and
being copied over to the failing system. :/


Not sure I understand this.  I thought the bios was being built on the 
system it would be used on, with the source residing on a shared disk 
mounted via NFS.




Oh dear... the system it was built on hopefully was missing the fix,
right? (I'm getting a bit paranoid here.)



I was also getting paranoid watching this.  So I did some poking...  It 
looks exactly like Peter suggested last week:


https://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg04822.html

There were multiple $QEMUSRC directories on this system.  At least one 
2.9.xx version didn't have commit 198c0d1f9df8c4 (and thus wouldn't care 
about the boundary alignment), while others did.  The aligned(8) fix 
described here was not applied universally, resulting in, uh, 
inconsistent results.  Shared systems are fun.  :)


After a little cleanup, the results from that system match what the rest 
of us have seen/expected.




Building the bios on the failing system with the fix, resolves the issue
and we did not see anymore failures.
So I think I can safely say this patch fixes the alignment problem.


Out of interest, which toolchain are you using? My rebuild is on F26.



F24 on the problematic system, F25 on mine, but this was a red herring.

 - Eric

[Qemu-devel] [PATCH for-2.11] tests: Fix broken ivshmem-server-msi/-irq tests

[Thomas Huth]

Broken with commit b4ba67d9a7025 ("libqos: Change PCI accessors to take
opaque BAR handle") a while ago, but nobody noticed since the tests are
only run in SPEED=slow mode: The msix_pba_bar is not correctly initialized
anymore if bir_pba has the same value as bir_table. With this fix,
"make check SPEED=slow" should work fine again.

Fixes: b4ba67d9a702507793c2724e56f98e9b0f7be02b
Signed-off-by: Thomas Huth 
---
 tests/libqos/pci.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c
index 2dcdead..28d576c 100644
--- a/tests/libqos/pci.c
+++ b/tests/libqos/pci.c
@@ -120,6 +120,8 @@ void qpci_msix_enable(QPCIDevice *dev)
 bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
 if (bir_pba != bir_table) {
 dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL);
+} else {
+dev->msix_pba_bar = dev->msix_table_bar;
 }
 dev->msix_pba_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
 
@@ -138,8 +140,11 @@ void qpci_msix_disable(QPCIDevice *dev)
 qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
 val & ~PCI_MSIX_FLAGS_ENABLE);
 
+if (dev->msix_pba_bar.addr != dev->msix_table_bar.addr) {
+qpci_iounmap(dev, dev->msix_pba_bar);
+}
 qpci_iounmap(dev, dev->msix_table_bar);
-qpci_iounmap(dev, dev->msix_pba_bar);
+
 dev->msix_enabled = 0;
 dev->msix_table_off = 0;
 dev->msix_pba_off = 0;
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH 0/3] scripts: add argparse module for Python 2.6 compatibility

[Philippe Mathieu-Daudé]

On 08/29/2017 07:01 AM, Stefan Hajnoczi wrote:

On Fri, Aug 25, 2017 at 12:42:44PM -0500, Eric Blake wrote:

On 08/25/2017 11:40 AM, Peter Maydell wrote:

Our choices about our dependencies are generally driven by "what
are the versions available on the oldest distros which we wish
to support building QEMU on", which typically is whatever the
long-term-support versions of Ubuntu, SUSE, Redhat, etc are.

Has somebody checked what that means for our Python version
requirements?


At least this one:

RHEL/CentOS 6: Python-2.6.6


$ docker run --rm qemu:centos6 yum -q list python
Installed Packages
python.x86_64 2.6.6-66.el6_8 
@CentOS/6.9


Good news, we have a docker image using Python2.6

Do you have some migration/guestperf test we can add to the testsuite?

Regards,

Phil.

Re: [Qemu-devel] [PATCH] arm_gicv3_kvm: Fix compile warning

[Pranith Kumar]

I should have worded the subject better. The warning is pointing to an
actual bug.

On Tue, Aug 29, 2017 at 1:32 PM, Pranith Kumar  wrote:
> Fix the following warning:
>
> /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is 
> only applied to the left hand side of this bitwise operator 
> [-Wlogical-not-parentheses]
> if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
> ^ ~
> /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses 
> after the '!' to evaluate the bitwise operator first
> if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
> ^
> /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses 
> around left hand side expression to silence this warning
> if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
> ^
>
> Signed-off-by: Pranith Kumar 
> ---
>  hw/intc/arm_gicv3_kvm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
> index 6051c77705..481fe5405a 100644
> --- a/hw/intc/arm_gicv3_kvm.c
> +++ b/hw/intc/arm_gicv3_kvm.c
> @@ -293,7 +293,7 @@ static void kvm_arm_gicv3_put(GICv3State *s)
>  kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, , true);
>
>  reg64 = c->gicr_pendbaser;
> -if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
> +if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {
>  /* Setting PTZ is advised if LPIs are disabled, to reduce
>   * GIC initialization time.
>   */
> --
> 2.11.0
>



-- 
Pranith

Re: [Qemu-devel] [Qemu-block] [PATCH v3] qemu-iotests: Extend non-shared storage migration test (194)

[Stefan Hajnoczi]

On Tue, Aug 29, 2017 at 5:50 PM, Kashyap Chamarthy  wrote:
> This is the follow-up patch that was discussed[*] as part of feedback to
> qemu-iotest 194.
>
> Changes in this patch:
>
>   - Supply 'job-id' parameter to `drive-mirror` invocation.
>
>   - Once migration completes, issue QMP `block-job-cancel` command on
> the source QEMU to gracefully complete `drive-mirror` operation.
>
>   - Once the BLOCK_JOB_COMPLETED event is emitted, stop the NBD server
> on the destination QEMU.
>
>   - Check for both the events: MIGRATION and BLOCK_JOB_COMPLETED.
>
> With the above, the test will also be (almost) in sync with the
> procedure outlined in the document 'live-block-operations.rst'[+]
> (section: "QMP invocation for live storage migration with
> ``drive-mirror`` + NBD").
>
> [*] https://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg04820.html
> -- qemu-iotests: add 194 non-shared storage migration test
> [+] 
> https://git.qemu.org/gitweb.cgi?p=qemu.git;a=blob;f=docs/interop/live-block-operations.rst
>
> Signed-off-by: Kashyap Chamarthy 
> ---
> Changes in v3:
>  - Wait for migration to complete before issuing `block-job-cancel`
>(StefanH)
>  - Wait for the event BLOCK_JOB_COMPLETED on the source before stopping
>the NBD server on the destination (StefanH)
>
> Changes in v2:
>  - Check for both the events: MIGRATION and BLOCK_JOB_COMPLETED (EricB)
> ---
>  tests/qemu-iotests/194 | 23 +--
>  tests/qemu-iotests/194.out | 11 ---
>  2 files changed, 25 insertions(+), 9 deletions(-)

Reviewed-by: Stefan Hajnoczi 

Re: [Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches

[Richard Henderson]

On 08/29/2017 10:23 AM, Pranith Kumar wrote:
> This patch increases the number of entries cached in the TLB. I went
> over a few architectures to see if increasing it is problematic. Only
> armv6 seems to have a limitation that only 8 bits can be used for
> indexing these entries. For other architectures, the number of TLB
> entries is increased to a 4K-sized cache. The patch also doubles the
> number of victim TLB entries.
> 
> Some statistics collected from a build benchmark for various cache
> sizes is listed below:
> 
> | TLB bits\vTLB entires | 8 |16  |32 |
> | 8 | 952.94(+0.0%) | 929.99(+2.4%)  | 919.02(+3.6%) |
> |10 | 898.92(+5.6%) | 886.13(+7.0%)  | 887.03(+6.9%) |
> |12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
> 
> The best combination for this workload came out to be 12 bits for the
> TLB and a 16 entry vTLB cache.
> 
> Signed-off-by: Pranith Kumar 
> ---
>  include/exec/cpu-defs.h  | 6 +++---
>  tcg/aarch64/tcg-target.h | 1 +
>  tcg/arm/tcg-target.h | 1 +
>  tcg/i386/tcg-target.h| 2 ++
>  tcg/ia64/tcg-target.h| 1 +
>  tcg/mips/tcg-target.h| 2 ++
>  tcg/ppc/tcg-target.h | 1 +
>  tcg/s390/tcg-target.h| 1 +
>  tcg/sparc/tcg-target.h   | 1 +
>  tcg/tci/tcg-target.h | 1 +
>  10 files changed, 14 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson 


r~

Re: [Qemu-devel] [PATCH v4 03/10] tests: Add vm test lib

[Philippe Mathieu-Daudé]

On 08/28/2017 02:47 PM, Fam Zheng wrote:
[...]

+def __init__(self, debug=False, vcpus=None):
+self._guest = None
+self._tmpdir = tempfile.mkdtemp(prefix="qemu-vm-")
+atexit.register(shutil.rmtree, self._tmpdir)
+
+self._ssh_key_file = os.path.join(self._tmpdir, "id_rsa")
+open(self._ssh_key_file, "w").write(SSH_KEY)
+subprocess.check_call(["chmod", "600", self._ssh_key_file])
+
+self._ssh_pub_key_file = os.path.join(self._tmpdir, "id_rsa.pub")
+open(self._ssh_pub_key_file, "w").write(SSH_PUB_KEY)
+
+self.debug = debug
+self._stderr = sys.stderr
+self._devnull = open("/dev/null", "w")
+if self.debug:
+self._stdout = sys.stdout
+else:
+self._stdout = self._devnull
+self._args = [ \
+"-nodefaults", "-m", "2G",
+"-cpu", "host",
+"-netdev", "user,id=vnet,hostfwd=:0.0.0.0:0-:22",
+"-device", "virtio-net-pci,netdev=vnet",
+"-vnc", ":0,to=20",
+"-serial", "file:%s" % os.path.join(self._tmpdir, "serial.out")]
+if vcpus:
+self._args += ["-smp", str(vcpus)]


What about enabling mttcg which isn't default?

self._args += ["--accel", "tcg,thread=multi"]


+if os.access("/dev/kvm", os.R_OK | os.W_OK):
+self._args += ["-enable-kvm"]
+else:
+logging.info("KVM not available, not using -enable-kvm")
+self._data_args = []

[...]

[Qemu-devel] [PATCH] arm_gicv3_kvm: Fix compile warning

[Pranith Kumar]

Fix the following warning:

/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is only 
applied to the left hand side of this bitwise operator 
[-Wlogical-not-parentheses]
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^ ~
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses after 
the '!' to evaluate the bitwise operator first
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses around 
left hand side expression to silence this warning
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^

Signed-off-by: Pranith Kumar 
---
 hw/intc/arm_gicv3_kvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 6051c77705..481fe5405a 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -293,7 +293,7 @@ static void kvm_arm_gicv3_put(GICv3State *s)
 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, , true);
 
 reg64 = c->gicr_pendbaser;
-if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
+if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {
 /* Setting PTZ is advised if LPIs are disabled, to reduce
  * GIC initialization time.
  */
-- 
2.11.0

[Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches

[Pranith Kumar]

This patch increases the number of entries cached in the TLB. I went
over a few architectures to see if increasing it is problematic. Only
armv6 seems to have a limitation that only 8 bits can be used for
indexing these entries. For other architectures, the number of TLB
entries is increased to a 4K-sized cache. The patch also doubles the
number of victim TLB entries.

Some statistics collected from a build benchmark for various cache
sizes is listed below:

| TLB bits\vTLB entires | 8 |16  |32 |
| 8 | 952.94(+0.0%) | 929.99(+2.4%)  | 919.02(+3.6%) |
|10 | 898.92(+5.6%) | 886.13(+7.0%)  | 887.03(+6.9%) |
|12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |

The best combination for this workload came out to be 12 bits for the
TLB and a 16 entry vTLB cache.

Signed-off-by: Pranith Kumar 
---
 include/exec/cpu-defs.h  | 6 +++---
 tcg/aarch64/tcg-target.h | 1 +
 tcg/arm/tcg-target.h | 1 +
 tcg/i386/tcg-target.h| 2 ++
 tcg/ia64/tcg-target.h| 1 +
 tcg/mips/tcg-target.h| 2 ++
 tcg/ppc/tcg-target.h | 1 +
 tcg/s390/tcg-target.h| 1 +
 tcg/sparc/tcg-target.h   | 1 +
 tcg/tci/tcg-target.h | 1 +
 10 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index bc8e7f848d..1957e3f32c 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -57,8 +57,8 @@ typedef uint64_t target_ulong;
 #endif
 
 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
-/* use a fully associative victim tlb of 8 entries */
-#define CPU_VTLB_SIZE 8
+/* use a fully associative victim tlb of 16 entries */
+#define CPU_VTLB_SIZE 16
 
 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
 #define CPU_TLB_ENTRY_BITS 4
@@ -89,7 +89,7 @@ typedef uint64_t target_ulong;
  * of tlb_table inside env (which is non-trivial but not huge).
  */
 #define CPU_TLB_BITS \
-MIN(8,   \
+MIN(MIN(12, TCG_TARGET_TLB_MAX_INDEX_BITS),  \
 TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS -  \
 (NB_MMU_MODES <= 1 ? 0 : \
  NB_MMU_MODES <= 2 ? 1 : \
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index b41a248bee..9f4558cd83 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -15,6 +15,7 @@
 
 #define TCG_TARGET_INSN_UNIT_SIZE  4
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24
+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32
 #undef TCG_TARGET_STACK_GROWSUP
 
 typedef enum {
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index a38be15a39..ebe27991f3 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -60,6 +60,7 @@ extern int arm_arch;
 #undef TCG_TARGET_STACK_GROWSUP
 #define TCG_TARGET_INSN_UNIT_SIZE 4
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
+#define TCG_TARGET_TLB_MAX_INDEX_BITS 8
 
 typedef enum {
 TCG_REG_R0 = 0,
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 73a15f7e80..5279af6eb1 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -162,6 +162,8 @@ extern bool have_popcnt;
 # define TCG_AREG0 TCG_REG_EBP
 #endif
 
+#define TCG_TARGET_TLB_MAX_INDEX_BITS (32 - CPU_TLB_ENTRY_BITS)
+
 static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
 }
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index 8f475fe742..35878e20c7 100644
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -28,6 +28,7 @@
 
 #define TCG_TARGET_INSN_UNIT_SIZE 16
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 21
+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32
 
 typedef struct {
 uint64_t lo __attribute__((aligned(16)));
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index e9558d15bc..1b60e53169 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -39,6 +39,8 @@
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
 #define TCG_TARGET_NB_REGS 32
 
+#define TCG_TARGET_TLB_MAX_INDEX_BITS (16 - CPU_TLB_ENTRY_BITS)
+
 typedef enum {
 TCG_REG_ZERO = 0,
 TCG_REG_AT,
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 5a092b038a..82e10c9471 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -34,6 +34,7 @@
 #define TCG_TARGET_NB_REGS 32
 #define TCG_TARGET_INSN_UNIT_SIZE 4
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32
 
 typedef enum {
 TCG_REG_R0,  TCG_REG_R1,  TCG_REG_R2,  TCG_REG_R3,
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index dc0e59193c..57f0e22532 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -27,6 +27,7 @@
 
 #define TCG_TARGET_INSN_UNIT_SIZE 2
 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19
+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32
 
 typedef enum TCGReg {
 TCG_REG_R0 = 0,
diff --git a/tcg/sparc/tcg-target.h 

Re: [Qemu-devel] make check speed

[Thomas Huth]

On 29.08.2017 18:34, Thomas Huth wrote:
> On 23.08.2017 14:20, Cornelia Huck wrote:
>> On Wed, 23 Aug 2017 10:35:43 +0200
>> Thomas Huth  wrote:
>>
>>> True. And I just learned that you can also already set the SPEED
>>> variable to either "quick" or "slow" and that we're already using
>>> g_test_quick() and g_test_slow() in a couple of places to check this. So
>>> the framework for running quick vs. thorough tests is already there ...
>>> we just might want to add this to some more tests, I guess...
>>>
>>> Question for the maintainers and the test automation folks: Is anybody
>>> already running "make check SPEED=slow" or is this just rather an
>>> unheard-of way of running the tests?
>>
>> So I tried this on master just for fun, and 'make V=1 SPEED=slow
>> check-qtest-x86_64' promptly failed for some ivshmem test.
>>
>> On x86_86:
>> TEST: tests/ivshmem-test... (pid=3672)
>>   /x86_64/ivshmem/single:  OK
>>   /x86_64/ivshmem/hotplug: OK
>>   /x86_64/ivshmem/memdev:  OK
>>   /x86_64/ivshmem/pair:OK
>>   /x86_64/ivshmem/server-msi:  **
>> ERROR:/home/cohuck/git/qemu/tests/ivshmem-test.c:367:test_ivshmem_server: 
>> assertion failed (ret == 0): (1 == 0)
>> FAIL
>> GTester: last random seed: R02Scde8fd6835fdf17450c73e2f74f25007
>> (pid=3697)
>>  /x86_64/ivshmem/server-irq:  OK
>> FAIL: tests/ivshmem-test
> 
> Bisecting this problem automatically ("git bisect run" rules!) revealed
> that this test broke with this commit:
> 
>   commit b4ba67d9a702507793c2724e56f98e9b0f7be02b
>   Author: David Gibson 
>   Title: libqos: Change PCI accessors to take opaque BAR handle
> 
> David, any ideas what's going wrong here?

Never mind, I've found the problem: dev->msix_pba_bar is not properly
initialized anymore if bir_pba == bir_table. I'm working on a patch...

 Thomas

Re: [Qemu-devel] [Qemu-arm] [PATCH v3 0/2] virtio-iommu: VFIO integration

[Linu Cherian]

Hi,

On Mon Aug 21, 2017 at 04:18:52PM +0530, Bharat Bhushan wrote:
> This V3 version is mainly about rebasing on v3 version on Virtio-iommu device
> framework from Eric Augur and addresing review comments.
> 
> This patch series allows PCI pass-through using virtio-iommu.
>   
> This series is based on:
>  - virtio-iommu specification written by Jean-Philippe Brucker
>[RFC 0/3] virtio-iommu: a paravirtualized IOMMU,
>  
>  - virtio-iommu driver by Jean-Philippe Brucker
>[RFC PATCH linux] iommu: Add virtio-iommu driver
>  
>  - virtio-iommu device emulation by Eric Augur.
>[RFC v3 0/8] VIRTIO-IOMMU device
> 
> PCI device pass-through and virtio-net-pci is tested with these changes using 
> dma-ops
> 

Facing issues while trying to test with VFIO.

vfio_dma_map fails as below, 
qemu-system-aarch64: vfio_dma_map(0x1ff0da0, 0xfdfc7000, 0x1000, 
0x79acc000) = -22 (Invalid argument)
Very likely this seem to be an issue with map size. Kernel PAGE_SIZE 
is 64k on my host and hence the map size for the physical SMMU also will
start with 64k. 

Qemu source: https://github.com/eauger/qemu.git + this patch series
 on branch v2.10.0-rc0-virtio-iommu-rfcv3
Linux source: git://linux-arm.org/linux-jpb.git
 on branch virtio-iommu/v0.1
Any pointers ?

The other related questions i had,
1.  In, virtio_iommu_device_realize in qemu,
   s->config.page_sizes = TARGET_PAGE_MASK;

  Same is being taken as pgsize_bitmap in virtio_iommu guest kernel driver.
  In, viommu_probe 
  virtio_cread(vdev, struct virtio_iommu_config, page_sizes,
 >pgsize_bitmap);

  Should s->config.page_sizes be initialized with page bitmap instead
  of page mask ?

2. Should we not populate the supported page sizes based on  
   host kernel size and SMMU hardware capability rather than 
   based on the machine emulated on qemu? Atleast that makes
   sense for VFIO case.

> This patch series does not implement RESV_MEM changes proposal by 
> Jean-Philippe 
> "https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg01796.html;
> 
> v2->v3:
>  - This series is based on "[RFC v3 0/8] VIRTIO-IOMMU device"
>Which is based on top of v2.10-rc0 that 
>  - Fixed issue with two PCI devices
>  - Addressed review comments
> 
> v1->v2:
>   - Added trace events
>   - removed vSMMU3 link in patch description
> 
> Bharat Bhushan (2):
>   target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route
>   virtio-iommu: vfio integration with virtio-iommu
> 
>  hw/virtio/trace-events   |   5 ++
>  hw/virtio/virtio-iommu.c | 163 
> +++
>  include/hw/virtio/virtio-iommu.h |   6 ++
>  target/arm/kvm.c |  27 +++
>  target/arm/trace-events  |   3 +
>  5 files changed, 204 insertions(+)
> 
> -- 
> 1.9.3
> 
> 

-- 
Linu cherian

[Qemu-devel] [PATCH v3] qemu-iotests: Extend non-shared storage migration test (194)

[Kashyap Chamarthy]

This is the follow-up patch that was discussed[*] as part of feedback to
qemu-iotest 194.

Changes in this patch:

  - Supply 'job-id' parameter to `drive-mirror` invocation.

  - Once migration completes, issue QMP `block-job-cancel` command on
the source QEMU to gracefully complete `drive-mirror` operation.

  - Once the BLOCK_JOB_COMPLETED event is emitted, stop the NBD server
on the destination QEMU.

  - Check for both the events: MIGRATION and BLOCK_JOB_COMPLETED.

With the above, the test will also be (almost) in sync with the
procedure outlined in the document 'live-block-operations.rst'[+]
(section: "QMP invocation for live storage migration with
``drive-mirror`` + NBD").

[*] https://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg04820.html
-- qemu-iotests: add 194 non-shared storage migration test
[+] 
https://git.qemu.org/gitweb.cgi?p=qemu.git;a=blob;f=docs/interop/live-block-operations.rst

Signed-off-by: Kashyap Chamarthy 
---
Changes in v3:
 - Wait for migration to complete before issuing `block-job-cancel`
   (StefanH)
 - Wait for the event BLOCK_JOB_COMPLETED on the source before stopping
   the NBD server on the destination (StefanH)

Changes in v2:
 - Check for both the events: MIGRATION and BLOCK_JOB_COMPLETED (EricB)
---
 tests/qemu-iotests/194 | 23 +--
 tests/qemu-iotests/194.out | 11 ---
 2 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/tests/qemu-iotests/194 b/tests/qemu-iotests/194
index 
8028111e21bed5cf4a2e8e32dc04aa5a9ea9caca..a3e3bad664b9d6aada7fbcbe7db907408a7c06de
 100755
--- a/tests/qemu-iotests/194
+++ b/tests/qemu-iotests/194
@@ -46,16 +46,17 @@ iotests.log('Launching NBD server on destination...')
 iotests.log(dest_vm.qmp('nbd-server-start', addr={'type': 'unix', 'data': 
{'path': nbd_sock_path}}))
 iotests.log(dest_vm.qmp('nbd-server-add', device='drive0', writable=True))
 
-iotests.log('Starting drive-mirror on source...')
+iotests.log('Starting `drive-mirror` on source...')
 iotests.log(source_vm.qmp(
   'drive-mirror',
   device='drive0',
   target='nbd+unix:///drive0?socket={0}'.format(nbd_sock_path),
   sync='full',
   format='raw', # always raw, the server handles the format
-  mode='existing'))
+  mode='existing',
+  job_id='mirror-job0'))
 
-iotests.log('Waiting for drive-mirror to complete...')
+iotests.log('Waiting for `drive-mirror` to complete...')
 iotests.log(source_vm.event_wait('BLOCK_JOB_READY'),
 filters=[iotests.filter_qmp_event])
 
@@ -67,7 +68,17 @@ dest_vm.qmp('migrate-set-capabilities',
 iotests.log(source_vm.qmp('migrate', 
uri='unix:{0}'.format(migration_sock_path)))
 
 while True:
-event = source_vm.event_wait('MIGRATION')
-iotests.log(event, filters=[iotests.filter_qmp_event])
-if event['data']['status'] in ('completed', 'failed'):
+event1 = source_vm.event_wait('MIGRATION')
+iotests.log(event1, filters=[iotests.filter_qmp_event])
+if event1['data']['status'] in ('completed', 'failed'):
+iotests.log('Gracefully ending the `drive-mirror` job on source...')
+iotests.log(source_vm.qmp('block-job-cancel', device='mirror-job0'))
+break
+
+while True:
+event2 = source_vm.event_wait('BLOCK_JOB_COMPLETED')
+iotests.log(event2, filters=[iotests.filter_qmp_event])
+if event2['event'] == 'BLOCK_JOB_COMPLETED':
+iotests.log('Stopping the NBD server on destination...')
+iotests.log(dest_vm.qmp('nbd-server-stop'))
 break
diff --git a/tests/qemu-iotests/194.out b/tests/qemu-iotests/194.out
index 
ae501fecacb706b1851cb9063ce9c9d5a28bb7ea..50ac50da5e7736912cbbc1825ae5629b15f0e3fe
 100644
--- a/tests/qemu-iotests/194.out
+++ b/tests/qemu-iotests/194.out
@@ -2,12 +2,17 @@ Launching VMs...
 Launching NBD server on destination...
 {u'return': {}}
 {u'return': {}}
-Starting drive-mirror on source...
+Starting `drive-mirror` on source...
 {u'return': {}}
-Waiting for drive-mirror to complete...
-{u'timestamp': {u'seconds': 'SECS', u'microseconds': 'USECS'}, u'data': 
{u'device': u'drive0', u'type': u'mirror', u'speed': 0, u'len': 1073741824, 
u'offset': 1073741824}, u'event': u'BLOCK_JOB_READY'}
+Waiting for `drive-mirror` to complete...
+{u'timestamp': {u'seconds': 'SECS', u'microseconds': 'USECS'}, u'data': 
{u'device': u'mirror-job0', u'type': u'mirror', u'speed': 0, u'len': 
1073741824, u'offset': 1073741824}, u'event': u'BLOCK_JOB_READY'}
 Starting migration...
 {u'return': {}}
 {u'timestamp': {u'seconds': 'SECS', u'microseconds': 'USECS'}, u'data': 
{u'status': u'setup'}, u'event': u'MIGRATION'}
 {u'timestamp': {u'seconds': 'SECS', u'microseconds': 'USECS'}, u'data': 
{u'status': u'active'}, u'event': u'MIGRATION'}
 {u'timestamp': {u'seconds': 'SECS', u'microseconds': 'USECS'}, u'data': 
{u'status': u'completed'}, u'event': u'MIGRATION'}
+Gracefully ending the `drive-mirror` job on 

Re: [Qemu-devel] [PATCH] io: fix check for handshake completion in TLS test

[Eric Blake]

On 08/29/2017 11:40 AM, Daniel P. Berrange wrote:
> The TLS I/O channel test had mistakenly used && instead
> of || when checking for handshake completion. As a
> result it could terminate the handshake process before
> it had actually completed. This was harmless before but
> changes in GNUTLS 3.6.0 exposed this bug and caused the
> test suite to fail.
> 
> Signed-off-by: Daniel P. Berrange 
> ---
>  tests/test-io-channel-tls.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Eric Blake 

> diff --git a/tests/test-io-channel-tls.c b/tests/test-io-channel-tls.c
> index 8eaa208e1b..e7c80f46cf 100644
> --- a/tests/test-io-channel-tls.c
> +++ b/tests/test-io-channel-tls.c
> @@ -218,7 +218,7 @@ static void test_io_channel_tls(const void *opaque)
>  mainloop = g_main_context_default();
>  do {
>  g_main_context_iteration(mainloop, TRUE);
> -} while (!clientHandshake.finished &&
> +} while (!clientHandshake.finished ||
>   !serverHandshake.finished);
>  
>  g_assert(clientHandshake.failed == data->expectClientFail);
> 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



signature.asc
Description: OpenPGP digital signature

[Qemu-devel] [PATCH v2 2/3] Test for full Backup

[Ishani Chugh]

This patch is the test for full backup implementation in Backup tool.
The test employs two basic substests:
1) Backing up an empty guest and comparing it with base image.
2) Writing a pattern to the guest, creating backup and comparing
   with the base image.

Signed-off-by: Ishani Chugh 
---
 tests/qemu-iotests/191 | 86 ++
 tests/qemu-iotests/191.out | 35 +++
 tests/qemu-iotests/group   |  2 ++
 3 files changed, 123 insertions(+)
 create mode 100755 tests/qemu-iotests/191
 create mode 100644 tests/qemu-iotests/191.out

diff --git a/tests/qemu-iotests/191 b/tests/qemu-iotests/191
new file mode 100755
index 000..16988d8
--- /dev/null
+++ b/tests/qemu-iotests/191
@@ -0,0 +1,86 @@
+#!/bin/bash
+#
+# Test full backup functionality of qemu-backup tool
+#
+# Copyright (C) 2017 Ishani Chugh 
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see .
+#
+
+# creator
+owner=chugh.ish...@research.iiit.ac.in
+
+seq=`basename $0`
+echo "QA output created by $seq"
+
+here=`pwd`
+status=1   # failure is the default!
+
+
+# get standard environment, filters and checks
+. ./common.rc
+. ./common.filter
+. ./common.qemu
+
+_supported_fmt generic
+_supported_proto generic
+_supported_os Linux
+
+_cleanup()
+{
+rm -f "$TEST_DIR"/virtio0
+rm -f "$CONFIG_FILE"
+}
+trap "_cleanup; exit \$status" 0 1 2 3 15
+
+CONFIG_FILE="$TEST_DIR"/backup-config
+SOCKET=unix:"$TEST_DIR"/backup_socket
+size=128M
+
+_make_test_img "$size"
+export QEMU_BACKUP_CONFIG="$CONFIG_FILE"
+qemu_comm_method="monitor"
+echo
+_launch_qemu -drive if=virtio,file="$TEST_IMG" -qmp "$SOCKET",server,nowait
+$PYTHON ../../contrib/backup/qemu-backup.py guest add --guest adad --qmp 
"$SOCKET"
+$PYTHON ../../contrib/backup/qemu-backup.py drive add --id virtio0 --guest 
adad --target "$TEST_DIR"/virtio0
+echo
+echo "== Creating backup =="
+$PYTHON ../../contrib/backup/qemu-backup.py backup --guest adad
+_send_qemu_cmd $QEMU_HANDLE 'quit' ''
+wait=1 _cleanup_qemu
+echo
+echo "== Comparing images =="
+$QEMU_IMG compare "$TEST_DIR"/virtio0 "$TEST_IMG"
+_cleanup
+
+_launch_qemu -drive if=virtio,id=virtio0,file="$TEST_IMG" -qmp 
"$SOCKET",server,nowait
+$PYTHON ../../contrib/backup/qemu-backup.py guest add --guest adad --qmp 
"$SOCKET"
+$PYTHON ../../contrib/backup/qemu-backup.py drive add --id virtio0 --guest 
adad --target "$TEST_DIR"/virtio0
+echo
+echo "== Writing Pattern =="
+_send_qemu_cmd $QEMU_HANDLE 'qemu-io virtio0 "write -P 0x22 0 1M"' "(qemu)" | 
_filter_qemu_io
+echo
+echo "== Creating backup =="
+$PYTHON ../../contrib/backup/qemu-backup.py backup --guest adad
+_send_qemu_cmd $QEMU_HANDLE 'quit' ''
+wait=1 _cleanup_qemu
+echo
+echo "== Comparing images =="
+$QEMU_IMG compare "$TEST_DIR"/virtio0 "$TEST_IMG"
+_cleanup
+_cleanup_test_img
+
+echo "*** done"
+status=0
\ No newline at end of file
diff --git a/tests/qemu-iotests/191.out b/tests/qemu-iotests/191.out
new file mode 100644
index 000..c60d47a
--- /dev/null
+++ b/tests/qemu-iotests/191.out
@@ -0,0 +1,35 @@
+QA output created by 191
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728
+
+Successfully Added Guest
+Successfully Added Drive
+
+== Creating backup ==
+Backup Started
+*virtio0
+Backup Complete
+QEMU X.Y.Z monitor - type 'help' for more information
+(qemu) Formatting 'TEST_DIR/virtio0', fmt=qcow2 size=134217728 
cluster_size=65536 lazy_refcounts=off refcount_bits=16
+quit
+
+== Comparing images ==
+Images are identical.
+Successfully Added Guest
+Successfully Added Drive
+
+== Writing Pattern ==
+QEMU X.Y.Z monitor - type 'help' for more information
+(qemu) qemu-io virtio0 "write -P 0x22 0 1M"
+
+== Creating backup ==
+Backup Started
+*virtio0
+Backup Complete
+wrote 1048576/1048576 bytes at offset 0
+1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+(qemu) Formatting 'TEST_DIR/virtio0', fmt=qcow2 size=134217728 
cluster_size=65536 lazy_refcounts=off refcount_bits=16
+quit
+
+== Comparing images ==
+Images are identical.
+*** done
diff --git a/tests/qemu-iotests/group b/tests/qemu-iotests/group
index afbdc42..66fa231 100644
--- a/tests/qemu-iotests/group
+++ b/tests/qemu-iotests/group
@@ -186,4 +186,6 @@
 188 rw auto quick
 189 rw auto
 190 rw auto quick
+191 rw auto
 192 rw auto quick
+193 rw auto
-- 
2.7.4

[Qemu-devel] [PATCH v2 3/3] Add manpage for QEMU Backup Tool

[Ishani Chugh]

qemu-backup will be a command-line tool for performing full and
incremental disk backups on running VMs. It is intended as a
reference implementation for management stack and backup developers
to see QEMU's backup features in action. The following commit is an
initial implementation of manpage listing the commands which the
backup tool will support. The manpage wil be build along with other
docs when configure is provided with --enable-docs flag in the
location contrib/backup in build directory.


Signed-off-by: Ishani Chugh 
---
 Makefile|  14 ++--
 contrib/backup/qemu-backup.texi | 144 
 2 files changed, 154 insertions(+), 4 deletions(-)
 create mode 100644 contrib/backup/qemu-backup.texi

diff --git a/Makefile b/Makefile
index 81447b1..ba1574d 100644
--- a/Makefile
+++ b/Makefile
@@ -209,6 +209,7 @@ ifdef BUILD_DOCS
 DOCS=qemu-doc.html qemu-doc.txt qemu.1 qemu-img.1 qemu-nbd.8 qemu-ga.8
 DOCS+=docs/interop/qemu-qmp-ref.html docs/interop/qemu-qmp-ref.txt 
docs/interop/qemu-qmp-ref.7
 DOCS+=docs/interop/qemu-ga-ref.html docs/interop/qemu-ga-ref.txt 
docs/interop/qemu-ga-ref.7
+DOCS+=contrib/backup/qemu-backup.html contrib/backup/qemu-backup.txt
 ifdef CONFIG_VIRTFS
 DOCS+=fsdev/virtfs-proxy-helper.1
 endif
@@ -508,6 +509,8 @@ VERSION ?= $(shell cat VERSION)
 
 dist: qemu-$(VERSION).tar.bz2
 
+qemu-backup.8: contrib/backup/qemu-backup.texi
+
 qemu-%.tar.bz2:
$(SRC_PATH)/scripts/make-release "$(SRC_PATH)" "$(patsubst 
qemu-%.tar.bz2,%,$@)"
 
@@ -719,16 +722,19 @@ fsdev/virtfs-proxy-helper.1: 
fsdev/virtfs-proxy-helper.texi
 qemu-nbd.8: qemu-nbd.texi qemu-option-trace.texi
 qemu-ga.8: qemu-ga.texi
 
-html: qemu-doc.html docs/interop/qemu-qmp-ref.html 
docs/interop/qemu-ga-ref.html
-info: qemu-doc.info docs/interop/qemu-qmp-ref.info 
docs/interop/qemu-ga-ref.info
-pdf: qemu-doc.pdf docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf
-txt: qemu-doc.txt docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt
+html: qemu-doc.html docs/interop/qemu-qmp-ref.html 
docs/interop/qemu-ga-ref.html contrib/backup/qemu-backup.html
+info: qemu-doc.info docs/interop/qemu-qmp-ref.info 
docs/interop/qemu-ga-ref.info contrib/backup/qemu-backup.info
+pdf: qemu-doc.pdf docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf 
contrib/backup/qemu-backup.pdf
+txt: qemu-doc.txt docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt 
contrib/backup/qemu-backup.txt
 
 qemu-doc.html qemu-doc.info qemu-doc.pdf qemu-doc.txt: \
qemu-img.texi qemu-nbd.texi qemu-options.texi qemu-option-trace.texi \
qemu-monitor.texi qemu-img-cmds.texi qemu-ga.texi \
qemu-monitor-info.texi
 
+contrib/backup/qemu-backup.html contrib/backup/qemu-backup.pdf 
contrib/backup/qemu-backup.txt contrib/backup/qemu-backup.info: \
+   contrib/backup/qemu-backup.texi
+
 docs/interop/qemu-ga-ref.dvi docs/interop/qemu-ga-ref.html \
 docs/interop/qemu-ga-ref.info docs/interop/qemu-ga-ref.pdf \
 docs/interop/qemu-ga-ref.txt docs/interop/qemu-ga-ref.7: \
diff --git a/contrib/backup/qemu-backup.texi b/contrib/backup/qemu-backup.texi
new file mode 100644
index 000..68e7231
--- /dev/null
+++ b/contrib/backup/qemu-backup.texi
@@ -0,0 +1,144 @@
+\input texinfo
+@setfilename qemu-backup
+
+@documentlanguage en
+@documentencoding UTF-8
+
+@settitle QEMU Backup Tool
+@copying
+
+Copyright @copyright{} 2017 The QEMU Project developers
+@end copying
+@ifinfo
+@direntry
+* QEMU: (QEMU-backup).Man page for QEMU Backup Tool.
+@end direntry
+@end ifinfo
+@iftex
+@titlepage
+@sp 7
+@center @titlefont{QEMU Backup Tool}
+@sp 1
+@sp 3
+@end titlepage
+@end iftex
+@ifnottex
+@node Top
+@top Short Sample
+
+@menu
+* Name::
+* Synopsis::
+* List of Commands::
+* Command Parameters::
+* Command Descriptions::
+* License::
+@end menu
+
+@end ifnottex
+
+@node Name
+@chapter Name
+
+QEMU disk backup tool.
+
+@node Synopsis
+@chapter Synopsis
+
+qemu-backup command [command options].
+
+@node  List of Commands
+@chapter  List of Commands
+@itemize
+@item qemu-backup guest add --guest guestname --qmp socketpath
+@item qemu-backup guest list
+@item qemu-backup drive add --id driveid --guest guestname --target target
+@item qemu-backup drive add --all --guest guestname --target target
+@item qemu-backup drive list --guest guestname
+@item qemu-backup backup [--inc] --guest guestname
+@item qemu-backup restore --guest guestname
+@item qemu-backup guest remove --guest guestname
+@item qemu-backup drive remove --guest guestname --id driveid
+@end itemize
+@node  Command Parameters
+@chapter  Command Parameters
+@itemize
+@item --all: Add all the drives present in a guest which are suitable for 
backup.
+@item --guest: Name of the guest.
+@item --id: id of guest or drive.
+@item --inc: (Optional) For incremental backup.
+@item --qmp: Path of qmp socket.
+@item --target: Destination path on which you want your backup to be made.
+@end 

Re: [Qemu-devel] [PATCH v2 0/7] Misc throttle fixes

[Stefan Hajnoczi]

On Thu, Aug 24, 2017 at 04:24:42PM +0300, Alberto Garcia wrote:
> Hi,
> 
> here's the new version of my patch series with misc fixes for the
> throttling code.
> 
> Stefan, once this is reviewed, can you please remove the "Make
> LeakyBucket.avg and LeakyBucket.max integer types" commit (id
> 218f470639117a8e39) from your block-next branch? This series contains
> a new version of that patch that replaces the one that you have.
> 
> v2:
> - Patch 3: Make the code a bit more concise
> - Patch 5: LeakyBucket.avg and LeakyBucket.max are now unsigned
> - Patch 6: Make burst_length 64bit and check its range
> - Patch 7: Add unit tests
> 
> v1: https://lists.gnu.org/archive/html/qemu-block/2017-08/msg00753.html
> - Initial version
> 
> Output of backport-diff against v1:
> 
> Key:
> [] : patches are identical
> [] : number of functional differences between upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual differences, 
> respectively
> 
> 001/7:[] [--] 'throttle: Fix wrong variable name in the header 
> documentation'
> 002/7:[] [--] 'throttle: Update the throttle_fix_bucket() documentation'
> 003/7:[down] 'throttle: Make throttle_is_valid() a bit less verbose'
> 004/7:[] [--] 'throttle: Remove throttle_fix_bucket() / 
> throttle_unfix_bucket()'
> 005/7:[0010] [FC] 'throttle: Make LeakyBucket.avg and LeakyBucket.max integer 
> types'
> 006/7:[down] 'throttle: Make burst_length 64bit and add range checks'
> 007/7:[down] 'throttle: Test the valid range of config values'
> 
> Alberto Garcia (7):
>   throttle: Fix wrong variable name in the header documentation
>   throttle: Update the throttle_fix_bucket() documentation
>   throttle: Make throttle_is_valid() a bit less verbose
>   throttle: Remove throttle_fix_bucket() / throttle_unfix_bucket()
>   throttle: Make LeakyBucket.avg and LeakyBucket.max integer types
>   throttle: Make burst_length 64bit and add range checks
>   throttle: Test the valid range of config values
> 
>  include/qemu/throttle.h |  8 ++---
>  tests/test-throttle.c   | 80 -
>  util/throttle.c | 86 
> +++--
>  3 files changed, 117 insertions(+), 57 deletions(-)
> 
> -- 
> 2.11.0
> 
> 

I have dropped the previous "Make LeakyBucket.avg and LeakyBucket.max
integer types" commit and merged this series instead.

Thanks, applied to my block-next tree:
https://github.com/stefanha/qemu/commits/block-next

Stefan

[Qemu-devel] [PATCH v2 0/3] QEMU Backup Tool

[Ishani Chugh]

This patch series is intended to introduce QEMU Backup tool.
qemu-backup will be a command-line tool for performing full and
incremental disk backups on running VMs. It is intended as a
reference implementation for management stack and backup developers
to see QEMU's backup features in action.
This patch series contains three patches,
   1) QEMU Backup command line tool.
   2) Test for full backup.
   3) Manpage for the tool.

Ishani Chugh (3):
  backup: QEMU Backup Tool
  Test for full Backup
  Add manpage for QEMU Backup Tool

 Makefile|  14 +-
 contrib/backup/qemu-backup.py   | 335 
 contrib/backup/qemu-backup.texi | 144 +
 tests/qemu-iotests/191  |  86 +++
 tests/qemu-iotests/191.out  |  35 +
 tests/qemu-iotests/group|   2 +
 6 files changed, 612 insertions(+), 4 deletions(-)
 create mode 100644 contrib/backup/qemu-backup.py
 create mode 100644 contrib/backup/qemu-backup.texi
 create mode 100755 tests/qemu-iotests/191
 create mode 100644 tests/qemu-iotests/191.out

-- 
2.7.4

[Qemu-devel] [PATCH v2 1/3] backup: QEMU Backup Tool

[Ishani Chugh]

qemu-backup will be a command-line tool for performing full and
incremental disk backups on running VMs. It is intended as a
reference implementation for management stack and backup developers
to see QEMU's backup features in action. The tool writes details of
guest in a configuration file and the data is retrieved from the file
while creating a backup. The location of config file can be set as an
environment variable QEMU_BACKUP_CONFIG. The usage is as follows:

Add a guest
python qemu-backup.py guest add --guest  --qmp 

Add a drive for backup in a specified guest
python qemu-backup.py drive add --guest  --id  [--target 
]

Create backup of the added drives:
python qemu-backup.py backup --guest 

List all guest configs in configuration file:
python qemu-backup.py guest list

Restore operation
python qemu-backup.py restore --guest 

Remove a guest
python qemu-backup.py guest remove --guest 

Signed-off-by: Ishani Chugh 
---
 contrib/backup/qemu-backup.py | 335 ++
 1 file changed, 335 insertions(+)
 create mode 100644 contrib/backup/qemu-backup.py

diff --git a/contrib/backup/qemu-backup.py b/contrib/backup/qemu-backup.py
new file mode 100644
index 000..9a2ce63
--- /dev/null
+++ b/contrib/backup/qemu-backup.py
@@ -0,0 +1,335 @@
+#!/usr/bin/python
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017 Ishani Chugh 
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see .
+#
+
+"""
+This file is an implementation of backup tool
+"""
+from __future__ import print_function
+from argparse import ArgumentParser
+import os
+import errno
+from socket import error as socket_error
+try:
+import configparser
+except ImportError:
+import ConfigParser as configparser
+import sys
+sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..',
+ 'scripts', 'qmp'))
+from qmp import QEMUMonitorProtocol
+
+
+class BackupTool(object):
+"""BackupTool Class"""
+def __init__(self, config_file=os.path.expanduser('~') +
+ '/.config/qemu/qemu-backup-config'):
+if "QEMU_BACKUP_CONFIG" in os.environ:
+self.config_file = os.environ["QEMU_BACKUP_CONFIG"]
+else:
+self.config_file = config_file
+try:
+if not os.path.isdir(os.path.dirname(self.config_file)):
+os.makedirs(os.path.dirname(self.config_file))
+except:
+print("Cannot create config directory", file=sys.stderr)
+sys.exit(1)
+self.config = configparser.ConfigParser()
+self.config.read(self.config_file)
+
+def write_config(self):
+"""
+Writes configuration to ini file.
+"""
+config_file = open(self.config_file + ".tmp", 'w')
+self.config.write(config_file)
+config_file.flush()
+os.fsync(config_file.fileno())
+config_file.close()
+os.rename(self.config_file + ".tmp", self.config_file)
+
+def get_socket_address(self, socket_address):
+"""
+Return Socket address in form of string or tuple
+"""
+if socket_address.startswith('tcp'):
+return (socket_address.split(':')[1],
+int(socket_address.split(':')[2]))
+return socket_address.split(':', 2)[1]
+
+def _full_backup(self, guest_name):
+"""
+Performs full backup of guest
+"""
+if guest_name not in self.config.sections():
+print("Cannot find specified guest", file=sys.stderr)
+sys.exit(1)
+
+self.verify_guest_running(guest_name)
+connection = QEMUMonitorProtocol(
+ self.get_socket_address(
+ self.config[guest_name]['qmp']))
+connection.connect()
+cmd = {"execute": "transaction", "arguments": {"actions": []}}
+drive_list = []
+for key in self.config[guest_name]:
+if key.startswith("drive_"):
+drive = key[len('drive_'):]
+drive_list.append(drive)
+target = self.config[guest_name][key]
+sub_cmd = {"type": "drive-backup", "data": {"device": drive,
+"target": target,
+ 

Re: [Qemu-devel] [PATCH] crypto: fix test cert generation to not use SHA1 algorithm

[Eric Blake]

On 08/29/2017 11:34 AM, Daniel P. Berrange wrote:
> On Tue, Aug 29, 2017 at 11:31:24AM -0500, Eric Blake wrote:
>> On 08/29/2017 11:27 AM, Daniel P. Berrange wrote:
>>> GNUTLS 3.6.0 marked SHA1 as untrusted for certificates.
>>> Unfortunately the gnutls_x509_crt_sign() method we are
>>> using to create certificates in the test suite is fixed
>>> to always use SHA1. We must switch to a different method
>>> and explicitly ask for SHA256.
>>>
>>> Signed-off-by: Daniel P. Berrange 
>>> ---
>>>  tests/crypto-tls-x509-helpers.c | 3 ++-
>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/tests/crypto-tls-x509-helpers.c 
>>> b/tests/crypto-tls-x509-helpers.c
>>> index 64073d3bd3..173d4e28fb 100644
>>> --- a/tests/crypto-tls-x509-helpers.c
>>> +++ b/tests/crypto-tls-x509-helpers.c
>>> @@ -406,7 +406,8 @@ test_tls_generate_cert(QCryptoTLSTestCertReq *req,
>>>   * If no 'ca' is set then we are self signing
>>>   * the cert. This is done for the root CA certs
>>>   */
>>> -err = gnutls_x509_crt_sign(crt, ca ? ca : crt, privkey);
>>> +err = gnutls_x509_crt_sign2(crt, ca ? ca : crt, privkey,
>>> +GNUTLS_DIG_SHA256, 0);
>>
>> Is _sign2() available on all the older versions of gnutls that we must
>> support, or do we need this to be a conditional compilation?
> 
> It dates to gnutls 1.2.0 from 2005, so we're fine even if using RHEL5
> vintage :-)

Good to know. Not sure if it's worth mentioning that in the commit
message.  Either way,

Reviewed-by: Eric Blake 

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org



signature.asc
Description: OpenPGP digital signature

[Qemu-devel] [PATCH] io: fix check for handshake completion in TLS test

[Daniel P. Berrange]

The TLS I/O channel test had mistakenly used && instead
of || when checking for handshake completion. As a
result it could terminate the handshake process before
it had actually completed. This was harmless before but
changes in GNUTLS 3.6.0 exposed this bug and caused the
test suite to fail.

Signed-off-by: Daniel P. Berrange 
---
 tests/test-io-channel-tls.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/test-io-channel-tls.c b/tests/test-io-channel-tls.c
index 8eaa208e1b..e7c80f46cf 100644
--- a/tests/test-io-channel-tls.c
+++ b/tests/test-io-channel-tls.c
@@ -218,7 +218,7 @@ static void test_io_channel_tls(const void *opaque)
 mainloop = g_main_context_default();
 do {
 g_main_context_iteration(mainloop, TRUE);
-} while (!clientHandshake.finished &&
+} while (!clientHandshake.finished ||
  !serverHandshake.finished);
 
 g_assert(clientHandshake.failed == data->expectClientFail);
-- 
2.13.5

Re: [Qemu-devel] [PATCH] crypto: fix test cert generation to not use SHA1 algorithm

[Daniel P. Berrange]

On Tue, Aug 29, 2017 at 11:31:24AM -0500, Eric Blake wrote:
> On 08/29/2017 11:27 AM, Daniel P. Berrange wrote:
> > GNUTLS 3.6.0 marked SHA1 as untrusted for certificates.
> > Unfortunately the gnutls_x509_crt_sign() method we are
> > using to create certificates in the test suite is fixed
> > to always use SHA1. We must switch to a different method
> > and explicitly ask for SHA256.
> > 
> > Signed-off-by: Daniel P. Berrange 
> > ---
> >  tests/crypto-tls-x509-helpers.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/tests/crypto-tls-x509-helpers.c 
> > b/tests/crypto-tls-x509-helpers.c
> > index 64073d3bd3..173d4e28fb 100644
> > --- a/tests/crypto-tls-x509-helpers.c
> > +++ b/tests/crypto-tls-x509-helpers.c
> > @@ -406,7 +406,8 @@ test_tls_generate_cert(QCryptoTLSTestCertReq *req,
> >   * If no 'ca' is set then we are self signing
> >   * the cert. This is done for the root CA certs
> >   */
> > -err = gnutls_x509_crt_sign(crt, ca ? ca : crt, privkey);
> > +err = gnutls_x509_crt_sign2(crt, ca ? ca : crt, privkey,
> > +GNUTLS_DIG_SHA256, 0);
> 
> Is _sign2() available on all the older versions of gnutls that we must
> support, or do we need this to be a conditional compilation?

It dates to gnutls 1.2.0 from 2005, so we're fine even if using RHEL5
vintage :-)

Regards,
Daniel
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