From: Xiao Guangrong
Currently we have two behaviors if all threads are busy to do compression,
the main thread mush wait one of them becoming free if @compress-wait-thread
set to on or the main thread can directly return without wait and post
the page out as normal one
Both of them have its pro
From: Xiao Guangrong
It introduces a new statistic, pages-per-second, as bandwidth or mbps is
not enough to measure the performance of posting pages out as we have
compression, xbzrle, which can significantly reduce the amount of the
data size, instead, pages-per-second if the one we want
Signed
Patchew URL:
https://patchew.org/QEMU/20181213040126.6768-1-da...@gibson.dropbear.id.au/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20181213040126.6768-1-da...@gibson.dropbear.id.au
Subject: [Qemu-devel] [PULL 00/2
There's a question for David Gibson inline. Please search for /ppc/.
Fei Li writes:
> Make qemu_thread_create() return a Boolean to indicate if it succeeds
> rather than failing with an error. And add an Error parameter to hold
> the error message and let the callers handle it.
The "rather tha
It's been deprecated since QEMU 3.0, and nobody complained so far, so
it is time to remove this option now.
Signed-off-by: Thomas Huth
---
docs/qdev-device-use.txt | 4
include/hw/boards.h | 1 -
qemu-deprecated.texi | 5
qemu-options.hx | 10
vl.c
On 2018-10-30 13:35, Kashyap Chamarthy wrote:
> The intended functionality of QMP `cpu-add` is replaced with
> `device_add` (and `query-hotpluggable-cpus`). So let's deprecate
> `cpu-add`.
>
> A complete example of vCPU hotplug with the recommended way (using
> `device_add`) is provided as part o
On 2018-12-10 14:58, Peter Maydell wrote:
> Taking the address of a field in a packed struct is a bad idea, because
> it might not be actually aligned enough for that pointer type (and
> thus cause a crash on dereference on some host architectures). Newer
> versions of clang warn about this.
>
> A
Patchew URL: https://patchew.org/QEMU/20181213015013.15350-1-js...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20181213015013.15350-1-js...@redhat.com
Subject: [Qemu-devel] [PATCH v2 0/7] bitmaps: remove
Fei Li writes:
> In our current code, when multifd is used during migration, if there
> is an error before the destination receives all new channels, the
> source keeps running, however the destination does not exit but keeps
> waiting until the source is killed deliberately.
>
> Fix this by dump
Marc-André Lureau writes:
> Hi
>
> On Wed, Dec 12, 2018 at 9:18 PM Markus Armbruster wrote:
>>
>> Marc-André Lureau writes:
>>
>> > This is the second part of the "add #if pre-processor conditions to
>> > generated code" series, adding schema member conditions (roughly
>> > 16-38/49).
>> >
>> >
Soon we will call cpu_has_work without the BQL.
Cc: Cornelia Huck
Cc: Alexander Graf
Cc: David Hildenbrand
Cc: qemu-s3...@nongnu.org
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/s390x/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/targ
Soon we will call cpu_has_work without the BQL.
Cc: Mark Cave-Ayland
Cc: Artyom Tarasenko
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/sparc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 88
In ppce500_spin.c, acquire the lock just once to update
both cpu->halted and cpu->stopped.
In hw/ppc/spapr_hcall.c, acquire the lock just once to
update cpu->halted and call cpu_has_work, since later
in the series we'll acquire the BQL (if not already held)
from cpu_has_work.
Cc: David Gibson
Cc
This yields sizable scalability improvements, as the below results show.
Host: Two Intel E5-2683 v3 14-core CPUs at 2.00 GHz (Haswell)
Workload: Ubuntu 18.04 ppc64 compiling the linux kernel with
"make -j N", where N is the number of cores in the guest.
Speedup vs a single
After completing the conversion to per-CPU locks, there is no need
to release the BQL after having called cpu_kick.
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
cpus-common.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/cpus-commo
This function is only called from TCG rr mode, so add
a prefix to mark this as well as an assertion.
Signed-off-by: Emilio G. Cota
---
cpus.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/cpus.c b/cpus.c
index fa66d84bc7..b89d3790d7 100644
--- a/cpus.c
+++ b/cpus
Cc: David Gibson
Cc: Alexander Graf
Cc: qemu-...@nongnu.org
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
hw/ppc/ppc.c| 2 +-
target/ppc/excp_helper.c| 2 +-
target/ppc/kvm.c| 4 ++--
target/ppc/translate_init.inc.c | 14 +++
Soon we will call cpu_has_work without the BQL.
Cc: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/riscv/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 del
Cc: Chris Wulff
Cc: Marek Vasut
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/nios2/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index fbfaa2ce26..49a75414d3 100644
--- a/ta
Cc: Andrzej Zaborowski
Cc: Peter Maydell
Cc: qemu-...@nongnu.org
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
hw/arm/omap1.c| 4 ++--
hw/arm/pxa2xx_gpio.c | 2 +-
hw/arm/pxa2xx_pic.c | 2 +-
target/arm/arm-powerctl.c | 4 ++--
Soon we will call cpu_has_work without the BQL.
Cc: David Gibson
Cc: Alexander Graf
Cc: qemu-...@nongnu.org
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/ppc/translate_init.inc.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/ta
Soon we will call cpu_has_work without the BQL.
Cc: Aurelien Jarno
Cc: Aleksandar Markovic
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/mips/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index fdae
It will gain some users soon.
Suggested-by: Paolo Bonzini
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 8d4
On Thu, Dec 13, 2018 at 01:00:39AM +0530, P J P wrote:
> From: Prasad J Pandit
>
> pvrdma_idx_ring_has_[data/space] routines also return invalid
> index PVRDMA_INVALID_IDX[=-1], if ring has no data/space. Check
> return value from these routines to avoid plausible infinite loops.
>
> Reported-by
Soon we will call cpu_has_work without the BQL.
Cc: Max Filippov
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/xtensa/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index d4ca35e6cc..5f3b4a70b0 10
Cc: Cornelia Huck
Cc: Christian Borntraeger
Cc: Alexander Graf
Cc: David Hildenbrand
Cc: qemu-s3...@nongnu.org
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Cornelia Huck
Signed-off-by: Emilio G. Cota
---
hw/intc/s390_flic.c | 2 +-
target/s390x/cpu.c | 2 +-
2 file
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 95747f5abf..8d4160689f 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -84,7
On Thu, Dec 13, 2018 at 01:00:38AM +0530, P J P wrote:
> From: Prasad J Pandit
>
> With commit 4481985c (rdma: check num_sge does not exceed MAX_SGE)
> macro VENDOR_ERR_NO_SGE is no longer in use - delete it.
>
> Signed-off-by: Prasad J Pandit
> ---
> hw/rdma/rdma_backend.c | 3 +--
> 1 file c
From: Paolo Bonzini
Cc: Cornelia Huck
Cc: Alexander Graf
Cc: David Hildenbrand
Cc: qemu-s3...@nongnu.org
Reviewed-by: David Hildenbrand
Reviewed-by: Richard Henderson
Reviewed-by: Cornelia Huck
Reviewed-by: Alex Bennée
Signed-off-by: Paolo Bonzini
Signed-off-by: Emilio G. Cota
---
targe
Use the per-CPU locks to protect the CPUs' state, instead of
using the BQL. These locks are uncontended (they are mostly
acquired by the corresponding vCPU thread), so acquiring them
is cheaper than acquiring the BQL, which particularly in
MTTCG can be contended at high core counts.
In this conver
Cc: Guan Xuetao
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/unicore32/cpu.c | 2 +-
target/unicore32/softmmu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 2
Cc: Peter Maydell
Cc: qemu-...@nongnu.org
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/arm/cpu.c| 6 +++---
target/arm/helper.c | 16 +++-
2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8baa5
Some async jobs do not need the BQL.
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h | 14 ++
cpus-common.c | 39 ++-
2 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/include/qom/cpu.h b/includ
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/i386/kvm.c | 54 +++
1 file changed, 31 insertions(+), 23 deletions(-)
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index a3d1f47556..61b9473403 100644
--- a/target/i386/kvm
Cc: Stafford Horne
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
hw/openrisc/cputimer.c | 2 +-
target/openrisc/cpu.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 850f
Cc: Cornelia Huck
Cc: Christian Borntraeger
Cc: Alexander Graf
Cc: David Hildenbrand
Cc: qemu-s3...@nongnu.org
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
hw/intc/s390_flic.c| 2 +-
target/s390x/cpu.c | 22 +++---
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/cpu-exec.c | 15 ---
accel/tcg/tcg-all.c | 12 +---
accel/tcg/translate-all.c | 2 +-
3 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/accel/tcg/cp
Cc: Anthony Green
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/moxie/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 8d67eb6727..bad92cfc61 100644
--- a/target/moxie/cpu.
Cc: "Edgar E. Iglesias"
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/cris/cpu.c| 2 +-
target/cris/helper.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index a23aba2688.
Cc: "Edgar E. Iglesias"
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/microblaze/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 9b546a2c18..206fdd8651 100644
--
Cc: Mark Cave-Ayland
Cc: Artyom Tarasenko
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
hw/sparc64/sparc64.c | 4 ++--
target/sparc/cpu.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/spar
Cc: Aurelien Jarno
Cc: Aleksandar Markovic
Cc: James Hogan
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/mips/cpu.c | 7 ---
target/mips/kvm.c | 2 +-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index e217f
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/i386/hax-all.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c
index 8b53a9708f..70cea8b1a1 100644
--- a/target/i386/hax-all.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/hppa/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 00bf444620..1ab4e62850 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu
Cc: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
Signed-off-by: Emilio G. Cota
---
target/m68k/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 582e3a73b3..99a7eb4340 100644
--- a/target/m68k/cpu.
This finishes the conversion to interrupt_request.
Signed-off-by: Emilio G. Cota
---
qom/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qom/cpu.c b/qom/cpu.c
index 44b78f1892..7452109833 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -275,7 +275,7 @@ static void cpu_com
Cc: Stafford Horne
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/openrisc/sys_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index b66a45c1e0..ab4d8fb520
From: Paolo Bonzini
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Paolo Bonzini
Signed-off-by: Emilio G. Cota
---
target/i386/hax-all.c| 4 ++--
target/i386/hvf/x86hvf.c | 8
target/i386/kvm.c| 14 +++---
target/i386/seg_helper.c | 13 +
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/alpha/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index a953897fcc..4e8965fb6c 100644
--- a/target/alpha/cpu.c
+++ b/tar
This finishes the conversion to cpu_halted.
Signed-off-by: Emilio G. Cota
---
cpus.c| 8
qom/cpu.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index e85dbbb166..fa66d84bc7 100644
--- a/cpus.c
+++ b/cpus.c
@@ -204,7 +204,7 @@ static bool cpu
Add a comment about how atomic_read works here. The comment refers to
a "BQL-less CPU loop", which will materialize toward the end
of this series.
Note that the modifications to cpu_reset_interrupt are there to
avoid deadlock during the CPU lock transition; once that is complete,
cpu_interrupt_req
From: Paolo Bonzini
Cc: Stafford Horne
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Paolo Bonzini
Signed-off-by: Emilio G. Cota
---
target/openrisc/sys_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: Paolo Bonzini
Cc: David Gibson
Cc: Alexander Graf
Cc: qemu-...@nongnu.org
Acked-by: David Gibson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Paolo Bonzini
Signed-off-by: Emilio G. Cota
---
target/ppc/excp_helper.c | 2 +
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdbstub.c b/gdbstub.c
index c4e4f9f082..4e809ceddb 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1304,7 +1304,7 @@ static int gdb_
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index bb6170dbff..04d505500b 100644
--- a/exec.c
+++ b/exec.c
@@ -776,7 +776,7 @@ static int cpu_common_post_load(
Cc: Aurelien Jarno
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/sh4/cpu.c| 2 +-
target/sh4/helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index b9f393b7c7..58ea212f53 1
Cc: Fabien Chouteau
Cc: Mark Cave-Ayland
Cc: Artyom Tarasenko
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
hw/sparc/leon3.c | 2 +-
hw/sparc/sun4m.c | 8
hw/sparc64/sparc64.c | 4 ++--
target/sparc/helper.c | 2 +-
4 files chan
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/i386/whpx-all.c | 41 -
1 file changed, 24 insertions(+), 17 deletions(-)
diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c
index 9673bdc219..0d8cfa3a19 100644
--- a/target
Cc: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/m68k/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 8d09ed91
Cc: "Edgar E. Iglesias"
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/microblaze/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 78ca265b04.
Cc: Aurelien Jarno
Cc: Aleksandar Markovic
Cc: James Hogan
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
hw/mips/cps.c | 2 +-
hw/misc/mips_itu.c | 4 ++--
target/mips/kvm.c | 2 +-
target/mips/op_helper.c | 8
target/
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/i386/hvf/hvf.c| 8 +---
target/i386/hvf/x86hvf.c | 26 +++---
2 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index c1ff220985..619a
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/tcg-runtime.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 4aa038465f..70e3c9de71 100644
--- a/accel/tcg/tcg-runtime
Cc: Eduardo Habkost
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/i386/cpu.h | 2 +-
target/i386/cpu.c | 2 +-
target/i386/hax-all.c | 4 ++--
target/i386/helper.c | 4 ++--
target/i386/hvf/hvf.c | 8
Cc: Michael Walle
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/lm32/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index b7499cb627..1508bb6199 100644
--- a/target/lm32/cpu.c
++
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/alpha/translate.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index e5d62850c5..25cd95931d 100644
--- a/target/alpha
We don't pass a pointer to qemu_global_mutex anymore.
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h | 10 --
cpus-common.c | 2 +-
cpus.c| 5 -
3 files changed, 1 insertion(+), 16 deletions(-)
diff --git a/include/qom/cpu.h b/i
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/i386/cpu.c| 2 +-
target/i386/helper.c | 4 ++--
target/i386/svm_helper.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 22cca17b9e..35d1d2d10
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
accel/tcg/tcg-runtime.h | 2 ++
accel/tcg/tcg-runtime.c | 7 +++
2 files changed, 9 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 1bd39d136d..d767f8515b 100644
--- a/accel/tcg/tcg-runtime.h
Cc: Aurelien Jarno
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/sh4/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 4f825bae5a..57cc363ccc 100644
--- a/targ
Before we can switch from the BQL to per-CPU locks in
the CPU loop, we have to accommodate the fact that TCG
rr mode (i.e. !MTTCG) cannot work with separate per-vCPU
locks. That would lead to deadlock since we need a single
lock/condvar pair on which to wait for events that affect
any vCPU, e.g. in
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
accel/tcg/cpu-exec.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 870027d435..b4f46134d3 100644
--- a/accel/tcg/cpu-exec.c
+++ b/ac
Cc: Michael Walle
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/lm32/op_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c
index 234d55e056..392634441b 100644
---
Cc: Max Filippov
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/xtensa/cpu.c | 2 +-
target/xtensa/helper.c| 2 +-
target/xtensa/op_helper.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/xtensa/cpu.c b/
This eliminates the need to use the BQL to queue CPU work.
While at it, give the per-cpu field a generic name ("cond") since
it will soon be used for more than just queueing CPU work.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h |
cpu->halted will soon be protected by cpu->lock.
We will use these helpers to ease the transition,
since right now cpu->halted has many direct callers.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h | 24
1 f
Cc: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Laurent Vivier
Signed-off-by: Emilio G. Cota
---
target/m68k/translate.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index
Cc: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
target/riscv/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ta
Cc: David Gibson
Cc: Alexander Graf
Cc: qemu-...@nongnu.org
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/ppc/translate.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.
And fix the temp leak along the way.
Cc: "Edgar E. Iglesias"
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/cris/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/transla
Instead of open-coding it.
While at it, make sure that all accesses to the list are
performed while holding the list's lock.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h | 6 +++---
cpus-common.c | 25
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
target/hppa/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ce05d5619d..df9179e70f 100644
--- a/target/hppa/transla
This completes the conversion to cpu_mutex_lock/unlock in the file.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
cpus-common.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/cpus-common.c b/cpus-common.c
index
This lock will soon protect more fields of the struct. Give
it a more appropriate name.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h | 5 +++--
cpus-common.c | 14 +++---
cpus.c| 4 ++--
qom/cpu.c
The few direct users of &cpu->lock will be converted soon.
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h | 33 +++
cpus.c | 48 +++--
stubs/cpu-lock.c| 28
v4: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg05624.html
Changes since v4:
- Add R-b's -- thanks everyone!
- Rebase on v3.1.0
+ Add an additional conversion to cpu_interrupt_request in target/arm
due to 89430fc6f8 ("target/arm: Correctly implement handling of
HCR_EL2.{VI
From: Cédric Le Goater
The IVPE scans the O/S CAM line of the XIVE thread interrupt contexts
to find a matching Notification Virtual Target (NVT) among the NVTs
dispatched on the HW processor threads.
On a real system, the thread interrupt contexts are updated by the
hypervisor when a Virtual Pr
From: "Paul A. Clarke"
Changes requirement for "vsubsbs" instruction, which has been supported
since ISA 2.03. (Please see section 5.9.1.2 of ISA 2.03)
Reported-by: Paul A. Clarke
Signed-off-by: Paul A. Clarke
Signed-off-by: Leonardo Bras
Signed-off-by: David Gibson
---
target/ppc/translate
From: Cédric Le Goater
After the event data was enqueued in the O/S Event Queue, the IVPE
raises the bit corresponding to the priority of the pending interrupt
in the register IBP (Interrupt Pending Buffer) to indicate there is an
event pending in one of the 8 priority queues. The Pending Interru
From: Cédric Le Goater
sPAPRXive models the XIVE interrupt controller of the sPAPR machine.
It inherits from the XiveRouter and provisions storage for the routing
tables :
- Event Assignment Structure (EAS)
- Event Notification Descriptor (END)
The sPAPRXive model incorporates an internal X
From: Cédric Le Goater
The first sub-engine of the overall XIVE architecture is the Interrupt
Virtualization Source Engine (IVSE). An IVSE can be integrated into
another logic, like in a PCI PHB or in the main interrupt controller
to manage IPIs.
Each IVSE instance is associated with an Event St
From: Cédric Le Goater
The XIVE sPAPR IRQ backend will use it to define the number of ENDs of
the IC controller.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 8
include/hw/ppc/spapr.h | 1 +
2 files changed, 5 insertions(+), 4 deletions(-)
From: Cédric Le Goater
To complete the event routing, the IVRE sub-engine uses a second table
containing Event Notification Descriptor (END) structures.
An END specifies on which Event Queue (EQ) the event notification
data, defined in the associated EAS, should be posted when an
exception occur
From: Cédric Le Goater
Each POWER9 processor chip has a XIVE presenter that can generate four
different exceptions to its threads:
- hypervisor exception,
- O/S exception
- Event-Based Branch (EBB)
- msgsnd (doorbell).
Each exception has a state independent from the others called a Thre
From: Greg Kurz
The OpenPIC have 5 outputs per connected CPU. The machine init code hence
needs a bi-dimensional array (smp_cpu lines, 5 columns) to wire up the irqs
between the PIC and the CPUs.
The current code first allocates an array of smp_cpus pointers to qemu_irq
type, then it allocates a
From: Cédric Le Goater
The Event Notification Descriptor (END) XIVE structure also contains
two Event State Buffers providing further coalescing of interrupts,
one for the notification event (ESn) and one for the escalation events
(ESe). A MMIO page is assigned for each to control the EOI through
From: Cédric Le Goater
The 'sent' status of the LSI interrupt source is modeled with the 'P'
bit of the ESB and the assertion status of the source is maintained
with an extra bit under the main XiveSource object. The type of the
source is stored in the same array for practical reasons.
Signed-of
From: Cédric Le Goater
The last sub-engine of the XIVE architecture is the Interrupt
Virtualization Presentation Engine (IVPE). On HW, the IVRE and the
IVPE share elements, the Power Bus interface (CQ), the routing table
descriptors, and they can be combined in the same HW logic. We do the
same i
From: Greg Kurz
Because it is a recommended coding practice (see HACKING).
Signed-off-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Signed-off-by: David Gibson
---
hw/ppc/ppc440_bamboo.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --gi
From: Cédric Le Goater
The XiveNotifier offers a simple interface, between the XiveSource
object and the main interrupt controller of the machine. It will
forward event notifications to the XIVE Interrupt Virtualization
Routing Engine (IVRE).
Signed-off-by: Cédric Le Goater
[dwg: Adjust type na
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