[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1585533
Title:
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1590322
Title:
On Fri, Jul 26, 2019 at 10:10:59AM +0100, Stefan Hajnoczi wrote:
> When debug output is disabled there is no need to calculate the number
> of in/out bytes available.
>
> There is also no need to skip a request if there are 0 out bytes. The
> request parsing code already handles invalid
On Fri, Jul 26, 2019 at 10:11:00AM +0100, Stefan Hajnoczi wrote:
> Most lo_do_lookup() have already checked that the parent inode exists.
> lo_lookup() hasn't and can therefore hit a NULL pointer dereference when
> lo_inode(req, parent) returns NULL.
>
Sigh...this one has been fixed by 3
When we account for DMA aliases in the PCI address space, we can no
longer use a single IVHD entry in the IVRS covering all devices. We
instead need to walk the PCI bus and create alias ranges when we find
a conventional bus. These alias ranges cannot overlap with a "Select
All" range (as
Please see patch 1/ for the motivation and utility of this series.
This v1 submission improves on the previous RFC with revised commit
logs, comments, and more testing, and the missing IVRS support for DMA
alias ranges is now included. Testing has been done with Linux guests
with both SeaBIOS and
PCIe requester IDs are used by modern IOMMUs to differentiate devices
in order to provide a unique IOVA address space per device. These
requester IDs are composed of the bus/device/function (BDF) of the
requesting device. Conventional PCI pre-dates this concept and is
simply a shared parallel
John, please see inline...
Regards,
Dmitry
On Thu, 2019-07-25 at 13:58 -0400, John Snow wrote:
>
> On 7/23/19 6:19 PM, Dmitry Fomichev wrote:
> > Currently, attaching zoned block devices (i.e., storage devices
> > compliant to ZAC/ZBC standards) using several virtio methods doesn't
> > work
Hello
I am working with qemu tracing support and combined with tcg.
I read that if tcg property is used for trace-event, it generates a
trace-event once during translation and another trace-event after the
execution.
I made the following change in target/i386/translate.c
-static inline void
From: Alistair Francis
Fix a typo in the warning message displayed to users, don't print the
message when running inside qtest and don't mention a specific QEMU
version for the deprecation.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
The following changes since commit bf8b024372bf8abf5a9f40bfa65eeefad23ff988:
Update version for v4.1.0-rc2 release (2019-07-23 18:28:08 +0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-rc3
for you to fetch changes up to
We can turn logging on/off globally instead of per-function.
Remove use_log from run_job, and use python logging to turn on
diffable output when we run through a script entry point.
(No, I have no idea why output on 245 changed. I really don't.)
Signed-off-by: John Snow
---
Like script_main, but doesn't require a single point of entry.
Replace all existing initialization sections with this drop-in replacement.
This brings debug support to all existing script-style iotests.
Note: supported_oses=['linux'] was omitted, as it is a default argument.
Signed-off-by: John
Based-on: https://github.com/jnsnow/qemu/tree/bitmaps
This is a quick hack-em-up of what it might look like to use python
logging to enable output conditionally on iotests.log(). We unify an
initialization call (which also enables debugging output for those tests
with -d) and then make the switch
On Fri, Jul 26, 2019 at 2:00 PM Jonathan Behrens wrote:
>
> The remaining checks are not sufficient. If you look at the bottom of csr.c,
> you'll see that for most of the M-mode CSRs the predicate is set to "any"
> which unconditionally allows access regardless of privilege mode. The S-mode
>
The remaining checks are not sufficient. If you look at the bottom of
csr.c, you'll see that for most of the M-mode CSRs the predicate is set to
"any" which unconditionally allows access regardless of privilege mode. The
S-mode CSR predicates similarly only check that supervisor mode exists, but
CCing Cleber and Gabriel. Comments at the "conclusions" section
below:
On Wed, Jul 24, 2019 at 05:06:41PM -0400, John Snow wrote:
> Has anyone on this list experimented with these tools?
>
> I was hoping to use them to document things like the python/machine.py
> and python/qmp.py modules to
On 26/07/19 15:04, Stefan Hajnoczi wrote:
> On Thu, Jul 25, 2019 at 03:23:51AM +, Oleinik, Alexander wrote:
>> Locate mmio and port i/o addresses that are mapped to devices so we can
>> limit the fuzzer to only these addresses. This should be replaced with
>> a sane way of enumaring these
26 июля 2019 г. 2:25:03 GMT+02:00, John Snow пишет:
>Oh, this is fun.
...
>I can worry about a proper fix for 4.2+.
Hello John,
Thanks for your letter.
I double-checked the git history and mailing list, I'm still sure
that my fix for this assertion is correct.
You know this code very
On 26/07/19 14:56, Stefan Hajnoczi wrote:
> This should use indirection: a function pointer to dispatch to either
> the socket or the internal qtest_process_inbuf() call.
>
> With a bit of refactoring you can eliminate the #ifdefs and treat the
> socket fd as one backend and direct invocation as
Patchew URL:
https://patchew.org/QEMU/20190726164921.1655115-1-stef...@linux.vnet.ibm.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
On Fri, Jul 26, 2019 at 5:10 AM Markus Armbruster wrote:
>
> hw/boards.h pulls in almost 60 headers. The less we include it into
> headers, the better. As a first step, drop superfluous inclusions,
> and downgrade some more to what's actually needed. Gets rid of just
> one inclusion into a
On Fri, Jul 26, 2019 at 10:41 AM Chih-Min Chao wrote:
>
>
>
> On Fri, Jul 26, 2019 at 2:55 AM Alistair Francis
> wrote:
>>
>> Update the Hypervisor CSR addresses to match the v0.4 spec.
>>
>> Signed-off-by: Alistair Francis
>> ---
>> target/riscv/cpu_bits.h | 35
On Fri, Jul 19, 2019 at 6:41 AM Guenter Roeck wrote:
>
> The riscv uart needs valid clocks. This requires a refereence
> to the clock node. Since the SOC clock is not emulated by qemu,
> add a reference to a fixed clock instead. The clock-frequency
> entry in the uart node does not seem to be
On Fri, Jul 26, 2019 at 10:12 AM Chih-Min Chao wrote:
>
>
>
> On Thu, Jul 25, 2019 at 8:12 AM Alistair Francis wrote:
>>
>> On Tue, Jul 23, 2019 at 11:46 PM Chih-Min Chao
>> wrote:
>> >
>> > Similar to the mips + malta test, it boots a Linux kernel on a virt
>> > board and verify the serial is
On Thu, Jul 25, 2019 at 2:48 PM Jonathan Behrens wrote:
>
> Unless I'm missing something, this is the only place that QEMU checks the
> privilege level for read and writes to CSRs. The exact computation used here
> won't work with the hypervisor extension, but we also can't just get rid of
>
Paolo, Stefan and Kevin: can I loop you in here? I'm quite uncertain
about this and I'd like to clear this up quickly if it's possible:
On 7/25/19 8:58 PM, John Snow wrote:
>
>
> On 7/7/19 10:55 PM, shaju.abra...@nutanix.com wrote:
>> From: Shaju Abraham
>>
>> During the IDE DMA transfer for
On 26/07/19 21:36, Oleinik, Alexander wrote:
>>
>> Please add the ram file to qemu-file.c instead of duplicating QEMUFile.
>>
> I think we should be able to replace all of this simply by using
> memfd_create. Since it acts as a regular file, it will work with the
> existing code (likely with
On 7/26/19 8:47 AM, Stefan Hajnoczi wrote:
> On Thu, Jul 25, 2019 at 03:23:49AM +, Oleinik, Alexander wrote:
>> The ramfile allows vmstate to be saved and restored directly onto the
>> heap.
>>
>> Signed-off-by: Alexander Oleinik
>> ---
>> tests/fuzz/ramfile.c | 127
On 7/26/19 11:13 AM, Peter Maydell wrote:
> On Fri, 26 Jul 2019 at 18:51, Richard Henderson
> wrote:
>>
>> We miss quite a number of single-step events by having
>> the check in the wrong place.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> target/arm/translate.c | 16 ++--
>> 1
Patchew URL:
https://patchew.org/QEMU/20190726175032.6769-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to
decodetree
Fold away all of the cases that now just goto illegal_op,
because all of their internal bits are now in decodetree.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 69 ++
1 file changed, 16 insertions(+), 53 deletions(-)
diff --git
vandersonmr writes:
> Adding info [tbs|tb|coverset] commands to HMP.
> These commands allow the exploration of TBs
> generated by the TCG. Understand which one
> hotter, with more guest/host instructions...
> and examine their guest, host and IR code.
>
> The goal of this command is to allow
On Fri, 26 Jul 2019 at 18:51, Richard Henderson
wrote:
>
> We miss quite a number of single-step events by having
> the check in the wrong place.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/translate.c | 16 ++--
> 1 file changed, 6 insertions(+), 10 deletions(-)
>
>
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 152 ++---
target/arm/t16.decode | 36 ++
2 files changed, 43 insertions(+), 145 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index db93b12608..17a0eea425
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 3 +--
target/arm/t16.decode | 17 +
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c9386ceefb..55404414a2 100644
--- a/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 14 +-
target/arm/t16.decode | 10 ++
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8dd88419fe..9c8e11bd3a 100644
---
We miss quite a number of single-step events by having
the check in the wrong place.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 89 +++---
target/arm/t16.decode | 3 ++
2 files changed, 43 insertions(+), 49 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 480515a0a9..a8db6e9280 100644
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 26 ++
target/arm/t16.decode | 8
2 files changed, 10 insertions(+), 24 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f3a946d8c9..f9022fe65c 100644
---
Add the infrastructure that will become the new decoder.
No instructions adjusted so far.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 45 +++-
target/arm/Makefile.objs | 18 +++
target/arm/a32-uncond.decode | 23
This is the only remaining use of gen_bx_im. Simplify, since we know
the destination mode is changing. Use gen_jmp for the actual branch.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 23 +++
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 83 ++
target/arm/t16.decode | 10 +
2 files changed, 22 insertions(+), 71 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 55404414a2..5d0d0779c8 100644
---
Fold away all of the cases that now just goto illegal_op,
because all of their internal bits are now in decodetree.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 78 ++
1 file changed, 3 insertions(+), 75 deletions(-)
diff --git
Now that everything is converted, remove the rest of
the legacy decode.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 27 ++-
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 64 +++---
target/arm/t16.decode | 10 +++
2 files changed, 33 insertions(+), 41 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9bdcb91537..e2183eb543 100644
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 85 --
target/arm/t16.decode | 12 ++
2 files changed, 52 insertions(+), 45 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9c8e11bd3a..8f2adbbc7d 100644
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 18 +++---
target/arm/t16.decode | 9 +
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8f2adbbc7d..c9386ceefb 100644
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 111 -
target/arm/t16.decode | 31
2 files changed, 54 insertions(+), 88 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 97c472c8f7..f3a946d8c9
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 49 ++
target/arm/t16.decode | 10 +
2 files changed, 12 insertions(+), 47 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e2183eb543..23f5f982f5 100644
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 9 ++---
target/arm/t16.decode | 6 ++
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f1cab437e0..480515a0a9 100644
--- a/target/arm/translate.c
+++
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 42 ++
target/arm/t16.decode | 4
2 files changed, 6 insertions(+), 40 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f9022fe65c..f1cab437e0 100644
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 26 +++---
target/arm/t16.decode | 12
2 files changed, 15 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5d0d0779c8..97c472c8f7 100644
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 15 ++-
target/arm/t16.decode | 9 +
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 23f5f982f5..8dd88419fe 100644
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 6 ++
target/arm/Makefile.objs | 6 ++
target/arm/t16.decode| 20
3 files changed, 32 insertions(+)
create mode 100644 target/arm/t16.decode
diff --git a/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 62 +++---
target/arm/t32.decode | 8 +-
2 files changed, 41 insertions(+), 29 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 87cbadc6cb..9c6623fb6b 100644
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 12 +---
target/arm/t16.decode | 7 +++
2 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 28f274ca7c..525276ed13 100644
--- a/target/arm/translate.c
+++
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 26 ++
target/arm/t16.decode | 16
2 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f551fde3db..692891dbe0 100644
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 19 +--
target/arm/a32.decode | 4
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3f14e5c7f3..7ea118a795 100644
--- a/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 88 ++
target/arm/t32.decode | 5 ++-
2 files changed, 32 insertions(+), 61 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index df515e9341..a750a2c092 100644
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 87 +++-
target/arm/a32-uncond.decode | 3 ++
target/arm/t32.decode| 3 ++
3 files changed, 42 insertions(+), 51 deletions(-)
diff --git a/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 122 +++
target/arm/a32-uncond.decode | 10 +++
target/arm/t32.decode| 10 +++
3 files changed, 73 insertions(+), 69 deletions(-)
diff --git a/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 51 --
target/arm/t32.decode | 5 -
2 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9c6623fb6b..df515e9341 100644
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 150 ++-
target/arm/a32-uncond.decode | 8 ++
target/arm/t32.decode| 12 +++
3 files changed, 81 insertions(+), 89 deletions(-)
diff --git a/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 134 +++
target/arm/a32-uncond.decode | 8 +++
target/arm/a32.decode| 8 +++
target/arm/t32.decode| 79 +
4 files changed, 122 insertions(+), 107
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 47 +++---
target/arm/t16.decode | 8 +++
2 files changed, 16 insertions(+), 39 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 525276ed13..f551fde3db 100644
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 229 -
target/arm/a32.decode | 44
target/arm/t32.decode | 44
3 files changed, 200 insertions(+), 117 deletions(-)
diff --git a/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 216 ++---
target/arm/a32.decode | 20
target/arm/t32.decode | 29 ++
3 files changed, 167 insertions(+), 98 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 121 +++--
target/arm/a32.decode | 9 +++
target/arm/t32.decode | 7 +++
3 files changed, 72 insertions(+), 65 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 471 ++---
target/arm/a32.decode | 22 ++
target/arm/t32.decode | 18 ++
3 files changed, 248 insertions(+), 263 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 51 ++
target/arm/t16.decode | 15 +
2 files changed, 17 insertions(+), 49 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 17a0eea425..7b87621315
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 201 +
target/arm/a32.decode | 20
target/arm/t32.decode | 19
3 files changed, 144 insertions(+), 96 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 8
target/arm/a32-uncond.decode | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5366741d7b..87cbadc6cb 100644
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 37 +++-
target/arm/a32-uncond.decode | 10 ++
2 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1d07caa62a..5366741d7b
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 793 ++---
target/arm/a32.decode | 120 +++
target/arm/t32.decode | 141
3 files changed, 611 insertions(+), 443 deletions(-)
diff --git a/target/arm/translate.c
While unifying all of these paths, remove the constrained unpredictable
test for "wback && registers == 1" from the T2 encoding that isn't
constrained unpredictable for the A1 encoding. The A1 behaviour is
allowed for the T2 behaviour.
Signed-off-by: Richard Henderson
---
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 44 ++
target/arm/t16.decode | 11 +++
2 files changed, 13 insertions(+), 42 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 692891dbe0..9bdcb91537
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 89 --
target/arm/a32.decode | 6 +++
target/arm/t32.decode | 9 +
3 files changed, 48 insertions(+), 56 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 94 +++---
target/arm/t16.decode | 33 +++
2 files changed, 38 insertions(+), 89 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7b87621315..28f274ca7c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 554 +
target/arm/a32.decode | 32 +++
target/arm/t32.decode | 37 ++-
3 files changed, 302 insertions(+), 321 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 560 ++---
target/arm/a32.decode | 48
target/arm/t32.decode | 46
3 files changed, 396 insertions(+), 258 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 1 -
target/arm/op_helper.c | 15 -
target/arm/translate.c | 74 +++---
target/arm/a32.decode | 10 ++
target/arm/t32.decode | 9 +
5 files changed, 66 insertions(+), 43
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e316eeb312..53c46fcdc4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9161,11 +9161,7
Do these all in one lump because these are all logically intertwined.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 747 -
target/arm/a32.decode | 84 +
target/arm/t32.decode | 91 +
3 files changed, 536 insertions(+), 386
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 22 +-
target/arm/a32-uncond.decode | 4
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8dbe189df7..1d07caa62a 100644
---
This fixes an exiting bug with the T5 encoding of SUBS PC, LR, #IMM,
in that it may be executed from user mode as with any other encoding
of SUBS, not as ERET.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 273 +++--
target/arm/a32.decode |
We will shortly be calling this function much more often.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 28
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 53c46fcdc4..36419025db
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 226 ++---
target/arm/a32.decode | 14 +++
target/arm/t32.decode | 40 ++--
3 files changed, 142 insertions(+), 138 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 24 +---
target/arm/a32.decode | 1 +
target/arm/t32.decode | 19 +++
3 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
There is an extra always-true ARMv5 test, but this will
become more obvious once we start unifying the
implementation of A32+T32.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate.c
We currently have 3 different ways of computing the architectural
value of "PC" as seen in the ARM ARM.
The value of s->pc has been incremented past the current insn,
but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
for t16, PC = s->pc + 2. These differing computations make
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 61 +-
target/arm/a32.decode | 25 +
target/arm/t32.decode | 17
3 files changed, 84 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate.c
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 214 -
target/arm/a32.decode | 17
target/arm/t32.decode | 19
3 files changed, 163 insertions(+), 87 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
Used only on the thumb side so far, but will be more obvious
once we start unifying the implementation of A32+T32.
Signed-off-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 34 +--
target/arm/translate.c | 163 +++--
2 files changed, 76
Unify the code sequence for generating an illegal opcode exception.
Signed-off-by: Richard Henderson
---
target/arm/translate-vfp.inc.c | 3 +--
target/arm/translate.c | 21 +++--
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git
The actual argument is 0 for all callers.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 19b126d4f3..0848fb933a 100644
--- a/target/arm/translate.c
+++
The address of the current insn is still available in s->base.pc_next,
and need not be recomputed from s->pc - 4.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate.c
This unifies the implementation of the actual instructions
for a32, t32, and t16. In order to make this happen, we
need several preliminary cleanups. Most importantly to how
we handle the architectural representation of PC.
I attempt to convert single groups of instructions at once,
as they are
With this, we can have the function return a value from the DisasContext.
Signed-off-by: Richard Henderson
---
scripts/decodetree.py | 5 -
tests/decode/succ_function.decode | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
create mode 100644
The address of the current insn is still available in s->base.pc_next.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 33f78296eb..19b126d4f3 100644
---
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