[Qemu-devel] [PATCH qemu] spapr_iommu: Fix xlate trace to print translated address

[Alexey Kardashevskiy]

Currently we basically print IO address twice, fix this.

Fixes: 7e472264e9e2 ("PPC: spapr: iommu: rework traces")
Signed-off-by: Alexey Kardashevskiy 
---
 hw/ppc/spapr_iommu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index bd3d0256a65d..6fe57d799a10 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -137,7 +137,7 @@ static IOMMUTLBEntry 
spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
 ret.addr_mask = ~page_mask;
 ret.perm = spapr_tce_iommu_access_flags(tce);
 }
-trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
+trace_spapr_iommu_xlate(tcet->liobn, addr, ret.translated_addr, ret.perm,
 ret.addr_mask);
 
 return ret;
-- 
2.17.1

[Qemu-devel] [PATCH v4 29/29] sysemu: Split sysemu/runstate.h off sysemu/sysemu.h

[Markus Armbruster]

sysemu/sysemu.h is a rather unfocused dumping ground for stuff related
to the system-emulator.  Evidence:

* It's included widely: in my "build everything" tree, changing
  sysemu/sysemu.h still triggers a recompile of some 1100 out of 6600
  objects (not counting tests and objects that don't depend on
  qemu/osdep.h, down from 5400 due to the previous two commits).

* It pulls in more than a dozen additional headers.

Split stuff related to run state management into its own header
sysemu/runstate.h.

Touching sysemu/sysemu.h now recompiles some 850 objects.  qemu/uuid.h
also drops from 1100 to 850, and qapi/qapi-types-run-state.h from 4400
to 4200.  Touching new sysemu/runstate.h recompiles some 500 objects.

Since I'm touching MAINTAINERS to add sysemu/runstate.h anyway, also
add qemu/main-loop.h.

Suggested-by: Paolo Bonzini 
Signed-off-by: Markus Armbruster 
---
 include/hw/ppc/spapr_drc.h|  2 +-
 include/sysemu/runstate.h | 68 +++
 include/sysemu/sysemu.h   | 61 ---
 accel/kvm/kvm-all.c   |  1 +
 audio/audio.c |  2 +-
 block/block-backend.c |  2 +-
 blockdev.c|  1 +
 cpus.c|  2 +-
 dump/dump.c   |  2 +-
 gdbstub.c |  1 +
 hw/acpi/core.c|  2 +-
 hw/acpi/ich9.c|  2 +-
 hw/acpi/piix4.c   |  1 +
 hw/arm/highbank.c |  1 +
 hw/arm/integratorcp.c |  1 +
 hw/arm/msf2-soc.c |  1 +
 hw/arm/musicpal.c |  1 +
 hw/arm/nseries.c  |  1 +
 hw/arm/omap1.c|  1 +
 hw/arm/omap2.c|  1 +
 hw/arm/sbsa-ref.c |  1 +
 hw/arm/spitz.c|  1 +
 hw/arm/stellaris.c|  1 +
 hw/arm/tosa.c |  2 +-
 hw/arm/virt.c |  1 +
 hw/block/pflash_cfi01.c   |  2 +-
 hw/block/vhost-user-blk.c |  1 +
 hw/block/virtio-blk.c |  1 +
 hw/char/serial.c  |  2 +-
 hw/core/machine-qmp-cmds.c|  1 +
 hw/core/vm-change-state-handler.c |  2 +-
 hw/display/qxl-render.c   |  2 +-
 hw/display/qxl.c  |  2 +-
 hw/dma/etraxfs_dma.c  |  2 +-
 hw/i386/kvm/clock.c   |  2 +-
 hw/i386/kvm/i8254.c   |  2 +-
 hw/i386/kvmvapic.c|  1 +
 hw/i386/pc.c  |  1 +
 hw/i386/xen/xen-hvm.c |  1 +
 hw/i386/xen/xen-mapcache.c|  2 +-
 hw/ide/core.c |  2 +-
 hw/ide/qdev.c |  1 +
 hw/input/pckbd.c  |  2 +-
 hw/input/ps2.c|  2 +-
 hw/intc/arm_gicv3_its_kvm.c   |  2 +-
 hw/intc/arm_gicv3_kvm.c   |  2 +-
 hw/intc/spapr_xive_kvm.c  |  1 +
 hw/ipmi/ipmi.c|  2 +-
 hw/isa/lpc_ich9.c |  1 +
 hw/mips/boston.c  |  1 +
 hw/mips/mips_malta.c  |  1 +
 hw/mips/mips_r4k.c|  1 +
 hw/misc/arm_sysctl.c  |  2 +-
 hw/misc/cbus.c|  2 +-
 hw/misc/exynos4210_pmu.c  |  2 +-
 hw/misc/imx7_snvs.c   |  2 +-
 hw/misc/iotkit-sysctl.c   |  2 +-
 hw/misc/macio/cuda.c  |  2 +-
 hw/misc/macio/pmu.c   |  2 +-
 hw/misc/pvpanic.c |  2 +-
 hw/misc/slavio_misc.c |  2 +-
 hw/misc/zynq_slcr.c   |  2 +-
 hw/net/e1000e_core.c  |  2 +-
 hw/nvram/spapr_nvram.c|  2 +
 hw/pci-host/bonito.c  |  2 +-
 hw/pci-host/piix.c|  2 +-
 hw/pci-host/sabre.c   |  2 +-
 hw/ppc/e500.c |  1 +
 hw/ppc/mpc8544_guts.c |  2 +-
 hw/ppc/pnv.c  |  1 +
 hw/ppc/ppc.c  |  2 +-
 hw/ppc/ppc_booke.c|  2 +-
 hw/ppc/prep_systemio.c|  2 +-
 hw/ppc/spapr.c|  1 +
 hw/ppc/spapr_events.c |  2 +-
 hw/ppc/spapr_hcall.c  |  2 +-
 hw/ppc/spapr_rtas.c   |  2 +
 hw/rdma/vmw/pvrdma_main.c |  2 +-
 hw/s390x/ipl.c|  1 +
 hw/s390x/sclpquiesce.c|  2 +-
 hw/s390x/tod-kvm.c|  2 +-
 hw/scsi/scsi-bus.c|  1 +
 hw/sh4/r2d.c  |  1 +
 hw/sparc/sun4m.c  |  1 +
 hw/sparc64/sun4u.c|  1 +
 hw/timer/etraxfs_timer.c  |  2 +-
 hw/timer/m48t59.c |  1 +
 hw/timer/mc146818rtc.c|  1 +
 hw/timer/milkymist-sysctl.c   |  2 +-
 hw/timer/pxa2xx_timer.c   |  2 +-
 hw/usb/hcd-ehci.c |  2 +-
 hw/usb/host-libusb.c  |  1 +
 hw/usb/redirect.c |  1 +
 hw/vfio/pci.c |  1 +
 hw/virtio/virtio-rng.c|  3 +-
 hw/virtio/virtio.c

[Qemu-devel] [PATCH v4 00/29] Tame a few "touch this, recompile the world" headers

[Markus Armbruster]

We have quite a few "touch this, recompile the world" headers.  My
"build everything" tree has some 6600 objects (not counting tests and
objects that don't depend on qemu/osdep.h).  Touching any of 54
headers triggers a recompile of more than half of them.

This series reduces them to 46.

Six of the 54 are included always by design, via qemu/osdep.h.  These
are

bld/config-host.h
include/glib-compat.h
include/qemu/compiler.h
include/qemu/osdep.h
include/qemu/typedefs.h
include/sysemu/os-posix.h

Additionally, osdep.h includes either include/exec/poison.h or
bld/TARGET_DIR/config-target.h.

The seven headers this series improves to my satisfaction (for now)
are

bld/qapi/qapi-types-common.h
include/block/aio.h
include/hw/irq.h
include/qemu/event_notifier.h
include/qemu/main-loop.h
include/qemu/uuid.h
include/sysemu/sysemu.h

Of these, block/aio.h, qemu/main-loop.h and sysemu/sysemu.h are
particular significant, as they in turn include numerous other
headers.

The series makes real progress on a few more, but they're still bad:

bld/qapi/qapi-types-run-state.h
include/qemu/timer.h
include/qom/cpu.h
include/disas/dis-asm.h
include/qemu/notify.h
include/qemu/atomic.h

Minor improvements:

bld/qapi/qapi-builtin-types.h
bld/qapi/qapi-types-sockets.h
include/exec/cpu-common.h
include/exec/hwaddr.h
include/exec/memattrs.h
include/exec/memory.h
include/exec/memory_ldst.inc.h
include/exec/memory_ldst_cached.inc.h
include/exec/memory_ldst_phys.inc.h
include/exec/ramlist.h
include/fpu/softfloat-types.h
include/hw/hotplug.h
include/hw/qdev-core.h
include/qapi/util.h
include/qemu/bitmap.h
include/qemu/bitops.h
include/qemu/bswap.h
include/qemu/coroutine.h
include/qemu/host-utils.h
include/qemu/int128.h
include/qemu/lockable.h
include/qemu/module.h
include/qemu/processor.h
include/qemu/qsp.h
include/qemu/queue.h
include/qemu/rcu.h
include/qemu/rcu_queue.h
include/qemu/sys_membarrier.h
include/qemu/thread-posix.h
include/qemu/thread.h
include/qom/object.h

Untouched:

include/exec/cpu-all.h
include/exec/cpu-defs.h
tcg/i386/tcg-target.h
tcg/tcg-mo.h

Further improvement is certainly possible.  exec/cpu-all.h,
exec/cpu-defs.h, exec/memory.h, hw/qdev-core.h, qemu/coroutine.h,
qemu/lockable.h, and qom/cpu.h each pull in more than ten other
headers, which makes them particularly wortwhile targets.

Observed patterns of #include misuse:

* Copy pasta

  I found and deleted quite a few #include that were almost certainly
  never needed.  The most likely explanation is lazy copying from a
  "similar" file.  My deletions produced only minor improvements,
  though.

* "Convenience" headers

  We sometimes have a header include a bunch of other headers the
  header itself doesn't need, so the header's users don't have to.  An
  extreme case is hw/hw.h: it pulls in more than 40 other headers,
  then declares just hw_error().  Most of its users need only a
  fraction of it.  PATCH 08-09,12-18 fix that, trading the very
  occasional convenience of not having to type a few #include
  directives for build speed.

* "Fat" headers

  Some headers provide many things to many customers.  Bad when the
  customers generally need only parts.  Worse when such a "fat" header
  pulls in loads more.  This series grapples with three instances:
  qapi/qapi-types-common.h (PATCH 03), hw/boards.h, which pulls in
  almost 70 headers (PATCH 19-23), and sysemu/sysemu.h, which pulls in
  more than 20 (PATCH 23-28).

* Design erosion

  Off-the-cuff additions to headers can erode design.  For instance,
  the generated trace.h were carefully designed for minimal
  dependencies.  We let them balloon when we added the per-vCPU
  tracing feature a few years later.  PATCH 07 grapples with that.

PATCH 01 was previously posted separately.  Since it needs a rebase
now, I include it.

Related prior discussion:
Subject: Re: Our use of #include is undisciplined, and what to do about it
Date: Mon, 27 May 2019 15:12:34 +0200
Message-ID: <877eac82il@dusky.pond.sub.org>
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg06291.html

Detailed measurements, improvements under 10% omitted:

 before   after  improvement
   5557 5265031  91% include/hw/irq.h
   5585 8474738  85% include/sysemu/sysemu.h
   5591 8584733  85% include/qemu/uuid.h
   569416814013  70% include/qemu/main-loop.h
   571327552958  52% include/block/aio.h
   571527772938  51% include/qemu/event_notifier.h
   2814 2682546  90% bld/qapi/qapi-types-block.h
   2473 old2473 100% include/hw/qdev.h
   2596 1792417  93% include/hw/hw.h
   2600 1842416  93% include/sysemu/reset.h
   2598 1942404  93% include/migration/qemu-file-types.h
   3033 8702163  71% bld/qapi/qapi-types-misc.h
   5713

[Qemu-devel] [PATCH v4 01/29] include: Make headers more self-contained

[Markus Armbruster]

Back in 2016, we discussed[1] rules for headers, and these were
generally liked:

1. Have a carefully curated header that's included everywhere first.  We
   got that already thanks to Peter: osdep.h.

2. Headers should normally include everything they need beyond osdep.h.
   If exceptions are needed for some reason, they must be documented in
   the header.  If all that's needed from a header is typedefs, put
   those into qemu/typedefs.h instead of including the header.

3. Cyclic inclusion is forbidden.

This patch gets include/ closer to obeying 2.

It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically.  It passes the RFC test there.

[1] Message-ID: <87h9g8j57d@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-arm...@redhat.com>
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html

Signed-off-by: Markus Armbruster 
Reviewed-by: Alistair Francis 
---
 include/block/raw-aio.h   | 2 ++
 include/block/write-threshold.h   | 2 ++
 include/disas/disas.h | 1 +
 include/exec/cputlb.h | 3 +++
 include/exec/exec-all.h   | 1 +
 include/exec/ioport.h | 2 ++
 include/exec/memory-internal.h| 2 ++
 include/exec/ram_addr.h   | 1 +
 include/exec/softmmu-semi.h   | 2 ++
 include/exec/tb-hash.h| 2 ++
 include/exec/user/thunk.h | 2 ++
 include/fpu/softfloat-macros.h| 2 ++
 include/hw/acpi/pci.h | 3 +++
 include/hw/acpi/tco.h | 3 +++
 include/hw/adc/stm32f2xx_adc.h| 2 ++
 include/hw/arm/allwinner-a10.h| 1 +
 include/hw/arm/aspeed_soc.h   | 1 +
 include/hw/arm/bcm2836.h  | 1 +
 include/hw/arm/exynos4210.h   | 3 +--
 include/hw/arm/fsl-imx25.h| 1 +
 include/hw/arm/fsl-imx31.h| 1 +
 include/hw/arm/sharpsl.h  | 3 +++
 include/hw/arm/xlnx-zynqmp.h  | 1 +
 include/hw/block/fdc.h| 2 ++
 include/hw/block/flash.h  | 1 +
 include/hw/char/escc.h| 1 +
 include/hw/char/xilinx_uartlite.h | 2 ++
 include/hw/core/generic-loader.h  | 1 +
 include/hw/cris/etraxfs.h | 1 +
 include/hw/cris/etraxfs_dma.h | 3 +++
 include/hw/display/i2c-ddc.h  | 1 +
 include/hw/empty_slot.h   | 2 ++
 include/hw/gpio/bcm2835_gpio.h| 1 +
 include/hw/i2c/aspeed_i2c.h   | 2 ++
 include/hw/i386/apic_internal.h   | 1 +
 include/hw/i386/ioapic_internal.h | 1 +
 include/hw/intc/allwinner-a10-pic.h   | 2 ++
 include/hw/intc/heathrow_pic.h| 2 ++
 include/hw/intc/mips_gic.h| 1 +
 include/hw/isa/vt82c686.h | 2 ++
 include/hw/mips/cps.h | 1 +
 include/hw/misc/macio/cuda.h  | 2 ++
 include/hw/misc/macio/gpio.h  | 3 +++
 include/hw/misc/macio/macio.h | 2 ++
 include/hw/misc/macio/pmu.h   | 3 +++
 include/hw/misc/mips_cmgcr.h  | 2 ++
 include/hw/misc/mips_cpc.h| 2 ++
 include/hw/misc/pvpanic.h | 3 +++
 include/hw/net/allwinner_emac.h   | 1 +
 include/hw/net/lance.h| 1 +
 include/hw/nvram/chrp_nvram.h | 2 ++
 include/hw/pci-host/sabre.h   | 2 ++
 include/hw/pci-host/uninorth.h| 2 +-
 include/hw/pci/pcie_aer.h | 1 +
 include/hw/ppc/pnv_core.h | 1 +
 include/hw/ppc/ppc4xx.h   | 4 
 include/hw/ppc/spapr_irq.h| 3 +++
 include/hw/ppc/spapr_vio.h| 1 +
 include/hw/ppc/spapr_xive.h   | 2 ++
 include/hw/ppc/xive_regs.h| 3 +++
 include/hw/riscv/boot.h   | 2 ++
 include/hw/riscv/riscv_hart.h | 3 +++
 include/hw/riscv/sifive_clint.h   | 2 ++
 include/hw/riscv/sifive_e.h   | 1 +
 include/hw/riscv/sifive_plic.h| 2 +-
 include/hw/riscv/sifive_prci.h| 2 ++
 include/hw/riscv/sifive_test.h| 2 ++
 include/hw/riscv/sifive_u.h   | 1 +
 include/hw/riscv/sifive_uart.h| 3 +++
 include/hw/riscv/spike.h  | 3 +++
 include/hw/riscv/virt.h   | 3 +++
 include/hw/s390x/ap-device.h  | 3 +++
 include/hw/s390x/css-bridge.h | 3 ++-
 include/hw/s390x/css.h| 1 +
 include/hw/s390x/tod.h| 2 +-
 include/hw/semihosting/console.h  | 2 ++
 include/hw/sh4/sh_intc.h  | 1 +
 include/hw/sparc/sparc64.h| 2 ++
 include/hw/ssi/aspeed_smc.h   | 1 +
 include/hw/ssi/xilinx_spips.h | 1 +
 include/hw/timer/allwinner-a10-pit.h  | 1 +
 include/hw/timer/i8254_internal.h | 1 +
 include/hw/timer/m48t59.h | 2 ++
 include/hw/timer/mc146818rtc_regs.h   | 2 ++
 include/hw/timer/xlnx-zynqmp-rtc.h| 1 +
 

[Qemu-devel] [PATCH v4 07/29] trace: Do not include qom/cpu.h into generated trace.h

[Markus Armbruster]

docs/devel/tracing.txt explains "since many source files include
trace.h, [the generated trace.h use] a minimum of types and other
header files included to keep the namespace clean and compile times
and dependencies down."

Commit 4815185902 "trace: Add per-vCPU tracing states for events with
the 'vcpu' property" made them all include qom/cpu.h via
control-internal.h.  qom/cpu.h in turn includes about thirty headers.
Ouch.

Per-vCPU tracing is currently not supported in sub-directories'
trace-events.  In other words, qom/cpu.h can only be used in
trace-root.h, not in any trace.h.

Split trace/control-vcpu.h off trace/control.h and
trace/control-internal.h.  Have the generated trace.h include
trace/control.h (which no longer includes qom/cpu.h), and trace-root.h
include trace/control-vcpu.h (which includes it).

The resulting improvement is a bit disappointing: in my "build
everything" tree, some 1100 out of 6600 objects (not counting tests
and objects that don't depend on qemu/osdep.h) depend on a trace.h,
and about 600 of them no longer depend on qom/cpu.h.  But more than
1300 others depend on trace-root.h.  More work is clearly needed.
Left for another day.

Cc: Stefan Hajnoczi 
Signed-off-by: Markus Armbruster 
Reviewed-by: Stefan Hajnoczi 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 trace/control-internal.h  | 25 --
 trace/control-vcpu.h  | 63 +++
 trace/control.h   | 24 -
 block/block-backend.c |  1 +
 qom/object.c  |  1 +
 trace/qmp.c   |  2 +-
 ui/vnc.c  |  1 +
 scripts/tracetool/format/c.py |  1 +
 scripts/tracetool/format/h.py |  7 +++-
 9 files changed, 74 insertions(+), 51 deletions(-)
 create mode 100644 trace/control-vcpu.h

diff --git a/trace/control-internal.h b/trace/control-internal.h
index c7fbe2d3bf..8b2b50a7cf 100644
--- a/trace/control-internal.h
+++ b/trace/control-internal.h
@@ -10,9 +10,6 @@
 #ifndef TRACE__CONTROL_INTERNAL_H
 #define TRACE__CONTROL_INTERNAL_H
 
-#include "qom/cpu.h"
-
-
 extern int trace_events_enabled_count;
 
 
@@ -59,28 +56,6 @@ static inline bool trace_event_get_state_dynamic(TraceEvent 
*ev)
 return unlikely(trace_events_enabled_count) && *ev->dstate;
 }
 
-static inline bool
-trace_event_get_vcpu_state_dynamic_by_vcpu_id(CPUState *vcpu,
-  uint32_t vcpu_id)
-{
-/* it's on fast path, avoid consistency checks (asserts) */
-if (unlikely(trace_events_enabled_count)) {
-return test_bit(vcpu_id, vcpu->trace_dstate);
-} else {
-return false;
-}
-}
-
-static inline bool trace_event_get_vcpu_state_dynamic(CPUState *vcpu,
-  TraceEvent *ev)
-{
-uint32_t vcpu_id;
-assert(trace_event_is_vcpu(ev));
-vcpu_id = trace_event_get_vcpu_id(ev);
-return trace_event_get_vcpu_state_dynamic_by_vcpu_id(vcpu, vcpu_id);
-}
-
-
 void trace_event_register_group(TraceEvent **events);
 
 #endif /* TRACE__CONTROL_INTERNAL_H */
diff --git a/trace/control-vcpu.h b/trace/control-vcpu.h
new file mode 100644
index 00..a8f1035c2e
--- /dev/null
+++ b/trace/control-vcpu.h
@@ -0,0 +1,63 @@
+/*
+ * Interface for configuring and controlling the state of tracing events.
+ *
+ * Copyright (C) 2011-2016 Lluís Vilanova 
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TRACE__CONTROL_VCPU_H
+#define TRACE__CONTROL_VCPU_H
+
+#include "control.h"
+#include "event-internal.h"
+#include "qom/cpu.h"
+
+/**
+ * trace_event_get_vcpu_state:
+ * @vcpu: Target vCPU.
+ * @id: Event identifier name.
+ *
+ * Get the tracing state of an event (both static and dynamic) for the given
+ * vCPU.
+ *
+ * If the event has the disabled property, the check will have no performance
+ * impact.
+ */
+#define trace_event_get_vcpu_state(vcpu, id)\
+((id ##_ENABLED) && \
+ trace_event_get_vcpu_state_dynamic_by_vcpu_id( \
+ vcpu, _ ## id ## _EVENT.vcpu_id))
+
+/**
+ * trace_event_get_vcpu_state_dynamic:
+ *
+ * Get the dynamic tracing state of an event for the given vCPU.
+ */
+static bool trace_event_get_vcpu_state_dynamic(CPUState *vcpu, TraceEvent *ev);
+
+#include "control-internal.h"
+
+static inline bool
+trace_event_get_vcpu_state_dynamic_by_vcpu_id(CPUState *vcpu,
+  uint32_t vcpu_id)
+{
+/* it's on fast path, avoid consistency checks (asserts) */
+if (unlikely(trace_events_enabled_count)) {
+return test_bit(vcpu_id, vcpu->trace_dstate);
+} else {
+return false;
+}
+}
+
+static inline bool trace_event_get_vcpu_state_dynamic(CPUState *vcpu,
+  TraceEvent *ev)
+{
+

[Qemu-devel] [PATCH v4 12/29] Include hw/irq.h a lot less

[Markus Armbruster]

In my "build everything" tree, changing hw/irq.h triggers a recompile
of some 5400 out of 6600 objects (not counting tests and objects that
don't depend on qemu/osdep.h).

hw/hw.h supposedly includes it for convenience.  Several other headers
include it just to get qemu_irq and.or qemu_irq_handler.

Move the qemu_irq and qemu_irq_handler typedefs from hw/irq.h to
qemu/typedefs.h, and then include hw/irq.h only where it's still
needed.  Touching it now recompiles only some 500 objects.

Signed-off-by: Markus Armbruster 
Reviewed-by: Alistair Francis 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 hw/alpha/alpha_sys.h | 1 -
 hw/hppa/hppa_sys.h   | 1 -
 include/hw/acpi/acpi.h   | 1 -
 include/hw/arm/boot.h| 1 -
 include/hw/arm/omap.h| 1 -
 include/hw/arm/soc_dma.h | 1 -
 include/hw/block/fdc.h   | 1 -
 include/hw/bt.h  | 1 -
 include/hw/core/split-irq.h  | 1 -
 include/hw/cris/etraxfs_dma.h| 1 -
 include/hw/display/blizzard.h| 1 -
 include/hw/display/tc6393xb.h| 1 -
 include/hw/hw.h  | 1 -
 include/hw/ide/internal.h| 1 +
 include/hw/input/gamepad.h   | 1 -
 include/hw/input/tsc2xxx.h   | 1 -
 include/hw/irq.h | 4 
 include/hw/isa/vt82c686.h| 1 -
 include/hw/mips/mips.h   | 1 -
 include/hw/misc/cbus.h   | 1 -
 include/hw/net/lan9118.h | 1 -
 include/hw/net/smc91c111.h   | 1 -
 include/hw/or-irq.h  | 1 -
 include/hw/ppc/spapr_irq.h   | 1 -
 include/hw/qdev-core.h   | 1 -
 include/hw/sh4/sh_intc.h | 1 -
 include/hw/timer/m48t59.h| 1 -
 include/hw/tricore/tricore.h | 1 -
 include/hw/vfio/vfio-platform.h  | 1 -
 include/hw/xen/xen.h | 1 -
 include/hw/xtensa/mx_pic.h   | 1 -
 include/qemu/typedefs.h  | 9 +
 include/sysemu/kvm.h | 1 -
 hw/acpi/core.c   | 1 +
 hw/acpi/piix4.c  | 1 +
 hw/alpha/typhoon.c   | 1 +
 hw/arm/armsse.c  | 1 +
 hw/arm/exynos4210.c  | 1 +
 hw/arm/exynos4_boards.c  | 1 +
 hw/arm/integratorcp.c| 1 +
 hw/arm/msf2-soc.c| 1 +
 hw/arm/musicpal.c| 1 +
 hw/arm/omap1.c   | 1 +
 hw/arm/omap2.c   | 1 +
 hw/arm/palm.c| 2 ++
 hw/arm/pxa2xx.c  | 1 +
 hw/arm/pxa2xx_gpio.c | 1 +
 hw/arm/realview.c| 1 +
 hw/arm/smmuv3.c  | 1 +
 hw/arm/spitz.c   | 1 +
 hw/arm/stellaris.c   | 1 +
 hw/arm/strongarm.c   | 1 +
 hw/arm/tosa.c| 1 +
 hw/arm/versatilepb.c | 1 +
 hw/arm/virt.c| 1 +
 hw/arm/z2.c  | 1 +
 hw/audio/cs4231a.c   | 1 +
 hw/audio/gus.c   | 1 +
 hw/audio/marvell_88w8618.c   | 1 +
 hw/audio/milkymist-ac97.c| 1 +
 hw/audio/pl041.c | 1 +
 hw/audio/sb16.c  | 1 +
 hw/block/fdc.c   | 1 +
 hw/char/bcm2835_aux.c| 1 +
 hw/char/cadence_uart.c   | 1 +
 hw/char/cmsdk-apb-uart.c | 1 +
 hw/char/escc.c   | 1 +
 hw/char/etraxfs_ser.c| 1 +
 hw/char/exynos4210_uart.c| 1 +
 hw/char/grlib_apbuart.c  | 1 +
 hw/char/imx_serial.c | 1 +
 hw/char/ipoctal232.c | 1 +
 hw/char/lm32_uart.c  | 1 +
 hw/char/mcf_uart.c   | 1 +
 hw/char/milkymist-uart.c | 1 +
 hw/char/nrf51_uart.c | 1 +
 hw/char/parallel.c   | 1 +
 hw/char/pl011.c  | 1 +
 hw/char/serial-pci-multi.c   | 1 +
 hw/char/serial-pci.c | 1 +
 hw/char/serial.c | 1 +
 hw/char/sh_serial.c  | 2 ++
 hw/char/spapr_vty.c  | 1 +
 hw/char/stm32f2xx_usart.c| 1 +
 hw/char/xilinx_uartlite.c| 1 +
 hw/core/or-irq.c | 1 +
 hw/core/qdev.c   | 1 +
 hw/core/split-irq.c  | 1 +
 hw/cpu/a15mpcore.c   | 1 +
 hw/cpu/a9mpcore.c| 1 +
 hw/cpu/arm11mpcore.c | 1 +
 hw/cpu/realview_mpcore.c | 1 +
 hw/display/ads7846.c | 1 +
 hw/display/bcm2835_fb.c  | 1 +
 hw/display/cg3.c | 1 +
 hw/display/exynos4210_fimd.c | 1 +
 hw/display/g364fb.c  | 1 +
 hw/display/milkymist-tmu2.c  | 1 +
 hw/display/omap_dss.c| 2 ++
 hw/display/omap_lcdc.c   | 2 ++
 hw/display/pl110.c   | 1 +
 hw/display/pxa2xx_lcd.c  | 1 +
 hw/display/tc6393xb.c| 2 ++
 hw/display/xlnx_dp.c | 1 +
 hw/dma/bcm2835_dma.c | 1 +
 hw/dma/etraxfs_dma.c | 2 ++
 hw/dma/pl080.c   | 1 +
 hw/dma/pl330.c   | 1 +
 hw/dma/pxa2xx_dma.c  

[Qemu-devel] [PATCH v4 08/29] Include sysemu/reset.h a lot less

[Markus Armbruster]

In my "build everything" tree, changing sysemu/reset.h triggers a
recompile of some 2600 out of 6600 objects (not counting tests and
objects that don't depend on qemu/osdep.h).

The main culprit is hw/hw.h, which supposedly includes it for
convenience.

Include sysemu/reset.h only where it's needed.  Touching it now
recompiles less than 200 objects.

Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Alistair Francis 
Tested-by: Philippe Mathieu-Daudé 
---
 include/hw/hw.h| 1 -
 hw/acpi/ich9.c | 2 ++
 hw/acpi/piix4.c| 2 ++
 hw/acpi/vmgenid.c  | 1 +
 hw/arm/armv7m.c| 1 +
 hw/arm/boot.c  | 1 +
 hw/arm/nseries.c   | 1 +
 hw/arm/omap1.c | 1 +
 hw/arm/omap2.c | 1 +
 hw/arm/virt-acpi-build.c   | 1 +
 hw/char/parallel.c | 1 +
 hw/char/serial.c   | 1 +
 hw/core/generic-loader.c   | 1 +
 hw/core/loader.c   | 1 +
 hw/cris/boot.c | 1 +
 hw/display/cirrus_vga.c| 1 +
 hw/display/ramfb.c | 2 ++
 hw/display/vga.c   | 2 ++
 hw/hppa/machine.c  | 1 +
 hw/i386/acpi-build.c   | 1 +
 hw/i386/pc.c   | 1 +
 hw/ide/cmd646.c| 1 +
 hw/ide/piix.c  | 1 +
 hw/ide/sii3112.c   | 1 +
 hw/ide/via.c   | 1 +
 hw/input/lm832x.c  | 1 +
 hw/input/pckbd.c   | 2 ++
 hw/input/ps2.c | 2 ++
 hw/input/tsc2005.c | 1 +
 hw/input/tsc210x.c | 1 +
 hw/intc/mips_gic.c | 1 +
 hw/intc/pnv_xive.c | 1 +
 hw/intc/spapr_xive.c   | 1 +
 hw/intc/xics.c | 1 +
 hw/intc/xive.c | 1 +
 hw/isa/piix4.c | 1 +
 hw/isa/vt82c686.c  | 1 +
 hw/lm32/lm32_boards.c  | 1 +
 hw/lm32/milkymist.c| 1 +
 hw/microblaze/boot.c   | 1 +
 hw/mips/cps.c  | 1 +
 hw/mips/mips_fulong2e.c| 1 +
 hw/mips/mips_jazz.c| 1 +
 hw/mips/mips_malta.c   | 1 +
 hw/mips/mips_mipssim.c | 2 ++
 hw/mips/mips_r4k.c | 2 ++
 hw/misc/vmcoreinfo.c   | 1 +
 hw/moxie/moxiesim.c| 2 ++
 hw/net/eepro100.c  | 1 +
 hw/nios2/boot.c| 1 +
 hw/nvram/fw_cfg.c  | 1 +
 hw/openrisc/openrisc_sim.c | 1 +
 hw/pci-host/bonito.c   | 1 +
 hw/pci-host/piix.c | 1 +
 hw/ppc/e500.c  | 1 +
 hw/ppc/mac_newworld.c  | 1 +
 hw/ppc/mac_oldworld.c  | 1 +
 hw/ppc/pnv.c   | 1 +
 hw/ppc/pnv_core.c  | 1 +
 hw/ppc/pnv_psi.c   | 1 +
 hw/ppc/ppc405_boards.c | 2 ++
 hw/ppc/ppc405_uc.c | 2 ++
 hw/ppc/ppc440_bamboo.c | 1 +
 hw/ppc/ppc440_uc.c | 1 +
 hw/ppc/ppc4xx_devs.c   | 2 ++
 hw/ppc/ppc4xx_pci.c| 1 +
 hw/ppc/ppc_booke.c | 2 ++
 hw/ppc/prep.c  | 2 ++
 hw/ppc/sam460ex.c  | 1 +
 hw/ppc/spapr.c | 1 +
 hw/ppc/spapr_cpu_core.c| 2 ++
 hw/ppc/spapr_drc.c | 1 +
 hw/ppc/virtex_ml507.c  | 1 +
 hw/riscv/riscv_hart.c  | 1 +
 hw/s390x/ipl.c | 1 +
 hw/s390x/s390-virtio-ccw.c | 1 +
 hw/sh4/r2d.c   | 1 +
 hw/sparc/leon3.c   | 2 ++
 hw/sparc/sun4m.c   | 2 ++
 hw/sparc64/sparc64.c   | 1 +
 hw/timer/etraxfs_timer.c   | 1 +
 hw/timer/mc146818rtc.c | 1 +
 hw/tpm/tpm_ppi.c   | 1 -
 hw/vfio/common.c   | 1 +
 hw/watchdog/wdt_diag288.c  | 1 +
 hw/xtensa/sim.c| 1 +
 hw/xtensa/xtfpga.c | 1 +
 target/i386/cpu.c  | 1 +
 target/i386/hax-all.c  | 1 +
 target/i386/kvm.c  | 1 +
 target/s390x/cpu.c | 1 +
 vl.c   | 1 +
 92 files changed, 107 insertions(+), 2 deletions(-)

diff --git a/include/hw/hw.h b/include/hw/hw.h
index b1b79964b5..a4fb2390e8 100644
--- a/include/hw/hw.h
+++ b/include/hw/hw.h
@@ -12,7 +12,6 @@
 #include "hw/irq.h"
 #include "migration/vmstate.h"
 #include "migration/qemu-file-types.h"
-#include "sysemu/reset.h"
 
 void QEMU_NORETURN hw_error(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
 
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index e53dfe1ee3..b4d987c811 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -23,6 +23,7 @@
  * Contributions after 2012-01-13 are licensed under the terms of the
  * GNU GPL, version 2 or (at your option) any later version.
  */
+
 #include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "qapi/error.h"
@@ -30,6 +31,7 @@
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"
 #include "qemu/timer.h"
+#include "sysemu/reset.h"
 #include "sysemu/sysemu.h"
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/tco.h"
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index ec4e186cec..a59e58d937 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -18,6 +18,7 @@
  * Contributions after 2012-01-13 are licensed under the terms of the
  * GNU GPL, version 2 or (at your option) any later version.
  */
+
 #include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/i386/pc.h"
@@ -25,6 +26,7 @@
 #include "hw/i2c/pm_smbus.h"
 #include 

[Qemu-devel] [PATCH v4 18/29] Include hw/hw.h exactly where needed

[Markus Armbruster]

In my "build everything" tree, changing hw/hw.h triggers a recompile
of some 2600 out of 6600 objects (not counting tests and objects that
don't depend on qemu/osdep.h).

The previous commits have left only the declaration of hw_error() in
hw/hw.h.  This permits dropping most of its inclusions.  Touching it
now recompiles less than 200 objects.

Signed-off-by: Markus Armbruster 
Reviewed-by: Alistair Francis 
---
 hw/display/qxl.h | 1 -
 hw/i386/amd_iommu.h  | 1 -
 hw/microblaze/boot.h | 1 -
 hw/net/ne2000.h  | 1 -
 hw/nios2/boot.h  | 1 -
 hw/usb/hcd-ehci.h| 1 -
 include/hw/audio/pcspk.h | 1 -
 include/hw/audio/wm8750.h| 1 -
 include/hw/char/serial.h | 1 -
 include/hw/char/stm32f2xx_usart.h| 1 -
 include/hw/dma/i8257.h   | 1 -
 include/hw/hw.h  | 1 -
 include/hw/i386/ich9.h   | 1 -
 include/hw/i386/ioapic_internal.h| 1 -
 include/hw/input/i8042.h | 1 -
 include/hw/isa/apm.h | 1 -
 include/hw/isa/i8259_internal.h  | 1 -
 include/hw/misc/stm32f2xx_syscfg.h   | 1 -
 include/hw/net/ne2000-isa.h  | 1 -
 include/hw/pci-host/designware.h | 1 -
 include/hw/pci-host/gpex.h   | 1 -
 include/hw/pci-host/q35.h| 1 -
 include/hw/pci-host/uninorth.h   | 1 -
 include/hw/pci-host/xilinx-pcie.h| 1 -
 include/hw/pci/pcie.h| 1 -
 include/hw/pci/pcie_aer.h| 1 -
 include/hw/qdev.h| 1 -
 include/hw/riscv/riscv_htif.h| 1 -
 include/hw/ssi/stm32f2xx_spi.h   | 1 -
 include/hw/timer/aspeed_rtc.h| 1 -
 include/hw/timer/i8254.h | 1 -
 include/hw/timer/i8254_internal.h| 1 -
 include/hw/virtio/vhost.h| 1 -
 include/hw/virtio/virtio.h   | 1 -
 include/hw/xen/xen_common.h  | 1 -
 include/sysemu/dma.h | 1 -
 include/sysemu/hax.h | 1 -
 include/sysemu/hvf.h | 1 -
 accel/kvm/kvm-all.c  | 1 -
 audio/audio.c| 1 -
 audio/spiceaudio.c   | 1 -
 audio/wavcapture.c   | 1 -
 cpus.c   | 1 +
 device-hotplug.c | 1 -
 exec.c   | 1 -
 hw/9pfs/xen-9p-backend.c | 1 -
 hw/acpi/core.c   | 1 -
 hw/acpi/cpu_hotplug.c| 1 -
 hw/acpi/ich9.c   | 1 -
 hw/acpi/pcihp.c  | 1 -
 hw/acpi/piix4.c  | 1 -
 hw/adc/stm32f2xx_adc.c   | 1 -
 hw/alpha/dp264.c | 1 -
 hw/alpha/typhoon.c   | 1 -
 hw/arm/boot.c| 1 -
 hw/arm/collie.c  | 1 -
 hw/arm/gumstix.c | 1 -
 hw/arm/integratorcp.c| 1 +
 hw/arm/mainstone.c   | 1 -
 hw/arm/musicpal.c| 1 +
 hw/arm/omap2.c   | 1 -
 hw/arm/omap_sx1.c| 1 -
 hw/arm/palm.c| 1 -
 hw/arm/pxa2xx_pic.c  | 1 -
 hw/arm/spitz.c   | 1 -
 hw/arm/tosa.c| 1 -
 hw/arm/virt-acpi-build.c | 1 -
 hw/arm/z2.c  | 1 -
 hw/audio/ac97.c  | 1 -
 hw/audio/adlib.c | 1 -
 hw/audio/cs4231a.c   | 1 -
 hw/audio/es1370.c| 1 -
 hw/audio/gus.c   | 1 -
 hw/audio/hda-codec.c | 1 -
 hw/audio/intel-hda.c | 1 -
 hw/audio/marvell_88w8618.c   | 1 -
 hw/audio/milkymist-ac97.c| 1 -
 hw/audio/pcspk.c | 1 -
 hw/audio/sb16.c  | 1 -
 hw/block/dataplane/xen-block.c   | 1 -
 hw/block/ecc.c   | 1 -
 hw/block/fdc.c   | 1 -
 hw/block/m25p80.c| 1 -
 hw/block/nvme.c  | 1 -
 hw/block/pflash_cfi01.c  | 1 -
 hw/block/pflash_cfi02.c  | 1 -
 hw/block/tc58128.c   | 1 -
 hw/block/xen-block.c | 1 -
 hw/char/debugcon.c   | 1 -
 hw/char/digic-uart.c | 1 -
 hw/char/escc.c   | 1 -
 hw/char/lm32_juart.c | 1 -
 hw/char/lm32_uart.c  | 1 -
 hw/char/mcf_uart.c   | 1 -
 hw/char/milkymist-uart.c | 1 -
 hw/char/omap_uart.c  

[Qemu-devel] [PATCH v4 20/29] Include qemu/main-loop.h less

[Markus Armbruster]

In my "build everything" tree, changing qemu/main-loop.h triggers a
recompile of some 5600 out of 6600 objects (not counting tests and
objects that don't depend on qemu/osdep.h).  It includes block/aio.h,
which in turn includes qemu/event_notifier.h, qemu/notify.h,
qemu/processor.h, qemu/qsp.h, qemu/queue.h, qemu/thread-posix.h,
qemu/thread.h, qemu/timer.h, and a few more.

Include qemu/main-loop.h only where it's needed.  Touching it now
recompiles only some 1700 objects.  For block/aio.h and
qemu/event_notifier.h, these numbers drop from 5600 to 2800.  For the
others, they shrink only slightly.

Signed-off-by: Markus Armbruster 
---
 fsdev/qemu-fsdev-throttle.h | 1 -
 hw/9pfs/coth.h  | 1 -
 include/block/block_int.h   | 1 -
 include/chardev/char-fe.h   | 1 +
 include/chardev/char-io.h   | 1 +
 include/chardev/char.h  | 2 +-
 include/hw/scsi/scsi.h  | 1 +
 include/sysemu/sysemu.h | 1 -
 nbd/nbd-internal.h  | 1 -
 ui/vnc-auth-sasl.h  | 1 -
 accel/kvm/kvm-all.c | 1 +
 block.c | 1 +
 block/block-backend.c   | 1 +
 block/create.c  | 1 +
 block/io.c  | 1 +
 block/nbd.c | 1 +
 block/nfs.c | 1 +
 block/nvme.c| 1 +
 block/qcow2.c   | 1 +
 block/qed.c | 1 +
 block/sheepdog.c| 1 +
 block/throttle-groups.c | 1 +
 blockdev.c  | 1 +
 blockjob.c  | 1 +
 chardev/baum.c  | 1 +
 chardev/char-pipe.c | 1 +
 chardev/char-win-stdio.c| 1 +
 chardev/char-win.c  | 1 +
 dump/dump.c | 1 +
 fsdev/qemu-fsdev-throttle.c | 1 +
 hw/9pfs/9p.c| 1 +
 hw/9pfs/codir.c | 1 +
 hw/9pfs/cofile.c| 1 +
 hw/9pfs/cofs.c  | 1 +
 hw/9pfs/coth.c  | 1 +
 hw/9pfs/coxattr.c   | 1 +
 hw/9pfs/xen-9p-backend.c| 1 +
 hw/arm/omap1.c  | 1 +
 hw/block/dataplane/virtio-blk.c | 1 +
 hw/block/dataplane/xen-block.c  | 1 +
 hw/block/fdc.c  | 1 +
 hw/block/xen-block.c| 1 +
 hw/char/virtio-serial-bus.c | 1 +
 hw/core/machine-qmp-cmds.c  | 1 +
 hw/display/qxl.c| 1 +
 hw/dma/etraxfs_dma.c| 1 +
 hw/i386/intel_iommu.c   | 1 +
 hw/i386/xen/xen-hvm.c   | 1 +
 hw/ide/ahci.c   | 1 +
 hw/ide/core.c   | 1 +
 hw/ide/qdev.c   | 1 +
 hw/intc/s390_flic.c | 1 +
 hw/m68k/mcf5206.c   | 1 +
 hw/m68k/mcf5208.c   | 1 +
 hw/misc/imx6_src.c  | 1 +
 hw/net/fsl_etsec/etsec.c| 1 +
 hw/net/lan9118.c| 1 +
 hw/net/vhost_net.c  | 2 +-
 hw/net/virtio-net.c | 1 +
 hw/ppc/ppc.c| 1 +
 hw/ppc/ppc440_uc.c  | 1 +
 hw/ppc/spapr_hcall.c| 1 +
 hw/ppc/spapr_rng.c  | 1 +
 hw/scsi/mptsas.c| 1 +
 hw/scsi/scsi-disk.c | 1 +
 hw/scsi/vmw_pvscsi.c| 1 +
 hw/timer/allwinner-a10-pit.c| 1 +
 hw/timer/altera_timer.c | 1 +
 hw/timer/etraxfs_timer.c| 1 +
 hw/timer/exynos4210_rtc.c   | 1 +
 hw/timer/milkymist-sysctl.c | 1 +
 hw/usb/dev-uas.c| 1 +
 hw/usb/hcd-ehci.c   | 1 +
 hw/usb/host-libusb.c| 1 +
 hw/usb/xen-usb.c| 1 +
 hw/vfio/ccw.c   | 1 +
 hw/vfio/common.c| 1 +
 hw/vfio/pci.c   | 1 +
 hw/vfio/platform.c  | 1 +
 hw/virtio/vhost-backend.c   | 1 +
 hw/virtio/vhost-user.c  | 1 +
 hw/virtio/virtio-crypto.c   | 1 +
 hw/virtio/virtio-pmem.c | 1 +
 hw/virtio/virtio.c  | 1 +
 hw/xen/xen-legacy-backend.c | 1 +
 hw/xen/xen_pvdev.c  | 1 +
 memory.c| 1 +
 migration/block.c   | 1 +
 migration/colo.c| 1 +
 migration/migration.c   | 1 +
 migration/savevm.c  | 1 +
 net/can/can_socketcan.c | 1 +
 net/netmap.c| 1 +
 net/tap-win32.c | 1 +
 net/tap.c   | 1 +
 qemu-img.c  | 1 +
 qom/cpu.c   | 1 +
 replay/replay-internal.c| 1 +
 target/arm/helper-a64.c | 1 +
 target/arm/helper.c | 2 ++
 target/arm/kvm.c| 1 +
 target/arm/kvm64.c  | 1 +
 target/arm/m_helper.c   | 2 ++
 target/arm/psci.c   | 2 ++
 target/i386/kvm.c   | 1 +
 target/lm32/op_helper.c | 1 +
 target/mips/kvm.c   | 1 +
 target/ppc/int_helper.c | 2 ++
 target/ppc/kvm.c| 1 +
 target/ppc/machine.c| 1 +
 target/ppc/mem_helper.c | 2 ++
 

[Qemu-devel] [PATCH v4 22/29] Include hw/boards.h a bit less

[Markus Armbruster]

hw/boards.h pulls in almost 60 headers.  The less we include it into
headers, the better.  As a first step, drop superfluous inclusions,
and downgrade some more to what's actually needed.  Gets rid of just
one inclusion into a header.

Cc: Eduardo Habkost 
Cc: Marcel Apfelbaum 
Signed-off-by: Markus Armbruster 
Reviewed-by: Alistair Francis 
---
 include/hw/mem/pc-dimm.h| 1 -
 backends/cryptodev-builtin.c| 1 -
 backends/cryptodev-vhost-user.c | 1 -
 backends/cryptodev.c| 1 -
 hw/acpi/ich9.c  | 1 +
 hw/alpha/dp264.c| 1 -
 hw/alpha/typhoon.c  | 1 +
 hw/arm/boot.c   | 1 -
 hw/arm/exynos4210.c | 2 +-
 hw/arm/fsl-imx25.c  | 1 -
 hw/arm/fsl-imx31.c  | 1 -
 hw/arm/msf2-soc.c   | 1 -
 hw/arm/nrf51_soc.c  | 1 -
 hw/arm/omap1.c  | 1 +
 hw/arm/omap2.c  | 1 +
 hw/arm/smmuv3.c | 1 -
 hw/arm/virt.c   | 1 +
 hw/core/numa.c  | 2 ++
 hw/i386/pc_piix.c   | 1 -
 hw/i386/pc_q35.c| 1 -
 hw/i386/pc_sysfw.c  | 1 -
 hw/ppc/e500plat.c   | 1 -
 hw/ppc/mpc8544ds.c  | 1 -
 hw/ppc/pnv.c| 1 +
 hw/ppc/ppc405_uc.c  | 1 -
 hw/ppc/spapr_cpu_core.c | 1 -
 hw/ppc/spapr_vio.c  | 1 -
 hw/riscv/boot.c | 2 +-
 hw/s390x/s390-stattrib.c| 1 -
 hw/xtensa/xtensa_memory.c   | 1 -
 monitor/qmp-cmds.c  | 1 -
 target/alpha/machine.c  | 1 -
 target/arm/machine.c| 1 -
 target/arm/monitor.c| 1 -
 target/hppa/machine.c   | 1 -
 target/i386/hvf/hvf.c   | 1 -
 target/i386/hvf/x86_task.c  | 1 -
 target/i386/machine.c   | 1 -
 target/i386/whpx-all.c  | 1 -
 target/lm32/machine.c   | 1 -
 target/moxie/machine.c  | 1 -
 target/openrisc/machine.c   | 1 -
 target/ppc/machine.c| 1 -
 target/sparc/machine.c  | 1 -
 44 files changed, 10 insertions(+), 37 deletions(-)

diff --git a/include/hw/mem/pc-dimm.h b/include/hw/mem/pc-dimm.h
index 66dee284ac..47b246f95c 100644
--- a/include/hw/mem/pc-dimm.h
+++ b/include/hw/mem/pc-dimm.h
@@ -19,7 +19,6 @@
 #include "exec/memory.h"
 #include "sysemu/hostmem.h"
 #include "hw/qdev-core.h"
-#include "hw/boards.h"
 
 #define TYPE_PC_DIMM "pc-dimm"
 #define PC_DIMM(obj) \
diff --git a/backends/cryptodev-builtin.c b/backends/cryptodev-builtin.c
index 9fb0bd57a6..c8ae3b9742 100644
--- a/backends/cryptodev-builtin.c
+++ b/backends/cryptodev-builtin.c
@@ -23,7 +23,6 @@
 
 #include "qemu/osdep.h"
 #include "sysemu/cryptodev.h"
-#include "hw/boards.h"
 #include "qapi/error.h"
 #include "standard-headers/linux/virtio_crypto.h"
 #include "crypto/cipher.h"
diff --git a/backends/cryptodev-vhost-user.c b/backends/cryptodev-vhost-user.c
index 1052a5d0e9..b344283940 100644
--- a/backends/cryptodev-vhost-user.c
+++ b/backends/cryptodev-vhost-user.c
@@ -22,7 +22,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/boards.h"
 #include "qapi/error.h"
 #include "qapi/qmp/qerror.h"
 #include "qemu/error-report.h"
diff --git a/backends/cryptodev.c b/backends/cryptodev.c
index f35be377ef..3c071eab95 100644
--- a/backends/cryptodev.c
+++ b/backends/cryptodev.c
@@ -23,7 +23,6 @@
 
 #include "qemu/osdep.h"
 #include "sysemu/cryptodev.h"
-#include "hw/boards.h"
 #include "qapi/error.h"
 #include "qapi/visitor.h"
 #include "qemu/config-file.h"
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 39649cbe6a..c1aaa07d43 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -31,6 +31,7 @@
 #include "hw/pci/pci.h"
 #include "migration/vmstate.h"
 #include "qemu/timer.h"
+#include "qom/cpu.h"
 #include "sysemu/reset.h"
 #include "sysemu/sysemu.h"
 #include "hw/acpi/acpi.h"
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index 546b89bbcc..51feee8558 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -11,7 +11,6 @@
 #include "cpu.h"
 #include "elf.h"
 #include "hw/loader.h"
-#include "hw/boards.h"
 #include "alpha_sys.h"
 #include "qemu/error-report.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 5d7f8f3342..1c0565acc1 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -11,6 +11,7 @@
 #include "qemu/units.h"
 #include "qapi/error.h"
 #include "cpu.h"
+#include "hw/boards.h"
 #include "hw/irq.h"
 #include "sysemu/sysemu.h"
 #include "alpha_sys.h"
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 8563672942..eff89ab80e 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -18,7 +18,6 @@
 #include "sysemu/sysemu.h"
 #include "sysemu/numa.h"
 #include "sysemu/reset.h"
-#include "hw/boards.h"
 #include "hw/loader.h"
 #include "elf.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 0e403f3e78..a9f8a5c868 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -27,7 +27,7 @@
 #include "cpu.h"
 

[Qemu-devel] [PATCH v4 23/29] numa: Don't include hw/boards.h into sysemu/numa.h

[Markus Armbruster]

sysemu/numa.h includes hw/boards.h just for the CPUArchId typedef, at
the cost of pulling in more than two dozen extra headers indirectly.

I could move the typedef from hw/boards.h to qemu/typedefs.h.  But
it's used in just two headers: boards.h and numa.h.

I could move it to another header both its users include.
exec/cpu-common.h seems to be the least bad fit.

But I'm keeping this simple & stupid: declare the struct tag in
numa.h.

Cc: Eduardo Habkost 
Cc: Marcel Apfelbaum 
Signed-off-by: Markus Armbruster 
Reviewed-by: Eduardo Habkost 
---
 include/hw/boards.h   | 2 +-
 include/sysemu/numa.h | 9 +++--
 hw/mem/pc-dimm.c  | 1 +
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/include/hw/boards.h b/include/hw/boards.h
index 67e551636a..739d109fe1 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -86,7 +86,7 @@ void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, 
const char *type);
  * @props - CPU object properties, initialized by board
  * #vcpus_count - number of threads provided by @cpu object
  */
-typedef struct {
+typedef struct CPUArchId {
 uint64_t arch_id;
 int64_t vcpus_count;
 CpuInstanceProperties props;
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 01a263eba2..4c4c1dee9b 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -4,7 +4,10 @@
 #include "qemu/bitmap.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/hostmem.h"
-#include "hw/boards.h"
+#include "qapi/qapi-types-machine.h"
+#include "exec/cpu-common.h"
+
+struct CPUArchId;
 
 extern int nb_numa_nodes;   /* Number of NUMA nodes */
 extern bool have_numa_distance;
@@ -32,5 +35,7 @@ void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo 
*nodes,
  int nb_nodes, ram_addr_t size);
 void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
   int nb_nodes, ram_addr_t size);
-void numa_cpu_pre_plug(const CPUArchId *slot, DeviceState *dev, Error **errp);
+void numa_cpu_pre_plug(const struct CPUArchId *slot, DeviceState *dev,
+   Error **errp);
+
 #endif
diff --git a/hw/mem/pc-dimm.c b/hw/mem/pc-dimm.c
index 1f3e676066..dea48f9163 100644
--- a/hw/mem/pc-dimm.c
+++ b/hw/mem/pc-dimm.c
@@ -19,6 +19,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/boards.h"
 #include "hw/mem/pc-dimm.h"
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
-- 
2.21.0

[Qemu-devel] [PATCH v4 27/29] Include sysemu/sysemu.h a lot less

[Markus Armbruster]

In my "build everything" tree, changing sysemu/sysemu.h triggers a
recompile of some 5400 out of 6600 objects (not counting tests and
objects that don't depend on qemu/osdep.h).

hw/qdev-core.h includes sysemu/sysemu.h since recent commit e965ffa70a
"qdev: add qdev_add_vm_change_state_handler()".  This is a bad idea:
hw/qdev-core.h is widely included.

Move the declaration of qdev_add_vm_change_state_handler() to
sysemu/sysemu.h, and drop the problematic include from hw/qdev-core.h.

Touching sysemu/sysemu.h now recompiles some 1800 objects.
qemu/uuid.h also drops from 5400 to 1800.  A few more headers show
smaller improvement: qemu/notify.h drops from 5600 to 5200,
qemu/timer.h from 5600 to 4500, and qapi/qapi-types-run-state.h from
5500 to 5000.

Cc: Stefan Hajnoczi 
Signed-off-by: Markus Armbruster 
Reviewed-by: Alistair Francis 
Reviewed-by: Stefan Hajnoczi 
---
 hw/usb/hcd-ehci.h | 1 +
 include/hw/qdev-core.h| 5 -
 include/sysemu/sysemu.h   | 3 +++
 accel/kvm/kvm-all.c   | 1 +
 backends/hostmem.c| 1 +
 cpus.c| 1 +
 hw/arm/allwinner-a10.c| 1 +
 hw/arm/aspeed_soc.c   | 1 +
 hw/arm/kzm.c  | 1 +
 hw/arm/msf2-soc.c | 1 +
 hw/arm/stm32f205_soc.c| 1 +
 hw/char/serial-isa.c  | 1 +
 hw/char/xen_console.c | 1 +
 hw/core/numa.c| 1 +
 hw/core/vm-change-state-handler.c | 1 +
 hw/display/qxl-render.c   | 1 +
 hw/i386/xen/xen-hvm.c | 1 +
 hw/i386/xen/xen-mapcache.c| 1 +
 hw/intc/ioapic.c  | 1 +
 hw/pci/pci.c  | 1 +
 hw/riscv/sifive_e.c   | 1 +
 hw/riscv/sifive_u.c   | 1 +
 hw/riscv/spike.c  | 1 +
 hw/riscv/virt.c   | 1 +
 hw/sparc64/niagara.c  | 2 +-
 hw/xen/xen-common.c   | 1 +
 hw/xen/xen_devconfig.c| 1 +
 hw/xenpv/xen_machine_pv.c | 1 +
 migration/global_state.c  | 1 +
 migration/migration.c | 1 +
 migration/savevm.c| 1 +
 31 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index 0298238f0b..fdbcfdcbeb 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -21,6 +21,7 @@
 #include "qemu/timer.h"
 #include "hw/usb.h"
 #include "sysemu/dma.h"
+#include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/sysbus.h"
 
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index e5b62dd2fc..de70b7a19a 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -5,7 +5,6 @@
 #include "qemu/bitmap.h"
 #include "qom/object.h"
 #include "hw/hotplug.h"
-#include "sysemu/sysemu.h"
 
 enum {
 DEV_NVECTORS_UNSPECIFIED = -1,
@@ -451,8 +450,4 @@ static inline bool qbus_is_hotpluggable(BusState *bus)
 void device_listener_register(DeviceListener *listener);
 void device_listener_unregister(DeviceListener *listener);
 
-VMChangeStateEntry *qdev_add_vm_change_state_handler(DeviceState *dev,
- VMChangeStateHandler *cb,
- void *opaque);
-
 #endif
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 227202999d..908f158677 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -29,6 +29,9 @@ VMChangeStateEntry 
*qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
  void *opaque);
 VMChangeStateEntry *qemu_add_vm_change_state_handler_prio(
 VMChangeStateHandler *cb, void *opaque, int priority);
+VMChangeStateEntry *qdev_add_vm_change_state_handler(DeviceState *dev,
+ VMChangeStateHandler *cb,
+ void *opaque);
 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
 void vm_state_notify(int running, RunState state);
 
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index e1a44eccf5..fc38d0b9e3 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -29,6 +29,7 @@
 #include "exec/gdbstub.h"
 #include "sysemu/kvm_int.h"
 #include "sysemu/cpus.h"
+#include "sysemu/sysemu.h"
 #include "qemu/bswap.h"
 #include "exec/memory.h"
 #include "exec/ram_addr.h"
diff --git a/backends/hostmem.c b/backends/hostmem.c
index 463102aa15..6d333dc23c 100644
--- a/backends/hostmem.c
+++ b/backends/hostmem.c
@@ -12,6 +12,7 @@
 
 #include "qemu/osdep.h"
 #include "sysemu/hostmem.h"
+#include "sysemu/sysemu.h"
 #include "hw/boards.h"
 #include "qapi/error.h"
 #include "qapi/qapi-builtin-visit.h"
diff --git a/cpus.c b/cpus.c
index e70cc58e31..a20a9a29c1 100644
--- a/cpus.c
+++ b/cpus.c
@@ -41,6 +41,7 @@
 #include "sysemu/kvm.h"
 #include "sysemu/hax.h"
 #include "sysemu/hvf.h"
+#include "sysemu/sysemu.h"
 #include "sysemu/whpx.h"
 #include "exec/exec-all.h"
 
diff 

[Qemu-devel] [PATCH v4 26/29] Clean up inclusion of sysemu/sysemu.h

[Markus Armbruster]

In my "build everything" tree, changing sysemu/sysemu.h triggers a
recompile of some 5400 out of 6600 objects (not counting tests and
objects that don't depend on qemu/osdep.h).

Almost a third of its inclusions are actually superfluous.  Delete
them.  Downgrade two more to qapi/qapi-types-run-state.h, and move one
from char/serial.h to char/serial.c.

hw/semihosting/config.c, monitor/monitor.c, qdev-monitor.c, and
stubs/semihost.c define variables declared in sysemu/sysemu.h without
including it.  The compiler is cool with that, but include it anyway.

This doesn't reduce actual use much, as it's still included into
widely included headers.  The next commit will tackle that.

Signed-off-by: Markus Armbruster 
Reviewed-by: Alistair Francis 
---
 hw/usb/hcd-ehci.h   | 1 -
 include/hw/arm/allwinner-a10.h  | 1 -
 include/hw/char/serial.h| 1 -
 include/hw/i386/pc.h| 1 -
 include/hw/riscv/riscv_htif.h   | 1 -
 include/hw/timer/stm32f2xx_timer.h  | 1 -
 include/hw/virtio/virtio-bus.h  | 1 -
 include/hw/xen/xen-legacy-backend.h | 1 -
 include/migration/global_state.h| 2 +-
 include/sysemu/kvm_int.h| 1 -
 include/sysemu/replay.h | 2 +-
 include/ui/spice-display.h  | 1 -
 accel/tcg/tcg-all.c | 1 -
 block/nfs.c | 1 -
 blockdev-nbd.c  | 1 -
 dump/win_dump.c | 1 -
 hw/acpi/pcihp.c | 1 -
 hw/acpi/vmgenid.c   | 1 -
 hw/alpha/pci.c  | 1 -
 hw/alpha/typhoon.c  | 1 -
 hw/arm/nrf51_soc.c  | 1 -
 hw/arm/smmu-common.c| 1 -
 hw/arm/smmuv3.c | 1 -
 hw/arm/sysbus-fdt.c | 1 -
 hw/arm/z2.c | 1 -
 hw/char/exynos4210_uart.c   | 1 -
 hw/char/imx_serial.c| 1 -
 hw/char/serial.c| 1 +
 hw/core/loader-fit.c| 1 -
 hw/core/platform-bus.c  | 1 -
 hw/core/qdev.c  | 1 -
 hw/display/ramfb-standalone.c   | 1 -
 hw/display/ramfb.c  | 1 -
 hw/dma/xlnx-zynq-devcfg.c   | 1 -
 hw/hppa/dino.c  | 1 -
 hw/hppa/pci.c   | 1 -
 hw/i2c/smbus_ich9.c | 1 -
 hw/ide/cmd646.c | 1 -
 hw/ide/ioport.c | 1 -
 hw/ide/piix.c   | 1 -
 hw/ide/via.c| 1 -
 hw/input/adb-kbd.c  | 1 -
 hw/intc/allwinner-a10-pic.c | 1 -
 hw/intc/mips_gic.c  | 1 -
 hw/intc/xics_pnv.c  | 1 -
 hw/ipmi/ipmi_bmc_extern.c   | 1 -
 hw/isa/vt82c686.c   | 1 -
 hw/misc/armsse-cpuid.c  | 1 -
 hw/misc/armsse-mhu.c| 1 -
 hw/misc/imx6_src.c  | 1 -
 hw/misc/imx7_gpr.c  | 1 -
 hw/misc/iotkit-sysinfo.c| 1 -
 hw/misc/mips_cmgcr.c| 1 -
 hw/misc/mos6522.c   | 1 -
 hw/misc/sga.c   | 1 -
 hw/misc/zynq-xadc.c | 1 -
 hw/net/fsl_etsec/etsec.c| 1 -
 hw/net/lan9118.c| 1 -
 hw/net/ne2000.c | 1 -
 hw/net/opencores_eth.c  | 1 -
 hw/net/pcnet.c  | 1 -
 hw/nios2/generic_nommu.c| 1 -
 hw/pci-host/pam.c   | 1 -
 hw/ppc/pnv_bmc.c| 1 -
 hw/ppc/pnv_core.c   | 1 -
 hw/ppc/pnv_lpc.c| 1 -
 hw/ppc/pnv_occ.c| 1 -
 hw/ppc/ppce500_spin.c   | 1 -
 hw/ppc/spapr_rng.c  | 1 -
 hw/ppc/spapr_vio.c  | 1 -
 hw/s390x/event-facility.c   | 1 -
 hw/s390x/sclpcpu.c  | 1 -
 hw/s390x/virtio-ccw.c   | 1 -
 hw/scsi/scsi-disk.c | 1 -
 hw/sd/milkymist-memcard.c   | 1 -
 hw/semihosting/config.c | 1 +
 hw/ssi/aspeed_smc.c | 1 -
 hw/ssi/imx_spi.c| 1 -
 hw/ssi/xilinx_spi.c | 1 -
 hw/ssi/xilinx_spips.c   | 1 -
 hw/timer/allwinner-a10-pit.c| 1 -
 hw/timer/altera_timer.c | 1 -
 hw/timer/exynos4210_rtc.c   | 1 -
 hw/tricore/tricore_testboard.c  | 1 -
 hw/vfio/ap.c| 1 -
 hw/vfio/platform.c  | 1 -
 hw/xen/xen_pt_load_rom.c| 1 -
 hw/xtensa/xtensa_memory.c   | 1 -
 monitor/monitor.c   | 1 +
 net/tap-bsd.c   | 1 -
 net/tap-linux.c | 1 -
 net/tap-solaris.c   | 1 -
 net/tap-win32.c | 1 -
 qdev-monitor.c  | 1 +
 qemu-img.c  | 1 -
 qom/cpu.c   | 1 -
 replay/replay-audio.c   | 1 -
 replay/replay-char.c| 1 -
 replay/replay-net.c

[Qemu-devel] [PATCH v4 16/29] Include exec/memory.h slightly less

[Markus Armbruster]

Drop unnecessary inclusions from headers.  Downgrade a few more to
exec/hwaddr.h.

Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 hw/audio/lm4549.h   | 1 +
 hw/net/can/can_sja1000.h| 1 +
 hw/xtensa/xtensa_memory.h   | 1 -
 include/hw/arm/boot.h   | 1 -
 include/hw/arm/fsl-imx7.h   | 1 -
 include/hw/arm/soc_dma.h| 2 +-
 include/hw/block/flash.h| 2 +-
 include/hw/boards.h | 1 +
 include/hw/char/parallel.h  | 1 -
 include/hw/display/milkymist_tmu2.h | 1 +
 include/hw/display/tc6393xb.h   | 2 --
 include/hw/display/vga.h| 2 +-
 include/hw/hw.h | 1 -
 include/hw/i2c/pm_smbus.h   | 1 +
 include/hw/i2c/smbus_eeprom.h   | 1 +
 include/hw/misc/auxbus.h| 1 +
 include/hw/ppc/xics.h   | 1 +
 include/hw/usb.h| 1 +
 include/hw/virtio/virtio.h  | 1 +
 migration/migration.h   | 1 +
 hw/display/edid-region.c| 1 +
 hw/display/tc6393xb.c   | 1 +
 hw/net/ne2000.c | 1 +
 migration/colo.c| 1 +
 migration/postcopy-ram.c| 1 +
 migration/rdma.c| 1 +
 26 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/hw/audio/lm4549.h b/hw/audio/lm4549.h
index 74c3ee8934..aba9bb5b07 100644
--- a/hw/audio/lm4549.h
+++ b/hw/audio/lm4549.h
@@ -13,6 +13,7 @@
 #define HW_LM4549_H
 
 #include "audio/audio.h"
+#include "exec/hwaddr.h"
 
 typedef void (*lm4549_callback)(void *opaque);
 
diff --git a/hw/net/can/can_sja1000.h b/hw/net/can/can_sja1000.h
index 4731cbbd2a..220a622087 100644
--- a/hw/net/can/can_sja1000.h
+++ b/hw/net/can/can_sja1000.h
@@ -27,6 +27,7 @@
 #ifndef HW_CAN_SJA1000_H
 #define HW_CAN_SJA1000_H
 
+#include "exec/hwaddr.h"
 #include "net/can_emu.h"
 
 #define CAN_SJA_MEM_SIZE  128
diff --git a/hw/xtensa/xtensa_memory.h b/hw/xtensa/xtensa_memory.h
index d50a30..af7e8025e3 100644
--- a/hw/xtensa/xtensa_memory.h
+++ b/hw/xtensa/xtensa_memory.h
@@ -29,7 +29,6 @@
 #define XTENSA_MEMORY_H
 
 #include "cpu.h"
-#include "exec/memory.h"
 
 void xtensa_create_memory_regions(const XtensaMemory *memory,
   const char *name,
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
index 350d4b0498..5714dea1a2 100644
--- a/include/hw/arm/boot.h
+++ b/include/hw/arm/boot.h
@@ -11,7 +11,6 @@
 #ifndef HW_ARM_BOOT_H
 #define HW_ARM_BOOT_H
 
-#include "exec/memory.h"
 #include "target/arm/cpu-qom.h"
 #include "qemu/notify.h"
 
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 8003d45d1e..706aef2e7e 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -38,7 +38,6 @@
 #include "hw/net/imx_fec.h"
 #include "hw/pci-host/designware.h"
 #include "hw/usb/chipidea.h"
-#include "exec/memory.h"
 #include "cpu.h"
 
 #define TYPE_FSL_IMX7 "fsl,imx7"
diff --git a/include/hw/arm/soc_dma.h b/include/hw/arm/soc_dma.h
index 7886291d54..e93a7499a8 100644
--- a/include/hw/arm/soc_dma.h
+++ b/include/hw/arm/soc_dma.h
@@ -21,7 +21,7 @@
 #ifndef HW_SOC_DMA_H
 #define HW_SOC_DMA_H
 
-#include "exec/memory.h"
+#include "exec/hwaddr.h"
 
 struct soc_dma_s;
 struct soc_dma_ch_s;
diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h
index 1acaf7de80..2136a2d5e4 100644
--- a/include/hw/block/flash.h
+++ b/include/hw/block/flash.h
@@ -3,7 +3,7 @@
 
 /* NOR flash devices */
 
-#include "exec/memory.h"
+#include "exec/hwaddr.h"
 
 /* pflash_cfi01.c */
 
diff --git a/include/hw/boards.h b/include/hw/boards.h
index a71d1a53a5..3a0be3131a 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -3,6 +3,7 @@
 #ifndef HW_BOARDS_H
 #define HW_BOARDS_H
 
+#include "exec/memory.h"
 #include "sysemu/blockdev.h"
 #include "sysemu/accel.h"
 #include "hw/qdev.h"
diff --git a/include/hw/char/parallel.h b/include/hw/char/parallel.h
index d6dd62fb9f..0a23c0f57e 100644
--- a/include/hw/char/parallel.h
+++ b/include/hw/char/parallel.h
@@ -1,7 +1,6 @@
 #ifndef HW_PARALLEL_H
 #define HW_PARALLEL_H
 
-#include "exec/memory.h"
 #include "hw/isa/isa.h"
 #include "chardev/char.h"
 
diff --git a/include/hw/display/milkymist_tmu2.h 
b/include/hw/display/milkymist_tmu2.h
index 148a119a1d..1fd978dcc5 100644
--- a/include/hw/display/milkymist_tmu2.h
+++ b/include/hw/display/milkymist_tmu2.h
@@ -27,6 +27,7 @@
 #ifndef HW_DISPLAY_MILKYMIST_TMU2_H
 #define HW_DISPLAY_MILKYMIST_TMU2_H
 
+#include "exec/hwaddr.h"
 #include "hw/qdev.h"
 
 #if defined(CONFIG_X11) && defined(CONFIG_OPENGL)
diff --git a/include/hw/display/tc6393xb.h b/include/hw/display/tc6393xb.h
index c653ef717b..f9263bf98a 100644
--- a/include/hw/display/tc6393xb.h
+++ b/include/hw/display/tc6393xb.h
@@ -12,8 +12,6 @@
 #ifndef HW_DISPLAY_TC6393XB_H
 #define HW_DISPLAY_TC6393XB_H
 
-#include "exec/memory.h"
-
 typedef struct TC6393xbState TC6393xbState;
 
 

[Qemu-devel] [PATCH v4 28/29] sysemu: Move the VMChangeStateEntry typedef to qemu/typedefs.h

[Markus Armbruster]

In my "build everything" tree, changing sysemu/sysemu.h triggers a
recompile of some 1800 out of 6600 objects (not counting tests and
objects that don't depend on qemu/osdep.h, down from 5400 due to the
previous commit).

Several headers include sysemu/sysemu.h just to get typedef
VMChangeStateEntry.  Move it from sysemu/sysemu.h to qemu/typedefs.h.
Spell its structure tag the same while there.  Drop the now
superfluous includes of sysemu/sysemu.h from headers.

Touching sysemu/sysemu.h now recompiles some 1100 objects.
qemu/uuid.h also drops from 1800 to 1100, and
qapi/qapi-types-run-state.h from 5000 to 4400.

Signed-off-by: Markus Armbruster 
---
 hw/usb/hcd-ehci.h   | 1 -
 include/hw/ide/internal.h   | 3 ++-
 include/hw/ppc/spapr_xive.h | 1 -
 include/hw/scsi/scsi.h  | 1 -
 include/hw/virtio/virtio.h  | 1 -
 include/qemu/typedefs.h | 1 +
 include/sysemu/sysemu.h | 1 -
 hw/block/vhost-user-blk.c   | 1 +
 hw/block/virtio-blk.c   | 1 +
 hw/display/virtio-gpu.c | 1 +
 hw/misc/macio/macio.c   | 1 +
 hw/net/virtio-net.c | 1 +
 hw/s390x/s390-ccw.c | 1 +
 hw/s390x/s390-virtio-ccw.c  | 1 +
 hw/scsi/scsi-bus.c  | 1 +
 hw/scsi/vhost-scsi.c| 1 +
 hw/scsi/vhost-user-scsi.c   | 1 +
 hw/usb/hcd-ehci.c   | 1 +
 hw/virtio/virtio-rng.c  | 1 +
 hw/virtio/virtio.c  | 1 +
 vl.c| 6 +++---
 21 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index fdbcfdcbeb..0298238f0b 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -21,7 +21,6 @@
 #include "qemu/timer.h"
 #include "hw/usb.h"
 #include "sysemu/dma.h"
-#include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/sysbus.h"
 
diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
index c6954c1d56..52ec197da0 100644
--- a/include/hw/ide/internal.h
+++ b/include/hw/ide/internal.h
@@ -6,11 +6,12 @@
  * only files in hw/ide/ are supposed to include this file.
  * non-internal declarations are in hw/ide.h
  */
+
+#include "qapi/qapi-types-run-state.h"
 #include "hw/ide.h"
 #include "hw/irq.h"
 #include "hw/isa/isa.h"
 #include "sysemu/dma.h"
-#include "sysemu/sysemu.h"
 #include "hw/block/block.h"
 #include "scsi/constants.h"
 
diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h
index a39e672f27..bfd40f01d8 100644
--- a/include/hw/ppc/spapr_xive.h
+++ b/include/hw/ppc/spapr_xive.h
@@ -12,7 +12,6 @@
 
 #include "hw/ppc/spapr_irq.h"
 #include "hw/ppc/xive.h"
-#include "sysemu/sysemu.h"
 
 #define TYPE_SPAPR_XIVE "spapr-xive"
 #define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE)
diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h
index 2bfaad0fe9..d77a92361b 100644
--- a/include/hw/scsi/scsi.h
+++ b/include/hw/scsi/scsi.h
@@ -4,7 +4,6 @@
 #include "block/aio.h"
 #include "hw/block/block.h"
 #include "hw/qdev-core.h"
-#include "sysemu/sysemu.h"
 #include "scsi/utils.h"
 #include "qemu/notify.h"
 
diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index df40a46d60..48e8d04ff6 100644
--- a/include/hw/virtio/virtio.h
+++ b/include/hw/virtio/virtio.h
@@ -17,7 +17,6 @@
 #include "exec/memory.h"
 #include "hw/qdev-core.h"
 #include "net/net.h"
-#include "sysemu/sysemu.h"
 #include "migration/vmstate.h"
 #include "qemu/event_notifier.h"
 #include "standard-headers/linux/virtio_config.h"
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index f569f5f270..3fcdde8bfc 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -102,6 +102,7 @@ typedef struct SHPCDevice SHPCDevice;
 typedef struct SSIBus SSIBus;
 typedef struct VirtIODevice VirtIODevice;
 typedef struct Visitor Visitor;
+typedef struct VMChangeStateEntry VMChangeStateEntry;
 typedef struct VMStateDescription VMStateDescription;
 
 /*
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 908f158677..7606eaaf2a 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -22,7 +22,6 @@ void runstate_set(RunState new_state);
 int runstate_is_running(void);
 bool runstate_needs_reset(void);
 bool runstate_store(char *str, size_t size);
-typedef struct vm_change_state_entry VMChangeStateEntry;
 typedef void VMChangeStateHandler(void *opaque, int running, RunState state);
 
 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c
index 7b44cca6d9..6b6cd07362 100644
--- a/hw/block/vhost-user-blk.c
+++ b/hw/block/vhost-user-blk.c
@@ -28,6 +28,7 @@
 #include "hw/virtio/virtio.h"
 #include "hw/virtio/virtio-bus.h"
 #include "hw/virtio/virtio-access.h"
+#include "sysemu/sysemu.h"
 
 static const int user_feature_bits[] = {
 VIRTIO_BLK_F_SIZE_MAX,
diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c
index 8cc2a232e0..78ac371eba 100644
--- a/hw/block/virtio-blk.c
+++ b/hw/block/virtio-blk.c
@@ -20,6 +20,7 @@
 #include "hw/block/block.h"
 #include 

[Qemu-devel] [PATCH v4 14/29] migration: Move the VMStateDescription typedef to typedefs.h

[Markus Armbruster]

We declare incomplete struct VMStateDescription in a couple of places
so we don't have to include migration/vmstate.h for the typedef.
That's fine with me.  However, the next commit will drop
migration/vmstate.h from a massive number of compiles.  Move the
typedef to qemu/typedefs.h now, so I don't have to insert struct in
front of VMStateDescription all over the place then.

Signed-off-by: Markus Armbruster 
Reviewed-by: Alex Bennée 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 include/hw/qdev-core.h  | 6 ++
 include/migration/vmstate.h | 1 -
 include/qemu/typedefs.h | 1 +
 include/qom/cpu.h   | 4 ++--
 target/alpha/cpu.h  | 2 +-
 target/arm/cpu.h| 2 +-
 target/cris/cpu.h   | 2 +-
 target/hppa/cpu.h   | 2 +-
 target/i386/cpu.h   | 2 +-
 target/lm32/cpu.h   | 2 +-
 target/mips/internal.h  | 2 +-
 target/openrisc/cpu.h   | 2 +-
 target/ppc/cpu-qom.h| 2 +-
 target/ppc/cpu.h| 2 +-
 target/s390x/cpu.h  | 2 +-
 target/sparc/cpu.h  | 2 +-
 16 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index b870c8ceeb..e5b62dd2fc 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -35,8 +35,6 @@ typedef void (*DeviceReset)(DeviceState *dev);
 typedef void (*BusRealize)(BusState *bus, Error **errp);
 typedef void (*BusUnrealize)(BusState *bus, Error **errp);
 
-struct VMStateDescription;
-
 /**
  * DeviceClass:
  * @props: Properties accessing state fields.
@@ -112,7 +110,7 @@ typedef struct DeviceClass {
 DeviceUnrealize unrealize;
 
 /* device state */
-const struct VMStateDescription *vmsd;
+const VMStateDescription *vmsd;
 
 /* Private to qdev / bus.  */
 const char *bus_type;
@@ -425,7 +423,7 @@ void device_class_set_parent_unrealize(DeviceClass *dc,
DeviceUnrealize dev_unrealize,
DeviceUnrealize *parent_unrealize);
 
-const struct VMStateDescription *qdev_get_vmsd(DeviceState *dev);
+const VMStateDescription *qdev_get_vmsd(DeviceState *dev);
 
 const char *qdev_fw_name(DeviceState *dev);
 
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index c2bfa7a7f0..1fbfd099dd 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -28,7 +28,6 @@
 #define QEMU_VMSTATE_H
 
 typedef struct VMStateInfo VMStateInfo;
-typedef struct VMStateDescription VMStateDescription;
 typedef struct VMStateField VMStateField;
 
 /* VMStateInfo allows customized migration of objects that don't fit in
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index c32efb5b18..9e1283aacf 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -101,6 +101,7 @@ typedef struct SHPCDevice SHPCDevice;
 typedef struct SSIBus SSIBus;
 typedef struct VirtIODevice VirtIODevice;
 typedef struct Visitor Visitor;
+typedef struct VMStateDescription VMStateDescription;
 
 /*
  * Pointer types
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 5ee0046b62..ddb91bbaff 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -215,7 +215,7 @@ typedef struct CPUClass {
 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 void *opaque);
 
-const struct VMStateDescription *vmsd;
+const VMStateDescription *vmsd;
 const char *gdb_core_xml_file;
 gchar * (*gdb_arch_name)(CPUState *cpu);
 const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
@@ -1108,7 +1108,7 @@ bool target_words_bigendian(void);
 #ifdef NEED_CPU_H
 
 #ifdef CONFIG_SOFTMMU
-extern const struct VMStateDescription vmstate_cpu_common;
+extern const VMStateDescription vmstate_cpu_common;
 #else
 #define vmstate_cpu_common vmstate_dummy
 #endif
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index b3e8a823e1..4619530660 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -277,7 +277,7 @@ struct AlphaCPU {
 
 
 #ifndef CONFIG_USER_ONLY
-extern const struct VMStateDescription vmstate_alpha_cpu;
+extern const VMStateDescription vmstate_alpha_cpu;
 #endif
 
 void alpha_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 94c990cddb..2cdde6c4bc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -922,7 +922,7 @@ void arm_cpu_post_init(Object *obj);
 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
 
 #ifndef CONFIG_USER_ONLY
-extern const struct VMStateDescription vmstate_arm_cpu;
+extern const VMStateDescription vmstate_arm_cpu;
 #endif
 
 void arm_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index fb14ad51f1..aba0a66474 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -183,7 +183,7 @@ struct CRISCPU {
 
 
 #ifndef CONFIG_USER_ONLY
-extern const struct VMStateDescription vmstate_cris_cpu;
+extern const VMStateDescription 

[Qemu-devel] [PATCH v4 19/29] Include qemu/queue.h slightly less

[Markus Armbruster]

Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 include/exec/cpu-defs.h | 1 -
 include/hw/xen/xen_common.h | 1 -
 include/net/can_emu.h   | 1 +
 include/net/filter.h| 1 +
 include/qemu/range.h| 2 --
 include/qom/object.h| 1 -
 include/sysemu/cryptodev.h  | 1 +
 include/sysemu/rng.h| 1 +
 include/sysemu/sysemu.h | 1 -
 linux-user/qemu.h   | 1 -
 nbd/nbd-internal.h  | 1 -
 hw/scsi/vhost-scsi.c| 1 -
 hw/vfio/ap.c| 1 -
 linux-user/elfload.c| 1 +
 linux-user/main.c   | 1 +
 linux-user/syscall.c| 1 +
 nbd/client.c| 1 +
 nbd/server.c| 1 +
 qapi/qapi-dealloc-visitor.c | 1 -
 target/i386/whpx-all.c  | 1 -
 ui/kbd-state.c  | 1 -
 util/vfio-helpers.c | 1 -
 22 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 9bc713a70b..57a9a4ffd9 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -25,7 +25,6 @@
 
 #include "qemu/host-utils.h"
 #include "qemu/thread.h"
-#include "qemu/queue.h"
 #ifdef CONFIG_TCG
 #include "tcg-target.h"
 #endif
diff --git a/include/hw/xen/xen_common.h b/include/hw/xen/xen_common.h
index 1e3ec4e16e..82e56339dd 100644
--- a/include/hw/xen/xen_common.h
+++ b/include/hw/xen/xen_common.h
@@ -16,7 +16,6 @@
 
 #include "hw/xen/xen.h"
 #include "hw/pci/pci.h"
-#include "qemu/queue.h"
 #include "hw/xen/trace.h"
 
 extern xc_interface *xen_xc;
diff --git a/include/net/can_emu.h b/include/net/can_emu.h
index 1da4d01b95..d4fc51b57d 100644
--- a/include/net/can_emu.h
+++ b/include/net/can_emu.h
@@ -28,6 +28,7 @@
 #ifndef NET_CAN_EMU_H
 #define NET_CAN_EMU_H
 
+#include "qemu/queue.h"
 #include "qom/object.h"
 
 /* NOTE: the following two structures is copied from . */
diff --git a/include/net/filter.h b/include/net/filter.h
index 9bc6fa3cc6..e8fb6259db 100644
--- a/include/net/filter.h
+++ b/include/net/filter.h
@@ -10,6 +10,7 @@
 #define QEMU_NET_FILTER_H
 
 #include "qapi/qapi-types-net.h"
+#include "qemu/queue.h"
 #include "qom/object.h"
 #include "net/queue.h"
 
diff --git a/include/qemu/range.h b/include/qemu/range.h
index 71b8b215c6..f62b363e0d 100644
--- a/include/qemu/range.h
+++ b/include/qemu/range.h
@@ -20,8 +20,6 @@
 #ifndef QEMU_RANGE_H
 #define QEMU_RANGE_H
 
-#include "qemu/queue.h"
-
 /*
  * Operations on 64 bit address ranges.
  * Notes:
diff --git a/include/qom/object.h b/include/qom/object.h
index 7bb82a7f56..128d00c77f 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -15,7 +15,6 @@
 #define QEMU_OBJECT_H
 
 #include "qapi/qapi-builtin-types.h"
-#include "qemu/queue.h"
 #include "qemu/module.h"
 
 struct TypeImpl;
diff --git a/include/sysemu/cryptodev.h b/include/sysemu/cryptodev.h
index 92bbb79131..a9afb7e5b5 100644
--- a/include/sysemu/cryptodev.h
+++ b/include/sysemu/cryptodev.h
@@ -23,6 +23,7 @@
 #ifndef CRYPTODEV_H
 #define CRYPTODEV_H
 
+#include "qemu/queue.h"
 #include "qom/object.h"
 
 /**
diff --git a/include/sysemu/rng.h b/include/sysemu/rng.h
index 2a02f47771..9b22c156f8 100644
--- a/include/sysemu/rng.h
+++ b/include/sysemu/rng.h
@@ -13,6 +13,7 @@
 #ifndef QEMU_RNG_H
 #define QEMU_RNG_H
 
+#include "qemu/queue.h"
 #include "qom/object.h"
 
 #define TYPE_RNG_BACKEND "rng-backend"
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 984c439ac9..77f5df59b0 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -3,7 +3,6 @@
 /* Misc. things related to the system emulator.  */
 
 #include "qapi/qapi-types-run-state.h"
-#include "qemu/queue.h"
 #include "qemu/timer.h"
 #include "qemu/notify.h"
 #include "qemu/main-loop.h"
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index aac0334627..f6f5fe5fbb 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -16,7 +16,6 @@
 #include "syscall_defs.h"
 #include "target_syscall.h"
 #include "exec/gdbstub.h"
-#include "qemu/queue.h"
 
 /* This is the size of the host kernel's sigset_t, needed where we make
  * direct system calls that take a sigset_t pointer and a size.
diff --git a/nbd/nbd-internal.h b/nbd/nbd-internal.h
index 049f83df77..ec3d2e2ebc 100644
--- a/nbd/nbd-internal.h
+++ b/nbd/nbd-internal.h
@@ -28,7 +28,6 @@
 #endif
 
 #include "qemu/bswap.h"
-#include "qemu/queue.h"
 #include "qemu/main-loop.h"
 
 /* This is all part of the "official" NBD API.
diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-scsi.c
index 343ca8be7a..83c9d83459 100644
--- a/hw/scsi/vhost-scsi.c
+++ b/hw/scsi/vhost-scsi.c
@@ -20,7 +20,6 @@
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "qemu/module.h"
-#include "qemu/queue.h"
 #include "monitor/monitor.h"
 #include "migration/blocker.h"
 #include "hw/virtio/vhost-scsi.h"
diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c
index d1c86abb76..2bfc402037 100644
--- a/hw/vfio/ap.c
+++ b/hw/vfio/ap.c
@@ -20,7 +20,6 @@
 #include "hw/s390x/ap-device.h"
 

[Qemu-devel] [PATCH v4 25/29] numa: Move remaining NUMA declarations from sysemu.h to numa.h

[Markus Armbruster]

Commit e35704ba9c "numa: Move NUMA declarations from sysemu.h to
numa.h" left a few NUMA-related macros behind.  Move them now.

Cc: Eduardo Habkost 
Cc: Marcel Apfelbaum 
Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Eduardo Habkost 
---
 include/sysemu/hostmem.h | 2 +-
 include/sysemu/numa.h| 9 +++--
 include/sysemu/sysemu.h  | 7 ---
 exec.c   | 2 +-
 hw/core/numa.c   | 1 +
 hw/mem/pc-dimm.c | 1 +
 hw/pci/pci.c | 2 +-
 hw/ppc/spapr.c   | 1 +
 8 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/include/sysemu/hostmem.h b/include/sysemu/hostmem.h
index afeb5db1b1..4dbdadd39e 100644
--- a/include/sysemu/hostmem.h
+++ b/include/sysemu/hostmem.h
@@ -13,7 +13,7 @@
 #ifndef SYSEMU_HOSTMEM_H
 #define SYSEMU_HOSTMEM_H
 
-#include "sysemu/sysemu.h" /* for MAX_NODES */
+#include "sysemu/numa.h"
 #include "qapi/qapi-types-machine.h"
 #include "qom/object.h"
 #include "exec/memory.h"
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 4c4c1dee9b..7a4ce89765 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -2,13 +2,18 @@
 #define SYSEMU_NUMA_H
 
 #include "qemu/bitmap.h"
-#include "sysemu/sysemu.h"
-#include "sysemu/hostmem.h"
 #include "qapi/qapi-types-machine.h"
 #include "exec/cpu-common.h"
 
 struct CPUArchId;
 
+#define MAX_NODES 128
+#define NUMA_NODE_UNASSIGNED MAX_NODES
+#define NUMA_DISTANCE_MIN 10
+#define NUMA_DISTANCE_DEFAULT 20
+#define NUMA_DISTANCE_MAX 254
+#define NUMA_DISTANCE_UNREACHABLE 255
+
 extern int nb_numa_nodes;   /* Number of NUMA nodes */
 extern bool have_numa_distance;
 
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index ac18a1184a..227202999d 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -117,13 +117,6 @@ extern QEMUClockType rtc_clock;
 extern const char *mem_path;
 extern int mem_prealloc;
 
-#define MAX_NODES 128
-#define NUMA_NODE_UNASSIGNED MAX_NODES
-#define NUMA_DISTANCE_MIN 10
-#define NUMA_DISTANCE_DEFAULT 20
-#define NUMA_DISTANCE_MAX 254
-#define NUMA_DISTANCE_UNREACHABLE 255
-
 #define MAX_OPTION_ROMS 16
 typedef struct QEMUOptionRom {
 const char *name;
diff --git a/exec.c b/exec.c
index 78f849de99..4aaa14b075 100644
--- a/exec.c
+++ b/exec.c
@@ -45,7 +45,7 @@
 #include "exec/memory.h"
 #include "exec/ioport.h"
 #include "sysemu/dma.h"
-#include "sysemu/numa.h"
+#include "sysemu/hostmem.h"
 #include "sysemu/hw_accel.h"
 #include "exec/address-spaces.h"
 #include "sysemu/xen-mapcache.h"
diff --git a/hw/core/numa.c b/hw/core/numa.c
index d817f06ead..450c522dd8 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -23,6 +23,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "sysemu/hostmem.h"
 #include "sysemu/numa.h"
 #include "exec/cpu-common.h"
 #include "exec/ramlist.h"
diff --git a/hw/mem/pc-dimm.c b/hw/mem/pc-dimm.c
index dea48f9163..7c324a1329 100644
--- a/hw/mem/pc-dimm.c
+++ b/hw/mem/pc-dimm.c
@@ -28,6 +28,7 @@
 #include "qapi/error.h"
 #include "qapi/visitor.h"
 #include "qemu/module.h"
+#include "sysemu/hostmem.h"
 #include "sysemu/numa.h"
 #include "trace.h"
 
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 9001b81daa..4b6ffab13d 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -34,7 +34,7 @@
 #include "migration/vmstate.h"
 #include "monitor/monitor.h"
 #include "net/net.h"
-#include "sysemu/sysemu.h"
+#include "sysemu/numa.h"
 #include "hw/loader.h"
 #include "qemu/error-report.h"
 #include "qemu/range.h"
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 06d23a5004..4044e61a0c 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -29,6 +29,7 @@
 #include "qapi/error.h"
 #include "qapi/visitor.h"
 #include "sysemu/sysemu.h"
+#include "sysemu/hostmem.h"
 #include "sysemu/numa.h"
 #include "sysemu/qtest.h"
 #include "sysemu/reset.h"
-- 
2.21.0

[Qemu-devel] [PATCH v4 09/29] Include migration/qemu-file-types.h a lot less

[Markus Armbruster]

In my "build everything" tree, changing migration/qemu-file-types.h
triggers a recompile of some 2600 out of 6600 objects (not counting
tests and objects that don't depend on qemu/osdep.h).

The culprit is again hw/hw.h, which supposedly includes it for
convenience.

Include migration/qemu-file-types.h only where it's needed.  Touching
it now recompiles less than 200 objects.

Signed-off-by: Markus Armbruster 
---
 include/hw/hw.h | 1 -
 include/migration/cpu.h | 1 +
 hw/acpi/piix4.c | 1 +
 hw/block/virtio-blk.c   | 1 +
 hw/char/virtio-serial-bus.c | 1 +
 hw/display/virtio-gpu.c | 1 +
 hw/intc/apic_common.c   | 1 +
 hw/intc/s390_flic_kvm.c | 1 +
 hw/nvram/eeprom93xx.c   | 1 +
 hw/nvram/fw_cfg.c   | 1 +
 hw/pci-host/piix.c  | 1 +
 hw/pci/msix.c   | 1 +
 hw/pci/pci.c| 1 +
 hw/pci/shpc.c   | 1 +
 hw/ppc/spapr.c  | 1 +
 hw/s390x/s390-skeys.c   | 1 +
 hw/s390x/tod.c  | 1 +
 hw/s390x/virtio-ccw.c   | 1 +
 hw/scsi/mptsas.c| 1 +
 hw/scsi/scsi-bus.c  | 1 +
 hw/scsi/scsi-disk.c | 1 +
 hw/scsi/scsi-generic.c  | 1 +
 hw/scsi/virtio-scsi.c   | 1 +
 hw/timer/i8254_common.c | 1 +
 hw/timer/twl92230.c | 1 +
 hw/usb/redirect.c   | 1 +
 hw/virtio/vhost.c   | 1 +
 hw/virtio/virtio-mmio.c | 1 +
 hw/virtio/virtio-pci.c  | 1 +
 hw/virtio/virtio.c  | 1 +
 target/ppc/kvm.c| 1 +
 31 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/include/hw/hw.h b/include/hw/hw.h
index a4fb2390e8..b399627cbe 100644
--- a/include/hw/hw.h
+++ b/include/hw/hw.h
@@ -11,7 +11,6 @@
 #include "exec/memory.h"
 #include "hw/irq.h"
 #include "migration/vmstate.h"
-#include "migration/qemu-file-types.h"
 
 void QEMU_NORETURN hw_error(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
 
diff --git a/include/migration/cpu.h b/include/migration/cpu.h
index da1618d620..2a22470d0d 100644
--- a/include/migration/cpu.h
+++ b/include/migration/cpu.h
@@ -4,6 +4,7 @@
 #define MIGRATION_CPU_H
 
 #include "exec/cpu-defs.h"
+#include "migration/qemu-file-types.h"
 
 #if TARGET_LONG_BITS == 64
 #define qemu_put_betl qemu_put_be64
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index a59e58d937..0d8c821f37 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -40,6 +40,7 @@
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/acpi/acpi_dev_interface.h"
 #include "hw/xen/xen.h"
+#include "migration/qemu-file-types.h"
 #include "qom/cpu.h"
 #include "trace.h"
 
diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c
index cbb3729158..1f40834d27 100644
--- a/hw/block/virtio-blk.c
+++ b/hw/block/virtio-blk.c
@@ -26,6 +26,7 @@
 # include 
 #endif
 #include "hw/virtio/virtio-bus.h"
+#include "migration/qemu-file-types.h"
 #include "hw/virtio/virtio-access.h"
 
 /* Config size before the discard support (hide associated config fields) */
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
index f7a54f261b..b868e54d72 100644
--- a/hw/char/virtio-serial-bus.c
+++ b/hw/char/virtio-serial-bus.c
@@ -22,6 +22,7 @@
 #include "qapi/error.h"
 #include "qemu/iov.h"
 #include "qemu/module.h"
+#include "migration/qemu-file-types.h"
 #include "monitor/monitor.h"
 #include "qemu/error-report.h"
 #include "qemu/queue.h"
diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c
index 25d9e327fc..ed92071963 100644
--- a/hw/display/virtio-gpu.c
+++ b/hw/display/virtio-gpu.c
@@ -18,6 +18,7 @@
 #include "trace.h"
 #include "sysemu/dma.h"
 #include "hw/virtio/virtio.h"
+#include "migration/qemu-file-types.h"
 #include "hw/virtio/virtio-gpu.h"
 #include "hw/virtio/virtio-gpu-bswap.h"
 #include "hw/virtio/virtio-gpu-pixman.h"
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index e764a2bb03..7045761281 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -31,6 +31,7 @@
 #include "sysemu/kvm.h"
 #include "hw/qdev.h"
 #include "hw/sysbus.h"
+#include "migration/qemu-file-types.h"
 
 static int apic_irq_delivered;
 bool apic_report_tpr_access;
diff --git a/hw/intc/s390_flic_kvm.c b/hw/intc/s390_flic_kvm.c
index ff45b4ab0b..819aa5e198 100644
--- a/hw/intc/s390_flic_kvm.c
+++ b/hw/intc/s390_flic_kvm.c
@@ -22,6 +22,7 @@
 #include "hw/s390x/s390_flic.h"
 #include "hw/s390x/adapter.h"
 #include "hw/s390x/css.h"
+#include "migration/qemu-file-types.h"
 #include "trace.h"
 
 #define FLIC_SAVE_INITIAL_SIZE getpagesize()
diff --git a/hw/nvram/eeprom93xx.c b/hw/nvram/eeprom93xx.c
index 2db3d7cce6..5fc23df1d4 100644
--- a/hw/nvram/eeprom93xx.c
+++ b/hw/nvram/eeprom93xx.c
@@ -38,6 +38,7 @@
 #include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/nvram/eeprom93xx.h"
+#include "migration/qemu-file-types.h"
 
 /* Debug EEPROM emulation. */
 //~ #define DEBUG_EEPROM
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 3032f1c65f..8db0297d59 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -31,6 +31,7 @@
 #include "hw/boards.h"
 

[Qemu-devel] [PATCH v4 24/29] Include sysemu/hostmem.h less

[Markus Armbruster]

Move the HostMemoryBackend typedef from sysemu/hostmem.h to
qemu/typedefs.h.  This renders a few inclusions of sysemu/hostmem.h
superfluous; drop them.

Cc: Eduardo Habkost 
Cc: Igor Mammedov 
Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Eduardo Habkost 
Reviewed-by: Igor Mammedov 
Tested-by: Philippe Mathieu-Daudé 
---
 include/hw/mem/pc-dimm.h| 1 -
 include/hw/virtio/virtio-pmem.h | 1 -
 include/qemu/typedefs.h | 1 +
 include/sysemu/hostmem.h| 1 -
 hw/mem/nvdimm.c | 1 +
 hw/virtio/virtio-pmem.c | 1 +
 6 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/hw/mem/pc-dimm.h b/include/hw/mem/pc-dimm.h
index 47b246f95c..289edc0f3d 100644
--- a/include/hw/mem/pc-dimm.h
+++ b/include/hw/mem/pc-dimm.h
@@ -17,7 +17,6 @@
 #define QEMU_PC_DIMM_H
 
 #include "exec/memory.h"
-#include "sysemu/hostmem.h"
 #include "hw/qdev-core.h"
 
 #define TYPE_PC_DIMM "pc-dimm"
diff --git a/include/hw/virtio/virtio-pmem.h b/include/hw/virtio/virtio-pmem.h
index 8bf2ae780f..33f1999320 100644
--- a/include/hw/virtio/virtio-pmem.h
+++ b/include/hw/virtio/virtio-pmem.h
@@ -16,7 +16,6 @@
 
 #include "hw/virtio/virtio.h"
 #include "qapi/qapi-types-misc.h"
-#include "sysemu/hostmem.h"
 
 #define TYPE_VIRTIO_PMEM "virtio-pmem"
 
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 9e1283aacf..f569f5f270 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -33,6 +33,7 @@ typedef struct FWCfgEntry FWCfgEntry;
 typedef struct FWCfgIoState FWCfgIoState;
 typedef struct FWCfgMemState FWCfgMemState;
 typedef struct FWCfgState FWCfgState;
+typedef struct HostMemoryBackend HostMemoryBackend;
 typedef struct HVFX86EmulatorState HVFX86EmulatorState;
 typedef struct I2CBus I2CBus;
 typedef struct I2SCodec I2SCodec;
diff --git a/include/sysemu/hostmem.h b/include/sysemu/hostmem.h
index 92fa0e458c..afeb5db1b1 100644
--- a/include/sysemu/hostmem.h
+++ b/include/sysemu/hostmem.h
@@ -27,7 +27,6 @@
 #define MEMORY_BACKEND_CLASS(klass) \
 OBJECT_CLASS_CHECK(HostMemoryBackendClass, (klass), TYPE_MEMORY_BACKEND)
 
-typedef struct HostMemoryBackend HostMemoryBackend;
 typedef struct HostMemoryBackendClass HostMemoryBackendClass;
 
 /**
diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c
index 6fefd65092..375f9a588a 100644
--- a/hw/mem/nvdimm.c
+++ b/hw/mem/nvdimm.c
@@ -30,6 +30,7 @@
 #include "hw/mem/nvdimm.h"
 #include "hw/qdev-properties.h"
 #include "hw/mem/memory-device.h"
+#include "sysemu/hostmem.h"
 
 static void nvdimm_get_label_size(Object *obj, Visitor *v, const char *name,
   void *opaque, Error **errp)
diff --git a/hw/virtio/virtio-pmem.c b/hw/virtio/virtio-pmem.c
index ff1a2ddb36..c0c9395e55 100644
--- a/hw/virtio/virtio-pmem.c
+++ b/hw/virtio/virtio-pmem.c
@@ -21,6 +21,7 @@
 #include "hw/virtio/virtio-access.h"
 #include "standard-headers/linux/virtio_ids.h"
 #include "standard-headers/linux/virtio_pmem.h"
+#include "sysemu/hostmem.h"
 #include "block/aio.h"
 #include "block/thread-pool.h"
 
-- 
2.21.0

[Qemu-devel] [PATCH v4 17/29] Include qom/object.h slightly less

[Markus Armbruster]

hw/hw.h used to include headers hardware emulation "usually" needs.
The previous commits removed all but one of them, to good effect.
Only qom/object.h is left.  Remove that one, too.

Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 include/hw/display/edid.h | 2 +-
 include/hw/hw.h   | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/hw/display/edid.h b/include/hw/display/edid.h
index 7948bd2c40..ff99dc0a05 100644
--- a/include/hw/display/edid.h
+++ b/include/hw/display/edid.h
@@ -1,7 +1,7 @@
 #ifndef EDID_H
 #define EDID_H
 
-#include "hw/hw.h"
+#include "qom/object.h"
 
 typedef struct qemu_edid_info {
 const char *vendor; /* http://www.uefi.org/pnp_id_list */
diff --git a/include/hw/hw.h b/include/hw/hw.h
index 8e18358e6a..8079b911fa 100644
--- a/include/hw/hw.h
+++ b/include/hw/hw.h
@@ -6,8 +6,6 @@
 #error Cannot include hw/hw.h from user emulation
 #endif
 
-#include "qom/object.h"
-
 void QEMU_NORETURN hw_error(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
 
 #endif
-- 
2.21.0

[Qemu-devel] [PATCH v4 13/29] Clean up inclusion of exec/cpu-common.h

[Markus Armbruster]

migration/qemu-file.h neglects to include it even though it needs
ram_addr_t.  Fix that.  Drop a few superfluous inclusions elsewhere.

Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 include/hw/hw.h | 1 -
 include/hw/ppc/ppc4xx.h | 1 -
 include/migration/misc.h| 1 -
 include/sysemu/kvm_int.h| 1 -
 include/sysemu/memory_mapping.h | 1 -
 migration/migration.h   | 1 -
 migration/qemu-file.h   | 1 +
 accel/stubs/tcg-stub.c  | 1 -
 balloon.c   | 1 -
 hw/smbios/smbios.c  | 1 -
 migration/qemu-file-channel.c   | 1 -
 migration/vmstate-types.c   | 1 -
 qom/cpu.c   | 1 -
 tcg/optimize.c  | 1 -
 tcg/tcg-common.c| 1 -
 tcg/tcg.c   | 1 -
 16 files changed, 1 insertion(+), 15 deletions(-)

diff --git a/include/hw/hw.h b/include/hw/hw.h
index 38d2fb1f40..86ff26b712 100644
--- a/include/hw/hw.h
+++ b/include/hw/hw.h
@@ -6,7 +6,6 @@
 #error Cannot include hw/hw.h from user emulation
 #endif
 
-#include "exec/cpu-common.h"
 #include "qom/object.h"
 #include "exec/memory.h"
 #include "migration/vmstate.h"
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 90f8866138..7d82259051 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -26,7 +26,6 @@
 #define PPC4XX_H
 
 #include "hw/ppc/ppc.h"
-#include "exec/cpu-common.h"
 #include "exec/memory.h"
 
 /* PowerPC 4xx core initialization */
diff --git a/include/migration/misc.h b/include/migration/misc.h
index 5cdbabd094..b9d8e787af 100644
--- a/include/migration/misc.h
+++ b/include/migration/misc.h
@@ -14,7 +14,6 @@
 #ifndef MIGRATION_MISC_H
 #define MIGRATION_MISC_H
 
-#include "exec/cpu-common.h"
 #include "qemu/notify.h"
 #include "qapi/qapi-types-net.h"
 
diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
index 787dbc7770..5d341cc29b 100644
--- a/include/sysemu/kvm_int.h
+++ b/include/sysemu/kvm_int.h
@@ -9,7 +9,6 @@
 #ifndef QEMU_KVM_INT_H
 #define QEMU_KVM_INT_H
 
-#include "exec/cpu-common.h"
 #include "exec/memory.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/accel.h"
diff --git a/include/sysemu/memory_mapping.h b/include/sysemu/memory_mapping.h
index 1b440df486..4b20f1a639 100644
--- a/include/sysemu/memory_mapping.h
+++ b/include/sysemu/memory_mapping.h
@@ -15,7 +15,6 @@
 #define MEMORY_MAPPING_H
 
 #include "qemu/queue.h"
-#include "exec/cpu-common.h"
 #include "exec/cpu-defs.h"
 #include "exec/memory.h"
 
diff --git a/migration/migration.h b/migration/migration.h
index 1fdd7b21fd..26f01d00f6 100644
--- a/migration/migration.h
+++ b/migration/migration.h
@@ -16,7 +16,6 @@
 
 #include "qapi/qapi-types-migration.h"
 #include "qemu/thread.h"
-#include "exec/cpu-common.h"
 #include "qemu/coroutine_int.h"
 #include "hw/qdev.h"
 #include "io/channel.h"
diff --git a/migration/qemu-file.h b/migration/qemu-file.h
index 13baf896bd..21f3ae4be2 100644
--- a/migration/qemu-file.h
+++ b/migration/qemu-file.h
@@ -26,6 +26,7 @@
 #define MIGRATION_QEMU_FILE_H
 
 #include 
+#include "exec/cpu-common.h"
 
 /* Read a chunk of data from a file at the given position.  The pos argument
  * can be ignored if the file is only be used for streaming.  The number of
diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
index 76ae461749..e2d23edafe 100644
--- a/accel/stubs/tcg-stub.c
+++ b/accel/stubs/tcg-stub.c
@@ -14,7 +14,6 @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "tcg/tcg.h"
-#include "exec/cpu-common.h"
 #include "exec/exec-all.h"
 
 void tb_flush(CPUState *cpu)
diff --git a/balloon.c b/balloon.c
index 914b3662db..f104b42961 100644
--- a/balloon.c
+++ b/balloon.c
@@ -26,7 +26,6 @@
 
 #include "qemu/osdep.h"
 #include "qemu/atomic.h"
-#include "exec/cpu-common.h"
 #include "sysemu/kvm.h"
 #include "sysemu/balloon.h"
 #include "trace-root.h"
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index 7bcd67b098..11d476c4a2 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -28,7 +28,6 @@
 #include "hw/firmware/smbios.h"
 #include "hw/loader.h"
 #include "hw/boards.h"
-#include "exec/cpu-common.h"
 #include "smbios_build.h"
 
 /* legacy structures and constants for <= 2.0 machines */
diff --git a/migration/qemu-file-channel.c b/migration/qemu-file-channel.c
index 8e639eb496..78ef248820 100644
--- a/migration/qemu-file-channel.c
+++ b/migration/qemu-file-channel.c
@@ -24,7 +24,6 @@
 
 #include "qemu/osdep.h"
 #include "qemu-file-channel.h"
-#include "exec/cpu-common.h"
 #include "qemu-file.h"
 #include "io/channel-socket.h"
 #include "qemu/iov.h"
diff --git a/migration/vmstate-types.c b/migration/vmstate-types.c
index 845f4649ee..bee658a1b2 100644
--- a/migration/vmstate-types.c
+++ b/migration/vmstate-types.c
@@ -11,7 +11,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "exec/cpu-common.h"
 #include "qemu-file.h"
 #include "migration.h"
 #include "migration/vmstate.h"
diff --git 

[Qemu-devel] [PATCH v4 05/29] queue: Drop superfluous #include qemu/atomic.h

[Markus Armbruster]

When commit 5f7d05ecfda added QLIST_INSERT_HEAD_RCU() to qemu/queue.h,
it had to include qemu/atomic.h.  Commit 341774fe6cc removed
QLIST_INSERT_HEAD_RCU() again, but neglected to remove the #include.
Do that now.

Signed-off-by: Markus Armbruster 
Reviewed-by: Thomas Huth 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
Reviewed-by: Alex Bennée 
---
 include/qemu/queue.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/qemu/queue.h b/include/qemu/queue.h
index 0379bd8fdb..73bf4a984d 100644
--- a/include/qemu/queue.h
+++ b/include/qemu/queue.h
@@ -78,8 +78,6 @@
  * For details on the use of these macros, see the queue(3) manual page.
  */
 
-#include "qemu/atomic.h" /* for smp_wmb() */
-
 /*
  * List definitions.
  */
-- 
2.21.0

[Qemu-devel] [PATCH v4 02/29] Include generated QAPI headers less

[Markus Armbruster]

Some of the generated qapi-types-MODULE.h are included all over the
place.  Changing a QAPI type can trigger massive recompiling.  Top
scorers recompile more than 1000 out of some 6600 objects (not
counting tests and objects that don't depend on qemu/osdep.h):

6300 qapi/qapi-builtin-types.h
5700 qapi/qapi-types-run-state.h
3900 qapi/qapi-types-common.h
3300 qapi/qapi-types-sockets.h
3000 qapi/qapi-types-misc.h
3000 qapi/qapi-types-crypto.h
3000 qapi/qapi-types-job.h
3000 qapi/qapi-types-block-core.h
2800 qapi/qapi-types-block.h
1300 qapi/qapi-types-net.h

Clean up headers to include generated QAPI headers only where needed.
Impact is negligible except for hw/qdev-properties.h.

This header includes qapi/qapi-types-block.h and
qapi/qapi-types-misc.h.  They are used only in expansions of property
definition macros such as DEFINE_PROP_BLOCKDEV_ON_ERROR() and
DEFINE_PROP_OFF_AUTO().  Moving their inclusion from
hw/qdev-properties.h to the users of these macros avoids pointless
recompiles.  This is how other property definition macros, such as
DEFINE_PROP_NETDEV(), already work.

Improves things for some of the top scorers:

3600 qapi/qapi-types-common.h
2800 qapi/qapi-types-sockets.h
 900 qapi/qapi-types-misc.h
2200 qapi/qapi-types-crypto.h
2100 qapi/qapi-types-job.h
2100 qapi/qapi-types-block-core.h
 270 qapi/qapi-types-block.h

Signed-off-by: Markus Armbruster 
Reviewed-by: Eric Blake 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 include/authz/listfile.h | 1 -
 include/block/block.h| 1 -
 include/hw/acpi/acpi_dev_interface.h | 1 +
 include/hw/mem/memory-device.h   | 1 +
 include/hw/ppc/spapr_drc.h   | 1 -
 include/hw/qdev-properties.h | 2 --
 include/hw/virtio/virtio-pmem.h  | 1 +
 include/migration/global_state.h | 1 -
 include/qemu/job.h   | 2 +-
 include/sysemu/arch_init.h   | 1 -
 include/ui/egl-helpers.h | 1 -
 monitor/monitor-internal.h   | 1 -
 target/i386/sev_i386.h   | 2 +-
 ui/vnc.h | 1 -
 hw/core/qdev-properties.c| 2 ++
 hw/i386/kvm/i8254.c  | 1 +
 hw/ide/qdev.c| 1 +
 target/i386/monitor.c| 1 +
 18 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/include/authz/listfile.h b/include/authz/listfile.h
index 33b728d873..24ae2e606c 100644
--- a/include/authz/listfile.h
+++ b/include/authz/listfile.h
@@ -22,7 +22,6 @@
 #define QAUTHZ_LISTFILE_H
 
 #include "authz/list.h"
-#include "qapi/qapi-types-authz.h"
 #include "qemu/filemonitor.h"
 
 #define TYPE_QAUTHZ_LIST_FILE "authz-list-file"
diff --git a/include/block/block.h b/include/block/block.h
index 50a07c1c33..ae79b70e2d 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -2,7 +2,6 @@
 #define BLOCK_H
 
 #include "block/aio.h"
-#include "qapi/qapi-types-block-core.h"
 #include "block/aio-wait.h"
 #include "qemu/iov.h"
 #include "qemu/coroutine.h"
diff --git a/include/hw/acpi/acpi_dev_interface.h 
b/include/hw/acpi/acpi_dev_interface.h
index 43ff119179..6465072b7d 100644
--- a/include/hw/acpi/acpi_dev_interface.h
+++ b/include/hw/acpi/acpi_dev_interface.h
@@ -1,6 +1,7 @@
 #ifndef ACPI_DEV_INTERFACE_H
 #define ACPI_DEV_INTERFACE_H
 
+#include "qapi/qapi-types-misc.h"
 #include "qom/object.h"
 #include "hw/boards.h"
 
diff --git a/include/hw/mem/memory-device.h b/include/hw/mem/memory-device.h
index 0293a96abb..2ada6e7bde 100644
--- a/include/hw/mem/memory-device.h
+++ b/include/hw/mem/memory-device.h
@@ -13,6 +13,7 @@
 #ifndef MEMORY_DEVICE_H
 #define MEMORY_DEVICE_H
 
+#include "qapi/qapi-types-misc.h"
 #include "qom/object.h"
 #include "hw/qdev.h"
 
diff --git a/include/hw/ppc/spapr_drc.h b/include/hw/ppc/spapr_drc.h
index c2c543a591..576c711b86 100644
--- a/include/hw/ppc/spapr_drc.h
+++ b/include/hw/ppc/spapr_drc.h
@@ -14,7 +14,6 @@
 #define HW_SPAPR_DRC_H
 
 #include 
-#include "qapi/qapi-types-run-state.h"
 #include "qom/object.h"
 #include "sysemu/sysemu.h"
 #include "hw/qdev.h"
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 1eae5ab056..bb34a614e2 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -1,8 +1,6 @@
 #ifndef QEMU_QDEV_PROPERTIES_H
 #define QEMU_QDEV_PROPERTIES_H
 
-#include "qapi/qapi-types-block.h"
-#include "qapi/qapi-types-misc.h"
 #include "hw/qdev-core.h"
 
 /*** qdev-properties.c ***/
diff --git a/include/hw/virtio/virtio-pmem.h b/include/hw/virtio/virtio-pmem.h
index 19b6ee6d75..8bf2ae780f 100644
--- a/include/hw/virtio/virtio-pmem.h
+++ b/include/hw/virtio/virtio-pmem.h
@@ -15,6 +15,7 @@
 #define HW_VIRTIO_PMEM_H
 
 #include "hw/virtio/virtio.h"
+#include "qapi/qapi-types-misc.h"
 #include "sysemu/hostmem.h"
 
 #define TYPE_VIRTIO_PMEM "virtio-pmem"
diff --git a/include/migration/global_state.h b/include/migration/global_state.h
index 

[Qemu-devel] [PATCH v4 10/29] ide: Include hw/ide/internal a bit less outside hw/ide/

[Markus Armbruster]

According to hw/ide/internal's file comment, only files in hw/ide/ are
supposed to include it.  Drag reality slightly closer to supposition.

Three includes outside hw/ide remain: hw/arm/sbsa-ref.c,
include/hw/ide/pci.h, and include/hw/misc/macio/macio.h.  Turns out
board code needs ide-internal.h to wire up IDE stuff.  More cleanup is
needed.  Left for another day.

Cc: John Snow 
Signed-off-by: Markus Armbruster 
Reviewed-by: John Snow 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 hw/ide/ahci_internal.h | 1 +
 hw/ppc/mac.h   | 1 -
 include/hw/arm/allwinner-a10.h | 1 -
 include/hw/arm/xlnx-zynqmp.h   | 1 -
 include/hw/misc/mos6522.h  | 1 -
 hw/arm/allwinner-a10.c | 1 +
 hw/arm/cubieboard.c| 1 +
 hw/arm/xlnx-zynqmp.c   | 1 +
 8 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h
index 95ecddcd3c..73424516da 100644
--- a/hw/ide/ahci_internal.h
+++ b/hw/ide/ahci_internal.h
@@ -25,6 +25,7 @@
 #define HW_IDE_AHCI_INTERNAL_H
 
 #include "hw/ide/ahci.h"
+#include "hw/ide/internal.h"
 #include "hw/sysbus.h"
 
 #define AHCI_MEM_BAR_SIZE 0x1000
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index a741300ac9..6af87d1fa0 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -30,7 +30,6 @@
 #include "exec/memory.h"
 #include "hw/boards.h"
 #include "hw/sysbus.h"
-#include "hw/ide/internal.h"
 #include "hw/input/adb.h"
 #include "hw/misc/mos6522.h"
 #include "hw/pci/pci_host.h"
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index 7182ce5c4b..101b72a71d 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -7,7 +7,6 @@
 #include "hw/timer/allwinner-a10-pit.h"
 #include "hw/intc/allwinner-a10-pic.h"
 #include "hw/net/allwinner_emac.h"
-#include "hw/ide/pci.h"
 #include "hw/ide/ahci.h"
 
 #include "sysemu/sysemu.h"
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 6cb65e7537..d7483c3b42 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,7 +22,6 @@
 #include "hw/intc/arm_gic.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/char/cadence_uart.h"
-#include "hw/ide/pci.h"
 #include "hw/ide/ahci.h"
 #include "hw/sd/sdhci.h"
 #include "hw/ssi/xilinx_spips.h"
diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h
index 03d9f0c059..493c907537 100644
--- a/include/hw/misc/mos6522.h
+++ b/include/hw/misc/mos6522.h
@@ -29,7 +29,6 @@
 
 #include "exec/memory.h"
 #include "hw/sysbus.h"
-#include "hw/ide/internal.h"
 #include "hw/input/adb.h"
 
 /* Bits in ACR */
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 35e906ca54..3b0d3eccdd 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -16,6 +16,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "exec/address-spaces.h"
 #include "qapi/error.h"
 #include "qemu/module.h"
 #include "cpu.h"
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index f7c8a5985a..38e0ca0f53 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -16,6 +16,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "exec/address-spaces.h"
 #include "qapi/error.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index a60830d37a..0f587e63d3 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -24,6 +24,7 @@
 #include "hw/boards.h"
 #include "exec/address-spaces.h"
 #include "sysemu/kvm.h"
+#include "sysemu/sysemu.h"
 #include "kvm_arm.h"
 
 #define GIC_NUM_SPI_INTR 160
-- 
2.21.0

[Qemu-devel] [PATCH v4 04/29] memory: Fix type of IOMMUMemoryRegionClass member @parent_class

[Markus Armbruster]

TYPE_IOMMU_MEMORY_REGION is a direct subtype of TYPE_MEMORY_REGION.
Its instance struct is IOMMUMemoryRegion, and its first member is a
MemoryRegion.  Correct.  Its class struct is IOMMUMemoryRegionClass,
and its first member is a DeviceClass.  Wrong.  Messed up when commit
1221a474676 introduced the QOM type.  It even included hw/qdev-core.h
just for that.

TYPE_MEMORY_REGION doesn't bother to define a class struct.  This is
fine, it simply defaults to its super-type TYPE_OBJECT's class struct
ObjectClass.  Changing IOMMUMemoryRegionClass's first member's type to
ObjectClass would be a minimal fix, if a bit brittle: if
TYPE_MEMORY_REGION ever acquired own class struct, we'd have to update
IOMMUMemoryRegionClass to use it.

Fix it the clean and robust way instead: give TYPE_MEMORY_REGION its
own class struct MemoryRegionClass now, and use it for
IOMMUMemoryRegionClass's first member.

Revert the include of hw/qdev-core.h, and fix the few files that have
come to rely on it.

Cc: Paolo Bonzini 
Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
Acked-by: Paolo Bonzini 
---
 hw/net/pcnet.h  |  1 +
 include/exec/memory.h   | 10 --
 hw/display/vga-isa-mm.c |  1 +
 memory.c|  1 +
 4 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/hw/net/pcnet.h b/hw/net/pcnet.h
index 40831a7845..28d19a5c6f 100644
--- a/hw/net/pcnet.h
+++ b/hw/net/pcnet.h
@@ -8,6 +8,7 @@
 #define PCNET_LOOPTEST_NOCRC   2
 
 #include "exec/memory.h"
+#include "hw/irq.h"
 
 /* BUS CONFIGURATION REGISTERS */
 #define BCR_MSRDA0
diff --git a/include/exec/memory.h b/include/exec/memory.h
index bb0961ddb9..d99eb25d2e 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -20,12 +20,12 @@
 #include "exec/hwaddr.h"
 #include "exec/memattrs.h"
 #include "exec/ramlist.h"
+#include "qemu/bswap.h"
 #include "qemu/queue.h"
 #include "qemu/int128.h"
 #include "qemu/notify.h"
 #include "qom/object.h"
 #include "qemu/rcu.h"
-#include "hw/qdev-core.h"
 
 #define RAM_ADDR_INVALID (~(ram_addr_t)0)
 
@@ -205,6 +205,12 @@ struct MemoryRegionOps {
 } impl;
 };
 
+typedef struct MemoryRegionClass {
+/* private */
+ObjectClass parent_class;
+} MemoryRegionClass;
+
+
 enum IOMMUMemoryRegionAttr {
 IOMMU_ATTR_SPAPR_TCE_FD
 };
@@ -237,7 +243,7 @@ enum IOMMUMemoryRegionAttr {
  */
 typedef struct IOMMUMemoryRegionClass {
 /* private */
-struct DeviceClass parent_class;
+MemoryRegionClass parent_class;
 
 /*
  * Return a TLB entry that contains a given address.
diff --git a/hw/display/vga-isa-mm.c b/hw/display/vga-isa-mm.c
index 215e649719..a790f69b6d 100644
--- a/hw/display/vga-isa-mm.c
+++ b/hw/display/vga-isa-mm.c
@@ -22,6 +22,7 @@
  * THE SOFTWARE.
  */
 #include "qemu/osdep.h"
+#include "qemu/bitops.h"
 #include "qemu/units.h"
 #include "hw/hw.h"
 #include "hw/display/vga.h"
diff --git a/memory.c b/memory.c
index 5d8c9a9234..09d9b254fd 100644
--- a/memory.c
+++ b/memory.c
@@ -3245,6 +3245,7 @@ void memory_region_init_rom_device(MemoryRegion *mr,
 static const TypeInfo memory_region_info = {
 .parent = TYPE_OBJECT,
 .name   = TYPE_MEMORY_REGION,
+.class_size = sizeof(MemoryRegionClass),
 .instance_size  = sizeof(MemoryRegion),
 .instance_init  = memory_region_initfn,
 .instance_finalize  = memory_region_finalize,
-- 
2.21.0

[Qemu-devel] [PATCH v4 03/29] qapi: Split error.json off common.json

[Markus Armbruster]

In my "build everything" tree, changing a type in qapi/common.json
triggers a recompile of some 3600 out of 6600 objects (not counting
tests and objects that don't depend on qemu/osdep.h).

One common dependency is QapiErrorClass: it's used only in in
qapi/error.h, which uses nothing else, and is widely included.

Move QapiErrorClass from common.json to new error.json.  Touching
common.json now recompiles only some 2900 objects.

Cc: Eric Blake 
Signed-off-by: Markus Armbruster 
Reviewed-by: Eric Blake 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 qapi/common.json  | 24 
 qapi/error.json   | 29 +
 qapi/qapi-schema.json |  1 +
 include/qapi/error.h  |  2 +-
 MAINTAINERS   |  2 ++
 qapi/Makefile.objs|  2 +-
 6 files changed, 34 insertions(+), 26 deletions(-)
 create mode 100644 qapi/error.json

diff --git a/qapi/common.json b/qapi/common.json
index 99d313ef3b..3d4e8de1e0 100644
--- a/qapi/common.json
+++ b/qapi/common.json
@@ -4,30 +4,6 @@
 # = Common data types
 ##
 
-##
-# @QapiErrorClass:
-#
-# QEMU error classes
-#
-# @GenericError: this is used for errors that don't require a specific error
-#class. This should be the default case for most errors
-#
-# @CommandNotFound: the requested command has not been found
-#
-# @DeviceNotActive: a device has failed to be become active
-#
-# @DeviceNotFound: the requested device has not been found
-#
-# @KVMMissingCap: the requested operation can't be fulfilled because a
-# required KVM capability is missing
-#
-# Since: 1.2
-##
-{ 'enum': 'QapiErrorClass',
-  # Keep this in sync with ErrorClass in error.h
-  'data': [ 'GenericError', 'CommandNotFound',
-'DeviceNotActive', 'DeviceNotFound', 'KVMMissingCap' ] }
-
 ##
 # @IoOperationType:
 #
diff --git a/qapi/error.json b/qapi/error.json
new file mode 100644
index 00..3fad08f506
--- /dev/null
+++ b/qapi/error.json
@@ -0,0 +1,29 @@
+# -*- Mode: Python -*-
+
+##
+# = QMP errors
+##
+
+##
+# @QapiErrorClass:
+#
+# QEMU error classes
+#
+# @GenericError: this is used for errors that don't require a specific error
+#class. This should be the default case for most errors
+#
+# @CommandNotFound: the requested command has not been found
+#
+# @DeviceNotActive: a device has failed to be become active
+#
+# @DeviceNotFound: the requested device has not been found
+#
+# @KVMMissingCap: the requested operation can't be fulfilled because a
+# required KVM capability is missing
+#
+# Since: 1.2
+##
+{ 'enum': 'QapiErrorClass',
+  # Keep this in sync with ErrorClass in error.h
+  'data': [ 'GenericError', 'CommandNotFound',
+'DeviceNotActive', 'DeviceNotFound', 'KVMMissingCap' ] }
diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json
index 38af54d6b3..920b03b0aa 100644
--- a/qapi/qapi-schema.json
+++ b/qapi/qapi-schema.json
@@ -80,6 +80,7 @@
 # stable order, it's best to include each sub-schema just once, or
 # include it first right here.
 
+{ 'include': 'error.json' }
 { 'include': 'common.json' }
 { 'include': 'sockets.json' }
 { 'include': 'run-state.json' }
diff --git a/include/qapi/error.h b/include/qapi/error.h
index 51b63dd4b5..3f95141a01 100644
--- a/include/qapi/error.h
+++ b/include/qapi/error.h
@@ -119,7 +119,7 @@
 #ifndef ERROR_H
 #define ERROR_H
 
-#include "qapi/qapi-types-common.h"
+#include "qapi/qapi-types-error.h"
 
 /*
  * Overall category of an error.
diff --git a/MAINTAINERS b/MAINTAINERS
index d6de200453..adc64cfe33 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1874,6 +1874,7 @@ M: Markus Armbruster 
 S: Supported
 F: include/qapi/error.h
 F: include/qemu/error-report.h
+F: qapi/error.json
 F: util/error.c
 F: util/qemu-error.c
 
@@ -2062,6 +2063,7 @@ F: monitor/monitor-internal.h
 F: monitor/qmp*
 F: monitor/misc.c
 F: monitor/monitor.c
+F: qapi/error.json
 F: docs/devel/*qmp-*
 F: docs/interop/*qmp-*
 F: scripts/qmp/
diff --git a/qapi/Makefile.objs b/qapi/Makefile.objs
index c5a29e86e2..dd3f5e6f94 100644
--- a/qapi/Makefile.objs
+++ b/qapi/Makefile.objs
@@ -6,7 +6,7 @@ util-obj-y += qmp-event.o
 util-obj-y += qapi-util.o
 
 QAPI_COMMON_MODULES = audio authz block-core block char common crypto
-QAPI_COMMON_MODULES += dump introspect job machine migration misc net
+QAPI_COMMON_MODULES += dump error introspect job machine migration misc net
 QAPI_COMMON_MODULES += qdev qom rdma rocker run-state sockets tpm
 QAPI_COMMON_MODULES += trace transaction ui
 QAPI_TARGET_MODULES = machine-target misc-target
-- 
2.21.0

[Qemu-devel] [PATCH v4 11/29] typedefs: Separate incomplete types and function types

[Markus Armbruster]

While there, drop the obsolete file comment.

Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
---
 include/qemu/typedefs.h | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index fcdaae58c4..29346648d4 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -1,10 +1,10 @@
 #ifndef QEMU_TYPEDEFS_H
 #define QEMU_TYPEDEFS_H
 
-/* A load of opaque types so that device init declarations don't have to
-   pull in all the real definitions.  */
-
-/* Please keep this list in case-insensitive alphabetical order */
+/*
+ * Incomplete struct types
+ * Please keep this list in case-insensitive alphabetical order.
+ */
 typedef struct AdapterInfo AdapterInfo;
 typedef struct AddressSpace AddressSpace;
 typedef struct AioContext AioContext;
@@ -101,6 +101,10 @@ typedef struct SHPCDevice SHPCDevice;
 typedef struct SSIBus SSIBus;
 typedef struct VirtIODevice VirtIODevice;
 typedef struct Visitor Visitor;
+
+/*
+ * Function types
+ */
 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
 
-- 
2.21.0

[Qemu-devel] [PATCH v4 06/29] trace: Eliminate use of TARGET_FMT_plx

[Markus Armbruster]

hw/tpm/trace-events uses TARGET_FMT_plx formats with uint64_t
arguments.  That's wrong, TARGET_FMT_plx takes hwaddr.  Since hwaddr
happens to be uint64_t, it works anyway.  Messed up in commit
ec427498da5, v2.12.0.  Clean up by replacing TARGET_FMT_plx with its
macro expansion.

scripts/tracetool/format/log_stap.py (commit 62dd1048c0b, v4.0.0) has
a special case for TARGET_FMT_plx.  Delete it.

Cc: Stefan Hajnoczi 
Signed-off-by: Markus Armbruster 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: Philippe Mathieu-Daudé 
Reviewed-by: Stefan Hajnoczi 
---
 hw/tpm/trace-events  | 4 ++--
 scripts/tracetool/format/log_stap.py | 3 ---
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/hw/tpm/trace-events b/hw/tpm/trace-events
index 0b94aa1526..89804bcd64 100644
--- a/hw/tpm/trace-events
+++ b/hw/tpm/trace-events
@@ -1,8 +1,8 @@
 # See docs/devel/tracing.txt for syntax documentation.
 
 # tpm_crb.c
-tpm_crb_mmio_read(uint64_t addr, unsigned size, uint32_t val) "CRB read 0x" 
TARGET_FMT_plx " len:%u val: 0x%" PRIx32
-tpm_crb_mmio_write(uint64_t addr, unsigned size, uint32_t val) "CRB write 0x" 
TARGET_FMT_plx " len:%u val: 0x%" PRIx32
+tpm_crb_mmio_read(uint64_t addr, unsigned size, uint32_t val) "CRB read 
0x%016" PRIx64 " len:%u val: 0x%" PRIx32
+tpm_crb_mmio_write(uint64_t addr, unsigned size, uint32_t val) "CRB write 
0x%016" PRIx64 " len:%u val: 0x%" PRIx32
 
 # tpm_passthrough.c
 tpm_passthrough_handle_request(void *cmd) "processing command %p"
diff --git a/scripts/tracetool/format/log_stap.py 
b/scripts/tracetool/format/log_stap.py
index 3ccbc09d61..9ab0cf2cce 100644
--- a/scripts/tracetool/format/log_stap.py
+++ b/scripts/tracetool/format/log_stap.py
@@ -30,9 +30,6 @@ def c_macro_to_format(macro):
 if macro.startswith("PRI"):
 return macro[3]
 
-if macro == "TARGET_FMT_plx":
-return "%016x"
-
 raise Exception("Unhandled macro '%s'" % macro)
 
 def c_fmt_to_stap(fmt):
-- 
2.21.0

Re: [Qemu-devel] [PATCH v9 09/11] numa: Extend the CLI to provide memory latency and bandwidth information

[Daniel Black]

Tao Xu, Liu Jingqi,

Thanks for doing these updates.

On Fri,  9 Aug 2019 14:57:29 +0800
Tao  wrote:

> From: Liu Jingqi 
> 
> Add -numa hmat-lb option to provide System Locality Latency and
> Bandwidth Information. These memory attributes help to build
> System Locality Latency and Bandwidth Information Structure(s)
> in ACPI Heterogeneous Memory Attribute Table (HMAT).
> 
> Signed-off-by: Liu Jingqi 
> Signed-off-by: Tao Xu 
> ---
>  hw/acpi/hmat.h|   3 +
>  hw/core/numa.c| 185
> ++ include/sysemu/numa.h |
> 2 + qapi/machine.json |  95 +-
>  qemu-options.hx   |  44 +-
>  5 files changed, 326 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h
> index 6c32f12e78..b7c1e02cf0 100644
> --- a/hw/acpi/hmat.h
> +++ b/hw/acpi/hmat.h
> @@ -42,6 +42,9 @@
>  
>  #define HMAT_IS_LATENCY(type) (type <= HMAT_LB_DATA_WRITE_LATENCY)
>  
> +#define PICO_PER_USEC 100
> +#define PICO_PER_NSEC 1000
> +
>  struct HMAT_LB_Info {
>  /*
>   * Indicates total number of Proximity Domains
> diff --git a/hw/core/numa.c b/hw/core/numa.c
> index cfb6339810..9a494145f3 100644
> --- a/hw/core/numa.c
> +++ b/hw/core/numa.c
> @@ -37,6 +37,7 @@
>  #include "qemu/option.h"
>  #include "qemu/config-file.h"
>  #include "qemu/cutils.h"
> +#include "hw/acpi/hmat.h"
>  
>  QemuOptsList qemu_numa_opts = {
>  .name = "numa",
> @@ -183,6 +184,184 @@ void parse_numa_distance(MachineState *ms,
> NumaDistOptions *dist, Error **errp)
> ms->numa_state->have_numa_distance = true; }
>  
> +void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
> +Error **errp)
> +{
..

Optional; you could support not connected (0x) for latency/bandwidth in
this parsing.

> +if (*endptr == '\0') {
> +base_lat = 1;
> +} else if (*(endptr + 1) == 's') {
> +switch (*endptr) {
> +case 'p':
> +base_lat = 1;
> +break;
> +case 'n':
> +base_lat = PICO_PER_NSEC;
> +break;
> +case 'u':

Glad you picked up my mismatch of "u/micro".

> +} else {
> +error_setg(errp, "Invalid latency unit %s,"
> +"vaild units are \"ps\" \"ns\" \"us\"",
>node->latency);

typo "valid"

> +} else if (hmat_lb->base_lat != base_lat) {
> +error_setg(errp, "Invalid latency unit %s,"
> +" please unify the units.", node->latency);

This error is misleading. Should be something like "all latencies must be
specified in the same units"

> +switch (toupper(*endptr)) {
> +case '\0':
> +case 'M':
> +base_bw = 1;
> +break;
> +case 'G':
> +base_bw = UINT64_C(1) << 10;
> +break;

There was one more gap - Terra.

case 'T':
   base_bw = UINT64_C(1) << 20;
   break;

> +case 'P':
> +base_bw = UINT64_C(1) << 20;
and:
   base_bw = UINT64_C(1) << 30;

> +break;
> +}


Currently Linux 5.3.0-rc3+ doesn't cope with real corrected "bandwidth=2P" so
maybe not worth it.

[2.092060] HMAT: Locality: Flags:00 Type:Access Bandwidth Initiator
Domains:1 Target Domains:2 Base:1073741824 [2.092326]   
Initiator-Target[0-0]:-2147483648 MB/s

On values, testing for overflow is required. e.g:

 -numa 
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=4096T
bandwidth=4096T

[2.047676] HMAT: Locality: Flags:00 Type:Access Bandwidth Initiator 
Domains:1 Target Domains:2 Base:1048576
[2.048084]   Initiator-Target[0-0]:0 MB/s

Technically ACPI could support up to 4P with base/offset but you'd need to be a
lot trickier (i.e. base is highest common multiple of all entries and then see
if entry/base > 2^32-2 ) with base/entry values to arrive at this number.

+docs/commit message propagation of this.


> +} else if (hmat_lb->base_lat != base_lat) {

Bug: Incorrectly copied - base_lat should be base_bw (twice)

> +error_setg(errp, "Invalid bandwidth unit %s,"
> +" please unify the units.", node->bandwidth);

This error is misleading. Should be something like "all bandwidths must be
specified in the same units"

> diff --git a/qemu-options.hx b/qemu-options.hx
> index c480781992..cda4607f3a 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx

> +@example
> +-m 2G \
> +-object memory-backend-ram,size=1024M,policy=bind,host-nodes=0,id=ram-node0 
> -numa node,nodeid=0,memdev=ram-node0 \
> +-object memory-backend-ram,size=1024M,policy=bind,host-nodes=1,id=ram-node1 
> -numa node,nodeid=1,memdev=ram-node1 \
> +-smp 2 \
> +-numa cpu,node-id=0,socket-id=0 \
> +-numa cpu,node-id=0,socket-id=1 \
> +-numa 
> hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=5ns
>  \
> +-numa 
> 

Re: [Qemu-devel] [RFC PATCH 0/6] Enhancing Qemu MMIO emulation with scripting interface

[Balamuruhan S]

On 8/9/19 10:19 AM, David Gibson wrote:
> On Wed, Aug 07, 2019 at 10:15:48AM +0200, Cédric Le Goater wrote:
>> On 07/08/2019 09:14, Balamuruhan S wrote:
>>> Hi All,
>>>
>>> This is a proposal to extend mmio callbacks in Qemu with scripting interface
>>> that is prototyped with python in this implementation. It gives ability to
>>> feed runtime data through callbacks without recompiling Qemu in generic way.
>>> This patchset adds library that provides APIs for Qemu to talk with python
>>> scripts placed in path -module-path and how existing xscom can be extended
>>> with python interface infrastructure.
>>>
>>> We have also added an hacky emulation for memory region (OCC common area 
>>> and HOMER)
>>> which is shared between core and un-core engine (ideally this should be via
>>> sram device) to showcase the effectiveness of having the scripting interface
>>> (uncore engine taken for discussion here is powerpc specificed called OCC).
>> We should try to merge this part first. It is useful as it is after some
>> cleanups.
>>
>>> Having scripting interface helps to emulate/test different uncore-core
>>> interactions including uncore engine failure or hang. It also helps in 
>>> feeding
>>> randomized data at byte level access. This patchset is primarily to extend 
>>> mmio
>>> callbacks with scripting interface and to demonstrate effectiveness it.
>> It is already possible to feed device models with external data using QMP or
>> external agents using a chardev backend transport. What are the benefits
>> of using the embedded python approach ?  
> Yeah, I also think this needs better justification.
>
> In particular what's the case that Python makes this significantly
> easier than hacking up experimental interactions with C.  I mean you
> already have to understand POWER9 internals to work with this, right,
> so I wouldn't expect Python's greater accessibility to be a big
> concern here.

right, with python interface what I could think of is,

1. we don't have to patch up every experimental interactions and recompile.
2. we can easily feed in invalid data type to see the behavior for 
negative/error
   scenarios.
3. Similar to qtest and acceptance test we can use this to cover many scenarios.
4. Ease the CI and maintenance to have test/code separately.

>

Re: [Qemu-devel] [RFC PATCH 1/6] utils/python_api: add scripting interface for Qemu with python lib

[Balamuruhan S]

On 8/9/19 2:16 PM, Stefan Hajnoczi wrote:
> On Thu, Aug 08, 2019 at 11:53:07AM +0100, Daniel P. Berrangé wrote:
>> On Thu, Aug 08, 2019 at 11:10:13AM +0100, Stefan Hajnoczi wrote:
>>> On Wed, Aug 07, 2019 at 12:20:47PM +0200, Philippe Mathieu-Daudé wrote:
> +void python_args_clean(char *args[], int nargs)
> +{
> +for (int i = 0; i < nargs; i++) {
> +g_free(args[i]);
> +}
> +}
>
 Wondering about security, is this feature safe to enable in production
 environment? It seems to bypass all the hard effort to harden QEMU 
 security.
>>> This seems like a feature that distros would not enable.  Only users
>>> building QEMU from source could enable it.
>> Well that's true when this scripting is only used from one obscure ppc
>> device. Once merged though, its inevitable that people will want to
>> extend scripting to more & more parts of QEMU code. This is a big can
>> of worms...
> When it gets used in new contexts it will be necessary to address
> problems or accept that it is unsuitable for those use cases.  Starting
> simple and dealing with challenges as and when necessary seems okay to
> me.
>
> I think we should give features a chance in QEMU if there is a
> maintainer to support them.  I don't want to use this feature myself and
> I see lots of issues with it for my use cases, but if it is compiled out
> and doesn't place many requirements on code that does not use it, let's
> give it a chance.
>
> My main concern is licensing.  I think the QEMU Python API should be GPL
> licensed because these scripts are executing as part of the QEMU
> process.
>
> Beyond that, let's see if people find this feature useful.  Maybe it
> will die and be removed, maybe it will become popular and we'll have to
> change our perspective :).

Thank you all for review and sharing the thoughts :) 

>
> Stefan

Re: [Qemu-devel] [RFC PATCH 1/6] utils/python_api: add scripting interface for Qemu with python lib

[Balamuruhan S]

On 8/8/19 6:15 PM, Philippe Mathieu-Daudé wrote:
> On 8/8/19 12:49 PM, Daniel P. Berrangé wrote:
>> On Wed, Aug 07, 2019 at 12:44:40PM +0530, Balamuruhan S wrote:
>>> Adds scripting interface with python library to call functions in
>>> python modules from Qemu that can be used to feed input externally
>>> and without recompiling Qemu that can be used for early development,
>>> testing and can be extended to abstract some of Qemu code out to a
>>> python script to ease maintenance.
>> I admit the use case is interesting, but this is opening a can of
>> worms...
>>
>> Historically the project has held the view that we do not wish
>> to have an mechanism to support loading out of tree code into the
>> QEMU process. Much previously talk was around dlopen'd C plugins,
>> but dynanically loaded Python plugins are doing the same thing
>> at a conceptual level.
>>
>> We didn't wish to expose internals of QEMU in a plugin API to
>> avoid having any kind of API promise across releases.
>>
>> There was also the question of licensing with plugins opening
>> the door for people to extend QEMU with non-free/closed source
>> functionality.
>>
>> While this series only uses the plugin for one fairly obscure
>> device, once a python plugin feature is intergrated in QEMU
>> there will inevitably be requests to use it in further areas
>> of QEMU.
>>
>> IOW, acceptance of this patch is a significant question for
>> the project, and a broader discussion point, than just this
>> PPC feature patch series.
> Since performance is not an issue, we can use a QMP-PyMMIO bridge.
> Most of the functions required are already exposed, Damien completed the
> missing ones in his 'FAULT INJECTION FRAMEWORK' series:
> https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg06230.html

will look at this approach and try using QMP-PyMMIO bridge.

Thank you all for review and suggestions.

>
> Maybe we simply need a clearer (better documented) QMP 'MMIO' API?
>

Re: [Qemu-devel] [Fail] tests/test-util-filemonitor fails

[Wei Yang]

On Fri, Aug 09, 2019 at 10:12:14AM +0100, Daniel P. Berrangé wrote:
>On Fri, Aug 09, 2019 at 08:06:09AM +0800, Wei Yang wrote:
>> On Thu, Aug 08, 2019 at 10:22:13AM +0100, Daniel P. Berrangé wrote:
>> >On Thu, Aug 08, 2019 at 04:46:53PM +0800, Wei Yang wrote:
>> >> On Thu, Aug 08, 2019 at 09:02:29AM +0100, Daniel P. Berrangé wrote:
>> >> >On Thu, Aug 08, 2019 at 10:07:23AM +0800, Wei Yang wrote:
>> >> >> Current qemu fails tests/test-util-filemonitor.
>> >> >
>> >> >You'll need to provide more info. The test works for me and passes in all
>> >> >the QEMU CI environments.
>> >> >
>> >> 
>> >> The error message from my side is:
>> >> 
>> >> /util/filemonitor: Expected watch id 2 but got 1
>> >> **
>> >> ERROR:tests/test-util-filemonitor.c:665:test_file_monitor_events: 
>> >> assertion failed: (err == 0)
>> >> 
>> >> What else you'd prefer to have?
>> >
>> >Can you set the  "FILEMONITOR_DEBUG=1" env variable before running
>> >the test - it will print out lots more info
>> >
>> 
>> Here is the output with more info.
>> 
>> $ FILEMONITOR_DEBUG=1 
>> QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 
>> tests/test-util-filemonitor
>
>> Rmdir /tmp/test-util-filemonitor-151B6Z/fish
>> Event id=2 event=4 file=
>> Expected watch id 2 but got 1
>> **
>
>Ok, so the kernel is sending the events in an unexpected order
>
>> ERROR:tests/test-util-filemonitor.c:665:test_file_monitor_events: 
>> assertion failed: (err == 0)
>> Aborted (core dumped)
>> 
>> 
>> >Also what operating system are you using, and what kernel version
>> >
>> 
>> OS: Ubuntu 18.04.2 LTS
>> Kernel: I built the kernel whose last commit is bed38c3e2dca.
>
>Does it work if you use the normal LTS kernel package instead.
>

It looks good on LTS kernel.

$ uname -a
Linux richard 4.15.0-55-generic #60-Ubuntu SMP Tue Jul 2 18:22:20 UTC 2019 
x86_64 x86_64 x86_64 GNU/Linux

$ QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 
tests/test-util-filemonitor
/util/filemonitor: OK


>
>Regards,
>Daniel
>-- 
>|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
>|: https://libvirt.org -o-https://fstop138.berrange.com :|
>|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

-- 
Wei Yang
Help you, Help me

[Qemu-devel] [PATCH 4/7] ati-vga: Fix cursor color with guest_hwcursor=true

[BALATON Zoltan]

Fixes: a38127414bd007c5b6ae64c664d9e8839393277e
Signed-off-by: BALATON Zoltan 
---
 hw/display/ati.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/display/ati.c b/hw/display/ati.c
index 699f38223b..b849f5d510 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -207,7 +207,7 @@ static void ati_cursor_draw_line(VGACommonState *vga, 
uint8_t *d, int scr_y)
 }
 } else {
 color = (xbits & BIT(7) ? s->regs.cur_color1 :
-  s->regs.cur_color0) << 8 | 0xff;
+  s->regs.cur_color0) | 0xff00;
 }
 if (vga->hw_cursor_x + i * 8 + j >= h) {
 return; /* end of screen, don't span to next line */
-- 
2.13.7

[Qemu-devel] [PATCH 5/7] ati-vga: Fix hardware cursor image offset

[BALATON Zoltan]

The crtc_offset is not needed, cur_offset is relative to the start of
vram not the start of displayed area. This fixes broken pointer image
with MacOS that uses non-0 crtc_offset.

Signed-off-by: BALATON Zoltan 
---
 hw/display/ati.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/hw/display/ati.c b/hw/display/ati.c
index b849f5d510..bbcdd6bc83 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -132,9 +132,8 @@ static void ati_cursor_define(ATIVGAState *s)
 return; /* Do not update cursor if locked or rendered by guest */
 }
 /* FIXME handle cur_hv_offs correctly */
-src = s->vga.vram_ptr + (s->regs.crtc_offset & 0x07ff) +
-  s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
-  (s->regs.cur_hv_offs & 0x) * 16;
+src = s->vga.vram_ptr + s->regs.cur_offset -
+  (s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0x) * 16;
 for (i = 0; i < 64; i++) {
 for (j = 0; j < 8; j++, idx++) {
 data[idx] = src[i * 16 + j];
@@ -190,8 +189,7 @@ static void ati_cursor_draw_line(VGACommonState *vga, 
uint8_t *d, int scr_y)
 return;
 }
 /* FIXME handle cur_hv_offs correctly */
-src = s->vga.vram_ptr + (s->regs.crtc_offset & 0x07ff) +
-  s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16;
+src = s->vga.vram_ptr + s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16;
 dp = [vga->hw_cursor_x];
 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
 for (i = 0; i < 8; i++) {
-- 
2.13.7

[Qemu-devel] [PATCH 2/7] ati-vga: Add some register definitions for debugging

[BALATON Zoltan]

Add names for AMCGPIO regs to make it easier to identify these in
trace output. This is where rage128p has the DDC from the DVI port
among others but because we don't implement the flat panel controller
we don't want to connect an EDID here to make sure drivers use the VGA
output instead. But since these are often probed by drivers it helps
to see what happens by logging these registers by name.

Signed-off-by: BALATON Zoltan 
---
 hw/display/ati_dbg.c  | 4 
 hw/display/ati_regs.h | 4 
 2 files changed, 8 insertions(+)

diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c
index cbc52025d0..7e59c41ac2 100644
--- a/hw/display/ati_dbg.c
+++ b/hw/display/ati_dbg.c
@@ -23,6 +23,10 @@ static struct ati_regdesc ati_reg_names[] = {
 {"GPIO_DVI_DDC", 0x0064},
 {"GPIO_MONID", 0x0068},
 {"I2C_CNTL_1", 0x0094},
+{"AMCGPIO_MASK_MIR", 0x009c},
+{"AMCGPIO_A_MIR", 0x00a0},
+{"AMCGPIO_Y_MIR", 0x00a4},
+{"AMCGPIO_EN_MIR", 0x00a8},
 {"PALETTE_INDEX", 0x00b0},
 {"PALETTE_DATA", 0x00b4},
 {"CNFG_CNTL", 0x00e0},
diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h
index 81fb5302c0..91947ab1e7 100644
--- a/hw/display/ati_regs.h
+++ b/hw/display/ati_regs.h
@@ -41,6 +41,10 @@
 #define GPIO_DVI_DDC0x0064
 #define GPIO_MONID  0x0068
 #define I2C_CNTL_1  0x0094
+#define AMCGPIO_MASK_MIR0x009c
+#define AMCGPIO_A_MIR   0x00a0
+#define AMCGPIO_Y_MIR   0x00a4
+#define AMCGPIO_EN_MIR  0x00a8
 #define PALETTE_INDEX   0x00b0
 #define PALETTE_DATA0x00b4
 #define CNFG_CNTL   0x00e0
-- 
2.13.7

[Qemu-devel] [PATCH 6/7] ati-vga: Attempt to handle CRTC offset not exact multiple of stride

[BALATON Zoltan]

MacOS uses non-0 offset so it needs this and the resulting
vbe_start_addr seems correct but picture is still broken with OpenBIOS
after FCode runs but that maybe due to firmware problems now. After
boot, picture is now correct.

It also occured to me that these CRTC regs are also present in VGA so
I wonder if they should be shared in case some drivers try to poke
them via VGA regs or these are a separate set of regs for extended
mode. Added a comment noting this but drivers I've tried so far
program the card accessing ati regs so I did not attempt to change it.

Signed-off-by: BALATON Zoltan 
---
 hw/display/ati.c | 22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/hw/display/ati.c b/hw/display/ati.c
index bbcdd6bc83..0bfe73179d 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -50,6 +50,7 @@ static void ati_vga_switch_mode(ATIVGAState *s)
 s->mode = EXT_MODE;
 if (s->regs.crtc_gen_cntl & CRTC2_EN) {
 /* CRT controller enabled, use CRTC values */
+/* FIXME Should these be the same as VGA CRTC regs? */
 uint32_t offs = s->regs.crtc_offset & 0x07ff;
 int stride = (s->regs.crtc_pitch & 0x7ff) * 8;
 int bpp = 0;
@@ -101,16 +102,23 @@ static void ati_vga_switch_mode(ATIVGAState *s)
 (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0));
 /* now set offset and stride after enable as that resets these */
 if (stride) {
+int bypp = DIV_ROUND_UP(bpp, BITS_PER_BYTE);
+
 vbe_ioport_write_index(>vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH);
 vbe_ioport_write_data(>vga, 0, stride);
-if (offs % stride == 0) {
-vbe_ioport_write_index(>vga, 0, 
VBE_DISPI_INDEX_Y_OFFSET);
-vbe_ioport_write_data(>vga, 0, offs / stride);
-} else {
-/* FIXME what to do with this? */
-error_report("VGA offset is not multiple of pitch, "
- "expect bad picture");
+stride *= bypp;
+if (offs % stride) {
+DPRINTF("CRTC offset is not multiple of pitch\n");
+vbe_ioport_write_index(>vga, 0,
+   VBE_DISPI_INDEX_X_OFFSET);
+vbe_ioport_write_data(>vga, 0, offs % stride / bypp);
 }
+vbe_ioport_write_index(>vga, 0, VBE_DISPI_INDEX_Y_OFFSET);
+vbe_ioport_write_data(>vga, 0, offs / stride);
+DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n",
+s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET],
+s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET],
+s->vga.vbe_start_addr);
 }
 }
 } else {
-- 
2.13.7

[Qemu-devel] [PATCH 1/7] ati-vga: Add registers for getting apertures

[BALATON Zoltan]

Some drivers (e.g. Linux radeon drm and MacOS) access these to find
apertures to access card. Try to implement these but not sure these
are correct yet.

Signed-off-by: BALATON Zoltan 
---
 hw/display/ati.c  | 15 +++
 hw/display/ati_dbg.c  |  5 +
 hw/display/ati_regs.h |  5 +
 3 files changed, 25 insertions(+)

diff --git a/hw/display/ati.c b/hw/display/ati.c
index a747c4cc98..c8fc62505b 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -307,6 +307,21 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, 
unsigned int size)
 case CNFG_MEMSIZE:
 val = s->vga.vram_size;
 break;
+case CONFIG_APER_0_BASE:
+case CONFIG_APER_1_BASE:
+val = pci_default_read_config(>dev,
+  PCI_BASE_ADDRESS_0, size) & 0xfff0;
+break;
+case CONFIG_APER_SIZE:
+val = s->vga.vram_size;
+break;
+case CONFIG_REG_1_BASE:
+val = pci_default_read_config(>dev,
+  PCI_BASE_ADDRESS_2, size) & 0xfff0;
+break;
+case CONFIG_REG_APER_SIZE:
+val = memory_region_size(>mm);
+break;
 case MC_STATUS:
 val = 5;
 break;
diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c
index 88b3a11315..cbc52025d0 100644
--- a/hw/display/ati_dbg.c
+++ b/hw/display/ati_dbg.c
@@ -28,6 +28,11 @@ static struct ati_regdesc ati_reg_names[] = {
 {"CNFG_CNTL", 0x00e0},
 {"GEN_RESET_CNTL", 0x00f0},
 {"CNFG_MEMSIZE", 0x00f8},
+{"CONFIG_APER_0_BASE", 0x0100},
+{"CONFIG_APER_1_BASE", 0x0104},
+{"CONFIG_APER_SIZE", 0x0108},
+{"CONFIG_REG_1_BASE", 0x010c},
+{"CONFIG_REG_APER_SIZE", 0x0110},
 {"MEM_CNTL", 0x0140},
 {"MC_FB_LOCATION", 0x0148},
 {"MC_AGP_LOCATION", 0x014C},
diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h
index d7155c93d5..81fb5302c0 100644
--- a/hw/display/ati_regs.h
+++ b/hw/display/ati_regs.h
@@ -46,6 +46,11 @@
 #define CNFG_CNTL   0x00e0
 #define GEN_RESET_CNTL  0x00f0
 #define CNFG_MEMSIZE0x00f8
+#define CONFIG_APER_0_BASE  0x0100
+#define CONFIG_APER_1_BASE  0x0104
+#define CONFIG_APER_SIZE0x0108
+#define CONFIG_REG_1_BASE   0x010c
+#define CONFIG_REG_APER_SIZE0x0110
 #define MEM_CNTL0x0140
 #define MC_FB_LOCATION  0x0148
 #define MC_AGP_LOCATION 0x014C
-- 
2.13.7

[Qemu-devel] [PATCH 0/7] Resend of all outstanding ati-vga patches

[BALATON Zoltan]

Hello,

This is the latest version of all outstanding ati-vga patches
collected in one series. Some of these or previous versions of them
were sent individually before but these are now superceding all
previous patches that are not yet in master and this series is all
that should be needed.

This should fix color problems due to endianness with most drivers (if
such problems remain with some Linux drivers those should be cross
checked with real hardware), fixes running FCode ROM with appropriate
OpenBIOS patches for mac99 and includes fixes that will be needed to
get picture with MacOS 9 but that may also need VBlank interrupts
emulated so it won't boot yet.

Regards,
BALATON Zoltan

BALATON Zoltan (7):
  ati-vga: Add registers for getting apertures
  ati-vga: Add some register definitions for debugging
  ati-vga: Fix GPIO_MONID register write
  ati-vga: Fix cursor color with guest_hwcursor=true
  ati-vga: Fix hardware cursor image offset
  ati-vga: Attempt to handle CRTC offset not exact multiple of stride
  ati-vga: Add limited support for big endian frame buffer aperture

 hw/display/ati.c  | 68 +--
 hw/display/ati_dbg.c  |  9 +++
 hw/display/ati_int.h  |  1 +
 hw/display/ati_regs.h | 11 +
 4 files changed, 71 insertions(+), 18 deletions(-)

-- 
2.13.7

[Qemu-devel] [PATCH 3/7] ati-vga: Fix GPIO_MONID register write

[BALATON Zoltan]

Also update bitbang_i2c state when output bits are changed while
enable bits are set. This fixes EDID access by the ATI FCode ROM.

Signed-off-by: BALATON Zoltan 
---
 hw/display/ati.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/display/ati.c b/hw/display/ati.c
index c8fc62505b..699f38223b 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -564,12 +564,15 @@ static void ati_mm_write(void *opaque, hwaddr addr,
addr - GPIO_MONID, data, size);
 /*
  * Rage128p accesses DDC used to get EDID via these bits.
- * Only touch i2c when write overlaps 3rd byte because some
- * drivers access this reg via multiple partial writes and
- * without this spurious bits would be sent.
+ * Because some drivers access this via multiple byte writes
+ * we have to be careful when we send bits to avoid spurious
+ * changes in bitbang_i2c state. So only do it when mask is set
+ * and either the enable bits are changed or output bits changed
+ * while enabled.
  */
 if ((s->regs.gpio_monid & BIT(25)) &&
-addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) {
+((addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) ||
+ (addr == GPIO_MONID && (s->regs.gpio_monid & 0x6 {
 s->regs.gpio_monid = ati_i2c(>bbi2c, s->regs.gpio_monid, 1);
 }
 }
-- 
2.13.7

[Qemu-devel] [PATCH 7/7] ati-vga: Add limited support for big endian frame buffer aperture

[BALATON Zoltan]

Set frame buffer endianness according to requested endianness for
frame buffer apertures. We set frame buffer to big endian if any of
the two apertures are set to big endian. Using different endianness
for the two apertures is not implemented. This fixes inverted colors
with MacOS and Xorg frame buffer driver but some Linux drivers may
have endianness issues even on real hardware so this may not fix all
cases. MorphOS uses aper0 in LE, Linux uses aper0 in BE and MacOS uses
aper1 in BE but not sure about others or if MacOS also may need aper0
in which case we'll need a more complex fix but MacOS has other
problems yet so for now this might work.

Signed-off-by: BALATON Zoltan 
---
 hw/display/ati.c  | 10 +-
 hw/display/ati_int.h  |  1 +
 hw/display/ati_regs.h |  2 ++
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/hw/display/ati.c b/hw/display/ati.c
index 0bfe73179d..a365e2455d 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -90,7 +90,9 @@ static void ati_vga_switch_mode(ATIVGAState *s)
 DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, 
offs);
 vbe_ioport_write_index(>vga, 0, VBE_DISPI_INDEX_ENABLE);
 vbe_ioport_write_data(>vga, 0, VBE_DISPI_DISABLED);
-s->vga.big_endian_fb = false;
+s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN ||
+s->regs.config_cntl & APER_1_ENDIAN ?
+true : false);
 /* reset VBE regs then set up mode */
 s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h;
 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v;
@@ -310,6 +312,9 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, 
unsigned int size)
 case PALETTE_DATA:
 val = vga_ioport_read(>vga, VGA_PEL_D);
 break;
+case CNFG_CNTL:
+val = s->regs.config_cntl;
+break;
 case CNFG_MEMSIZE:
 val = s->vga.vram_size;
 break;
@@ -604,6 +609,9 @@ static void ati_mm_write(void *opaque, hwaddr addr,
 data >>= 8;
 vga_ioport_write(>vga, VGA_PEL_D, data & 0xff);
 break;
+case CNFG_CNTL:
+s->regs.config_cntl = data;
+break;
 case CRTC_H_TOTAL_DISP:
 s->regs.crtc_h_total_disp = data & 0x07ff07ff;
 break;
diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h
index 31a1927b3e..5b4d3be1e6 100644
--- a/hw/display/ati_int.h
+++ b/hw/display/ati_int.h
@@ -39,6 +39,7 @@ typedef struct ATIVGARegs {
 uint32_t gpio_vga_ddc;
 uint32_t gpio_dvi_ddc;
 uint32_t gpio_monid;
+uint32_t config_cntl;
 uint32_t crtc_h_total_disp;
 uint32_t crtc_h_sync_strt_wid;
 uint32_t crtc_v_total_disp;
diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h
index 91947ab1e7..02046e97c2 100644
--- a/hw/display/ati_regs.h
+++ b/hw/display/ati_regs.h
@@ -317,6 +317,8 @@
 #define X_MPLL_REF_DIV_MASK 0x00FF
 
 /* Config control values (CONFIG_CNTL) */
+#define APER_0_ENDIAN   0x0003
+#define APER_1_ENDIAN   0x000c
 #define CFG_VGA_IO_DIS  0x0400
 
 /* CRTC control values (CRTC_GEN_CNTL) */
-- 
2.13.7

[Qemu-devel] [PATCH v2] block: posix: Handle undetectable alignment

[Nir Soffer]

In some cases buf_align or request_alignment cannot be detected:

- With Gluster, buf_align cannot be detected since the actual I/O is
  done on Gluster server, and qemu buffer alignment does not matter.

- With local XFS filesystem, buf_align cannot be detected if reading
  from unallocated area.

- With Gluster backed by XFS, request_alignment cannot be detected if
  reading from unallocated area.

- With NFS, the server does not use direct I/O, so both buf_align cannot
  be detected.

These cases seems to work when storage sector size is 512 bytes, because
the current code starts checking align=512. If the check succeeds
because alignment cannot be detected we use 512. But this does not work
for storage with 4k sector size.

Practically the alignment requirements are the same for buffer
alignment, buffer length, and offset in file. So in case we cannot
detect buf_align, we can use request alignment. If we cannot detect
request alignment, we can fallback to a safe value.

With this change:

- Provisioning VM and copying disks on local XFS and Gluster with 4k
  sector size works, resolving bugs [1],[2].

- With NFS we fallback to buf_align and request_alignment of 4096
  instead of 512. This may cause unneeded data copying, but so far I see
  better performance with this change.

[1] https://bugzilla.redhat.com/1737256
[2] https://bugzilla.redhat.com/1738657

Signed-off-by: Nir Soffer 
---

v1 was a minimal hack; this version is a more generic fix that works for
any storage without requiring users to allocate the first block of an
image. Allocting the first block of an image is still a good idea since
it allows detecting the right alignment in some cases.

v1 could also affect cases when we could detect buf_align to use
request_alignment instead; v2 will only affect cases when buf_align or
request_alignment cannot be detected.

v1 was hare:
https://lists.nongnu.org/archive/html/qemu-block/2019-08/msg00133.html

 block/file-posix.c | 40 +---
 1 file changed, 29 insertions(+), 11 deletions(-)

diff --git a/block/file-posix.c b/block/file-posix.c
index f33b542b33..511468f166 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -323,6 +323,7 @@ static void raw_probe_alignment(BlockDriverState *bs, int 
fd, Error **errp)
 BDRVRawState *s = bs->opaque;
 char *buf;
 size_t max_align = MAX(MAX_BLOCKSIZE, getpagesize());
+size_t alignments[] = {1, 512, 1024, 2048, 4096};
 
 /* For SCSI generic devices the alignment is not really used.
With buffered I/O, we don't have any restrictions. */
@@ -349,25 +350,42 @@ static void raw_probe_alignment(BlockDriverState *bs, int 
fd, Error **errp)
 }
 #endif
 
-/* If we could not get the sizes so far, we can only guess them */
-if (!s->buf_align) {
+/*
+ * If we could not get the sizes so far, we can only guess them. First try
+ * to detect request alignment, since it is more likely to succeed. Then
+ * try to detect buf_align, which cannot be detected in some cases (e.g.
+ * Gluster). If buf_align cannot be detected, we fallback to the value of
+ * request_alignment.
+ */
+
+if (!bs->bl.request_alignment) {
+int i;
 size_t align;
-buf = qemu_memalign(max_align, 2 * max_align);
-for (align = 512; align <= max_align; align <<= 1) {
-if (raw_is_io_aligned(fd, buf + align, max_align)) {
-s->buf_align = align;
+buf = qemu_memalign(max_align, max_align);
+for (i = 0; i < ARRAY_SIZE(alignments); i++) {
+align = alignments[i];
+if (raw_is_io_aligned(fd, buf, align)) {
+/* Fallback to safe value. */
+bs->bl.request_alignment = (align != 1) ? align : max_align;
 break;
 }
 }
 qemu_vfree(buf);
 }
 
-if (!bs->bl.request_alignment) {
+if (!s->buf_align) {
+int i;
 size_t align;
-buf = qemu_memalign(s->buf_align, max_align);
-for (align = 512; align <= max_align; align <<= 1) {
-if (raw_is_io_aligned(fd, buf, align)) {
-bs->bl.request_alignment = align;
+buf = qemu_memalign(max_align, 2 * max_align);
+for (i = 0; i < ARRAY_SIZE(alignments); i++) {
+align = alignments[i];
+if (raw_is_io_aligned(fd, buf + align, max_align)) {
+/* Fallback to request_aligment or safe value. */
+s->buf_align = (align != 1)
+? align
+: (bs->bl.request_alignment != 0)
+? bs->bl.request_alignment
+: max_align;
 break;
 }
 }
-- 
2.20.1

[Qemu-devel] [PATCH] Fix hw/rdma/vmw/pvrdma_cmd.c build

[Stephen Kitt]

This was broken by the cherry-pick in 41dd30f. Fix by handling errors
as in the rest of the function: "goto out" instead of "return rc".

Signed-off-by: Stephen Kitt 
---
 hw/rdma/vmw/pvrdma_cmd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/rdma/vmw/pvrdma_cmd.c b/hw/rdma/vmw/pvrdma_cmd.c
index bb9a9f1cd1..a3a86d7c8e 100644
--- a/hw/rdma/vmw/pvrdma_cmd.c
+++ b/hw/rdma/vmw/pvrdma_cmd.c
@@ -514,7 +514,7 @@ static int create_qp(PVRDMADev *dev, union pvrdma_cmd_req 
*req,
  cmd->recv_cq_handle, rings, >qpn);
 if (resp->hdr.err) {
 destroy_qp_rings(rings);
-return rc;
+goto out;
 }
 
 resp->max_send_wr = cmd->max_send_wr;
-- 
2.20.1

Re: [Qemu-devel] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:13 AM Bin Meng  wrote:
>
> The Linux kernel SiFive UART driver expects an aliases node to be
> present in the device tree, from which the driver extracts the port
> number from "serial#" in the aliases node.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/sifive_u.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7eb2b7e..0c1a89f 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -284,6 +284,8 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  if (cmdline) {
>  qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
>  }
> +qemu_fdt_add_subnode(fdt, "/aliases");
> +qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
>  g_free(nodename);
>  }
>
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:18 AM Bin Meng  wrote:
>
> This removes "reg-names" and "riscv,max-priority" properties of the
> PLIC node from device tree.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Jonathan Behrens 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
> Changes in v3: None
> Changes in v2:
> - keep the PLIC compatible string unchanged as OpenSBI uses that
>   for DT fix up
>
>  hw/riscv/sifive_u.c | 2 --
>  hw/riscv/virt.c | 2 --
>  2 files changed, 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index b0026aa..8801ee2 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -238,8 +238,6 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  qemu_fdt_setprop_cells(fdt, nodename, "reg",
>  0x0, memmap[SIFIVE_U_PLIC].base,
>  0x0, memmap[SIFIVE_U_PLIC].size);
> -qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
> -qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
>  qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
>  qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
>  plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 127f005..2f75195 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -244,8 +244,6 @@ static void *create_fdt(RISCVVirtState *s, const struct 
> MemmapEntry *memmap,
>  qemu_fdt_setprop_cells(fdt, nodename, "reg",
>  0x0, memmap[VIRT_PLIC].base,
>  0x0, memmap[VIRT_PLIC].size);
> -qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
> -qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
>  qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
>  qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
>  plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH v3 27/28] riscv: virt: Change create_fdt() to return void

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:14 AM Bin Meng  wrote:
>
> There is no need to return fdt at the end of create_fdt() because
> it's already saved in s->fdt. Other machines (sifive_u, spike)
> don't do it neither.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Chih-Min Chao 
> Reviewed-by: Philippe Mathieu-Daudé 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/virt.c | 11 ---
>  1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 2f75195..6bfa721 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -112,7 +112,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
> 0x1800, 0, 0, 0x7);
>  }
>
> -static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
> +static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
>  uint64_t mem_size, const char *cmdline)
>  {
>  void *fdt;
> @@ -316,8 +316,6 @@ static void *create_fdt(RISCVVirtState *s, const struct 
> MemmapEntry *memmap,
>  qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
>  }
>  g_free(nodename);
> -
> -return fdt;
>  }
>
>
> @@ -373,7 +371,6 @@ static void riscv_virt_board_init(MachineState *machine)
>  size_t plic_hart_config_len;
>  int i;
>  unsigned int smp_cpus = machine->smp.cpus;
> -void *fdt;
>
>  /* Initialize SOC */
>  object_initialize_child(OBJECT(machine), "soc", >soc, sizeof(s->soc),
> @@ -392,7 +389,7 @@ static void riscv_virt_board_init(MachineState *machine)
>  main_mem);
>
>  /* create device tree */
> -fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
> +create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
>
>  /* boot rom */
>  memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
> @@ -411,9 +408,9 @@ static void riscv_virt_board_init(MachineState *machine)
>  hwaddr end = riscv_load_initrd(machine->initrd_filename,
> machine->ram_size, kernel_entry,
> );
> -qemu_fdt_setprop_cell(fdt, "/chosen",
> +qemu_fdt_setprop_cell(s->fdt, "/chosen",
>"linux,initrd-start", start);
> -qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
> +qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
>end);
>  }
>  }
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:17 AM Bin Meng  wrote:
>
> The loading of initramfs is currently not supported on 'sifive_u'.
> Add the support to make '-initrd' command line parameter useful.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Chih-Min Chao 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/sifive_u.c | 13 -
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index e8bef44..b0026aa 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -328,7 +328,18 @@ static void riscv_sifive_u_init(MachineState *machine)
>   memmap[SIFIVE_U_DRAM].base);
>
>  if (machine->kernel_filename) {
> -riscv_load_kernel(machine->kernel_filename);
> +uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
> +
> +if (machine->initrd_filename) {
> +hwaddr start;
> +hwaddr end = riscv_load_initrd(machine->initrd_filename,
> +   machine->ram_size, kernel_entry,
> +   );
> +qemu_fdt_setprop_cell(s->fdt, "/chosen",
> +  "linux,initrd-start", start);
> +qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
> +  end);
> +}
>  }
>
>  /* reset vector */
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH v3 23/28] riscv: sifive_u: Fix broken GEM support

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:15 AM Bin Meng  wrote:
>
> At present the GEM support in sifive_u machine is seriously broken.
>
> - The GEM block register base was set to a weird number (0x100900FC),
>   which for no way could work with the cadence_gem model in QEMU.
> - The generated DT node for GEM has a "clocks-names" which is an
>   invalid property name.
>
> Not like other GEM variants, the FU540-specific GEM has a management
> block to control 10/100/1000Mbps link speed changes, that is mapped
> to 0x100a. We can simply map it into MMIO space without special
> handling using create_unimplemented_device().
>
> Update the GEM node compatible string to use the official name used
> by the upstream Linux kernel, and add the management block reg base
> & size to the  property encoding.
>
> Tested with upstream U-Boot and Linux kernel MACB drivers.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
> Changes in v3: None
> Changes in v2:
> - use create_unimplemented_device() to create the GEM management
>   block instead of sifive_mmio_emulate()
> - add "phy-handle" property to the ethernet node
>
>  hw/riscv/sifive_u.c | 23 ++-
>  include/hw/riscv/sifive_u.h |  3 ++-
>  2 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 0c1a89f..e8bef44 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -3,6 +3,7 @@
>   *
>   * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
>   * Copyright (c) 2017 SiFive, Inc.
> + * Copyright (c) 2019 Bin Meng 
>   *
>   * Provides a board compatible with the SiFive Freedom U SDK:
>   *
> @@ -11,6 +12,7 @@
>   * 2) PLIC (Platform Level Interrupt Controller)
>   * 3) PRCI (Power, Reset, Clock, Interrupt)
>   * 4) OTP (One-Time Programmable) memory with stored serial number
> + * 5) GEM (Gigabit Ethernet Controller) and management block
>   *
>   * This board currently generates devicetree dynamically that indicates at 
> least
>   * two harts and up to five harts.
> @@ -38,6 +40,7 @@
>  #include "hw/loader.h"
>  #include "hw/sysbus.h"
>  #include "hw/char/serial.h"
> +#include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> @@ -69,7 +72,8 @@ static const struct MemmapEntry {
>  [SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
>  [SIFIVE_U_OTP] =  { 0x1007, 0x1000 },
>  [SIFIVE_U_DRAM] = { 0x8000,0x0 },
> -[SIFIVE_U_GEM] =  { 0x100900FC, 0x2000 },
> +[SIFIVE_U_GEM] =  { 0x1009, 0x2000 },
> +[SIFIVE_U_GEM_MGMT] = { 0x100a, 0x1000 },
>  };
>
>  #define SIFIVE_OTP_SERIAL   1
> @@ -84,7 +88,7 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  char *nodename;
>  char ethclk_names[] = "pclk\0hclk";
>  uint32_t plic_phandle, prci_phandle, phandle = 1;
> -uint32_t hfclk_phandle, rtcclk_phandle;
> +uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
>
>  fdt = s->fdt = create_device_tree(>fdt_size);
>  if (!fdt) {
> @@ -242,20 +246,25 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  g_free(cells);
>  g_free(nodename);
>
> +phy_phandle = phandle++;
>  nodename = g_strdup_printf("/soc/ethernet@%lx",
>  (long)memmap[SIFIVE_U_GEM].base);
>  qemu_fdt_add_subnode(fdt, nodename);
> -qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
> +qemu_fdt_setprop_string(fdt, nodename, "compatible",
> +"sifive,fu540-c000-gem");
>  qemu_fdt_setprop_cells(fdt, nodename, "reg",
>  0x0, memmap[SIFIVE_U_GEM].base,
> -0x0, memmap[SIFIVE_U_GEM].size);
> +0x0, memmap[SIFIVE_U_GEM].size,
> +0x0, memmap[SIFIVE_U_GEM_MGMT].base,
> +0x0, memmap[SIFIVE_U_GEM_MGMT].size);
>  qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
>  qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
> +qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
>  qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
>  qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
>  qemu_fdt_setprop_cells(fdt, nodename, "clocks",
>  prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
> -qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
> +qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
>  sizeof(ethclk_names));
>  qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
>  qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
> @@ -264,6 +273,7 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
>  (long)memmap[SIFIVE_U_GEM].base);
>  qemu_fdt_add_subnode(fdt, nodename);
> +

Re: [Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:13 AM Bin Meng  wrote:
>
> This adds an OTP memory with a given serial number to the sifive_u
> machine. With such support, the upstream U-Boot for sifive_fu540
> boots out of the box on the sifive_u machine.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/sifive_u.c | 5 +
>  include/hw/riscv/sifive_u.h | 1 +
>  2 files changed, 6 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 5022b8f..486b247 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -10,6 +10,7 @@
>   * 1) CLINT (Core Level Interruptor)
>   * 2) PLIC (Platform Level Interrupt Controller)
>   * 3) PRCI (Power, Reset, Clock, Interrupt)
> + * 4) OTP (One-Time Programmable) memory with stored serial number
>   *
>   * This board currently generates devicetree dynamically that indicates at 
> least
>   * two harts and up to five harts.
> @@ -43,6 +44,7 @@
>  #include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
> +#include "hw/riscv/sifive_u_otp.h"
>  #include "hw/riscv/sifive_u_prci.h"
>  #include "hw/riscv/boot.h"
>  #include "chardev/char.h"
> @@ -65,10 +67,12 @@ static const struct MemmapEntry {
>  [SIFIVE_U_PRCI] = { 0x1000, 0x1000 },
>  [SIFIVE_U_UART0] ={ 0x1001, 0x1000 },
>  [SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
> +[SIFIVE_U_OTP] =  { 0x1007, 0x1000 },
>  [SIFIVE_U_DRAM] = { 0x8000,0x0 },
>  [SIFIVE_U_GEM] =  { 0x100900FC, 0x2000 },
>  };
>
> +#define SIFIVE_OTP_SERIAL   1
>  #define GEM_REVISION0x10070109
>
>  static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> @@ -441,6 +445,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, 
> Error **errp)
>  memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
>  SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
>  sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base);
> +sifive_u_otp_create(memmap[SIFIVE_U_OTP].base, SIFIVE_OTP_SERIAL);
>
>  for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
>  plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index e318ecb..3ae75b5 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -54,6 +54,7 @@ enum {
>  SIFIVE_U_PRCI,
>  SIFIVE_U_UART0,
>  SIFIVE_U_UART1,
> +SIFIVE_U_OTP,
>  SIFIVE_U_DRAM,
>  SIFIVE_U_GEM
>  };
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:12 AM Bin Meng  wrote:
>
> This adds a simple PRCI model for FU540 (sifive_u). It has different
> register layout from the existing PRCI model for FE310 (sifive_e).
>
> Signed-off-by: Bin Meng 
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/Makefile.objs   |   1 +
>  hw/riscv/sifive_u_prci.c | 163 
> +++
>  include/hw/riscv/sifive_u_prci.h |  90 +
>  3 files changed, 254 insertions(+)
>  create mode 100644 hw/riscv/sifive_u_prci.c
>  create mode 100644 include/hw/riscv/sifive_u_prci.h
>
> diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
> index c859697..b95bbd5 100644
> --- a/hw/riscv/Makefile.objs
> +++ b/hw/riscv/Makefile.objs
> @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
>  obj-$(CONFIG_SIFIVE) += sifive_plic.o
>  obj-$(CONFIG_SIFIVE) += sifive_test.o
>  obj-$(CONFIG_SIFIVE_U) += sifive_u.o
> +obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
>  obj-$(CONFIG_SIFIVE) += sifive_uart.o
>  obj-$(CONFIG_SPIKE) += spike.o
>  obj-$(CONFIG_RISCV_VIRT) += virt.o
> diff --git a/hw/riscv/sifive_u_prci.c b/hw/riscv/sifive_u_prci.c
> new file mode 100644
> index 000..35e5962
> --- /dev/null
> +++ b/hw/riscv/sifive_u_prci.c
> @@ -0,0 +1,163 @@
> +/*
> + * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt)
> + *
> + * Copyright (c) 2019 Bin Meng 
> + *
> + * Simple model of the PRCI to emulate register reads made by the SDK BSP
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see .
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "qemu/module.h"
> +#include "target/riscv/cpu.h"
> +#include "hw/riscv/sifive_u_prci.h"
> +
> +static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int 
> size)
> +{
> +SiFivePRCIState *s = opaque;
> +
> +switch (addr) {
> +case SIFIVE_PRCI_HFXOSCCFG:
> +return s->hfxosccfg;
> +case SIFIVE_PRCI_COREPLLCFG0:
> +return s->corepllcfg0;
> +case SIFIVE_PRCI_DDRPLLCFG0:
> +return s->ddrpllcfg0;
> +case SIFIVE_PRCI_DDRPLLCFG1:
> +return s->ddrpllcfg1;
> +case SIFIVE_PRCI_GEMGXLPLLCFG0:
> +return s->gemgxlpllcfg0;
> +case SIFIVE_PRCI_GEMGXLPLLCFG1:
> +return s->gemgxlpllcfg1;
> +case SIFIVE_PRCI_CORECLKSEL:
> +return s->coreclksel;
> +case SIFIVE_PRCI_DEVICESRESET:
> +return s->devicesreset;
> +case SIFIVE_PRCI_CLKMUXSTATUS:
> +return s->clkmuxstatus;
> +}
> +
> +hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
> +return 0;
> +}
> +
> +static void sifive_prci_write(void *opaque, hwaddr addr,
> +  uint64_t val64, unsigned int size)
> +{
> +SiFivePRCIState *s = opaque;
> +
> +switch (addr) {
> +case SIFIVE_PRCI_HFXOSCCFG:
> +s->hfxosccfg = (uint32_t) val64;
> +/* OSC stays ready */
> +s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY;
> +break;
> +case SIFIVE_PRCI_COREPLLCFG0:
> +s->corepllcfg0 = (uint32_t) val64;
> +/* internal feedback */
> +s->corepllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE;
> +/* PLL stays locked */
> +s->corepllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK;
> +break;
> +case SIFIVE_PRCI_DDRPLLCFG0:
> +s->ddrpllcfg0 = (uint32_t) val64;
> +/* internal feedback */
> +s->ddrpllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE;
> +/* PLL stays locked */
> +s->ddrpllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK;
> +break;
> +case SIFIVE_PRCI_DDRPLLCFG1:
> +s->ddrpllcfg1 = (uint32_t) val64;
> +break;
> +case SIFIVE_PRCI_GEMGXLPLLCFG0:
> +s->gemgxlpllcfg0 = (uint32_t) val64;
> + /* internal feedback */
> +s->gemgxlpllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE;
> +   /* PLL stays locked */
> +s->gemgxlpllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK;
> +break;
> +case SIFIVE_PRCI_GEMGXLPLLCFG1:
> +s->gemgxlpllcfg1 = (uint32_t) val64;
> +break;
> +case SIFIVE_PRCI_CORECLKSEL:
> +s->coreclksel = (uint32_t) val64;
> +break;
> +case SIFIVE_PRCI_DEVICESRESET:
> +s->devicesreset = (uint32_t) val64;
> +break;
> +case SIFIVE_PRCI_CLKMUXSTATUS:
> +s->clkmuxstatus = (uint32_t) val64;
> +break;
> +default:
> +hw_error("%s: bad write: addr=0x%x v=0x%x\n",
> +   

Re: [Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:11 AM Bin Meng  wrote:
>
> Currently the PRCI register block size is set to 0x8000, but in fact
> 0x1000 is enough, which is also what the manual says.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Chih-Min Chao 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/sifive_e_prci.c | 2 +-
>  include/hw/riscv/sifive_e_prci.h | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
> index c906f11..4cbce48 100644
> --- a/hw/riscv/sifive_e_prci.c
> +++ b/hw/riscv/sifive_e_prci.c
> @@ -85,7 +85,7 @@ static void sifive_prci_init(Object *obj)
>  SiFivePRCIState *s = SIFIVE_E_PRCI(obj);
>
>  memory_region_init_io(>mmio, obj, _prci_ops, s,
> -  TYPE_SIFIVE_E_PRCI, 0x8000);
> +  TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE);
>  sysbus_init_mmio(SYS_BUS_DEVICE(obj), >mmio);
>
>  s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
> diff --git a/include/hw/riscv/sifive_e_prci.h 
> b/include/hw/riscv/sifive_e_prci.h
> index 7932fe7..81e506b 100644
> --- a/include/hw/riscv/sifive_e_prci.h
> +++ b/include/hw/riscv/sifive_e_prci.h
> @@ -47,6 +47,8 @@ enum {
>  SIFIVE_PRCI_PLLOUTDIV_DIV1  = (1 << 8)
>  };
>
> +#define SIFIVE_E_PRCI_REG_SIZE  0x1000
> +
>  #define TYPE_SIFIVE_E_PRCI  "riscv.sifive.e.prci"
>
>  #define SIFIVE_E_PRCI(obj) \
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:00 AM Bin Meng  wrote:
>
> Hi Alistair,
>
> On Sat, Aug 10, 2019 at 9:51 AM Alistair Francis  wrote:
> >
> > On Wed, Aug 7, 2019 at 12:49 AM Bin Meng  wrote:
> > >
> > > Current SiFive PRCI model only works with sifive_e machine, as it
> > > only emulates registers or PRCI block in the FE310 SoC.
> > >
> > > Rename the file name to make it clear that it is for sifive_e.
> > >
> > > Signed-off-by: Bin Meng 
> > > ---
> > >
> > > Changes in v2: None
> > >
> > >  hw/riscv/Makefile.objs  |  2 +-
> > >  hw/riscv/sifive_e.c |  4 ++--
> > >  hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 14 +++---
> > >  include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} | 14 +++---
> > >  4 files changed, 17 insertions(+), 17 deletions(-)
> > >  rename hw/riscv/{sifive_prci.c => sifive_e_prci.c} (90%)
> > >  rename include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} (82%)
> > >
> > > diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
> > > index eb9d4f9..c859697 100644
> > > --- a/hw/riscv/Makefile.objs
> > > +++ b/hw/riscv/Makefile.objs
> > > @@ -2,9 +2,9 @@ obj-y += boot.o
> > >  obj-$(CONFIG_SPIKE) += riscv_htif.o
> > >  obj-$(CONFIG_HART) += riscv_hart.o
> > >  obj-$(CONFIG_SIFIVE_E) += sifive_e.o
> > > +obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o
> > >  obj-$(CONFIG_SIFIVE) += sifive_clint.o
> > >  obj-$(CONFIG_SIFIVE) += sifive_gpio.o
> > > -obj-$(CONFIG_SIFIVE) += sifive_prci.o
> > >  obj-$(CONFIG_SIFIVE) += sifive_plic.o
> > >  obj-$(CONFIG_SIFIVE) += sifive_test.o
> > >  obj-$(CONFIG_SIFIVE_U) += sifive_u.o
> > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > > index 2a499d8..2d67670 100644
> > > --- a/hw/riscv/sifive_e.c
> > > +++ b/hw/riscv/sifive_e.c
> > > @@ -41,9 +41,9 @@
> > >  #include "hw/riscv/riscv_hart.h"
> > >  #include "hw/riscv/sifive_plic.h"
> > >  #include "hw/riscv/sifive_clint.h"
> > > -#include "hw/riscv/sifive_prci.h"
> > >  #include "hw/riscv/sifive_uart.h"
> > >  #include "hw/riscv/sifive_e.h"
> > > +#include "hw/riscv/sifive_e_prci.h"
> > >  #include "hw/riscv/boot.h"
> > >  #include "chardev/char.h"
> > >  #include "sysemu/arch_init.h"
> > > @@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState 
> > > *dev, Error **errp)
> > >  SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
> > >  sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
> > >  memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> > > -sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
> > > +sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
> > >
> > >  /* GPIO */
> > >
> > > diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_e_prci.c
> > > similarity index 90%
> > > rename from hw/riscv/sifive_prci.c
> > > rename to hw/riscv/sifive_e_prci.c
> > > index f406682..acb914d 100644
> > > --- a/hw/riscv/sifive_prci.c
> > > +++ b/hw/riscv/sifive_e_prci.c
> > > @@ -1,5 +1,5 @@
> > >  /*
> > > - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt)
> > > + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt)
> > >   *
> > >   * Copyright (c) 2017 SiFive, Inc.
> > >   *
> > > @@ -22,7 +22,7 @@
> > >  #include "hw/sysbus.h"
> > >  #include "qemu/module.h"
> > >  #include "target/riscv/cpu.h"
> > > -#include "hw/riscv/sifive_prci.h"
> > > +#include "hw/riscv/sifive_e_prci.h"
> > >
> > >  static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int 
> > > size)
> > >  {
> > > @@ -82,10 +82,10 @@ static const MemoryRegionOps sifive_prci_ops = {
> > >
> > >  static void sifive_prci_init(Object *obj)
> > >  {
> > > -SiFivePRCIState *s = SIFIVE_PRCI(obj);
> > > +SiFivePRCIState *s = SIFIVE_E_PRCI(obj);
> >
> > Should we not rename the struct as well?
> >
>
> I think this is OK given it's only used by sifive_e machine and will
> not be mixed with sifive_u.

Structs can be public though, so this seems risky. I feel like it
should be renamed with the file.

Alistair

>
> Regards,
> Bin

Re: [Qemu-devel] [PATCH v3 07/28] riscv: sifive_u: Set the minimum number of cpus to 2

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:08 AM Bin Meng  wrote:
>
> It is not useful if we only have one management CPU.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
> Changes in v3:
> - use management cpu count + 1 for the min_cpus
>
> Changes in v2:
> - update the file header to indicate at least 2 harts are created
>
>  hw/riscv/sifive_u.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 295ca77..f8ffc0b 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -10,8 +10,8 @@
>   * 1) CLINT (Core Level Interruptor)
>   * 2) PLIC (Platform Level Interrupt Controller)
>   *
> - * This board currently generates devicetree dynamically that indicates at 
> most
> - * five harts.
> + * This board currently generates devicetree dynamically that indicates at 
> least
> + * two harts and up to five harts.
>   *
>   * This program is free software; you can redistribute it and/or modify it
>   * under the terms and conditions of the GNU General Public License,
> @@ -425,6 +425,7 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
>  mc->desc = "RISC-V Board compatible with SiFive U SDK";
>  mc->init = riscv_sifive_u_init;
>  mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 
> SIFIVE_U_COMPUTE_CPU_COUNT;
> +mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
>  }
>
>  DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH v3 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:10 AM Bin Meng  wrote:
>
> The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
> RISC-V cores. Currently the sifive_u machine only populates 4 U54
> cores. Update the max cpu number to 5 to reflect the real hardware,
> and pass "cpu-type" to populate heterogeneous harts.
>
> The cpu nodes in the generated DTS have been updated as well.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
> Changes in v3:
> - changed to use macros for management and compute cpu count
>
> Changes in v2:
> - fixed the "interrupts-extended" property size
>
>  hw/riscv/sifive_u.c | 40 +++-
>  include/hw/riscv/sifive_u.h |  3 +++
>  2 files changed, 30 insertions(+), 13 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 623ee64..295ca77 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -10,7 +10,8 @@
>   * 1) CLINT (Core Level Interruptor)
>   * 2) PLIC (Platform Level Interrupt Controller)
>   *
> - * This board currently uses a hardcoded devicetree that indicates one hart.
> + * This board currently generates devicetree dynamically that indicates at 
> most
> + * five harts.
>   *
>   * This program is free software; you can redistribute it and/or modify it
>   * under the terms and conditions of the GNU General Public License,
> @@ -26,6 +27,7 @@
>   */
>
>  #include "qemu/osdep.h"
> +#include "qemu/cutils.h"
>  #include "qemu/log.h"
>  #include "qemu/error-report.h"
>  #include "qapi/error.h"
> @@ -117,7 +119,10 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  qemu_fdt_add_subnode(fdt, nodename);
>  qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
>SIFIVE_U_CLOCK_FREQ);
> -qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
> +/* cpu 0 is the management hart that does not have mmu */
> +if (cpu != 0) {
> +qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
> +}
>  qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
>  qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
>  qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
> @@ -157,15 +162,21 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  g_free(nodename);
>
>  plic_phandle = phandle++;
> -cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
> +cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4 - 2);
>  for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
>  nodename =
>  g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
>  uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
> -cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
> -cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
> -cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
> -cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
> +/* cpu 0 is the management hart that does not have S-mode */
> +if (cpu == 0) {
> +cells[0] = cpu_to_be32(intc_phandle);
> +cells[1] = cpu_to_be32(IRQ_M_EXT);
> +} else {
> +cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
> +cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
> +cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
> +cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
> +}
>  g_free(nodename);
>  }
>  nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
> @@ -175,7 +186,7 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
>  qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
>  qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
> -cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
> +cells, (s->soc.cpus.num_harts * 4 - 2) * sizeof(uint32_t));
>  qemu_fdt_setprop_cells(fdt, nodename, "reg",
>  0x0, memmap[SIFIVE_U_PLIC].base,
>  0x0, memmap[SIFIVE_U_PLIC].size);
> @@ -315,10 +326,16 @@ static void riscv_sifive_u_soc_init(Object *obj)
>  {
>  MachineState *ms = MACHINE(qdev_get_machine());
>  SiFiveUSoCState *s = RISCV_U_SOC(obj);
> +char cpu_type[64];
> +
> +/* create cpu type representing SiFive FU540 SoC */
> +pstrcpy(cpu_type, sizeof(cpu_type), SIFIVE_E_CPU);
> +pstrcat(cpu_type, sizeof(cpu_type), ",");
> +pstrcat(cpu_type, sizeof(cpu_type), SIFIVE_U_CPU);
>
>  object_initialize_child(obj, "cpus", >cpus, sizeof(s->cpus),
>  TYPE_RISCV_HART_ARRAY, _abort, NULL);
> -object_property_set_str(OBJECT(>cpus), SIFIVE_U_CPU, "cpu-type",
> +object_property_set_str(OBJECT(>cpus), cpu_type, "cpu-type",
>  _abort);
>  

Re: [Qemu-devel] [PATCH v3 04/28] riscv: hart: Extract hart realize to a separate routine

[Alistair Francis]

On Sun, Aug 11, 2019 at 1:07 AM Bin Meng  wrote:
>
> Currently riscv_harts_realize() creates all harts based on the
> same cpu type given in the hart array property. With current
> implementation it can only create symmetric harts. Exact the
> hart realize to a separate routine in preparation for supporting
> heterogeneous hart arrays.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/riscv_hart.c | 31 +++
>  1 file changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> index ca69a1b..3dd1c6a 100644
> --- a/hw/riscv/riscv_hart.c
> +++ b/hw/riscv/riscv_hart.c
> @@ -37,26 +37,33 @@ static void riscv_harts_cpu_reset(void *opaque)
>  cpu_reset(CPU(cpu));
>  }
>
> +static void riscv_hart_realize(RISCVHartArrayState *s, int hart,
> +   char *cpu_type, Error **errp)
> +{
> +Error *err = NULL;
> +
> +object_initialize_child(OBJECT(s), "harts[*]", >harts[hart],
> +sizeof(RISCVCPU), cpu_type,
> +_abort, NULL);
> +s->harts[hart].env.mhartid = hart;
> +qemu_register_reset(riscv_harts_cpu_reset, >harts[hart]);
> +object_property_set_bool(OBJECT(>harts[hart]), true,
> + "realized", );
> +if (err) {
> +error_propagate(errp, err);
> +return;
> +}
> +}
> +
>  static void riscv_harts_realize(DeviceState *dev, Error **errp)
>  {
>  RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
> -Error *err = NULL;
>  int n;
>
>  s->harts = g_new0(RISCVCPU, s->num_harts);
>
>  for (n = 0; n < s->num_harts; n++) {
> -object_initialize_child(OBJECT(s), "harts[*]", >harts[n],
> -sizeof(RISCVCPU), s->cpu_type,
> -_abort, NULL);
> -s->harts[n].env.mhartid = n;
> -qemu_register_reset(riscv_harts_cpu_reset, >harts[n]);
> -object_property_set_bool(OBJECT(>harts[n]), true,
> - "realized", );
> -if (err) {
> -error_propagate(errp, err);
> -return;
> -}
> +riscv_hart_realize(s, n, s->cpu_type, errp);
>  }
>  }
>
> --
> 2.7.4
>
>

Re: [Qemu-devel] RISC-V: Vector && DSP Extension

[Alistair Francis]

On Sat, Aug 10, 2019 at 6:55 AM LIU ZhiWei  wrote:
>
>
> On 8/9/19 6:54 PM, Alistair Francis wrote:
>
> On Thu, Aug 8, 2019 at 2:52 AM liuzhiwei  wrote:
>
> Hi all,
>
> My workmate  and I have been working on Vector & Dsp extension, and
> I'd like to share develop status  with folks.
>
> Cool!
>
> The spec references for  Vector extension is riscv-v-spec-0.7.1, and
> riscv-p-spec-0.5 for DSP extension. The code of vector extension is
> ready and under testing,  the first patch will be sent about two weeks
> later. After that we will forward working on DSP extension, and send the
> first patch in middle  October.
>
> What code are you talking about? Is this QEMU code?
>
> Hi Alistair,
>
> It's the QEMU code I have been working on these days, which implements Vector 
> extension. It is under testing,
> and will be sent later.

Great! Please send it when you have it ready. We can accept draft
extensions in QEMU as long as they are disabled by default.

Alistair

>
>  Could the maintainers  tell me whether the specs referenced are
> appropriate? Is anyone working on these extensions?  I'd like to get
> your status, and maybe discuss questions and work togather.
>
> Just use the latest (master) from the ISA spec git repo.
>
> I will follow your advice.Thanks for your attention to this matter.
>
> Best Regards,
>
> Zhiwei
>
> I don't know anyone doing vector work for QEMU. It would be very
> useful, but everyone is busy with something at the moment
> unfortunately.
>
> Alistair
>
> Best Regards
>
> LIU Zhiwei
>
>
>

Re: [Qemu-devel] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population

[Richard Henderson]

On 8/11/19 1:06 AM, Bin Meng wrote:
> +/* heterogeneous harts */
> +while (tmp_type) {
> +if (n >= s->num_harts) {
> +break;
> +}
> +riscv_hart_realize(s, n++, tmp_type, errp);
> +last_type = tmp_type;
> +tmp_type = strtok(NULL, ",");
> +}

You need to create clusters for each cpu type.

In particular, E51 does not have the fpu that U54 does, and so we need to
generate different code for each cluster.

Because each cluster generates different TBs, you'll minimize code generation
if you do more than just create one per cpu, e.g. pop these cpu type names into
a GHashTable as you create each cluster.

The only other example of clusters in tree is hw/arm/armsse.c.  Note that board
has one cpu per cluster, as each cpu may be configured differently via other
property settings.


r~

Re: [Qemu-devel] [RFC PATCH v2 00/39] rewrite MMX/SSE instruction translation

[Jan Bobek]

On 8/10/19 7:35 PM, Richard Henderson wrote:
> On 8/9/19 9:12 PM, Jan Bobek wrote:
>> This is a v2 of the patch series posted in [1]. Patches 1-9 are just
>> cleanups; patches 10-39 are something actually interesting. Compared
>> to v1, I started using preprocessor more extensively to generate
>> repetitive boilerplate code; opinions/alternatives are welcome and
>> appreciated.
> 
> This is tricky.  I'm not keen on code entirely expanded via macros because it
> becomes extremely difficult to debug.  All statements get recorded at the same
> line of the location of the expansion, which makes the gdb "step" command
> finish the entire function because there is no next line.
> 
> Once upon a time I wrote some code that's extremely macro crazy:
> 
> https://sourceware.org/git/?p=glibc.git;a=blob_plain;f=soft-fp/op-common.h;hb=HEAD
> 
> It has been extremely difficult to maintain over the years.

Thank you, that's exactly the feedback I'm looking for! I've played
with the preprocessor in the past just to try out what's possible, but
I've never maintained code that uses it as extensively as this
series. It didn't occur to me that there would be a problem with
stepping it in gdb, for example, but now it seems obvious.

> We have just recently gotten rid of some of the macros in the softmmu code
> 
> https://patchwork.ozlabs.org/project/qemu-devel/list/?series=105441
> 
> replacing most of them with inline functions.

I'll have to look at it and see how exactly it's done; perhaps I'll
find something that's applicable to my case, too.

> A lot of what you have needs very little adjustment to address the debugging
> problem.  E.g.
> 
>> +#define INSNOP_INIT(opT, init_stmt)\
>> +static int insnop_init(opT)(CPUX86State *env, DisasContext *s, \
>> +int modrm, insnop_t(opT) *op)  \
>> +{  \
>> +init_stmt; \
>> +}
> 
>> +INSNOP(
>> +M, TCGv,
>> +do {
>> +if (decode_modrm_mod(env, s, modrm) == 3) {
>> +INSNOP_INIT_FAIL;
>> +} else {
>> +INSNOP_INIT_OK(s->A0);
>> +}
>> +} while (0),
>> +do {
>> +assert(*op == s->A0);
>> +gen_lea_modrm(env, s, modrm);
>> +} while (0),
>> +INSNOP_FINALIZE_NOOP)
> 
> Rearrange this as
> 
> #define INSNOP_INIT(OPT) \
> static bool insnop_##OPT##_init(CPUX86State *env, DisasContext *s, \
> int modrm, insnop_##OPT##_t *op)
> 
> #define INSNOP_PREPARE(OPT) \
> static void insnop_##OPT##_prepare(CPUX86State *env, DisasContext *s, \
>int modrm, insnop_##OPT##_t *op)
> 
> INSNOP_INIT(M)
> {
> if (decode_modrm_mod(env, s, modrm) == 3) {
> INSNOP_INIT_FAIL;
> } else {
> INSNOP_INIT_OK(s->A0);
> }
> }
> 
> INSNOP_PREPARE(M)
> {
> assert(*op == s->A0);
> gen_lea_modrm(env, s, modrm);
> }
> 
> etc and suddenly the entire expansion does not occur on a single line.

That makes complete sense, thank you! I'll keep the debugging issue in
mind.

> Further specific commentary to follow.

Looking forward to it!

-Jan



signature.asc
Description: OpenPGP digital signature

Re: [Qemu-devel] [PATCH v3 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine

[Bin Meng]

On Sun, Aug 11, 2019 at 4:07 PM Bin Meng  wrote:
>
> As of today, the QEMU 'sifive_u' machine is a special target that does
> not boot the upstream OpenSBI/U-Boot firmware images built for the real
> SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform
> "qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced
> in the OpenSBI doc as its payload, but that does not boot at all due
> to various issues in current QEMU 'sifive_u' machine codes.
>
> This series aims to improve the emulation fidelity of sifive_u machine,
> so that the upstream OpenSBI, U-Boot and kernel images built for the
> SiFive HiFive Unleashed board can be used out of the box without any
> special hack.
>
> The major changes include:
> - Heterogeneous harts creation supported, so that we can create a CPU
>   that exactly mirrors the real hardware: 1 E51 + 4 U54.
> - Implemented a PRCI model for FU540
> - Implemented an OTP model for FU540, primarily used for storing serial
>   number of the board
> - Fixed GEM support that was seriously broken on sifive_u
> - Synced device tree with upstream Linux kernel on sifive_u
> - Adding initramfs loading support on sifive_u
>
> OpenSBI v0.4 image built for sifive/fu540 is included as the default
> bios image for 'sifive_u' machine.
>
> The series is tested against OpenSBI v0.4 image for sifive/fu540
> paltform, U-Boot v2019.10-rc1 image for sifive_fu540_defconfig,
> and Linux kernel v5.3-rc3 image with the following patch:
>
> macb: Update compatibility string for SiFive FU540-C000
> https://patchwork.kernel.org/patch/11050003/
>
> OpenSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well.
> Boot Linux 64-bit defconfig image, verified that system console on
> the serial 0 and ping host work pretty well.
>
> An OpenSBI patch was sent to drop the special "qemu/sifive_u" platform
> support in OpenSBI. It will be applied after this QEMU series is merged.
> http://lists.infradead.org/pipermail/opensbi/2019-August/000335.html
>
> Changes in v3:
> - changed to use macros for management and compute cpu count
> - use management cpu count + 1 for the min_cpus
> - update IRQ numbers of both UARTs to match hardware as well
>
> Changes in v2:
> - fixed the "interrupts-extended" property size
> - update the file header to indicate at least 2 harts are created
> - use create_unimplemented_device() to create the GEM management
>   block instead of sifive_mmio_emulate()
> - add "phy-handle" property to the ethernet node
> - keep the PLIC compatible string unchanged as OpenSBI uses that
>   for DT fix up
> - drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common place"
> - new patch "riscv: sifive_e: Drop sifive_mmio_emulate()"
>
> Bin Meng (28):
>   riscv: hw: Remove superfluous "linux,phandle" property
>   riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
>   riscv: Add a sifive_cpu.h to include both E and U cpu type defines
>   riscv: hart: Extract hart realize to a separate routine
>   riscv: hart: Support heterogeneous harts population
>   riscv: sifive_u: Update hart configuration to reflect the real FU540
> SoC
>   riscv: sifive_u: Set the minimum number of cpus to 2
>   riscv: sifive_u: Update PLIC hart topology configuration string
>   riscv: sifive_u: Update UART base addresses and IRQs
>   riscv: sifive_u: Remove the unnecessary include of prci header
>   riscv: sifive: Rename sifive_prci.{c,h} to sifive_e_prci.{c,h}
>   riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
>   riscv: sifive_e: prci: Update the PRCI register block size
>   riscv: sifive: Implement PRCI model for FU540
>   riscv: sifive_u: Generate hfclk and rtcclk nodes
>   riscv: sifive_u: Add PRCI block to the SoC
>   riscv: sifive_u: Change UART node name in device tree
>   riscv: hw: Implement a model for SiFive FU540 OTP
>   riscv: sifive_u: Instantiate OTP memory with a serial number
>   riscv: roms: Update default bios for sifive_u machine
>   riscv: sifive_u: Update UART and ethernet node clock properties
>   riscv: sifive_u: Generate an aliases node in the device tree
>   riscv: sifive_u: Fix broken GEM support
>   riscv: sifive_u: Support loading initramfs
>   riscv: hw: Remove not needed PLIC properties in device tree
>   riscv: sifive_e: Drop sifive_mmio_emulate()
>   riscv: virt: Change create_fdt() to return void
>   riscv: sifive_u: Update model and compatible strings in device tree
>

I have no idea on why patch [20/28] and [26/28] failed to arrive on
the mailing list. The "git send-email" logs said OK when these two
patches were sent. In v2, these 2 patches are missing on patchwork,
and unfortunately this is the same situation for v3.

Attached these 2 patches.

Regards,
Bin


0020-riscv-roms-Update-default-bios-for-sifive_u-machine.patch
Description: Binary data


0026-riscv-sifive_e-Drop-sifive_mmio_emulate.patch
Description: Binary data

[Qemu-devel] [PATCH v3 28/28] riscv: sifive_u: Update model and compatible strings in device tree

[Bin Meng]

This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 

---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 8801ee2..98fefbeb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -96,8 +96,9 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 exit(1);
 }
 
-qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
-qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
+qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
+qemu_fdt_setprop_string(fdt, "/", "compatible",
+"sifive,hifive-unleashed-a00");
 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 
-- 
2.7.4

[Qemu-devel] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree

[Bin Meng]

This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.

Signed-off-by: Bin Meng 
Reviewed-by: Jonathan Behrens 

---

Changes in v3: None
Changes in v2:
- keep the PLIC compatible string unchanged as OpenSBI uses that
  for DT fix up

 hw/riscv/sifive_u.c | 2 --
 hw/riscv/virt.c | 2 --
 2 files changed, 4 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b0026aa..8801ee2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -238,8 +238,6 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[SIFIVE_U_PLIC].base,
 0x0, memmap[SIFIVE_U_PLIC].size);
-qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
-qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 127f005..2f75195 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -244,8 +244,6 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[VIRT_PLIC].base,
 0x0, memmap[VIRT_PLIC].size);
-qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
-qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
-- 
2.7.4

[Qemu-devel] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs

[Bin Meng]

The loading of initramfs is currently not supported on 'sifive_u'.
Add the support to make '-initrd' command line parameter useful.

Signed-off-by: Bin Meng 
Reviewed-by: Chih-Min Chao 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e8bef44..b0026aa 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -328,7 +328,18 @@ static void riscv_sifive_u_init(MachineState *machine)
  memmap[SIFIVE_U_DRAM].base);
 
 if (machine->kernel_filename) {
-riscv_load_kernel(machine->kernel_filename);
+uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
+
+if (machine->initrd_filename) {
+hwaddr start;
+hwaddr end = riscv_load_initrd(machine->initrd_filename,
+   machine->ram_size, kernel_entry,
+   );
+qemu_fdt_setprop_cell(s->fdt, "/chosen",
+  "linux,initrd-start", start);
+qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+  end);
+}
 }
 
 /* reset vector */
-- 
2.7.4

[Qemu-devel] [PATCH v3 23/28] riscv: sifive_u: Fix broken GEM support

[Bin Meng]

At present the GEM support in sifive_u machine is seriously broken.

- The GEM block register base was set to a weird number (0x100900FC),
  which for no way could work with the cadence_gem model in QEMU.
- The generated DT node for GEM has a "clocks-names" which is an
  invalid property name.

Not like other GEM variants, the FU540-specific GEM has a management
block to control 10/100/1000Mbps link speed changes, that is mapped
to 0x100a. We can simply map it into MMIO space without special
handling using create_unimplemented_device().

Update the GEM node compatible string to use the official name used
by the upstream Linux kernel, and add the management block reg base
& size to the  property encoding.

Tested with upstream U-Boot and Linux kernel MACB drivers.

Signed-off-by: Bin Meng 

---

Changes in v3: None
Changes in v2:
- use create_unimplemented_device() to create the GEM management
  block instead of sifive_mmio_emulate()
- add "phy-handle" property to the ethernet node

 hw/riscv/sifive_u.c | 23 ++-
 include/hw/riscv/sifive_u.h |  3 ++-
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0c1a89f..e8bef44 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -3,6 +3,7 @@
  *
  * Copyright (c) 2016-2017 Sagar Karandikar, sag...@eecs.berkeley.edu
  * Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2019 Bin Meng 
  *
  * Provides a board compatible with the SiFive Freedom U SDK:
  *
@@ -11,6 +12,7 @@
  * 2) PLIC (Platform Level Interrupt Controller)
  * 3) PRCI (Power, Reset, Clock, Interrupt)
  * 4) OTP (One-Time Programmable) memory with stored serial number
+ * 5) GEM (Gigabit Ethernet Controller) and management block
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -38,6 +40,7 @@
 #include "hw/loader.h"
 #include "hw/sysbus.h"
 #include "hw/char/serial.h"
+#include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
@@ -69,7 +72,8 @@ static const struct MemmapEntry {
 [SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
 [SIFIVE_U_OTP] =  { 0x1007, 0x1000 },
 [SIFIVE_U_DRAM] = { 0x8000,0x0 },
-[SIFIVE_U_GEM] =  { 0x100900FC, 0x2000 },
+[SIFIVE_U_GEM] =  { 0x1009, 0x2000 },
+[SIFIVE_U_GEM_MGMT] = { 0x100a, 0x1000 },
 };
 
 #define SIFIVE_OTP_SERIAL   1
@@ -84,7 +88,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 char *nodename;
 char ethclk_names[] = "pclk\0hclk";
 uint32_t plic_phandle, prci_phandle, phandle = 1;
-uint32_t hfclk_phandle, rtcclk_phandle;
+uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
 
 fdt = s->fdt = create_device_tree(>fdt_size);
 if (!fdt) {
@@ -242,20 +246,25 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 g_free(cells);
 g_free(nodename);
 
+phy_phandle = phandle++;
 nodename = g_strdup_printf("/soc/ethernet@%lx",
 (long)memmap[SIFIVE_U_GEM].base);
 qemu_fdt_add_subnode(fdt, nodename);
-qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
+qemu_fdt_setprop_string(fdt, nodename, "compatible",
+"sifive,fu540-c000-gem");
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[SIFIVE_U_GEM].base,
-0x0, memmap[SIFIVE_U_GEM].size);
+0x0, memmap[SIFIVE_U_GEM].size,
+0x0, memmap[SIFIVE_U_GEM_MGMT].base,
+0x0, memmap[SIFIVE_U_GEM_MGMT].size);
 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
+qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
-qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
+qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
 sizeof(ethclk_names));
 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
@@ -264,6 +273,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
 (long)memmap[SIFIVE_U_GEM].base);
 qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 g_free(nodename);
 
@@ -456,6 +466,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, 
Error **errp)
 sysbus_mmio_map(SYS_BUS_DEVICE(>gem), 0, memmap[SIFIVE_U_GEM].base);
 

[Qemu-devel] [PATCH v3 27/28] riscv: virt: Change create_fdt() to return void

[Bin Meng]

There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt. Other machines (sifive_u, spike)
don't do it neither.

Signed-off-by: Bin Meng 
Reviewed-by: Chih-Min Chao 
Reviewed-by: Philippe Mathieu-Daudé 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/virt.c | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2f75195..6bfa721 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -112,7 +112,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
0x1800, 0, 0, 0x7);
 }
 
-static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
+static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 uint64_t mem_size, const char *cmdline)
 {
 void *fdt;
@@ -316,8 +316,6 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 }
 g_free(nodename);
-
-return fdt;
 }
 
 
@@ -373,7 +371,6 @@ static void riscv_virt_board_init(MachineState *machine)
 size_t plic_hart_config_len;
 int i;
 unsigned int smp_cpus = machine->smp.cpus;
-void *fdt;
 
 /* Initialize SOC */
 object_initialize_child(OBJECT(machine), "soc", >soc, sizeof(s->soc),
@@ -392,7 +389,7 @@ static void riscv_virt_board_init(MachineState *machine)
 main_mem);
 
 /* create device tree */
-fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 
 /* boot rom */
 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
@@ -411,9 +408,9 @@ static void riscv_virt_board_init(MachineState *machine)
 hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
);
-qemu_fdt_setprop_cell(fdt, "/chosen",
+qemu_fdt_setprop_cell(s->fdt, "/chosen",
   "linux,initrd-start", start);
-qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
   end);
 }
 }
-- 
2.7.4

[Qemu-devel] [PATCH v3 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes

[Bin Meng]

To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.

Signed-off-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 23 +++
 include/hw/riscv/sifive_u.h |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e071838..f2b711a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -77,6 +77,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 char *nodename;
 char ethclk_names[] = "pclk\0hclk\0tx_clk";
 uint32_t plic_phandle, ethclk_phandle, phandle = 1;
+uint32_t hfclk_phandle, rtcclk_phandle;
 
 fdt = s->fdt = create_device_tree(>fdt_size);
 if (!fdt) {
@@ -95,6 +96,28 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 
+hfclk_phandle = phandle++;
+nodename = g_strdup_printf("/hfclk");
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
+qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
+qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+SIFIVE_U_HFCLK_FREQ);
+qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+g_free(nodename);
+
+rtcclk_phandle = phandle++;
+nodename = g_strdup_printf("/rtcclk");
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
+qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
+qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+SIFIVE_U_RTCCLK_FREQ);
+qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+g_free(nodename);
+
 nodename = g_strdup_printf("/memory@%lx",
 (long)memmap[SIFIVE_U_DRAM].base);
 qemu_fdt_add_subnode(fdt, nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index d0d8528..2b57ffc 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -65,6 +65,8 @@ enum {
 
 enum {
 SIFIVE_U_CLOCK_FREQ = 10,
+SIFIVE_U_HFCLK_FREQ = ,
+SIFIVE_U_RTCCLK_FREQ = 100,
 SIFIVE_U_GEM_CLOCK_FREQ = 12500
 };
 
-- 
2.7.4

[Qemu-devel] [PATCH v3 21/28] riscv: sifive_u: Update UART and ethernet node clock properties

[Bin Meng]

Now that we have added PRCI nodes, update existing UART and ethernet
nodes to use PRCI as their clock sources, to keep in sync with the
Linux kernel device tree.

With above changes, the previously handcrafted "/soc/ethclk" node is
no longer needed. Remove it.

Signed-off-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c  | 21 +
 include/hw/riscv/sifive_u.h  |  3 +--
 include/hw/riscv/sifive_u_prci.h | 10 ++
 3 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 486b247..7eb2b7e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -82,8 +82,8 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 int cpu;
 uint32_t *cells;
 char *nodename;
-char ethclk_names[] = "pclk\0hclk\0tx_clk";
-uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
+char ethclk_names[] = "pclk\0hclk";
+uint32_t plic_phandle, prci_phandle, phandle = 1;
 uint32_t hfclk_phandle, rtcclk_phandle;
 
 fdt = s->fdt = create_device_tree(>fdt_size);
@@ -242,17 +242,6 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 g_free(cells);
 g_free(nodename);
 
-ethclk_phandle = phandle++;
-nodename = g_strdup_printf("/soc/ethclk");
-qemu_fdt_add_subnode(fdt, nodename);
-qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
-qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
-qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
-SIFIVE_U_GEM_CLOCK_FREQ);
-qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
-ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
-g_free(nodename);
-
 nodename = g_strdup_printf("/soc/ethernet@%lx",
 (long)memmap[SIFIVE_U_GEM].base);
 qemu_fdt_add_subnode(fdt, nodename);
@@ -265,7 +254,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
-ethclk_phandle, ethclk_phandle, ethclk_phandle);
+prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
 qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
 sizeof(ethclk_names));
 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
@@ -285,8 +274,8 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[SIFIVE_U_UART0].base,
 0x0, memmap[SIFIVE_U_UART0].size);
-qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
-  SIFIVE_U_CLOCK_FREQ / 2);
+qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+prci_phandle, PRCI_CLK_TLCLK);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 3ae75b5..2a7877e 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -68,8 +68,7 @@ enum {
 enum {
 SIFIVE_U_CLOCK_FREQ = 10,
 SIFIVE_U_HFCLK_FREQ = ,
-SIFIVE_U_RTCCLK_FREQ = 100,
-SIFIVE_U_GEM_CLOCK_FREQ = 12500
+SIFIVE_U_RTCCLK_FREQ = 100
 };
 
 #define SIFIVE_U_MANAGEMENT_CPU_COUNT   1
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h
index f3a4656..640c641 100644
--- a/include/hw/riscv/sifive_u_prci.h
+++ b/include/hw/riscv/sifive_u_prci.h
@@ -87,4 +87,14 @@ typedef struct SiFivePRCIState {
 
 DeviceState *sifive_u_prci_create(hwaddr addr);
 
+/*
+ * Clock indexes for use by Device Tree data and the PRCI driver.
+ *
+ * These values are from sifive-fu540-prci.h in the Linux kernel.
+ */
+#define PRCI_CLK_COREPLL0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL  2
+#define PRCI_CLK_TLCLK  3
+
 #endif /* HW_SIFIVE_U_PRCI_H */
-- 
2.7.4

[Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number

[Bin Meng]

This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.

Signed-off-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 5 +
 include/hw/riscv/sifive_u.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5022b8f..486b247 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,6 +10,7 @@
  * 1) CLINT (Core Level Interruptor)
  * 2) PLIC (Platform Level Interrupt Controller)
  * 3) PRCI (Power, Reset, Clock, Interrupt)
+ * 4) OTP (One-Time Programmable) memory with stored serial number
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -43,6 +44,7 @@
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
+#include "hw/riscv/sifive_u_otp.h"
 #include "hw/riscv/sifive_u_prci.h"
 #include "hw/riscv/boot.h"
 #include "chardev/char.h"
@@ -65,10 +67,12 @@ static const struct MemmapEntry {
 [SIFIVE_U_PRCI] = { 0x1000, 0x1000 },
 [SIFIVE_U_UART0] ={ 0x1001, 0x1000 },
 [SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
+[SIFIVE_U_OTP] =  { 0x1007, 0x1000 },
 [SIFIVE_U_DRAM] = { 0x8000,0x0 },
 [SIFIVE_U_GEM] =  { 0x100900FC, 0x2000 },
 };
 
+#define SIFIVE_OTP_SERIAL   1
 #define GEM_REVISION0x10070109
 
 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
@@ -441,6 +445,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, 
Error **errp)
 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base);
+sifive_u_otp_create(memmap[SIFIVE_U_OTP].base, SIFIVE_OTP_SERIAL);
 
 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index e318ecb..3ae75b5 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -54,6 +54,7 @@ enum {
 SIFIVE_U_PRCI,
 SIFIVE_U_UART0,
 SIFIVE_U_UART1,
+SIFIVE_U_OTP,
 SIFIVE_U_DRAM,
 SIFIVE_U_GEM
 };
-- 
2.7.4

[Qemu-devel] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree

[Bin Meng]

The Linux kernel SiFive UART driver expects an aliases node to be
present in the device tree, from which the driver extracts the port
number from "serial#" in the aliases node.

Signed-off-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7eb2b7e..0c1a89f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -284,6 +284,8 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 if (cmdline) {
 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 }
+qemu_fdt_add_subnode(fdt, "/aliases");
+qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 g_free(nodename);
 }
 
-- 
2.7.4

[Qemu-devel] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540

[Bin Meng]

This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).

Signed-off-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/Makefile.objs   |   1 +
 hw/riscv/sifive_u_prci.c | 163 +++
 include/hw/riscv/sifive_u_prci.h |  90 +
 3 files changed, 254 insertions(+)
 create mode 100644 hw/riscv/sifive_u_prci.c
 create mode 100644 include/hw/riscv/sifive_u_prci.h

diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index c859697..b95bbd5 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
 obj-$(CONFIG_SIFIVE) += sifive_plic.o
 obj-$(CONFIG_SIFIVE) += sifive_test.o
 obj-$(CONFIG_SIFIVE_U) += sifive_u.o
+obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
 obj-$(CONFIG_SIFIVE) += sifive_uart.o
 obj-$(CONFIG_SPIKE) += spike.o
 obj-$(CONFIG_RISCV_VIRT) += virt.o
diff --git a/hw/riscv/sifive_u_prci.c b/hw/riscv/sifive_u_prci.c
new file mode 100644
index 000..35e5962
--- /dev/null
+++ b/hw/riscv/sifive_u_prci.c
@@ -0,0 +1,163 @@
+/*
+ * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt)
+ *
+ * Copyright (c) 2019 Bin Meng 
+ *
+ * Simple model of the PRCI to emulate register reads made by the SDK BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qemu/module.h"
+#include "target/riscv/cpu.h"
+#include "hw/riscv/sifive_u_prci.h"
+
+static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
+{
+SiFivePRCIState *s = opaque;
+
+switch (addr) {
+case SIFIVE_PRCI_HFXOSCCFG:
+return s->hfxosccfg;
+case SIFIVE_PRCI_COREPLLCFG0:
+return s->corepllcfg0;
+case SIFIVE_PRCI_DDRPLLCFG0:
+return s->ddrpllcfg0;
+case SIFIVE_PRCI_DDRPLLCFG1:
+return s->ddrpllcfg1;
+case SIFIVE_PRCI_GEMGXLPLLCFG0:
+return s->gemgxlpllcfg0;
+case SIFIVE_PRCI_GEMGXLPLLCFG1:
+return s->gemgxlpllcfg1;
+case SIFIVE_PRCI_CORECLKSEL:
+return s->coreclksel;
+case SIFIVE_PRCI_DEVICESRESET:
+return s->devicesreset;
+case SIFIVE_PRCI_CLKMUXSTATUS:
+return s->clkmuxstatus;
+}
+
+hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
+return 0;
+}
+
+static void sifive_prci_write(void *opaque, hwaddr addr,
+  uint64_t val64, unsigned int size)
+{
+SiFivePRCIState *s = opaque;
+
+switch (addr) {
+case SIFIVE_PRCI_HFXOSCCFG:
+s->hfxosccfg = (uint32_t) val64;
+/* OSC stays ready */
+s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY;
+break;
+case SIFIVE_PRCI_COREPLLCFG0:
+s->corepllcfg0 = (uint32_t) val64;
+/* internal feedback */
+s->corepllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE;
+/* PLL stays locked */
+s->corepllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK;
+break;
+case SIFIVE_PRCI_DDRPLLCFG0:
+s->ddrpllcfg0 = (uint32_t) val64;
+/* internal feedback */
+s->ddrpllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE;
+/* PLL stays locked */
+s->ddrpllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK;
+break;
+case SIFIVE_PRCI_DDRPLLCFG1:
+s->ddrpllcfg1 = (uint32_t) val64;
+break;
+case SIFIVE_PRCI_GEMGXLPLLCFG0:
+s->gemgxlpllcfg0 = (uint32_t) val64;
+ /* internal feedback */
+s->gemgxlpllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE;
+   /* PLL stays locked */
+s->gemgxlpllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK;
+break;
+case SIFIVE_PRCI_GEMGXLPLLCFG1:
+s->gemgxlpllcfg1 = (uint32_t) val64;
+break;
+case SIFIVE_PRCI_CORECLKSEL:
+s->coreclksel = (uint32_t) val64;
+break;
+case SIFIVE_PRCI_DEVICESRESET:
+s->devicesreset = (uint32_t) val64;
+break;
+case SIFIVE_PRCI_CLKMUXSTATUS:
+s->clkmuxstatus = (uint32_t) val64;
+break;
+default:
+hw_error("%s: bad write: addr=0x%x v=0x%x\n",
+ __func__, (int)addr, (int)val64);
+}
+}
+
+static const MemoryRegionOps sifive_prci_ops = {
+.read = sifive_prci_read,
+.write = sifive_prci_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.valid = {
+.min_access_size = 4,
+.max_access_size = 4
+}
+};
+
+static void sifive_prci_init(Object 

[Qemu-devel] [PATCH v3 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

[Bin Meng]

Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.

Rename the file name to make it clear that it is for sifive_e.

Signed-off-by: Bin Meng 
Reviewed-by: Chih-Min Chao 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/Makefile.objs  |  2 +-
 hw/riscv/sifive_e.c |  4 ++--
 hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 14 +++---
 include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} | 14 +++---
 4 files changed, 17 insertions(+), 17 deletions(-)
 rename hw/riscv/{sifive_prci.c => sifive_e_prci.c} (90%)
 rename include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} (82%)

diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index eb9d4f9..c859697 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -2,9 +2,9 @@ obj-y += boot.o
 obj-$(CONFIG_SPIKE) += riscv_htif.o
 obj-$(CONFIG_HART) += riscv_hart.o
 obj-$(CONFIG_SIFIVE_E) += sifive_e.o
+obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o
 obj-$(CONFIG_SIFIVE) += sifive_clint.o
 obj-$(CONFIG_SIFIVE) += sifive_gpio.o
-obj-$(CONFIG_SIFIVE) += sifive_prci.o
 obj-$(CONFIG_SIFIVE) += sifive_plic.o
 obj-$(CONFIG_SIFIVE) += sifive_test.o
 obj-$(CONFIG_SIFIVE_U) += sifive_u.o
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 2a499d8..2d67670 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -41,9 +41,9 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_clint.h"
-#include "hw/riscv/sifive_prci.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
+#include "hw/riscv/sifive_e_prci.h"
 #include "hw/riscv/boot.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
@@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, 
Error **errp)
 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
-sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
+sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
 
 /* GPIO */
 
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_e_prci.c
similarity index 90%
rename from hw/riscv/sifive_prci.c
rename to hw/riscv/sifive_e_prci.c
index f406682..acb914d 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -1,5 +1,5 @@
 /*
- * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt)
+ * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt)
  *
  * Copyright (c) 2017 SiFive, Inc.
  *
@@ -22,7 +22,7 @@
 #include "hw/sysbus.h"
 #include "qemu/module.h"
 #include "target/riscv/cpu.h"
-#include "hw/riscv/sifive_prci.h"
+#include "hw/riscv/sifive_e_prci.h"
 
 static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
 {
@@ -82,10 +82,10 @@ static const MemoryRegionOps sifive_prci_ops = {
 
 static void sifive_prci_init(Object *obj)
 {
-SiFivePRCIState *s = SIFIVE_PRCI(obj);
+SiFivePRCIState *s = SIFIVE_E_PRCI(obj);
 
 memory_region_init_io(>mmio, obj, _prci_ops, s,
-  TYPE_SIFIVE_PRCI, 0x8000);
+  TYPE_SIFIVE_E_PRCI, 0x8000);
 sysbus_init_mmio(SYS_BUS_DEVICE(obj), >mmio);
 
 s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
@@ -97,7 +97,7 @@ static void sifive_prci_init(Object *obj)
 }
 
 static const TypeInfo sifive_prci_info = {
-.name  = TYPE_SIFIVE_PRCI,
+.name  = TYPE_SIFIVE_E_PRCI,
 .parent= TYPE_SYS_BUS_DEVICE,
 .instance_size = sizeof(SiFivePRCIState),
 .instance_init = sifive_prci_init,
@@ -114,9 +114,9 @@ type_init(sifive_prci_register_types)
 /*
  * Create PRCI device.
  */
-DeviceState *sifive_prci_create(hwaddr addr)
+DeviceState *sifive_e_prci_create(hwaddr addr)
 {
-DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI);
+DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI);
 qdev_init_nofail(dev);
 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 return dev;
diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_e_prci.h
similarity index 82%
rename from include/hw/riscv/sifive_prci.h
rename to include/hw/riscv/sifive_e_prci.h
index bd51c4a..7932fe7 100644
--- a/include/hw/riscv/sifive_prci.h
+++ b/include/hw/riscv/sifive_e_prci.h
@@ -1,5 +1,5 @@
 /*
- * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface
+ * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
  *
  * Copyright (c) 2017 SiFive, Inc.
  *
@@ -16,8 +16,8 @@
  * this program.  If not, see .
  */
 
-#ifndef HW_SIFIVE_PRCI_H
-#define HW_SIFIVE_PRCI_H
+#ifndef HW_SIFIVE_E_PRCI_H
+#define HW_SIFIVE_E_PRCI_H
 
 enum {
 SIFIVE_PRCI_HFROSCCFG   = 0x0,
@@ -47,10 +47,10 @@ enum {
 SIFIVE_PRCI_PLLOUTDIV_DIV1  = (1 << 8)
 };
 
-#define TYPE_SIFIVE_PRCI "riscv.sifive.prci"
+#define TYPE_SIFIVE_E_PRCI  

[Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size

[Bin Meng]

Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.

Signed-off-by: Bin Meng 
Reviewed-by: Chih-Min Chao 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_e_prci.c | 2 +-
 include/hw/riscv/sifive_e_prci.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index c906f11..4cbce48 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -85,7 +85,7 @@ static void sifive_prci_init(Object *obj)
 SiFivePRCIState *s = SIFIVE_E_PRCI(obj);
 
 memory_region_init_io(>mmio, obj, _prci_ops, s,
-  TYPE_SIFIVE_E_PRCI, 0x8000);
+  TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE);
 sysbus_init_mmio(SYS_BUS_DEVICE(obj), >mmio);
 
 s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h
index 7932fe7..81e506b 100644
--- a/include/hw/riscv/sifive_e_prci.h
+++ b/include/hw/riscv/sifive_e_prci.h
@@ -47,6 +47,8 @@ enum {
 SIFIVE_PRCI_PLLOUTDIV_DIV1  = (1 << 8)
 };
 
+#define SIFIVE_E_PRCI_REG_SIZE  0x1000
+
 #define TYPE_SIFIVE_E_PRCI  "riscv.sifive.e.prci"
 
 #define SIFIVE_E_PRCI(obj) \
-- 
2.7.4

[Qemu-devel] [PATCH v3 18/28] riscv: hw: Implement a model for SiFive FU540 OTP

[Bin Meng]

This implements a simple model for SiFive FU540 OTP (One-Time
Programmable) Memory interface, primarily for reading out the
stored serial number from the first 1 KiB of the 16 KiB OTP
memory reserved by SiFive for internal use.

Signed-off-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/Makefile.objs  |   1 +
 hw/riscv/sifive_u_otp.c | 194 
 include/hw/riscv/sifive_u_otp.h |  90 +++
 3 files changed, 285 insertions(+)
 create mode 100644 hw/riscv/sifive_u_otp.c
 create mode 100644 include/hw/riscv/sifive_u_otp.h

diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index b95bbd5..fc3c6dd 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
 obj-$(CONFIG_SIFIVE) += sifive_plic.o
 obj-$(CONFIG_SIFIVE) += sifive_test.o
 obj-$(CONFIG_SIFIVE_U) += sifive_u.o
+obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o
 obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
 obj-$(CONFIG_SIFIVE) += sifive_uart.o
 obj-$(CONFIG_SPIKE) += spike.o
diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c
new file mode 100644
index 000..f21d9f4
--- /dev/null
+++ b/hw/riscv/sifive_u_otp.c
@@ -0,0 +1,194 @@
+/*
+ * QEMU SiFive U OTP (One-Time Programmable) Memory interface
+ *
+ * Copyright (c) 2019 Bin Meng 
+ *
+ * Simple model of the OTP to emulate register reads made by the SDK BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qemu/module.h"
+#include "target/riscv/cpu.h"
+#include "hw/riscv/sifive_u_otp.h"
+
+static uint64_t sifive_otp_read(void *opaque, hwaddr addr, unsigned int size)
+{
+SiFiveOTPState *s = opaque;
+
+switch (addr) {
+case SIFIVE_OTP_PA:
+return s->pa;
+case SIFIVE_OTP_PAIO:
+return s->paio;
+case SIFIVE_OTP_PAS:
+return s->pas;
+case SIFIVE_OTP_PCE:
+return s->pce;
+case SIFIVE_OTP_PCLK:
+return s->pclk;
+case SIFIVE_OTP_PDIN:
+return s->pdin;
+case SIFIVE_OTP_PDOUT:
+if ((s->pce & SIFIVE_OTP_PCE_EN) &&
+(s->pdstb & SIFIVE_OTP_PDSTB_EN) &&
+(s->ptrim & SIFIVE_OTP_PTRIM_EN)) {
+return s->fuse[s->pa & SIFIVE_OTP_PA_MASK];
+} else {
+return 0xff;
+}
+case SIFIVE_OTP_PDSTB:
+return s->pdstb;
+case SIFIVE_OTP_PPROG:
+return s->pprog;
+case SIFIVE_OTP_PTC:
+return s->ptc;
+case SIFIVE_OTP_PTM:
+return s->ptm;
+case SIFIVE_OTP_PTM_REP:
+return s->ptm_rep;
+case SIFIVE_OTP_PTR:
+return s->ptr;
+case SIFIVE_OTP_PTRIM:
+return s->ptrim;
+case SIFIVE_OTP_PWE:
+return s->pwe;
+}
+
+hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
+return 0;
+}
+
+static void sifive_otp_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+SiFiveOTPState *s = opaque;
+
+switch (addr) {
+case SIFIVE_OTP_PA:
+s->pa = (uint32_t) val64 & SIFIVE_OTP_PA_MASK;
+break;
+case SIFIVE_OTP_PAIO:
+s->paio = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PAS:
+s->pas = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PCE:
+s->pce = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PCLK:
+s->pclk = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PDIN:
+s->pdin = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PDOUT:
+/* read-only */
+break;
+case SIFIVE_OTP_PDSTB:
+s->pdstb = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PPROG:
+s->pprog = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PTC:
+s->ptc = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PTM:
+s->ptm = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PTM_REP:
+s->ptm_rep = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PTR:
+s->ptr = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PTRIM:
+s->ptrim = (uint32_t) val64;
+break;
+case SIFIVE_OTP_PWE:
+s->pwe = (uint32_t) val64;
+break;
+default:
+hw_error("%s: bad write: addr=0x%x v=0x%x\n",
+ __func__, (int)addr, (int)val64);
+}
+}
+
+static const MemoryRegionOps 

[Qemu-devel] [PATCH v3 17/28] riscv: sifive_u: Change UART node name in device tree

[Bin Meng]

OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing U-Boot fail to find the serial node in DT.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index c0b7498..5022b8f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -274,7 +274,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 g_free(nodename);
 
-nodename = g_strdup_printf("/soc/uart@%lx",
+nodename = g_strdup_printf("/soc/serial@%lx",
 (long)memmap[SIFIVE_U_UART0].base);
 qemu_fdt_add_subnode(fdt, nodename);
 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
-- 
2.7.4

[Qemu-devel] [PATCH v3 08/28] riscv: sifive_u: Update PLIC hart topology configuration string

[Bin Meng]

With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.

Suggested-by: Fabien Chouteau 
Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f8ffc0b..16ab95c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -373,10 +373,11 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, 
Error **errp)
 plic_hart_config = g_malloc0(plic_hart_config_len);
 for (i = 0; i < ms->smp.cpus; i++) {
 if (i != 0) {
-strncat(plic_hart_config, ",", plic_hart_config_len);
+strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
+plic_hart_config_len);
+} else {
+strncat(plic_hart_config, "M", plic_hart_config_len);
 }
-strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
-plic_hart_config_len);
 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
 }
 
-- 
2.7.4

[Qemu-devel] [PATCH v3 16/28] riscv: sifive_u: Add PRCI block to the SoC

[Bin Meng]

Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.

Signed-off-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 21 -
 include/hw/riscv/sifive_u.h |  1 +
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f2b711a..c0b7498 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -9,6 +9,7 @@
  * 0) UART
  * 1) CLINT (Core Level Interruptor)
  * 2) PLIC (Platform Level Interrupt Controller)
+ * 3) PRCI (Power, Reset, Clock, Interrupt)
  *
  * This board currently generates devicetree dynamically that indicates at 
least
  * two harts and up to five harts.
@@ -42,6 +43,7 @@
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
+#include "hw/riscv/sifive_u_prci.h"
 #include "hw/riscv/boot.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
@@ -60,6 +62,7 @@ static const struct MemmapEntry {
 [SIFIVE_U_MROM] = { 0x1000,0x11000 },
 [SIFIVE_U_CLINT] ={  0x200,0x1 },
 [SIFIVE_U_PLIC] = {  0xc00,  0x400 },
+[SIFIVE_U_PRCI] = { 0x1000, 0x1000 },
 [SIFIVE_U_UART0] ={ 0x1001, 0x1000 },
 [SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
 [SIFIVE_U_DRAM] = { 0x8000,0x0 },
@@ -76,7 +79,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 uint32_t *cells;
 char *nodename;
 char ethclk_names[] = "pclk\0hclk\0tx_clk";
-uint32_t plic_phandle, ethclk_phandle, phandle = 1;
+uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
 uint32_t hfclk_phandle, rtcclk_phandle;
 
 fdt = s->fdt = create_device_tree(>fdt_size);
@@ -183,6 +186,21 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 g_free(cells);
 g_free(nodename);
 
+prci_phandle = phandle++;
+nodename = g_strdup_printf("/soc/clock-controller@%lx",
+(long)memmap[SIFIVE_U_PRCI].base);
+qemu_fdt_add_subnode(fdt, nodename);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
+qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+hfclk_phandle, rtcclk_phandle);
+qemu_fdt_setprop_cells(fdt, nodename, "reg",
+0x0, memmap[SIFIVE_U_PRCI].base,
+0x0, memmap[SIFIVE_U_PRCI].size);
+qemu_fdt_setprop_string(fdt, nodename, "compatible",
+"sifive,fu540-c000-prci");
+g_free(nodename);
+
 plic_phandle = phandle++;
 cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4 - 2);
 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
@@ -422,6 +440,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, 
Error **errp)
 sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
+sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base);
 
 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 2b57ffc..e318ecb 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -51,6 +51,7 @@ enum {
 SIFIVE_U_MROM,
 SIFIVE_U_CLINT,
 SIFIVE_U_PLIC,
+SIFIVE_U_PRCI,
 SIFIVE_U_UART0,
 SIFIVE_U_UART1,
 SIFIVE_U_DRAM,
-- 
2.7.4

[Qemu-devel] [PATCH v3 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC

[Bin Meng]

The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
and pass "cpu-type" to populate heterogeneous harts.

The cpu nodes in the generated DTS have been updated as well.

Signed-off-by: Bin Meng 

---

Changes in v3:
- changed to use macros for management and compute cpu count

Changes in v2:
- fixed the "interrupts-extended" property size

 hw/riscv/sifive_u.c | 40 +++-
 include/hw/riscv/sifive_u.h |  3 +++
 2 files changed, 30 insertions(+), 13 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 623ee64..295ca77 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,7 +10,8 @@
  * 1) CLINT (Core Level Interruptor)
  * 2) PLIC (Platform Level Interrupt Controller)
  *
- * This board currently uses a hardcoded devicetree that indicates one hart.
+ * This board currently generates devicetree dynamically that indicates at most
+ * five harts.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -26,6 +27,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/cutils.h"
 #include "qemu/log.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
@@ -117,7 +119,10 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_add_subnode(fdt, nodename);
 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
   SIFIVE_U_CLOCK_FREQ);
-qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
+/* cpu 0 is the management hart that does not have mmu */
+if (cpu != 0) {
+qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
+}
 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
@@ -157,15 +162,21 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 g_free(nodename);
 
 plic_phandle = phandle++;
-cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
+cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4 - 2);
 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
 nodename =
 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
-cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
-cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
-cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
-cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+/* cpu 0 is the management hart that does not have S-mode */
+if (cpu == 0) {
+cells[0] = cpu_to_be32(intc_phandle);
+cells[1] = cpu_to_be32(IRQ_M_EXT);
+} else {
+cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
+cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
+cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
+cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
+}
 g_free(nodename);
 }
 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
@@ -175,7 +186,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
-cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
+cells, (s->soc.cpus.num_harts * 4 - 2) * sizeof(uint32_t));
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[SIFIVE_U_PLIC].base,
 0x0, memmap[SIFIVE_U_PLIC].size);
@@ -315,10 +326,16 @@ static void riscv_sifive_u_soc_init(Object *obj)
 {
 MachineState *ms = MACHINE(qdev_get_machine());
 SiFiveUSoCState *s = RISCV_U_SOC(obj);
+char cpu_type[64];
+
+/* create cpu type representing SiFive FU540 SoC */
+pstrcpy(cpu_type, sizeof(cpu_type), SIFIVE_E_CPU);
+pstrcat(cpu_type, sizeof(cpu_type), ",");
+pstrcat(cpu_type, sizeof(cpu_type), SIFIVE_U_CPU);
 
 object_initialize_child(obj, "cpus", >cpus, sizeof(s->cpus),
 TYPE_RISCV_HART_ARRAY, _abort, NULL);
-object_property_set_str(OBJECT(>cpus), SIFIVE_U_CPU, "cpu-type",
+object_property_set_str(OBJECT(>cpus), cpu_type, "cpu-type",
 _abort);
 object_property_set_int(OBJECT(>cpus), ms->smp.cpus, "num-harts",
 _abort);
@@ -407,10 +424,7 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
 {
 mc->desc = "RISC-V Board compatible with SiFive U SDK";
 mc->init = riscv_sifive_u_init;
-/* The real hardware has 5 

[Qemu-devel] [PATCH v3 10/28] riscv: sifive_u: Remove the unnecessary include of prci header

[Bin Meng]

sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f24ec2e..e071838 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -41,7 +41,6 @@
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
-#include "hw/riscv/sifive_prci.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
 #include "chardev/char.h"
-- 
2.7.4

[Qemu-devel] [PATCH v3 09/28] riscv: sifive_u: Update UART base addresses and IRQs

[Bin Meng]

This updates the UART base address and IRQs to match the hardware.

Signed-off-by: Bin Meng 
Reviewed-by: Jonathan Behrens 
Acked-by: Alistair Francis 
Reviewed-by: Chih-Min Chao 

---

Changes in v3:
- update IRQ numbers of both UARTs to match hardware as well

Changes in v2: None

 hw/riscv/sifive_u.c | 4 ++--
 include/hw/riscv/sifive_u.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 16ab95c..f24ec2e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -61,8 +61,8 @@ static const struct MemmapEntry {
 [SIFIVE_U_MROM] = { 0x1000,0x11000 },
 [SIFIVE_U_CLINT] ={  0x200,0x1 },
 [SIFIVE_U_PLIC] = {  0xc00,  0x400 },
-[SIFIVE_U_UART0] ={ 0x10013000, 0x1000 },
-[SIFIVE_U_UART1] ={ 0x10023000, 0x1000 },
+[SIFIVE_U_UART0] ={ 0x1001, 0x1000 },
+[SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
 [SIFIVE_U_DRAM] = { 0x8000,0x0 },
 [SIFIVE_U_GEM] =  { 0x100900FC, 0x2000 },
 };
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 650bc4c..d0d8528 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -58,8 +58,8 @@ enum {
 };
 
 enum {
-SIFIVE_U_UART0_IRQ = 3,
-SIFIVE_U_UART1_IRQ = 4,
+SIFIVE_U_UART0_IRQ = 4,
+SIFIVE_U_UART1_IRQ = 5,
 SIFIVE_U_GEM_IRQ = 0x35
 };
 
-- 
2.7.4

[Qemu-devel] [PATCH v3 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming

[Bin Meng]

It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN
for hfxosccfg register programming.

Signed-off-by: Bin Meng 
Acked-by: Alistair Francis 
Reviewed-by: Chih-Min Chao 
Reviewed-by: Philippe Mathieu-Daudé 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_e_prci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index acb914d..c906f11 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -89,7 +89,7 @@ static void sifive_prci_init(Object *obj)
 sysbus_init_mmio(SYS_BUS_DEVICE(obj), >mmio);
 
 s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
-s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
+s->hfxosccfg = (SIFIVE_PRCI_HFXOSCCFG_RDY | SIFIVE_PRCI_HFXOSCCFG_EN);
 s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
 SIFIVE_PRCI_PLLCFG_LOCK);
 s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
-- 
2.7.4

[Qemu-devel] [PATCH v3 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell

[Bin Meng]

Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 16 
 hw/riscv/virt.c | 24 
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ef36948..623ee64 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -182,7 +182,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
-qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(cells);
 g_free(nodename);
@@ -207,20 +207,20 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 0x0, memmap[SIFIVE_U_GEM].size);
 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
-qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 ethclk_phandle, ethclk_phandle, ethclk_phandle);
 qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
 sizeof(ethclk_names));
-qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
-qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
+qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
+qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 g_free(nodename);
 
 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
 (long)memmap[SIFIVE_U_GEM].base);
 qemu_fdt_add_subnode(fdt, nodename);
-qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
+qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 g_free(nodename);
 
 nodename = g_strdup_printf("/soc/uart@%lx",
@@ -232,8 +232,8 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 0x0, memmap[SIFIVE_U_UART0].size);
 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
   SIFIVE_U_CLOCK_FREQ / 2);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 
 qemu_fdt_add_subnode(fdt, "/chosen");
 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 00be05a..127f005 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -233,8 +233,8 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 (long)memmap[VIRT_PLIC].base);
 qemu_fdt_add_subnode(fdt, nodename);
-qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
-   FDT_PLIC_ADDR_CELLS);
+qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
+  FDT_PLIC_ADDR_CELLS);
 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
   FDT_PLIC_INT_CELLS);
 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
@@ -247,7 +247,7 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
-qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(cells);
 g_free(nodename);
@@ -260,19 +260,19 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cells(fdt, nodename, "reg",
 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 0x0, memmap[VIRT_VIRTIO].size);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", 
plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
+qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+qemu_fdt_setprop_cell(fdt, nodename, 

[Qemu-devel] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population

[Bin Meng]

At present we only allow symmetric harts to be created. In order to
support heterogeneous harts like SiFive FU540, update hart array's
"cpu-type" property to allow cpu type to be set per hart, separated
by delimiter ",". The frist cpu type before the delimiter is assigned
to hart 0, and the second cpu type before delimiter is assigned to
hart 1, and so on.

If the total number of cpu types supplied in "cpu-type" property is
less than number of maximum harts, the last cpu type in the property
will be used to populate remaining harts.

Signed-off-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/riscv_hart.c | 48 +---
 1 file changed, 45 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 3dd1c6a..27093e0 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -58,13 +58,55 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int 
hart,
 static void riscv_harts_realize(DeviceState *dev, Error **errp)
 {
 RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
-int n;
+char *cpu_types;
+char *first_type, *last_type, *tmp_type;
+int n = 0;
 
 s->harts = g_new0(RISCVCPU, s->num_harts);
 
-for (n = 0; n < s->num_harts; n++) {
-riscv_hart_realize(s, n, s->cpu_type, errp);
+/* we should not touch the original s->cpu_type */
+cpu_types = g_strdup(s->cpu_type);
+
+/*
+ * Expect s->cpu_type property was initialized this way:
+ *
+ * "cpu-type-a": symmetric harts
+ * "cpu-type-a,cpu-type-b,cpu-type-c": heterogeneous harts
+ *
+ * For heterogeneous harts, hart cpu types are separated by delimiter ",".
+ * The frist cpu type before the delimiter is assigned to hart 0, and the
+ * second cpu type before delimiter is assigned to hart 1, and so on.
+ *
+ * If the total number of cpu types is less than s->num_harts, the last
+ * cpu type in s->cpu_type will be used to populate remaining harts.
+ */
+
+first_type = strtok(cpu_types, ",");
+riscv_hart_realize(s, n++, first_type, errp);
+tmp_type = strtok(NULL, ",");
+if (!tmp_type) {
+/* symmetric harts */
+for (; n < s->num_harts; n++) {
+riscv_hart_realize(s, n, first_type, errp);
+   }
+} else {
+/* heterogeneous harts */
+while (tmp_type) {
+if (n >= s->num_harts) {
+break;
+}
+riscv_hart_realize(s, n++, tmp_type, errp);
+last_type = tmp_type;
+tmp_type = strtok(NULL, ",");
+}
+
+/* populate remaining harts using the last cpu type in s->cpu_type */
+for (; n < s->num_harts; n++) {
+riscv_hart_realize(s, n, last_type, errp);
+}
 }
+
+g_free(cpu_types);
 }
 
 static void riscv_harts_class_init(ObjectClass *klass, void *data)
-- 
2.7.4

[Qemu-devel] [PATCH v3 07/28] riscv: sifive_u: Set the minimum number of cpus to 2

[Bin Meng]

It is not useful if we only have one management CPU.

Signed-off-by: Bin Meng 

---

Changes in v3:
- use management cpu count + 1 for the min_cpus

Changes in v2:
- update the file header to indicate at least 2 harts are created

 hw/riscv/sifive_u.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 295ca77..f8ffc0b 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,8 +10,8 @@
  * 1) CLINT (Core Level Interruptor)
  * 2) PLIC (Platform Level Interrupt Controller)
  *
- * This board currently generates devicetree dynamically that indicates at most
- * five harts.
+ * This board currently generates devicetree dynamically that indicates at 
least
+ * two harts and up to five harts.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -425,6 +425,7 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
 mc->desc = "RISC-V Board compatible with SiFive U SDK";
 mc->init = riscv_sifive_u_init;
 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
+mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
 }
 
 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
-- 
2.7.4

[Qemu-devel] [PATCH v3 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines

[Bin Meng]

Group SiFive E and U cpu type defines into one header file.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
Reviewed-by: Philippe Mathieu-Daudé 
---

Changes in v3: None
Changes in v2: None

 include/hw/riscv/sifive_cpu.h | 31 +++
 include/hw/riscv/sifive_e.h   |  7 +--
 include/hw/riscv/sifive_u.h   |  7 +--
 3 files changed, 33 insertions(+), 12 deletions(-)
 create mode 100644 include/hw/riscv/sifive_cpu.h

diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
new file mode 100644
index 000..1367996
--- /dev/null
+++ b/include/hw/riscv/sifive_cpu.h
@@ -0,0 +1,31 @@
+/*
+ * SiFive CPU types
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2019 Bin Meng 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#ifndef HW_SIFIVE_CPU_H
+#define HW_SIFIVE_CPU_H
+
+#if defined(TARGET_RISCV32)
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
+#elif defined(TARGET_RISCV64)
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
+#endif
+
+#endif /* HW_SIFIVE_CPU_H */
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index d175b24..e17cdfd 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -19,6 +19,7 @@
 #ifndef HW_SIFIVE_E_H
 #define HW_SIFIVE_E_H
 
+#include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_gpio.h"
 
 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
@@ -83,10 +84,4 @@ enum {
 #define SIFIVE_E_PLIC_CONTEXT_BASE 0x20
 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
 
-#if defined(TARGET_RISCV32)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
-#endif
-
 #endif
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 892f0ee..4abc621 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -20,6 +20,7 @@
 #define HW_SIFIVE_U_H
 
 #include "hw/net/cadence_gem.h"
+#include "hw/riscv/sifive_cpu.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
@@ -77,10 +78,4 @@ enum {
 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x20
 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
 
-#if defined(TARGET_RISCV32)
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
-#endif
-
 #endif
-- 
2.7.4

[Qemu-devel] [PATCH v3 04/28] riscv: hart: Extract hart realize to a separate routine

[Bin Meng]

Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create symmetric harts. Exact the
hart realize to a separate routine in preparation for supporting
heterogeneous hart arrays.

Signed-off-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/riscv_hart.c | 31 +++
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index ca69a1b..3dd1c6a 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -37,26 +37,33 @@ static void riscv_harts_cpu_reset(void *opaque)
 cpu_reset(CPU(cpu));
 }
 
+static void riscv_hart_realize(RISCVHartArrayState *s, int hart,
+   char *cpu_type, Error **errp)
+{
+Error *err = NULL;
+
+object_initialize_child(OBJECT(s), "harts[*]", >harts[hart],
+sizeof(RISCVCPU), cpu_type,
+_abort, NULL);
+s->harts[hart].env.mhartid = hart;
+qemu_register_reset(riscv_harts_cpu_reset, >harts[hart]);
+object_property_set_bool(OBJECT(>harts[hart]), true,
+ "realized", );
+if (err) {
+error_propagate(errp, err);
+return;
+}
+}
+
 static void riscv_harts_realize(DeviceState *dev, Error **errp)
 {
 RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
-Error *err = NULL;
 int n;
 
 s->harts = g_new0(RISCVCPU, s->num_harts);
 
 for (n = 0; n < s->num_harts; n++) {
-object_initialize_child(OBJECT(s), "harts[*]", >harts[n],
-sizeof(RISCVCPU), s->cpu_type,
-_abort, NULL);
-s->harts[n].env.mhartid = n;
-qemu_register_reset(riscv_harts_cpu_reset, >harts[n]);
-object_property_set_bool(OBJECT(>harts[n]), true,
- "realized", );
-if (err) {
-error_propagate(errp, err);
-return;
-}
+riscv_hart_realize(s, n, s->cpu_type, errp);
 }
 }
 
-- 
2.7.4

[Qemu-devel] [PATCH v3 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine

[Bin Meng]

As of today, the QEMU 'sifive_u' machine is a special target that does
not boot the upstream OpenSBI/U-Boot firmware images built for the real
SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform
"qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced
in the OpenSBI doc as its payload, but that does not boot at all due
to various issues in current QEMU 'sifive_u' machine codes.

This series aims to improve the emulation fidelity of sifive_u machine,
so that the upstream OpenSBI, U-Boot and kernel images built for the
SiFive HiFive Unleashed board can be used out of the box without any
special hack.

The major changes include:
- Heterogeneous harts creation supported, so that we can create a CPU
  that exactly mirrors the real hardware: 1 E51 + 4 U54.
- Implemented a PRCI model for FU540
- Implemented an OTP model for FU540, primarily used for storing serial
  number of the board
- Fixed GEM support that was seriously broken on sifive_u
- Synced device tree with upstream Linux kernel on sifive_u
- Adding initramfs loading support on sifive_u

OpenSBI v0.4 image built for sifive/fu540 is included as the default
bios image for 'sifive_u' machine.

The series is tested against OpenSBI v0.4 image for sifive/fu540
paltform, U-Boot v2019.10-rc1 image for sifive_fu540_defconfig,
and Linux kernel v5.3-rc3 image with the following patch:

macb: Update compatibility string for SiFive FU540-C000
https://patchwork.kernel.org/patch/11050003/

OpenSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well.
Boot Linux 64-bit defconfig image, verified that system console on
the serial 0 and ping host work pretty well.

An OpenSBI patch was sent to drop the special "qemu/sifive_u" platform
support in OpenSBI. It will be applied after this QEMU series is merged.
http://lists.infradead.org/pipermail/opensbi/2019-August/000335.html

Changes in v3:
- changed to use macros for management and compute cpu count
- use management cpu count + 1 for the min_cpus
- update IRQ numbers of both UARTs to match hardware as well

Changes in v2:
- fixed the "interrupts-extended" property size
- update the file header to indicate at least 2 harts are created
- use create_unimplemented_device() to create the GEM management
  block instead of sifive_mmio_emulate()
- add "phy-handle" property to the ethernet node
- keep the PLIC compatible string unchanged as OpenSBI uses that
  for DT fix up
- drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common place"
- new patch "riscv: sifive_e: Drop sifive_mmio_emulate()"

Bin Meng (28):
  riscv: hw: Remove superfluous "linux,phandle" property
  riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
  riscv: Add a sifive_cpu.h to include both E and U cpu type defines
  riscv: hart: Extract hart realize to a separate routine
  riscv: hart: Support heterogeneous harts population
  riscv: sifive_u: Update hart configuration to reflect the real FU540
SoC
  riscv: sifive_u: Set the minimum number of cpus to 2
  riscv: sifive_u: Update PLIC hart topology configuration string
  riscv: sifive_u: Update UART base addresses and IRQs
  riscv: sifive_u: Remove the unnecessary include of prci header
  riscv: sifive: Rename sifive_prci.{c,h} to sifive_e_prci.{c,h}
  riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
  riscv: sifive_e: prci: Update the PRCI register block size
  riscv: sifive: Implement PRCI model for FU540
  riscv: sifive_u: Generate hfclk and rtcclk nodes
  riscv: sifive_u: Add PRCI block to the SoC
  riscv: sifive_u: Change UART node name in device tree
  riscv: hw: Implement a model for SiFive FU540 OTP
  riscv: sifive_u: Instantiate OTP memory with a serial number
  riscv: roms: Update default bios for sifive_u machine
  riscv: sifive_u: Update UART and ethernet node clock properties
  riscv: sifive_u: Generate an aliases node in the device tree
  riscv: sifive_u: Fix broken GEM support
  riscv: sifive_u: Support loading initramfs
  riscv: hw: Remove not needed PLIC properties in device tree
  riscv: sifive_e: Drop sifive_mmio_emulate()
  riscv: virt: Change create_fdt() to return void
  riscv: sifive_u: Update model and compatible strings in device tree

 hw/riscv/Makefile.objs |   4 +-
 hw/riscv/riscv_hart.c  |  75 ++--
 hw/riscv/sifive_e.c|  27 ++-
 hw/riscv/{sifive_prci.c => sifive_e_prci.c}|  16 +-
 hw/riscv/sifive_u.c| 185 ++--
 hw/riscv/sifive_u_otp.c| 194 +
 hw/riscv/sifive_u_prci.c   | 163 +
 hw/riscv/virt.c|  40 ++---
 include/hw/riscv/sifive_cpu.h  |  31 
 include/hw/riscv/sifive_e.h|   7 +-
 .../hw/riscv/{sifive_prci.h => sifive_e_prci.h}|  16 +-
 include/hw/riscv/sifive_u.h 

[Qemu-devel] [PATCH v3 01/28] riscv: hw: Remove superfluous "linux, phandle" property

[Bin Meng]

"linux,phandle" property is optional. Remove all instances in the
sifive_u and virt machine device tree.

Signed-off-by: Bin Meng 
Reviewed-by: Alistair Francis 
---

Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c | 3 ---
 hw/riscv/virt.c | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 71b8083..ef36948 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -125,7 +125,6 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 qemu_fdt_add_subnode(fdt, intc);
 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
-qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
@@ -184,7 +183,6 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
 qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(cells);
 g_free(nodename);
@@ -197,7 +195,6 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 SIFIVE_U_GEM_CLOCK_FREQ);
 qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
-qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle);
 ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(nodename);
 
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 25faf3b..00be05a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -170,11 +170,9 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
-qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle);
 intc_phandle = phandle++;
 qemu_fdt_add_subnode(fdt, intc);
 qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
-qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle);
 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
@@ -250,7 +248,6 @@ static void *create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
 qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
-qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 g_free(cells);
 g_free(nodename);
-- 
2.7.4

[Qemu-devel] [Bug 1811533] Re: Unstable Win10 guest with qemu 3.1 + huge pages + hv_stimer

[Žilvinas Žaltiena]

Other users are having similar issues:
https://github.com/virtio-win/kvm-guest-drivers-windows/issues/402
https://www.reddit.com/r/VFIO/comments/cc2473/virtio_network_drivers_failing_on_win10_guest/etk6f6i/


** Bug watch added: github.com/virtio-win/kvm-guest-drivers-windows/issues #402
   https://github.com/virtio-win/kvm-guest-drivers-windows/issues/402

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1811533

Title:
  Unstable Win10 guest with qemu 3.1 + huge pages + hv_stimer

Status in QEMU:
  Confirmed

Bug description:
  Host:
  Gentoo linux x86_64, kernel 4.20.1
  Qemu 3.1.0 
  CPU: Intel i7 6850K
  Chipset: X99

  Guest:
  Windows 10 Pro 64bit (1809)
  Machine type: pc-q35_3.1
  Hyper-V enlightenments: 
hv_stimer,hv_reenlightenment,hv_frequencies,hv_vapic,hv_reset,hv_synic,hv_runtime,hv_vpindex,hv_time,hv_relaxed,hv_spinlocks=0x1fff
  Memory: 16GB backed by 2MB huge pages

  Issue:
  Once guest is started, log gets flooded with:

  qemu-system-x86_64: vhost_region_add_section: Overlapping but not
  coherent sections at 103000

  or

  qemu-system-x86_64: vhost_region_add_section:Section rounded to 0
  prior to previous 1f000

  (line endings change)

  and as time goes guest loses network access (virtio-net-pci) and
  general performance diminishes to extent of freezing applications.

  Observations:
  1) problem disappears when hv_stimer is removed
  2) problem disappears when memory backing with huge pages is disabled
  3) problem disappears when machine type is downgraded to pc-q35_3.0

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1811533/+subscriptions

Re: [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios

[Bin Meng]

Hi Palmer,

On Tue, Aug 6, 2019 at 1:04 AM Alistair Francis  wrote:
>
> On Fri, Aug 2, 2019 at 11:08 PM Bin Meng  wrote:
> >
> > Currently the make rules are wrongly using qemu/virt opensbi image
> > for sifive_u machine. Correct it.
> >
> > Signed-off-by: Bin Meng 
>
> Good catch.
>
> @Palmer Dabbelt can you take this for 4.1?
>

Is this patch merged for 4.1? Thanks!

> Reviewed-by: Alistair Francis 
>

Regards,
Bin

Re: [Qemu-devel] [RFC PATCH 1/6] utils/python_api: add scripting interface for Qemu with python lib

[Balamuruhan S]

On 8/8/19 3:39 PM, Stefan Hajnoczi wrote:
> On Wed, Aug 07, 2019 at 12:44:40PM +0530, Balamuruhan S wrote:
>> +void python_args_init_cast_int(char *args[], int arg, int pos)
>> +{
>> +args[pos]= malloc(sizeof(int));
>> +sprintf(args[pos], "%d", arg);
>> +}
> This is broken.  args[pos] is a (possibly NULL) pointer to 4 bytes.
> sprintf() will buffer overflow if arg has more than 3 digits.
>
> A correct way to do this is:
>
>   args[pos] = g_strdup_printf("%d", arg);

Thanks for correcting it.

>
>> +void python_args_init_cast_long(char *args[], uint64_t arg, int pos)
>> +{
>> +args[pos]= g_malloc(sizeof(uint64_t) * 2);
>> +sprintf(args[pos], "%lx", arg);
>> +}
> Same issue.
>
>> +void python_args_clean(char *args[], int nargs)
>> +{
>> +for (int i = 0; i < nargs; i++) {
>> +g_free(args[i]);
>> +}
>> +}
> Mixing malloc() and g_free() is unsafe.  If you switch to
> g_strdup_printf() then g_free() is correct.

sure, I will fix it.

Re: [Qemu-devel] [RFC PATCH 3/6] hw/ppc/pnv_homer: add homer/occ common area emulation for PowerNV

[Balamuruhan S]

On 8/9/19 10:14 AM, David Gibson wrote:
> On Wed, Aug 07, 2019 at 09:54:55AM +0200, Cédric Le Goater wrote:
>> On 07/08/2019 09:14, Balamuruhan S wrote:
>>> Add mmio callback functions to enable homer/occ common area
>>> to emulate pstate table, occ-sensors, slw, occ static and
>>> dynamic values for Power8 and Power9 chips. It also works for
>>> multiple chips as offset remains the same whereas the base
>>> address are handled appropriately while initializing device
>>> tree.
>>>
>>> currently skiboot disables the homer/occ code path with
>>> `QUIRK_NO_PBA`, this quirk have to be removed in skiboot
>>> for it to use this infrastructure.
>>
>> I think this patch can come before the others as it is adding
>> support without the python extra facilities.
> Right.  In fact it seems to me having it as an entirely separate
> series would be preferable.  I don't think we want to tie review of a
> basic OCC extension to to the frankly not all that palatable idea of
> adding arbitrary scripting into the MMIO path.

sure, I will send them as separate series. But the idea is to demonstrate
how the scripting interface can be added and to leverage it and I can
get feedback/suggestions to correct/improve it.

>
>> Some comments below, 
>>  
>>> Signed-off-by: Hariharan T.S 
>>> Signed-off-by: Balamuruhan S 
>>> ---
>>>  hw/ppc/Makefile.objs   |   2 +-
>>>  hw/ppc/pnv_homer.c | 185 
>>> +
>>>  include/hw/ppc/pnv.h   |  14 
>>>  include/hw/ppc/pnv_homer.h |  41 ++
>>>  4 files changed, 241 insertions(+), 1 deletion(-)
>>>  create mode 100644 hw/ppc/pnv_homer.c
>>>  create mode 100644 include/hw/ppc/pnv_homer.h
>>>
>>> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
>>> index 9da93af905..7260b4a96c 100644
>>> --- a/hw/ppc/Makefile.objs
>>> +++ b/hw/ppc/Makefile.objs
>>> @@ -7,7 +7,7 @@ obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o
>>>  obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o spapr_irq.o
>>>  obj-$(CONFIG_SPAPR_RNG) +=  spapr_rng.o
>>>  # IBM PowerNV
>>> -obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o 
>>> pnv_occ.o pnv_bmc.o
>>> +obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o 
>>> pnv_occ.o pnv_bmc.o pnv_homer.o
>> add an extra line.
>>
>>>  ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
>>>  obj-y += spapr_pci_vfio.o spapr_pci_nvlink2.o
>>>  endif
>>> diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
>>> new file mode 100644
>>> index 00..73a94856d0
>>> --- /dev/null
>>> +++ b/hw/ppc/pnv_homer.c
>>> @@ -0,0 +1,185 @@
>>> +/*
>>> + * QEMU PowerPC PowerNV Homer and OCC common area region
>>> + *
>>> + * Copyright (c) 2019, IBM Corporation.
>>> + *
>>> + * This library is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU Lesser General Public
>>> + * License as published by the Free Software Foundation; either
>>> + * version 2 of the License, or (at your option) any later version.
>>> + *
>>> + * This library is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>>> + * Lesser General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU Lesser General Public
>>> + * License along with this library; if not, see 
>>> .
>>> + */
>>> +#include "qemu/osdep.h"
>>> +#include "sysemu/hw_accel.h"
>>> +#include "sysemu/cpus.h"
>>> +#include "hw/ppc/pnv.h"
>>> +
>>> +static bool core_max_array(hwaddr addr)
>>> +{
>>> +char *cpu_type;
>>> +hwaddr core_max_base = 0xe2819;
>> What is this representing ? 
>>
>>> +MachineState *ms = MACHINE(qdev_get_machine());
>>> +cpu_type = strstr(ms->cpu_type, "power8");
>> you need to get this information some other way. The PnvChip should have it.
>>
>>> +if (cpu_type)
>>> +core_max_base = 0x1f8810;
>> It could be a PnvChipClass value.
>>
>>> +for (int i = 0; i <= ms->smp.cores; i++)
>>> +   if (addr == (core_max_base + i))
>>> +   return true;
>>> +return false;
>>> +}
>>
>>> +static uint64_t homer_read(void *opaque, hwaddr addr, unsigned width)
>>> +{
>>> +switch (addr) {
>> We should be using defines for the case statements below. 
>>
>> Are we accessing one or more structures which are mapped at specific 
>> addresses ? If so I would define them in this file and change the 
>> memory ops to use well known offsets.
>>
>> Are these structures the same on P9 and P8 ? 
>>
>> Are there default values ? May be we could use a reset handler
>> in this case.
>>
>>> +case 0xe2006:  /* max pstate ultra turbo */
>>> +case 0xe2018:  /* pstate id for 0 */
>>> +case 0x1f8001: /* P8 occ pstate version */
>>> +case 0x1f8003: /* P8 pstate min */
>>> +case 0x1f8010: /* P8 pstate id for 0 */

Re: [Qemu-devel] [RFC PATCH 6/6] hw/ppc/pnv_homer: add python interface support for homer/occ common area

[Balamuruhan S]

On 8/9/19 10:16 AM, David Gibson wrote:
> On Wed, Aug 07, 2019 at 12:44:45PM +0530, Balamuruhan S wrote:
>> use python interface APIs in homer/occ common area emulation to
>> interact with scripts if provided else fallback to normal flow,
>> it shows how simple to use the interface to call python methods
>> with any number of arguments in any script placed in common
>> -module-path provided in qemu commandline.
> What's the use case for this?

The usecase can be performing multiple boot test of the vm or during runtime
with different values expected/unexpected by firmware/kernel and check
how it is behaving or how it should behave.

It can be used as a framework for CI or regression.

>
>> Signed-off-by: Balamuruhan S 
>> ---
>>  hw/ppc/pnv_homer.c  | 20 
>>  hw/ppc/pnv_xscom.c  |  9 +
>>  include/sysemu/sysemu.h |  4 
>>  vl.c| 24 
>>  4 files changed, 53 insertions(+), 4 deletions(-)
>>
>> diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
>> index 73a94856d0..6ae5e74f19 100644
>> --- a/hw/ppc/pnv_homer.c
>> +++ b/hw/ppc/pnv_homer.c
>> @@ -16,7 +16,9 @@
>>   * You should have received a copy of the GNU Lesser General Public
>>   * License along with this library; if not, see 
>> .
>>   */
>> +#include "sysemu/python_api.h"
>>  #include "qemu/osdep.h"
>> +#include "sysemu/sysemu.h"
>>  #include "sysemu/hw_accel.h"
>>  #include "sysemu/cpus.h"
>>  #include "hw/ppc/pnv.h"
>> @@ -37,6 +39,15 @@ static bool core_max_array(hwaddr addr)
>>  
>>  static uint64_t homer_read(void *opaque, hwaddr addr, unsigned width)
>>  {
>> +if (homer_module && homer) {
>> +uint64_t homer_ret;
>> +char **address = g_malloc(sizeof(uint64_t));
>> +python_args_init_cast_long(address, addr, 0);
>> +homer_ret = python_callback_int(module_path, homer_module, homer, 
>> address, 1);
>> +python_args_clean(address, 1);
>> +g_free(address);
>> +return homer_ret;
>> +}
>>  switch (addr) {
>>  case 0xe2006:  /* max pstate ultra turbo */
>>  case 0xe2018:  /* pstate id for 0 */
>> @@ -106,6 +117,15 @@ const MemoryRegionOps pnv_homer_ops = {
>>  
>>  static uint64_t occ_common_area_read(void *opaque, hwaddr addr, unsigned 
>> width)
>>  {
>> +if (occ_module && occ) {
>> +uint64_t occ_ret;
>> +char **address = g_malloc(sizeof(uint64_t));
>> +python_args_init_cast_long(address, addr, 0);
>> +occ_ret = python_callback_int(module_path, occ_module, occ, 
>> address, 1);
>> +python_args_clean(address, 1);
>> +g_free(address);
>> +return occ_ret;
>> +}
>>  switch (addr) {
>>  /*
>>   * occ-sensor sanity check that asserts the sensor
>> diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
>> index 18a780bcdf..5e41b7c953 100644
>> --- a/hw/ppc/pnv_xscom.c
>> +++ b/hw/ppc/pnv_xscom.c
>> @@ -179,13 +179,14 @@ static uint64_t xscom_read(void *opaque, hwaddr addr, 
>> unsigned width)
>>  MemTxResult result;
>>  
>>  if (xscom_module && xscom_readp) {
>> -char **args = g_malloc(2 * sizeof(uint64_t));
>> +char **args = g_malloc(3 * sizeof(uint64_t));
>>  PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
>>  python_args_init_cast_long(args, pcba, 0);
>> -python_args_init_cast_int(args, pcc->chip_type, 1);
>> +python_args_init_cast_int(args, chip->chip_num, 1);
>> +python_args_init_cast_int(args, pcc->chip_type, 2);
>>  val = python_callback_int(module_path, xscom_module, xscom_readp,
>> -  args, 2);
>> -python_args_clean(args, 2);
>> +  args, 3);
>> +python_args_clean(args, 3);
>>  g_free(args);
>>  }
>>  else {
>> diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
>> index 9b8dc346d6..3c8119e040 100644
>> --- a/include/sysemu/sysemu.h
>> +++ b/include/sysemu/sysemu.h
>> @@ -121,6 +121,10 @@ extern const char *module_path;
>>  extern const char *xscom_module;
>>  extern const char *xscom_readp;
>>  extern const char *xscom_writep;
>> +extern const char *homer_module;
>> +extern const char *homer;
>> +extern const char *occ_module;
>> +extern const char *occ;
>>  extern int mem_prealloc;
>>  
>>  #define MAX_NODES 128
>> diff --git a/vl.c b/vl.c
>> index 28f0dc1c1b..c96d35d907 100644
>> --- a/vl.c
>> +++ b/vl.c
>> @@ -144,6 +144,10 @@ const char *module_path = NULL;
>>  const char *xscom_module = NULL;
>>  const char *xscom_readp = NULL;
>>  const char *xscom_writep = NULL;
>> +const char *homer_module = NULL;
>> +const char *homer = NULL;
>> +const char *occ_module = NULL;
>> +const char *occ = NULL;
>>  int mem_prealloc = 0; /* force preallocation of physical target memory */
>>  bool enable_mlock = false;
>>  bool enable_cpu_pm = false;
>> @@ -495,6 +499,22 @@ static QemuOptsList qemu_module_opts = {
>>  

Re: [Qemu-devel] [RFC PATCH 6/6] hw/ppc/pnv_homer: add python interface support for homer/occ common area

[Balamuruhan S]

On 8/7/19 3:57 PM, Philippe Mathieu-Daudé wrote:
> On 8/7/19 9:14 AM, Balamuruhan S wrote:
>> use python interface APIs in homer/occ common area emulation to
>> interact with scripts if provided else fallback to normal flow,
>> it shows how simple to use the interface to call python methods
>> with any number of arguments in any script placed in common
>> -module-path provided in qemu commandline.
>>
>> Signed-off-by: Balamuruhan S 
>> ---
>>  hw/ppc/pnv_homer.c  | 20 
>>  hw/ppc/pnv_xscom.c  |  9 +
>>  include/sysemu/sysemu.h |  4 
>>  vl.c| 24 
>>  4 files changed, 53 insertions(+), 4 deletions(-)
>>
>> diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
>> index 73a94856d0..6ae5e74f19 100644
>> --- a/hw/ppc/pnv_homer.c
>> +++ b/hw/ppc/pnv_homer.c
>> @@ -16,7 +16,9 @@
>>   * You should have received a copy of the GNU Lesser General Public
>>   * License along with this library; if not, see 
>> .
>>   */
>> +#include "sysemu/python_api.h"
>>  #include "qemu/osdep.h"
>> +#include "sysemu/sysemu.h"
>>  #include "sysemu/hw_accel.h"
>>  #include "sysemu/cpus.h"
>>  #include "hw/ppc/pnv.h"
>> @@ -37,6 +39,15 @@ static bool core_max_array(hwaddr addr)
>>  
>>  static uint64_t homer_read(void *opaque, hwaddr addr, unsigned width)
>>  {
>> +if (homer_module && homer) {
>> +uint64_t homer_ret;
>> +char **address = g_malloc(sizeof(uint64_t));
>> +python_args_init_cast_long(address, addr, 0);
>> +homer_ret = python_callback_int(module_path, homer_module, homer, 
>> address, 1);
>> +python_args_clean(address, 1);
>> +g_free(address);
> Maybe the heap overhead can be simplified alloc'ing in the PnvChip
> structure.

But it also depends on with how many arguments that we need to call python

functions associated with read/write ops. sure, I will check the way to

adopt this suggestion.

Thanks Philippe.


>
>> +return homer_ret;
>> +}
>>  switch (addr) {
>>  case 0xe2006:  /* max pstate ultra turbo */
>>  case 0xe2018:  /* pstate id for 0 */
>> @@ -106,6 +117,15 @@ const MemoryRegionOps pnv_homer_ops = {
>>  
>>  static uint64_t occ_common_area_read(void *opaque, hwaddr addr, unsigned 
>> width)
>>  {
>> +if (occ_module && occ) {
>> +uint64_t occ_ret;
>> +char **address = g_malloc(sizeof(uint64_t));
>> +python_args_init_cast_long(address, addr, 0);
>> +occ_ret = python_callback_int(module_path, occ_module, occ, 
>> address, 1);
>> +python_args_clean(address, 1);
>> +g_free(address);
>> +return occ_ret;
>> +}
>>  switch (addr) {
>>  /*
>>   * occ-sensor sanity check that asserts the sensor
>> diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
>> index 18a780bcdf..5e41b7c953 100644
>> --- a/hw/ppc/pnv_xscom.c
>> +++ b/hw/ppc/pnv_xscom.c
>> @@ -179,13 +179,14 @@ static uint64_t xscom_read(void *opaque, hwaddr addr, 
>> unsigned width)
>>  MemTxResult result;
>>  
>>  if (xscom_module && xscom_readp) {
>> -char **args = g_malloc(2 * sizeof(uint64_t));
>> +char **args = g_malloc(3 * sizeof(uint64_t));
>>  PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
>>  python_args_init_cast_long(args, pcba, 0);
>> -python_args_init_cast_int(args, pcc->chip_type, 1);
>> +python_args_init_cast_int(args, chip->chip_num, 1);
>> +python_args_init_cast_int(args, pcc->chip_type, 2);
>>  val = python_callback_int(module_path, xscom_module, xscom_readp,
>> -  args, 2);
>> -python_args_clean(args, 2);
>> +  args, 3);
>> +python_args_clean(args, 3);
>>  g_free(args);
>>  }
>>  else {
>> diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
>> index 9b8dc346d6..3c8119e040 100644
>> --- a/include/sysemu/sysemu.h
>> +++ b/include/sysemu/sysemu.h
>> @@ -121,6 +121,10 @@ extern const char *module_path;
>>  extern const char *xscom_module;
>>  extern const char *xscom_readp;
>>  extern const char *xscom_writep;
>> +extern const char *homer_module;
>> +extern const char *homer;
>> +extern const char *occ_module;
>> +extern const char *occ;
>>  extern int mem_prealloc;
>>  
>>  #define MAX_NODES 128
>> diff --git a/vl.c b/vl.c
>> index 28f0dc1c1b..c96d35d907 100644
>> --- a/vl.c
>> +++ b/vl.c
>> @@ -144,6 +144,10 @@ const char *module_path = NULL;
>>  const char *xscom_module = NULL;
>>  const char *xscom_readp = NULL;
>>  const char *xscom_writep = NULL;
>> +const char *homer_module = NULL;
>> +const char *homer = NULL;
>> +const char *occ_module = NULL;
>> +const char *occ = NULL;
>>  int mem_prealloc = 0; /* force preallocation of physical target memory */
>>  bool enable_mlock = false;
>>  bool enable_cpu_pm = false;
>> @@ -495,6 +499,22 @@ static QemuOptsList qemu_module_opts = {
>>