[Qemu-devel] [Bug 1842787] Re: Writes permanently hang with very heavy I/O on virtio-scsi - worse on virtio-blk
** Description changed: Up to date Arch Linux on host and guest. linux 5.2.11. QEMU 4.1.0. Full command line at bottom. Host gives QEMU two thin LVM volumes. The first is the root filesystem, and the second is for heavy I/O, on a Samsung 970 Evo 1TB. When maxing out the I/O on the second virtual block device using virtio- blk, I often get a "lockup" in about an hour or two. From the advise of iggy in IRC, I switched over to virtio-scsi. It ran perfectly for a few days, but then "locked up" in the same way. By "lockup", I mean writes to the second virtual block device permanently hang. I can read files from it, but even "touch foo" never times out, cannot be "kill -9"'ed, and is stuck in uninterruptible sleep. When this happens, writes to the first virtual block device with the root filesystem are fine, so the O/S itself remains responsive. The second virtual block device uses BTRFS. But, I have also tried XFS and reproduced the issue. In guest, when this starts, it starts logging "task X blocked for more than Y seconds". Below is an example of one of these. At this point, anything that is or does in the future write to this block device gets stuck in uninterruptible sleep. - INFO: task kcompactd:232 blocked for more than 860 seconds. Not tained 5.2.11-1 #1 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this messae. kcompactd0 D0 232 2 0x80004000 Call Trace: ? __schedule+0x27f/0x6d0 schedule+0x3d/0xc0 io_schedule+0x12/0x40 __lock_page+0x14a/0x250 ? add_to_page_cache_lru+0xe0/0xe0 migrate_pages+0x803/0xb70 ? isolate_migratepages_block+0x9f0/0x9f0 ? __reset_isolation_suitable+0x110/0x110 compact_zone+0x6a2/0xd30 kcompactd_do_work+0x134/0x260 ? kvm_clock_read+0x14/0x30 ? kvm_sched_clock_read+0x5/0x10 kcompactd+0xd3/0x220 ? wait_woken+0x80/0x80 kthread+0xfd/0x130 ? kcompactd_do_work+0x260/0x260 ? kthread_park+0x80/0x80 ret_from_fork+0x35/0x40 - In guest, there are no other dmesg/journalctl entries other than "task...blocked". On host, there are no dmesg/journalctl entries whatsoever. Everything else in host continues to work fine, including other QEMU VM's on the same underlying SSD (but obviously different lvm volumes.) I understand there might not be enough to go on here, and I also understand it's possible this isn't a QEMU bug. Happy to run given commands or patches to help diagnose what's going on here. I'm now running a custom compiled QEMU 4.1.0, with debug symbols, so I can get a meaningful backtrace from the host point of view. I've only recently tried this level of I/O, so can't say if this is a new issue. + When writes are hanging, on host, I can connect to the monitor. Running + "info block" shows nothing unusual. + - /usr/bin/qemu-system-x86_64 -name arch,process=qemu:arch -no-user-config -nodefaults -nographic -uuid 0528162b-2371-41d5-b8da-233fe61b6458 -pidfile /tmp/0528162b-2371-41d5-b8da-233fe61b6458.pid -machine q35,accel=kvm,vmport=off,dump-guest-core=off -cpu SandyBridge-IBRS -smp cpus=24,cores=12,threads=1,sockets=2 -m 24G -drive if=pflash,format=raw,readonly,file=/usr/share/ovmf/x64/OVMF_CODE.fd -drive if=pflash,format=raw,readonly,file=/var/qemu/0528162b-2371-41d5-b8da-233fe61b6458.fd -monitor telnet:localhost:8000,server,nowait,nodelay -spice unix,addr=/tmp/0528162b-2371-41d5-b8da-233fe61b6458.sock,disable-ticketing -device ioh3420,id=pcie.1,bus=pcie.0,slot=0 -device virtio-vga,bus=pcie.1,addr=0 -usbdevice tablet -netdev bridge,id=network0,br=br0 -device virtio-net-pci,netdev=network0,mac=02:37:de:79:19:09,bus=pcie.0,addr=3 -device virtio-scsi-pci,id=scsi1 -drive driver=raw,node-name=hd0,file=/dev/lvm/arch_root,if=none,discard=unmap -device scsi-hd,drive=hd0,bootindex=1 -drive driver=raw,node-name=hd1,file=/dev/lvm/arch_nvme,if=none,discard=unmap -device scsi-hd,drive=hd1,bootindex=2 - -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1842787 Title: Writes permanently hang with very heavy I/O on virtio-scsi - worse on virtio-blk Status in QEMU: New Bug description: Up to date Arch Linux on host and guest. linux 5.2.11. QEMU 4.1.0. Full command line at bottom. Host gives QEMU two thin LVM volumes. The first is the root filesystem, and the second is for heavy I/O, on a Samsung 970 Evo 1TB. When maxing out the I/O on the second virtual block device using virtio-blk, I often get a "lockup" in about an hour or two. From the advise of iggy in IRC, I switched over to virtio-scsi. It ran perfectly for a few days, but then "locked up" in the same way. By "lockup", I mean writes to the second
[Qemu-devel] [Bug 1842787] Re: Writes permanently hang with very heavy I/O on virtio-scsi - worse on virtio-blk
** Description changed: Up to date Arch Linux on host and guest. linux 5.2.11. QEMU 4.1.0. Full command line at bottom. Host gives QEMU two thin LVM volumes. The first is the root filesystem, and the second is for heavy I/O, on a Samsung 970 Evo 1TB. When maxing out the I/O on the second virtual block device using virtio- blk, I often get a "lockup" in about an hour or two. From the advise of iggy in IRC, I switched over to virtio-scsi. It ran perfectly for a few days, but then "locked up" in the same way. By "lockup", I mean writes to the second virtual block device permanently hang. I can read files from it, but even "touch foo" never times out, cannot be "kill -9"'ed, and is stuck in uninterruptible sleep. When this happens, writes to the first virtual block device with the root filesystem are fine, so the O/S itself remains responsive. The second virtual block device uses BTRFS. But, I have also tried XFS and reproduced the issue. In guest, when this starts, it starts logging "task X blocked for more than Y seconds". Below is an example of one of these. At this point, anything that is or does in the future write to this block device gets stuck in uninterruptible sleep. - INFO: task kcompactd:232 blocked for more than 860 seconds. - Not tained 5.2.11-1 #1 + Not tained 5.2.11-1 #1 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this messae. kcompactd0 D0 232 2 0x80004000 Call Trace: - ? __schedule+0x27f/0x6d0 - schedule+0x3d/0xc0 - io_schedule+0x12/0x40 - __lock_page+0x14a/0x250 - ? add_to_page_cache_lru+0xe0/0xe0 - migrate_pages+0x803/0xb70 - ? isolate_migratepages_block+0x9f0/0x9f0 - ? __reset_isolation_suitable+0x110/0x110 - compact_zone+0x6a2/0xd30 - kcompactd_do_work+0x134/0x260 - ? kvm_clock_read+0x14/0x30 - ? kvm_sched_clock_read+0x5/0x10 - kcompactd+0xd3/0x220 - ? wait_woken+0x80/0x80 - kthread+0xfd/0x130 - ? kcompactd_do_work+0x260/0x260 - ? kthread_park+0x80/0x80 - ret_from_fork+0x35/0x40 + ? __schedule+0x27f/0x6d0 + schedule+0x3d/0xc0 + io_schedule+0x12/0x40 + __lock_page+0x14a/0x250 + ? add_to_page_cache_lru+0xe0/0xe0 + migrate_pages+0x803/0xb70 + ? isolate_migratepages_block+0x9f0/0x9f0 + ? __reset_isolation_suitable+0x110/0x110 + compact_zone+0x6a2/0xd30 + kcompactd_do_work+0x134/0x260 + ? kvm_clock_read+0x14/0x30 + ? kvm_sched_clock_read+0x5/0x10 + kcompactd+0xd3/0x220 + ? wait_woken+0x80/0x80 + kthread+0xfd/0x130 + ? kcompactd_do_work+0x260/0x260 + ? kthread_park+0x80/0x80 + ret_from_fork+0x35/0x40 - In guest, there are no other dmesg/journalctl entries other than "task...blocked". On host, there are no dmesg/journalctl entries whatsoever. Everything else in host continues to work fine, including other QEMU VM's on the same underlying SSD (but obviously different lvm volumes.) I understand there might not be enough to go on here, and I also understand it's possible this isn't a QEMU bug. Happy to run given commands or patches to help diagnose what's going on here. I'm now running a custom compiled QEMU 4.1.0, with debug symbols, so I can get a meaningful backtrace from the host point of view. + I've only recently tried this level of I/O, so can't say if this is a + new issue. + - /usr/bin/qemu-system-x86_64 --name arch,process=qemu:arch --no-user-config --nodefaults --nographic --uuid 0528162b-2371-41d5-b8da-233fe61b6458 --pidfile /tmp/0528162b-2371-41d5-b8da-233fe61b6458.pid --machine q35,accel=kvm,vmport=off,dump-guest-core=off --cpu SandyBridge-IBRS --smp cpus=24,cores=12,threads=1,sockets=2 --m 24G --drive if=pflash,format=raw,readonly,file=/usr/share/ovmf/x64/OVMF_CODE.fd --drive if=pflash,format=raw,readonly,file=/var/qemu/0528162b-2371-41d5-b8da-233fe61b6458.fd --monitor telnet:localhost:8000,server,nowait,nodelay --spice unix,addr=/tmp/0528162b-2371-41d5-b8da-233fe61b6458.sock,disable-ticketing --device ioh3420,id=pcie.1,bus=pcie.0,slot=0 --device virtio-vga,bus=pcie.1,addr=0 --usbdevice tablet --netdev bridge,id=network0,br=br0 --device virtio-net-pci,netdev=network0,mac=02:37:de:79:19:09,bus=pcie.0,addr=3 --device virtio-scsi-pci,id=scsi1 --drive driver=raw,node-name=hd0,file=/dev/lvm/arch_root,if=none,discard=unmap --device scsi-hd,drive=hd0,bootindex=1 --drive driver=raw,node-name=hd1,file=/dev/lvm/arch_nvme,if=none,discard=unmap --device scsi-hd,drive=hd1,bootindex=2 + -name arch,process=qemu:arch + -no-user-config + -nodefaults + -nographic + -uuid 0528162b-2371-41d5-b8da-233fe61b6458 + -pidfile /tmp/0528162b-2371-41d5-b8da-233fe61b6458.pid + -machine q35,accel=kvm,vmport=off,dump-guest-core=off + -cpu SandyBridge-IBRS + -smp cpus=24,cores=12,threads=1,sockets=2 + -m 24G + -drive
[Qemu-devel] [Bug 1842787] [NEW] Writes permanently hang with very heavy I/O on virtio-scsi - worse on virtio-blk
Public bug reported: Up to date Arch Linux on host and guest. linux 5.2.11. QEMU 4.1.0. Full command line at bottom. Host gives QEMU two thin LVM volumes. The first is the root filesystem, and the second is for heavy I/O, on a Samsung 970 Evo 1TB. When maxing out the I/O on the second virtual block device using virtio- blk, I often get a "lockup" in about an hour or two. From the advise of iggy in IRC, I switched over to virtio-scsi. It ran perfectly for a few days, but then "locked up" in the same way. By "lockup", I mean writes to the second virtual block device permanently hang. I can read files from it, but even "touch foo" never times out, cannot be "kill -9"'ed, and is stuck in uninterruptible sleep. When this happens, writes to the first virtual block device with the root filesystem are fine, so the O/S itself remains responsive. The second virtual block device uses BTRFS. But, I have also tried XFS and reproduced the issue. In guest, when this starts, it starts logging "task X blocked for more than Y seconds". Below is an example of one of these. At this point, anything that is or does in the future write to this block device gets stuck in uninterruptible sleep. - INFO: task kcompactd:232 blocked for more than 860 seconds. Not tained 5.2.11-1 #1 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this messae. kcompactd0 D0 232 2 0x80004000 Call Trace: ? __schedule+0x27f/0x6d0 schedule+0x3d/0xc0 io_schedule+0x12/0x40 __lock_page+0x14a/0x250 ? add_to_page_cache_lru+0xe0/0xe0 migrate_pages+0x803/0xb70 ? isolate_migratepages_block+0x9f0/0x9f0 ? __reset_isolation_suitable+0x110/0x110 compact_zone+0x6a2/0xd30 kcompactd_do_work+0x134/0x260 ? kvm_clock_read+0x14/0x30 ? kvm_sched_clock_read+0x5/0x10 kcompactd+0xd3/0x220 ? wait_woken+0x80/0x80 kthread+0xfd/0x130 ? kcompactd_do_work+0x260/0x260 ? kthread_park+0x80/0x80 ret_from_fork+0x35/0x40 - In guest, there are no other dmesg/journalctl entries other than "task...blocked". On host, there are no dmesg/journalctl entries whatsoever. Everything else in host continues to work fine, including other QEMU VM's on the same underlying SSD (but obviously different lvm volumes.) I understand there might not be enough to go on here, and I also understand it's possible this isn't a QEMU bug. Happy to run given commands or patches to help diagnose what's going on here. I'm now running a custom compiled QEMU 4.1.0, with debug symbols, so I can get a meaningful backtrace from the host point of view. - /usr/bin/qemu-system-x86_64 -name arch,process=qemu:arch -no-user-config -nodefaults -nographic -uuid 0528162b-2371-41d5-b8da-233fe61b6458 -pidfile /tmp/0528162b-2371-41d5-b8da-233fe61b6458.pid -machine q35,accel=kvm,vmport=off,dump-guest-core=off -cpu SandyBridge-IBRS -smp cpus=24,cores=12,threads=1,sockets=2 -m 24G -drive if=pflash,format=raw,readonly,file=/usr/share/ovmf/x64/OVMF_CODE.fd -drive if=pflash,format=raw,readonly,file=/var/qemu/0528162b-2371-41d5-b8da-233fe61b6458.fd -monitor telnet:localhost:8000,server,nowait,nodelay -spice unix,addr=/tmp/0528162b-2371-41d5-b8da-233fe61b6458.sock,disable-ticketing -device ioh3420,id=pcie.1,bus=pcie.0,slot=0 -device virtio-vga,bus=pcie.1,addr=0 -usbdevice tablet -netdev bridge,id=network0,br=br0 -device virtio-net-pci,netdev=network0,mac=02:37:de:79:19:09,bus=pcie.0,addr=3 -device virtio-scsi-pci,id=scsi1 -drive driver=raw,node-name=hd0,file=/dev/lvm/arch_root,if=none,discard=unmap -device scsi-hd,drive=hd0,bootindex=1 -drive driver=raw,node-name=hd1,file=/dev/lvm/arch_nvme,if=none,discard=unmap -device scsi-hd,drive=hd1,bootindex=2 - ** Affects: qemu Importance: Undecided Status: New ** Summary changed: - irtiWrites permanently hang with very heavy I/O on vo-scsi - worse on virtio-blk + Writes permanently hang with very heavy I/O on virtio-scsi - worse on virtio-blk -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1842787 Title: Writes permanently hang with very heavy I/O on virtio-scsi - worse on virtio-blk Status in QEMU: New Bug description: Up to date Arch Linux on host and guest. linux 5.2.11. QEMU 4.1.0. Full command line at bottom. Host gives QEMU two thin LVM volumes. The first is the root filesystem, and the second is for heavy I/O, on a Samsung 970 Evo 1TB. When maxing out the I/O on the second virtual block device using virtio-blk, I often get a "lockup" in about an hour or two. From the advise of iggy in IRC, I switched over to virtio-scsi. It ran perfectly for a few days, but then "locked up" in the same way. By "lockup", I mean writes to the second virtual block device permanently hang. I can read files from it, but even "touch foo" never times out, cannot be "kill -9"'ed, and is stuck in
Re: [Qemu-devel] Cryptic errors from PIP install if missing openssl-devel
On Wed, Sep 04, 2019 at 03:57:17PM -0400, Cleber Rosa wrote:
> On Sat, Aug 31, 2019 at 11:48:34AM +1000, David Gibson wrote:
> > On Fri, Aug 30, 2019 at 02:56:48PM -0300, Eduardo Habkost wrote:
> > > On Thu, Aug 29, 2019 at 11:31:25AM +1000, David Gibson wrote:
> > > > If I attempt to run "make check-acceptance" on my POWER9, RHEL8.1
> > > > machine when the openssl-devel package isn't installed, I get the
> > > > following very cryptic error:
> > > >
> > > > VENV/home/dwg/qemu/build/rhel8/tests/venv
> > > > PIP /home/dwg/qemu/tests/requirements.txt
> > > > Command "/home/dwg/qemu/build/rhel8/tests/venv/bin/python -u -c "import
> > > > setuptools,
> > > > tokenize;__file__='/tmp/pip-build-la4el5r5/cryptography/setup.py';f=getattr(tokenize,
> > > > 'open', open)(__file__);code=f.read().replace('\r\n',
> > > > '\n');f.close();exec(compile(code, __file__, 'exec'))" install --record
> > > > /tmp/pip-1efs22iz-record/install-record.txt
> > > > --single-version-externally-managed --compile --install-headers
> > > > /home/dwg/qemu/build/rhel8/tests/venv/include/site/python3.6/cryptography"
> > > > failed with error code 1 in /tmp/pip-build-la4el5r5/cryptography/
> > > >
> > > > Using V=1 doesn't give any more useful information, and it's not
> > > > (easily) possible to manually re-run the given command since it relies
> > > > on things in /tmp that are removed once the attempt finishes.
> > >
> > > V=1 is supposed to show the actual pip command being run. I see
> > > it here:
> > >
> > > $ make check-venv V=1
> > > [...]
> > > python3 -B -m venv --system-site-packages
> > > /home/ehabkost/rh/proj/virt/qemu/tests/venv
> > > * /home/ehabkost/rh/proj/virt/qemu/tests/venv/bin/python -m pip -q
> > > install -r /home/ehabkost/rh/proj/virt/qemu/tests/requirements.txt
> > > You are using pip version 19.0.3, however version 19.2.3 is available.
> > > You should consider upgrading via the 'pip install --upgrade pip'
> > > command.
> > > touch /home/ehabkost/rh/proj/virt/qemu/tests/venv
> > >
> > > Can you reproduce the problem if you re-run the pip command?
> >
> > Yes, I can, but it's basically just the same error without any extra
> > information.
> >
> > > > I only figured out it was openssl-devel being missing that was the
> > > > problem by (mostly) guesswork. It would be really great if we could
> > > > generate a more helpful error here.
> > >
> > > I don't think there's much we can do about it, as the error is generated
> > > by a
> > > package being built by pip.
> > >
> > > There's one thing we can do to make it slightly better: not passing `-q`
> > > to pip
> > > if running with V=1, so people can see which packages are being installed
> > > and
> > > which one is generating the error.
> >
> > That sounds like a good start to me.
> >
> > > > In addition, if I rerun "make check-acceptance" it no longer even
> > > > attempts the PIP install, since tests/venv already exists in my build
> > > > environment. It then sort of works, but I think it might be hitting
> > > > other errors because of the missing python packages. Sorry that's a
> > > > bit vague - I also seem to be getting unrelated errors that I'm still
> > > > trying to figure out.
> > >
> > > This sounds like a bug and we need to fix it.
> >
> > I agree.
>
> Hi David,
>
> I've pushed a branch here (most of the commits have already been sent
> separately):
>
>https://github.com/clebergnu/qemu/tree/ppc64
>
> I've tested on a RHEL 8 ppc64le Power 9, and it seems to work for me.
> My steps for building QEMU:
>
> - Configured with: '/home/cleber/src/qemu/configure' '--enable-slirp=git'
> '--python=/usr/bin/python3'
> '--target-list=x86_64-softmmu,ppc64-softmmu,arm-softmmu,aarch64-softmmu,mips-softmmu,mipsel-softmmu,mips64-softmmu,mips64el-softmmu,sh4-softmmu,s390x-softmmu,alpha-softmmu,m68k-softmmu,riscv64-softmmu'
> - make
> - make check-acceptance
>
> Would you be able to test if that branch works smoothly for you?
So, with this tree I'm no longer getting problems if openssl-devel is
not installed, so that much looks good.
I am getting some different errors - I was seeing this before (with
openssl-devel installed) sometimes, but only sometimes. I haven't yet
worked out a pattern for when they appeared. They also don't appear
to be fatal, the rest of the tests seem to be running ok. Any ideas?
VENV/home/dwg/qemu/build/rhel8/tests/venv
PIP /home/dwg/qemu/tests/requirements.txt
AVOCADO tests/acceptance
Error running method "run" of plugin "html": 'Namespace' object has no
attribute 'get'
Error running method "run" of plugin "varianter_cit": 'Namespace' object has no
attribute 'get'
JOB ID : 6808bb316632af2bf7652586b3fbb22ac497e090
JOB LOG:
/home/dwg/qemu/build/rhel8/tests/results/job-2019-09-04T22.06-6808bb3/job.log
Error running method "initialize" of plugin "varianter_cit": 'Namespace' object
has no attribute 'get'
Error running method "initialize" of
Re: [Qemu-devel] [PATCH] numa: Introduce MachineClass::auto_enable_numa for implicit NUMA node
On 9/5/2019 4:43 AM, Eduardo Habkost wrote:
On Wed, Sep 04, 2019 at 02:22:39PM +0800, Tao Xu wrote:
On 9/4/2019 1:52 AM, Eduardo Habkost wrote:
On Mon, Aug 05, 2019 at 03:13:02PM +0800, Tao Xu wrote:
Add MachineClass::auto_enable_numa field. When it is true, a NUMA node
is expected to be created implicitly.
Acked-by: David Gibson
Suggested-by: Igor Mammedov
Suggested-by: Eduardo Habkost
Signed-off-by: Tao Xu
This introduces spurious warnings when running qemu-system-ppc64.
See:
https://lore.kernel.org/qemu-devel/CAFEAcA-AvFS2cbDH-t5SxgY9hA=lgl81_8dn-vh193vtv9w...@mail.gmail.com/
To reproduce it, just run 'qemu-system-ppc64 -machine pseries'
without any -numa arguments.
I have removed this patch from machine-next so it won't block the
existing pull request.
I got it. If default splitting of RAM between nodes is
deprecated, this patch can't reuse the splitting code. I agree with droping
this patch.
Probably all we need to fix this issue is to replace
NumaNodeOptions node = { };
with
NumaNodeOptions node = { .size = ram_size };
in the auto_enable_numa block.
Do you plan to send v2?
OK, thank you for your suggestion. I will fix it and send v2.
Re: [Qemu-devel] [PATCH v1 03/42] tests/docker: fix "cc" command to work with podman
On 9/4/19 4:29 PM, Alex Bennée wrote:
> Podman requires a little bit of additional magic to the uid mapping
> which was already done for the normal RunCommand. We simplify the
> logic by pushing it directly into the Docker::run method to avoid
> instantiating an extra Docker() object and ensure the CC command
> always runs as the current user.
>
> Signed-off-by: Alex Bennée
> ---
> tests/docker/docker.py | 30 +++---
> tests/tcg/Makefile.include | 2 +-
> 2 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/tests/docker/docker.py b/tests/docker/docker.py
> index e23209f71ee..8f391eb278b 100755
> --- a/tests/docker/docker.py
> +++ b/tests/docker/docker.py
> @@ -318,10 +318,20 @@ class Docker(object):
> return False
> return checksum == _text_checksum(_dockerfile_preprocess(dockerfile))
>
> -def run(self, cmd, keep, quiet):
> +def run(self, cmd, keep, quiet, as_user=False):
> label = uuid.uuid1().hex
> if not keep:
> self._instances.append(label)
> +
> +if as_user:
> +uid = os.getuid()
> +cmd = [ "-u", str(uid) ] + cmd
> +# podman requires a bit more fiddling
> +if self._command[0] == "podman":
> +cmd = [ "--uidmap", "%d:0:1" % uid,
> +"--uidmap", "0:1:%d" % uid,
> +"--uidmap", "%d:%d:64536" % (uid + 1, uid + 1)] + cmd
> +
I was having problems with constructs like these recently. I think we
either need to use --userns=keep-id (vastly preferred) or adjust 64536
there to read as "65536 - uid" because not everyone will have a UID of 1000.
(My UID is over 20,000 and for whatever reason, this causes podman to
crash very badly when using this hackaround.)
> ret = self._do_check(["run", "--label",
> "com.qemu.instance.uuid=" + label] + cmd,
> quiet=quiet)
> @@ -364,15 +374,8 @@ class RunCommand(SubCommand):
> help="Run container using the current user's
> uid")
>
> def run(self, args, argv):
> -if args.run_as_current_user:
> -uid = os.getuid()
> -argv = [ "-u", str(uid) ] + argv
> -docker = Docker()
> -if docker._command[0] == "podman":
> -argv = [ "--uidmap", "%d:0:1" % uid,
> - "--uidmap", "0:1:%d" % uid,
> - "--uidmap", "%d:%d:64536" % (uid + 1, uid + 1)] +
> argv
> -return Docker().run(argv, args.keep, quiet=args.quiet)
> +return Docker().run(argv, args.keep, quiet=args.quiet,
> +as_user=args.run_as_current_user)
>
>
> class BuildCommand(SubCommand):
> @@ -556,8 +559,6 @@ class CcCommand(SubCommand):
> help="The docker image in which to run cc")
> parser.add_argument("--cc", default="cc",
> help="The compiler executable to call")
> -parser.add_argument("--user",
> -help="The user-id to run under")
> parser.add_argument("--source-path", "-s", nargs="*", dest="paths",
> help="""Extra paths to (ro) mount into container
> for
> reading sources""")
> @@ -571,11 +572,10 @@ class CcCommand(SubCommand):
> if args.paths:
> for p in args.paths:
> cmd += ["-v", "%s:%s:ro,z" % (p, p)]
> -if args.user:
> -cmd += ["-u", args.user]
> cmd += [args.image, args.cc]
> cmd += argv
> -return Docker().command("run", cmd, args.quiet)
> +return Docker().run(cmd, False, quiet=args.quiet,
> +as_user=True)
>
>
> class CheckCommand(SubCommand):
> diff --git a/tests/tcg/Makefile.include b/tests/tcg/Makefile.include
> index 73b5626fc5f..210f8428237 100644
> --- a/tests/tcg/Makefile.include
> +++ b/tests/tcg/Makefile.include
> @@ -41,7 +41,7 @@ ifneq ($(DOCKER_IMAGE),)
> # We also need the Docker make rules to depend on
> include $(SRC_PATH)/tests/docker/Makefile.include
>
> -DOCKER_COMPILE_CMD="$(DOCKER_SCRIPT) cc --user $(shell id -u) \
> +DOCKER_COMPILE_CMD="$(DOCKER_SCRIPT) cc \
> --cc $(DOCKER_CROSS_COMPILER) \
> -i qemu:$(DOCKER_IMAGE) \
> -s $(SRC_PATH) -- "
>
--
—js
[Qemu-devel] [PATCH] tests/docker: Use --userns=keep-id for podman
The workaround that attempts to accomplish the same result as --userns=keep-id does not appear to work well with UIDs much above 1000 (like mine, which is above 2.) Since we have official support for this "trick" now, use the supported method. Signed-off-by: John Snow --- tests/docker/docker.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/docker/docker.py b/tests/docker/docker.py index ac5baab4ca..fe17d5f709 100755 --- a/tests/docker/docker.py +++ b/tests/docker/docker.py @@ -368,9 +368,7 @@ class RunCommand(SubCommand): argv = [ "-u", str(uid) ] + argv docker = Docker() if docker._command[0] == "podman": -argv = [ "--uidmap", "%d:0:1" % uid, - "--uidmap", "0:1:%d" % uid, - "--uidmap", "%d:%d:64536" % (uid + 1, uid + 1)] + argv +argv.insert(0, '--userns=keep-id') return Docker().run(argv, args.keep, quiet=args.quiet) -- 2.21.0
Re: [Qemu-devel] [PATCH v4 00/69] target/arm: Convert aa32 base isa to decodetree
Patchew URL: https://patchew.org/QEMU/20190904193059.26202-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20190904193059.26202-1-richard.hender...@linaro.org Type: series Subject: [Qemu-devel] [PATCH v4 00/69] target/arm: Convert aa32 base isa to decodetree === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' f240e8f target/arm: Inline gen_bx_im into callers 10d4d3d target/arm: Clean up disas_thumb_insn e36cea5 target/arm: Convert T16, long branches 1061d1b target/arm: Convert T16, Unconditional branch 7c2aede target/arm: Convert T16, load (literal) fd73031 target/arm: Convert T16, shift immediate ac59480 target/arm: Convert T16, Miscellaneous 16-bit instructions d0ec6df target/arm: Convert T16, Conditional branches, Supervisor call 5c1ac2f target/arm: Convert T16, push and pop bdac1b8 target/arm: Split gen_nop_hint 0b3fed7 target/arm: Convert T16, nop hints 5021591 target/arm: Convert T16, Reverse bytes 3ec6264 target/arm: Convert T16, Change processor state 8bfb8e3 target/arm: Convert T16, extract 75466c7 target/arm: Convert T16 adjust sp (immediate) 9ab6de5 target/arm: Convert T16 add, compare, move (two high registers) f004a7c target/arm: Convert T16 branch and exchange cc1634d target/arm: Convert T16 one low register and immediate d92915a target/arm: Convert T16 add/sub (3 low, 2 low and imm) 1acf8f6 target/arm: Convert T16 load/store multiple af56e9a target/arm: Convert T16 add pc/sp (immediate) c0275cf target/arm: Convert T16 load/store (immediate offset) bfba5bf target/arm: Convert T16 load/store (register offset) 2f6c9ca target/arm: Convert T16 data-processing (two low regs) 994e0b4 target/arm: Add skeleton for T16 decodetree 25c88a8 target/arm: Simplify disas_arm_insn 446ed56 target/arm: Simplify disas_thumb2_insn ee41906 target/arm: Convert TT eb5f39d target/arm: Convert SG 39e761d target/arm: Convert Table Branch 86eec33 target/arm: Convert Unallocated memory hint d17b1df target/arm: Convert PLI, PLD, PLDW cdab118 target/arm: Convert SETEND b374ec7 target/arm: Convert CPS (privileged) fcf2c5a target/arm: Convert Clear-Exclusive, Barriers 6084bd7 target/arm: Convert RFE and SRS d3a1d7b target/arm: Convert SVC 967a9fd target/arm: Convert B, BL, BLX (immediate) e2925d5 target/arm: Diagnose base == pc for LDM/STM 80fca3c target/arm: Diagnose too few registers in list for LDM/STM b585071 target/arm: Diagnose writeback register in list for LDM for v7 0d41010 target/arm: Convert LDM, STM 0318d42 target/arm: Convert MOVW, MOVT f911da0 target/arm: Convert Signed multiply, signed and unsigned divide dc67f09 target/arm: Convert packing, unpacking, saturation, and reversal 76b3d60 target/arm: Convert Parallel addition and subtraction 90d3a3b target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF 5dbd48c target/arm: Diagnose UNPREDICTABLE ldrex/strex cases 3007337 target/arm: Convert Synchronization primitives e27fda5 target/arm: Convert load/store (register, immediate, literal) 7f75e0f target/arm: Convert T32 ADDW/SUBW 3da4ded target/arm: Convert the rest of A32 Miscelaneous instructions fd3df88 target/arm: Convert ERET 2116b98 target/arm: Convert CLZ 43f780c target/arm: Convert BX, BXJ, BLX (register) e46bd40 target/arm: Convert Cyclic Redundancy Check 9824eaa target/arm: Convert MRS/MSR (banked, register) 7c864c7 target/arm: Convert MSR (immediate) and hints f9b0422 target/arm: Simplify op_smlawx for SMLAW* 60dff02 target/arm: Simplify op_smlaxxx for SMLAL* 7de1dd4 target/arm: Convert Halfword multiply and multiply accumulate 620dfcd target/arm: Convert Saturating addition and subtraction d795a84 target/arm: Simplify UMAAL 6d5e8d6 target/arm: Convert multiply and multiply accumulate ed27304 target/arm: Convert Data Processing (immediate) 6b7986e target/arm: Convert Data Processing (reg-shifted-reg) 08c75f2 target/arm: Convert Data Processing (register) 92b92a6 target/arm: Add stubs for aa32 decodetree 010e06b target/arm: Use store_reg_from_load in thumb2 code === OUTPUT BEGIN === 1/69 Checking commit 010e06b2e758 (target/arm: Use store_reg_from_load in thumb2 code) 2/69 Checking commit 92b92a62ad69 (target/arm: Add stubs for aa32 decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #48: new file mode 100644 total: 0 errors, 1 warnings, 154 lines checked Patch 2/69 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/69 Checking commit 08c75f210ec5 (target/arm: Convert Data Processing (register)) 4/69 Checking commit 6b7986e01dc9 (target/arm: Convert Data Processing
[Qemu-devel] [PATCH v1 18/42] tests/docker: move our mips64 cross compile to Buster
Now Buster is released we can stop relying on the movable feast that is Sid for our cross-compiler for building tests. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 2 +- tests/docker/dockerfiles/debian-mips64-cross.docker | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index e946aae14fa..896c1c5a601 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -102,11 +102,11 @@ docker-image-debian-alpha-cross: docker-image-debian10 docker-image-debian-arm64-cross: docker-image-debian10 docker-image-debian-hppa-cross: docker-image-debian10 docker-image-debian-m68k-cross: docker-image-debian10 +docker-image-debian-mips64-cross: docker-image-debian10 docker-image-debian-powerpc-cross: docker-image-debian10 docker-image-debian-sh4-cross: docker-image-debian10 docker-image-debian-sparc64-cross: docker-image-debian10 -docker-image-debian-mips64-cross: docker-image-debian-sid docker-image-debian-riscv64-cross: docker-image-debian-sid docker-image-debian-ppc64-cross: docker-image-debian-sid docker-image-travis: NOUSER=1 diff --git a/tests/docker/dockerfiles/debian-mips64-cross.docker b/tests/docker/dockerfiles/debian-mips64-cross.docker index bf0073a4662..1a79505d696 100644 --- a/tests/docker/dockerfiles/debian-mips64-cross.docker +++ b/tests/docker/dockerfiles/debian-mips64-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -- 2.20.1
Re: [Qemu-devel] [PATCH for-4.2 v10 14/15] virtio-iommu-pci: Add virtio iommu pci support
On Wed, Sep 04, 2019 at 04:19:33PM +0200, Auger Eric wrote: > Hi Michael, > > On 9/1/19 8:40 AM, Michael S. Tsirkin wrote: > > On Thu, Aug 01, 2019 at 03:49:37PM +0200, Auger Eric wrote: > >> Hi Michael, > >> > >> On 8/1/19 3:06 PM, Michael S. Tsirkin wrote: > >>> On Thu, Aug 01, 2019 at 02:15:03PM +0200, Auger Eric wrote: > Hi Michael, > > On 7/30/19 9:35 PM, Michael S. Tsirkin wrote: > > On Tue, Jul 30, 2019 at 07:21:36PM +0200, Eric Auger wrote: > >> This patch adds virtio-iommu-pci, which is the pci proxy for > >> the virtio-iommu device. > >> > >> Signed-off-by: Eric Auger > > > > This part I'm not sure we should merge just yet. The reason being I > > think we should limit it to mmio where DT can be used to describe iommu > > topology. For PCI I don't see why we shouldn't always expose this > > in the config space, and I think it's preferable not to > > need to support a mix of DT,ACPI and PCI as options. > > For context, some discussion related to this topic already arose on v7 > revision of the driver: > > [1] Re: [PATCH v7 0/7] Add virtio-iommu driver > https://lore.kernel.org/linux-pci/87a7ioby9u.fsf@morokweng.localdomain/ > > Some additional thoughts. > > First considering DT boot. > > THE DT description features an iommu-map property in the > pci-host-ecam-generic node that describes which RIDs are handled by the > virtio-iommu and a possible offset/mask to be applied inbetween the RID > and the streamID at the input of the IOMMU > (Documentation/devicetree/bindings/pci/pci-iommu.txt) > > As far as I understand when a DMA capable device is setup, its DMA > configuration is built using that call chain: > > pci_dma_configure > |_ of_dma_configure > |_ of_iommu_configure > |_ of_pci_iommu_init > |_ of_map_rid > > I understand you would like the iommu-map/iommu-map-mask info to be > exposed directly into the config space of the device instead of inside > the DT or IORT table. Assuming a module is initialized sufficiently > early to retrieve this info, we would need the resulting info to be > consolidated to allow pci_dma_configure chain to work seemlessly. This > sounds a significant impact on above kernel infrastructure. > >>> > >>> I don't really know what consolidated means. > >>> It is pretty common for IOMMUs to expose config through > >>> PCI registers. This typically happens as a fixup. > >> I meant: instead of retrieving the info through the of_* code you need > >> to interoperate with the module to retrieve the same info and detect > >> when you need to take that path instead of the of one. > > > > The way to do it would be with a quirk, > > and the quirk would not be part of the > > virtio module - it can poke at the device using > > virtio_pci_cfg_cap. > > I got this preliminary quirk function working. However it only works for > a DECLARE_PCI_FIXUP_ENABLE quirk. In an EARLY quirk, the guest crashes > on the first ioread that attempts to read the BAR as mem accesses are > not enabled yet I guess. This is why I suggested using virtio_pci_cfg_cap. This allows bar access when mem accesses are disabled. > So assuming I get the proper system config data in the device > configuration, the iommu bindings will be set up late. If it all works with a late quirk, then great. If not we can fall back to config cycles. > By the way I have not yet attempted to generate iommu bindings from the > quirk function (job done in drivers/acpi/arm64/iort.c) which does not > sound to be straightforward. > > > >>> > >>> I would write a tiny driver to do exactly that, > >>> and run it from the fixup. > >>> > >>> > This comes in addition to the development of the "small module that > loads early and pokes at the IOMMU sufficiently to get the data about > which devices use the IOMMU out of it using standard virtio config > space" evoked in [1] + the definition of the data formats to be put in > the very cfg space. > >>> > >>> That last part is true but that's exactly why I propose we > >>> wait on this patch a bit. > >>> > With ACPI I understand we have the same kind of infrastructure: > drivers/acpi/arm64/iort.c currently extracts the mapping between RC RIDs > and IOMMU streamids > > pci_dma_configure( > |_ acpi_dma_configure > |_ iort_iommu_configure > |_ iort_pci_iommu_init > |_ iort_node_map_id > |_ iort_id_map > > Maybe I fail to see the easy and right way to do the integration at > kernel level but I am a bit frightened by the efforts that would be > requested to follow your suggestion, whereas the DT infra is ready and > fully upstreamed to accept the use case. > >>> > >>> Did you take a look at drivers/pci/quirks.c and how these run? >
[Qemu-devel] [PATCH v1 34/42] .travis.yml: Improve ccache use
From: Philippe Mathieu-Daudé
Per https://ccache.dev/manual/latest.html:
By default, ccache tries to give as few false cache hits as
possible. However, in certain situations it’s possible that
you know things that ccache can’t take for granted.
[The CCACHE_SLOPINESS environment variable] makes it possible
to tell ccache to relax some checks in order to increase the
hit rate.
We can relax the ctime/mtime header checks:
- include_file_ctime
By default, ccache also will not cache a file if it
includes a header whose ctime is too new. This option
disables that check.
- include_file_mtime
By default, ccache will not cache a file if it includes
a header whose mtime is too new. This option disables
that check.
We also add a call to clear the cache statistics before running
the build, and display them when the build finishes.
See https://docs.travis-ci.com/user/caching/#ccache-cache
Suggested-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 8d2e89da533..5a878ae6ae9 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -70,6 +70,9 @@ env:
- TEST_CMD="make check -j3 V=1"
# This is broadly a list of "mainline" softmmu targets which have support
across the major distros
-
MAIN_SOFTMMU_TARGETS="aarch64-softmmu,arm-softmmu,i386-softmmu,mips-softmmu,mips64-softmmu,ppc64-softmmu,riscv64-softmmu,s390x-softmmu,x86_64-softmmu"
+- CCACHE_SLOPPINESS="include_file_ctime,include_file_mtime"
+- CCACHE_MAXSIZE=1G
+
git:
# we want to do this ourselves
@@ -77,10 +80,13 @@ git:
before_script:
+ - command -v ccache && ccache --zero-stats
- mkdir -p ${BUILD_DIR} && cd ${BUILD_DIR}
- ${SRC_DIR}/configure ${BASE_CONFIG} ${CONFIG} || { cat config.log && exit
1; }
script:
- make -j3 && travis_retry ${TEST_CMD}
+after_script:
+ - command -v ccache && ccache --show-stats
matrix:
--
2.20.1
[Qemu-devel] [PATCH v6 3/4] block/ide/scsi: Set BLK_PERM_SUPPORT_HM_ZONED
Added a new boolean argument to blkconf_apply_backend_options()
to let the common block code know whether the chosen block
backend can handle host managed zoned block devices.
blkconf_apply_backend_options() then sets BLK_PERM_SUPPORT_HM_ZONED
permission accordingly. The raw code can then use this permission
to allow or deny opening a zone device by a particular block driver.
Signed-off-by: Dmitry Fomichev
Acked-by: Paul Durrant
Reviewed-by: Stefan Hajnoczi
---
hw/block/block.c | 8 ++--
hw/block/fdc.c | 5 +++--
hw/block/nvme.c | 2 +-
hw/block/virtio-blk.c| 2 +-
hw/block/xen-block.c | 2 +-
hw/ide/qdev.c| 2 +-
hw/scsi/scsi-disk.c | 13 +++--
hw/scsi/scsi-generic.c | 2 +-
hw/usb/dev-storage.c | 2 +-
include/hw/block/block.h | 3 ++-
10 files changed, 24 insertions(+), 17 deletions(-)
diff --git a/hw/block/block.c b/hw/block/block.c
index bf56c7612b..19f0e77bb2 100644
--- a/hw/block/block.c
+++ b/hw/block/block.c
@@ -86,7 +86,8 @@ void blkconf_blocksizes(BlockConf *conf)
}
bool blkconf_apply_backend_options(BlockConf *conf, bool readonly,
- bool resizable, Error **errp)
+ bool resizable, bool zoned_support,
+ Error **errp)
{
BlockBackend *blk = conf->blk;
BlockdevOnError rerror, werror;
@@ -98,9 +99,12 @@ bool blkconf_apply_backend_options(BlockConf *conf, bool
readonly,
if (!readonly) {
perm |= BLK_PERM_WRITE;
}
+if (zoned_support) {
+perm |= BLK_PERM_SUPPORT_HM_ZONED;
+}
shared_perm = BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE_UNCHANGED |
- BLK_PERM_GRAPH_MOD;
+ BLK_PERM_GRAPH_MOD | BLK_PERM_SUPPORT_HM_ZONED;
if (resizable) {
shared_perm |= BLK_PERM_RESIZE;
}
diff --git a/hw/block/fdc.c b/hw/block/fdc.c
index ac5d31e8c1..673a8b39bc 100644
--- a/hw/block/fdc.c
+++ b/hw/block/fdc.c
@@ -477,7 +477,7 @@ static void fd_change_cb(void *opaque, bool load, Error
**errp)
} else {
if (!blkconf_apply_backend_options(drive->conf,
blk_is_read_only(drive->blk), false,
- errp)) {
+ false, errp)) {
return;
}
}
@@ -569,7 +569,8 @@ static void floppy_drive_realize(DeviceState *qdev, Error
**errp)
dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
-if (!blkconf_apply_backend_options(>conf, read_only, false, errp)) {
+if (!blkconf_apply_backend_options(>conf, read_only, false, false,
+ errp)) {
return;
}
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 12d8254250..07f08d0768 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -1334,7 +1334,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
}
blkconf_blocksizes(>conf);
if (!blkconf_apply_backend_options(>conf, blk_is_read_only(n->conf.blk),
- false, errp)) {
+ false, false, errp)) {
return;
}
diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c
index 18851601cb..8be62903e2 100644
--- a/hw/block/virtio-blk.c
+++ b/hw/block/virtio-blk.c
@@ -1127,7 +1127,7 @@ static void virtio_blk_device_realize(DeviceState *dev,
Error **errp)
if (!blkconf_apply_backend_options(>conf,
blk_is_read_only(conf->conf.blk), true,
- errp)) {
+ false, errp)) {
return;
}
s->original_wce = blk_enable_write_cache(conf->conf.blk);
diff --git a/hw/block/xen-block.c b/hw/block/xen-block.c
index f77343db60..57fe970908 100644
--- a/hw/block/xen-block.c
+++ b/hw/block/xen-block.c
@@ -229,7 +229,7 @@ static void xen_block_realize(XenDevice *xendev, Error
**errp)
}
if (!blkconf_apply_backend_options(conf, blockdev->info & VDISK_READONLY,
- true, errp)) {
+ true, false, errp)) {
return;
}
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
index 6fba6b62b8..a57a8f1a8f 100644
--- a/hw/ide/qdev.c
+++ b/hw/ide/qdev.c
@@ -200,7 +200,7 @@ static void ide_dev_initfn(IDEDevice *dev, IDEDriveKind
kind, Error **errp)
}
}
if (!blkconf_apply_backend_options(>conf, kind == IDE_CD,
- kind != IDE_CD, errp)) {
+ kind != IDE_CD, false, errp)) {
return;
}
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index 915641a0f1..8a57caafd7 100644
--- a/hw/scsi/scsi-disk.c
+++ b/hw/scsi/scsi-disk.c
@@ -2318,7 +2318,7 @@ static void scsi_disk_unit_attention_reported(SCSIDevice
*dev)
Re: [Qemu-devel] [PATCH v1 00/42] current testing/next queue (podman, docker, ci)
Patchew URL: https://patchew.org/QEMU/20190904203013.9028-1-alex.ben...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PATCH v1 00/42] current testing/next queue (podman, docker, ci) Message-id: 20190904203013.9028-1-alex.ben...@linaro.org === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 0fbbd2b tests/docker: don't always encoding for subprocess.check_output 5b2ad81 tests/docker: --disable-libssh on ubuntu1804 builds c3ee1ae Fedora images: use URLs from stable "archives.fedoraproject.org" 942403a .travis.yml: Cache Linux/Clang jobs together 5e27a63 .travis.yml: Cache Linux/GCC 'non-debug profile' jobs together eb3387c .travis.yml: Cache Linux/GCC 'debug profile' jobs together b88f2bb .travis.yml: Document how the build matrix use caches a655c67 .travis.yml: Enable ccache on OSX 5ffee09 .travis.yml: Improve ccache use aff75d2 .travis.yml: Cache Avocado cache f16c75b .travis.yml: Cache Python PIP packages 0833369 .travis.yml: Increase cache timeout from 3min to 20min 0b7ee1a .travis.yml: Enable multiple caching features cc73e57 configure: check if --no-pie is supported first 08b9a33 tests/docker: add more images to PARTIAL_IMAGES when not on x86_64 5cc1f1f tests/docker: use --arch-only for installing deps 0134450 tests/docker: add debian-amd64-cross for non-x86 hosts 2a70b8d tests/docker: avoid $SHELL invoke bash directly 3d28ab1 tests/docker: add debian9-mxe to DEBIAN_PARTIAL_IMAGES 324696f tests/docker: add debian-xtensa-cross to DEBIAN_PARTIAL_IMAGES c465faa tests/docker: drop powerpc-user image for QEMU cross builds 213eeb6 tests/docker: drop debian-sid image 9f2f21c tests/docker: move our ppc64 cross compile to Buster f898a09 tests/docker: move our riscv64 cross compile to Buster a60a7b9 tests/docker: move our mips64 cross compile to Buster 2e05203 tests/docker: move our sh4 cross compile to Buster dbcdf48 tests/docker: move our sparc64 cross compile to Buster 1c3befa tests/docker: move our m68k cross compile to Buster 654bcae tests/docker: move our HPPA cross compile to Buster 0e725a4 tests/docker: move our Alpha cross compile to Buster ca3a13e tests/docker: move our powerpc cross compile to Buster b92b820 tests/docker: move our arm64 cross compile to Buster 388f703 tests/docker: add Buster to DOCKER_PARTIAL_IMAGES 102d04a tests/docker: set DEF_TARGET_LIST for some containers fc29026 tests/docker: move DEF_TARGET_LIST setting to common.rc 56cd636 tests/tcg: add .gitignore for in source builds 3bad540 tests/tcg: move configuration to a sub-shell script 5f89352 tests/tcg: cleanup Makefile inclusions e9af276 tests/tcg: use EXTRA_CFLAGS everywhere dac6b94 tests/docker: fix "cc" command to work with podman eefeff4 configure: clean-up container cross compile detect 1cd7a8b hw/misc: Mark most objects as "common" code to speed up compilation a litte bit === OUTPUT BEGIN === 1/42 Checking commit 1cd7a8bf605d (hw/misc: Mark most objects as "common" code to speed up compilation a litte bit) 2/42 Checking commit eefeff4f57f7 (configure: clean-up container cross compile detect) 3/42 Checking commit dac6b9434eb1 (tests/docker: fix "cc" command to work with podman) 4/42 Checking commit e9af276e922a (tests/tcg: use EXTRA_CFLAGS everywhere) 5/42 Checking commit 5f89352ea324 (tests/tcg: cleanup Makefile inclusions) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #84: rename from tests/tcg/Makefile.probe total: 0 errors, 1 warnings, 341 lines checked Patch 5/42 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 6/42 Checking commit 3bad54027509 (tests/tcg: move configuration to a sub-shell script) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #706: deleted file mode 100644 WARNING: line over 80 characters #920: FILE: tests/tcg/configure.sh:174: + container_cross_cc=/opt/2018.02/xtensa-dc232b-elf/bin/xtensa-dc232b-elf-gcc WARNING: line over 80 characters #926: FILE: tests/tcg/configure.sh:180: + echo "# Automatically generated by configure - do not modify" > $config_target_mak ERROR: line over 90 characters #953: FILE: tests/tcg/configure.sh:207: +if ! do_compiler "$target_compiler" $target_compiler_cflags -o $TMPE $TMPC -static ; then WARNING: line over 80 characters #955: FILE: tests/tcg/configure.sh:209: + if ! do_compiler "$target_compiler" $target_compiler_cflags -o $TMPE $TMPC ; then WARNING: line over 80 characters #968: FILE: tests/tcg/configure.sh:222: + if test $got_cross_cc = no && test "$docker" != no && test -n "$container_image";
[Qemu-devel] [PATCH v6 2/4] raw: Recognize zoned backing devices
The purpose of this patch is to recognize a zoned block device (ZBD)
when it is opened as a raw file. The new code initializes the zoned
model propery introduced by the previous commit.
This commit is Linux-specific as it gets the Zoned Block Device Model
value (none/host-managed/host-aware) from sysfs on the host.
In order to avoid code duplication in file-posix.c, a common helper
function is added to read values of sysfs entries under
/sys/block//queue. This way, the existing function that reads
the value of "max_segments" entry and the the new function that reads
"zoned" value both share the same helper code.
Signed-off-by: Dmitry Fomichev
---
block/file-posix.c | 75 ++
block/io.c | 5
2 files changed, 67 insertions(+), 13 deletions(-)
diff --git a/block/file-posix.c b/block/file-posix.c
index fbeb0068db..c7e1aff6eb 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -1067,15 +1067,13 @@ static int sg_get_max_transfer_length(int fd)
#endif
}
-static int sg_get_max_segments(int fd)
+static int hdev_read_blk_queue_entry(int fd, const char *key,
+char *buf, int buf_len)
{
#ifdef CONFIG_LINUX
-char buf[32];
-const char *end;
char *sysfspath = NULL;
int ret;
int sysfd = -1;
-long max_segments;
struct stat st;
if (fstat(fd, )) {
@@ -1083,23 +1081,45 @@ static int sg_get_max_segments(int fd)
goto out;
}
-sysfspath = g_strdup_printf("/sys/dev/block/%u:%u/queue/max_segments",
-major(st.st_rdev), minor(st.st_rdev));
+sysfspath = g_strdup_printf("/sys/dev/block/%u:%u/queue/%s",
+major(st.st_rdev), minor(st.st_rdev), key);
sysfd = open(sysfspath, O_RDONLY);
if (sysfd == -1) {
ret = -errno;
goto out;
}
do {
-ret = read(sysfd, buf, sizeof(buf) - 1);
+ret = read(sysfd, buf, buf_len - 1);
} while (ret == -1 && errno == EINTR);
if (ret < 0) {
ret = -errno;
-goto out;
} else if (ret == 0) {
ret = -EIO;
+}
+out:
+if (sysfd != -1) {
+close(sysfd);
+}
+g_free(sysfspath);
+return ret;
+#else
+return -ENOTSUP;
+#endif
+}
+
+static int sg_get_max_segments(int fd)
+{
+#ifdef CONFIG_LINUX
+char buf[32];
+const char *end;
+int ret;
+long max_segments;
+
+ret = hdev_read_blk_queue_entry(fd, "max_segments", buf, sizeof(buf));
+if (ret < 0) {
goto out;
}
+
buf[ret] = 0;
/* The file is ended with '\n', pass 'end' to accept that. */
ret = qemu_strtol(buf, , 10, _segments);
@@ -1108,22 +1128,45 @@ static int sg_get_max_segments(int fd)
}
out:
-if (sysfd != -1) {
-close(sysfd);
-}
-g_free(sysfspath);
return ret;
#else
return -ENOTSUP;
#endif
}
+static BdrvZonedModel hdev_get_zoned_model(int fd)
+{
+#ifdef CONFIG_LINUX
+char buf[32];
+BdrvZonedModel zm = BDRV_ZONED_MODEL_NONE;
+int ret;
+
+ret = hdev_read_blk_queue_entry(fd, "zoned", buf, sizeof(buf));
+if (ret < 0) {
+goto out;
+}
+
+buf[ret - 1] = '\0'; /* replace the newline character with NULL */
+if (strcmp(buf, "host-managed") == 0) {
+zm = BDRV_ZONED_MODEL_HM;
+} else if (strcmp(buf, "host-aware") == 0) {
+zm = BDRV_ZONED_MODEL_HA;
+}
+
+out:
+return zm;
+#else
+return BDRV_ZONED_MODEL_NONE;
+#endif
+}
+
static void raw_refresh_limits(BlockDriverState *bs, Error **errp)
{
BDRVRawState *s = bs->opaque;
+int ret;
if (bs->sg) {
-int ret = sg_get_max_transfer_length(s->fd);
+ret = sg_get_max_transfer_length(s->fd);
if (ret > 0 && ret <= BDRV_REQUEST_MAX_BYTES) {
bs->bl.max_transfer = pow2floor(ret);
@@ -1133,6 +1176,12 @@ static void raw_refresh_limits(BlockDriverState *bs,
Error **errp)
if (ret > 0) {
bs->bl.max_transfer = MIN(bs->bl.max_transfer, ret *
getpagesize());
}
+
+}
+
+ret = hdev_get_zoned_model(s->fd);
+if (ret >= 0) {
+bs->bl.zoned_model = ret;
}
raw_probe_alignment(bs, s->fd, errp);
diff --git a/block/io.c b/block/io.c
index 0fa10831ed..147c320061 100644
--- a/block/io.c
+++ b/block/io.c
@@ -157,6 +157,11 @@ void bdrv_refresh_limits(BlockDriverState *bs, Error
**errp)
return;
}
bdrv_merge_limits(>bl, >file->bs->bl);
+
+/* Propagate zoned model */
+if (!bs->probed) {
+bs->bl.zoned_model = bs->file->bs->bl.zoned_model;
+}
} else {
bs->bl.min_mem_alignment = 512;
bs->bl.opt_mem_alignment = getpagesize();
--
2.21.0
[Qemu-devel] [PATCH v6 4/4] raw: Don't open ZBDs if backend can't handle them
Abort opening a zoned device as a raw file in case the chosen
block backend driver lacks proper support for this type of
storage.
Signed-off-by: Dmitry Fomichev
---
block/file-posix.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/block/file-posix.c b/block/file-posix.c
index c7e1aff6eb..f11d589f90 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -2883,6 +2883,20 @@ static int raw_check_perm(BlockDriverState *bs, uint64_t
perm, uint64_t shared,
goto fail;
}
}
+
+/*
+ * If we are opening a zoned block device, check if the backend
+ * driver can properly handle host-managed devices, abort if not.
+ */
+if (bdrv_is_hm_zoned(bs) &&
+(shared & BLK_PERM_SUPPORT_HM_ZONED) &&
+!(perm & BLK_PERM_SUPPORT_HM_ZONED)) {
+error_setg(errp,
+ "block backend driver doesn't support host-managed zoned
devices");
+ret = -ENOTSUP;
+goto fail;
+}
+
return 0;
fail:
--
2.21.0
Re: [Qemu-devel] [Qemu-block] [PATCH v5 0/4] virtio/block: handle zoned backing devices
On Wed, 2019-08-28 at 10:41 +0100, Stefan Hajnoczi wrote: > On Fri, Aug 23, 2019 at 03:49:23PM -0400, Dmitry Fomichev wrote: > > Dmitry Fomichev (4): > > block: Add zoned device model property > > raw: Recognize zoned backing devices > > block/ide/scsi: Set BLK_PERM_SUPPORT_ZONED > > raw: Don't open ZBDs if backend can't handle them > > The overall approach looks good. > > I wonder if bdrv_get_zoned_info() is really needed since zone_model is > part of BlockLimits and is already fetched via bdrv_refresh_limits(). > Was it introduced because the block limits haven't been or cannot be > fetched when zone_model is queried the first time? It would be nice to > get rid of bdrv_get_zoned_info() if possible. Stefan, Thank you for your review. I've just sent out the new version of the patchset, v6, that addresses you comments. I was able to get rid of bdrv_get_zoned_info() template function as a part of the latest changes. Best regards, Dmitry
[Qemu-devel] [PATCH v1 37/42] .travis.yml: Cache Linux/GCC 'debug profile' jobs together
From: Philippe Mathieu-Daudé
These jobs build different components but use the same
host features. Put them in the same cache bucket.
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index ab3e4ebaadf..ab4ee425e4f 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -120,11 +120,13 @@ matrix:
- env:
- CONFIG="--enable-debug --enable-debug-tcg --disable-user"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-debug"
# TCG debug can be run just on it's own and is mostly agnostic to
user/softmmu distinctions
- env:
- CONFIG="--enable-debug-tcg --disable-system"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-debug"
- env:
--
2.20.1
[Qemu-devel] [PATCH v1 22/42] tests/docker: drop powerpc-user image for QEMU cross builds
Now Jessie has entered LTS the powerpc architecture has been dropped
so we can no longer build the image from scratch. We will still
support a minimal powerpc-cross image for building testcases.
Signed-off-by: Alex Bennée
Cc: David Gibson
---
tests/docker/Makefile.include | 8
.../dockerfiles/debian-powerpc-user-cross.docker | 15 ---
2 files changed, 23 deletions(-)
delete mode 100644 tests/docker/dockerfiles/debian-powerpc-user-cross.docker
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index 59fbebbe2e6..f4e9dfc0120 100644
--- a/tests/docker/Makefile.include
+++ b/tests/docker/Makefile.include
@@ -126,14 +126,6 @@ DOCKER_PARTIAL_IMAGES += fedora-cris-cross
# work around issues with poorly working multi-arch systems and broken
# packages.
-# Jessie is the last supported release for powerpc, but multi-arch is
-# broken so we need a qemu-linux-user for this target
-docker-binfmt-image-debian-powerpc-user: DEB_ARCH = powerpc
-docker-binfmt-image-debian-powerpc-user: DEB_TYPE = jessie
-docker-binfmt-image-debian-powerpc-user: EXECUTABLE =
${BUILD_DIR}/ppc-linux-user/qemu-ppc
-docker-image-debian-powerpc-user-cross: docker-binfmt-image-debian-powerpc-user
-DOCKER_USER_IMAGES += debian-powerpc-user
-
# Expand all the pre-requistes for each docker image and test combination
$(foreach i,$(filter-out $(DOCKER_PARTIAL_IMAGES),$(DOCKER_IMAGES)
$(DOCKER_DEPRECATED_IMAGES)), \
$(foreach t,$(DOCKER_TESTS) $(DOCKER_TOOLS), \
diff --git a/tests/docker/dockerfiles/debian-powerpc-user-cross.docker
b/tests/docker/dockerfiles/debian-powerpc-user-cross.docker
deleted file mode 100644
index 6938a845ee2..000
--- a/tests/docker/dockerfiles/debian-powerpc-user-cross.docker
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Docker powerpc cross-compiler target for QEMU
-#
-# We can't use current Debian stable cross-compilers to build powerpc
-# as it has been dropped as a release architecture. Using Debian Sid
-# is just far too sketchy a build environment. This leaves us the
-# final option of using linux-user. This image is based of the
-# debootstrapped qemu:debian-powerpc-user but doesn't need any extra
-# magic once it is setup.
-#
-FROM qemu:debian-powerpc-user
-
-RUN echo man-db man-db/auto-update boolean false | debconf-set-selections
-RUN apt-get update && \
-DEBIAN_FRONTEND=noninteractive apt-get build-dep -yy qemu
--
2.20.1
[Qemu-devel] [PATCH v6 0/4] virtio/block: handle zoned backing devices
Currently, attaching zoned block devices (i.e., storage devices compliant to ZAC/ZBC standards) using several virtio methods doesn't work properly as zoned devices appear as regular block devices at the guest. This may cause unexpected i/o errors and, potentially, some data corruption. To be more precise, attaching a zoned device via virtio-pci-blk, virtio-scsi-pci/scsi-disk or virtio-scsi-pci/scsi-hd demonstrates the above behavior. The virtio-scsi-pci/scsi-block method works with a recent patch. The virtio-scsi-pci/scsi-generic method also appears to handle zoned devices without problems. This patch set adds code to check if the backing device that is being opened is a zoned Host Managed device. If this is the case, the patch prohibits attaching such device for all use cases lacking proper zoned support. Host Aware zoned block devices are designed to work as regular block devices at a guest system that does not support ZBD. Therefore, this patch set doesn't prohibit attachment of Host Aware devices. Considering that there is still a couple of different working ways to attach a ZBD, this patch set provides a reasonable short-term solution for this problem. ZBD support for virtio-scsi-pci/scsi-disk and virtio-scsi-pci/scsi-hd does not seem as necessary. Users will be expected to attach zoned block devices via virtio-scsi-pci/scsi-block instead. This patch set contains some Linux-specific code. This code is necessary to obtain Zoned Block Device model value from Linux sysfs. History: v1 -> v2: - rework code to be permission-based - always allow Host Aware devices to be attached - add fix for Host Aware attachments aka RCAP output snoop v2 -> v3: - drop the patch for RCAP output snoop - merged separately v3 -> v4: - rebase to the current code v4 -> v5: - avoid checkpatch warning v5 -> v6: - address review comments from Stefan Hajnoczi Dmitry Fomichev (4): block: Add zoned device model property raw: Recognize zoned backing devices block/ide/scsi: Set BLK_PERM_SUPPORT_HM_ZONED raw: Don't open ZBDs if backend can't handle them block.c | 15 +++ block/file-posix.c| 89 +-- block/io.c| 5 +++ hw/block/block.c | 8 +++- hw/block/fdc.c| 5 ++- hw/block/nvme.c | 2 +- hw/block/virtio-blk.c | 2 +- hw/block/xen-block.c | 2 +- hw/ide/qdev.c | 2 +- hw/scsi/scsi-disk.c | 13 +++--- hw/scsi/scsi-generic.c| 2 +- hw/usb/dev-storage.c | 2 +- include/block/block.h | 19 - include/block/block_int.h | 3 ++ include/hw/block/block.h | 3 +- 15 files changed, 141 insertions(+), 31 deletions(-) -- 2.21.0
[Qemu-devel] [RFC PATCH 12/15] aspeed: add support for the AST2600 eval board
Initial definitions for a simple machine using an AST2600 SoC (Cortex
CPU).
Differences with the AST2400 and the AST2500 SoCs are handled using
the ASPEED_IS_AST2600() macro. This is not optimal but it is not too
invasive either. We could modify the model to add custom instance_init
and realize handlers in the future.
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 4 +
include/hw/misc/aspeed_scu.h | 1 +
hw/arm/aspeed.c | 18
hw/arm/aspeed_soc.c | 189 ---
4 files changed, 197 insertions(+), 15 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index b427f2668a8a..74db48374531 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -12,6 +12,7 @@
#ifndef ASPEED_SOC_H
#define ASPEED_SOC_H
+#include "hw/cpu/a15mpcore.h"
#include "hw/intc/aspeed_vic.h"
#include "hw/misc/aspeed_scu.h"
#include "hw/misc/aspeed_sdmc.h"
@@ -38,6 +39,7 @@ typedef struct AspeedSoCState {
/*< public >*/
ARMCPU cpu[ASPEED_CPUS_NUM];
uint32_t num_cpus;
+A15MPPrivState a7mpcore;
MemoryRegion sram;
AspeedVICState vic;
AspeedRtcState rtc;
@@ -51,6 +53,7 @@ typedef struct AspeedSoCState {
AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
AspeedGPIOState gpio;
+AspeedGPIOState gpio_1_8v;
AspeedSDHCIState sdhci;
} AspeedSoCState;
@@ -97,6 +100,7 @@ enum {
ASPEED_SRAM,
ASPEED_SDHCI,
ASPEED_GPIO,
+ASPEED_GPIO_1_8V,
ASPEED_RTC,
ASPEED_TIMER1,
ASPEED_TIMER2,
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 1d7f7ffc1598..670804e85f28 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -43,6 +43,7 @@ typedef struct AspeedSCUState {
#define AST2600_A0_SILICON_REV 0x05000303U
#define ASPEED_IS_AST2500(si_rev) si_rev) >> 24) & 0xff) == 0x04)
+#define ASPEED_IS_AST2600(si_rev) si_rev) >> 24) & 0xff) == 0x05)
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 03cc0952e8f3..f4f1dd29b011 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -88,6 +88,9 @@ struct AspeedBoardState {
/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
+/* AST2600 evb hardware value: (QEMU prototype) */
+#define AST2600_EVB_HW_STRAP1 AST2500_EVB_HW_STRAP1
+
/*
* The max ram region is for firmwares that scan the address space
* with load/store to guess how much RAM the SoC has.
@@ -294,6 +297,12 @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(>i2c), 11), "ds1338",
0x32);
}
+static void ast2600_evb_i2c_init(AspeedBoardState *bmc)
+{
+/* Start with some devices on our I2C busses */
+ast2500_evb_i2c_init(bmc);
+}
+
static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
{
AspeedSoCState *soc = >soc;
@@ -441,6 +450,15 @@ static const AspeedBoardConfig aspeed_boards[] = {
.num_cs= 2,
.i2c_init = witherspoon_bmc_i2c_init,
.ram = 512 * MiB,
+}, {
+.name = MACHINE_TYPE_NAME("ast2600-evb"),
+.desc = "Aspeed AST2600 EVB (Cortex A7)",
+.soc_name = "ast2600-a0",
+.hw_strap1 = AST2600_EVB_HW_STRAP1,
+.fmc_model = "mx25l25635e",
+.spi_model = "mx25l25635e",
+.num_cs= 1,
+.i2c_init = ast2600_evb_i2c_init,
},
};
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 5c5fcb810944..80d7f206004c 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -81,6 +81,38 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_SDRAM] = 0x8000,
};
+static const hwaddr aspeed_soc_ast2600_memmap[] = {
+[ASPEED_SRAM] = 0x1000,
+/* 0x1600 0x17FF : AHB BUS do LPC Bus bridge */
+[ASPEED_IOMEM] = 0x1E60,
+[ASPEED_PWM] = 0x1E61,
+[ASPEED_FMC] = 0x1E62,
+[ASPEED_SPI1] = 0x1E63,
+[ASPEED_SPI2] = 0x1E641000,
+[ASPEED_ETH1] = 0x1E66,
+[ASPEED_ETH2] = 0x1E68,
+[ASPEED_VIC] = 0x1E6C,
+[ASPEED_SDMC] = 0x1E6E,
+[ASPEED_SCU] = 0x1E6E2000,
+[ASPEED_XDMA] = 0x1E6E7000,
+[ASPEED_ADC] = 0x1E6E9000,
+[ASPEED_SDHCI] = 0x1E74,
+[ASPEED_GPIO] = 0x1E78,
+[ASPEED_GPIO_1_8V] = 0x1E780800,
+[ASPEED_RTC] = 0x1E781000,
+[ASPEED_TIMER1]= 0x1E782000,
+[ASPEED_WDT] = 0x1E785000,
+[ASPEED_LPC] = 0x1E789000,
+[ASPEED_IBT] = 0x1E789140,
+[ASPEED_I2C] = 0x1E78A000,
+[ASPEED_UART1] = 0x1E783000,
+[ASPEED_UART5] = 0x1E784000,
+[ASPEED_VUART] = 0x1E787000,
+[ASPEED_SDRAM] = 0x8000,
+};
+
+#define
[Qemu-devel] [RFC PATCH 14/15] aspeed: add support for the Aspeed MII controller of the AST2600
The AST2600 SoC has an extra controller to set the PHY registers.
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 5 ++
include/hw/net/ftgmac100.h | 17
hw/arm/aspeed_soc.c | 25 ++
hw/net/ftgmac100.c | 162
4 files changed, 209 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 30b67a09f13c..9e06a6ad4fbd 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -52,6 +52,7 @@ typedef struct AspeedSoCState {
AspeedSDMCState sdmc;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
+AspeedMiiState mii[ASPEED_MACS_NUM];
AspeedGPIOState gpio;
AspeedGPIOState gpio_1_8v;
AspeedSDHCIState sdhci;
@@ -120,6 +121,10 @@ enum {
ASPEED_ETH2,
ASPEED_ETH3,
ASPEED_ETH4,
+ASPEED_MII1,
+ASPEED_MII2,
+ASPEED_MII3,
+ASPEED_MII4,
ASPEED_SDRAM,
ASPEED_XDMA,
};
diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h
index 94cfe0533297..ab37e7b2b8ae 100644
--- a/include/hw/net/ftgmac100.h
+++ b/include/hw/net/ftgmac100.h
@@ -66,4 +66,21 @@ typedef struct FTGMAC100State {
uint32_t rxdes0_edorr;
} FTGMAC100State;
+#define TYPE_ASPEED_MII "aspeed-mmi"
+#define ASPEED_MII(obj) OBJECT_CHECK(AspeedMiiState, (obj), TYPE_ASPEED_MII)
+
+/*
+ * AST2600 MII controller
+ */
+typedef struct AspeedMiiState {
+/*< private >*/
+SysBusDevice parent_obj;
+
+FTGMAC100State *nic;
+
+MemoryRegion iomem;
+uint32_t phycr;
+uint32_t phydata;
+} AspeedMiiState;
+
#endif
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 8069de8d5a36..c3f99849b7f0 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -89,6 +89,10 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_FMC] = 0x1E62,
[ASPEED_SPI1] = 0x1E63,
[ASPEED_SPI2] = 0x1E641000,
+[ASPEED_MII1] = 0x1E65,
+[ASPEED_MII2] = 0x1E650008,
+[ASPEED_MII3] = 0x1E650010,
+[ASPEED_MII4] = 0x1E650018,
[ASPEED_ETH1] = 0x1E66,
[ASPEED_ETH3] = 0x1E67,
[ASPEED_ETH2] = 0x1E68,
@@ -313,6 +317,14 @@ static void aspeed_soc_init(Object *obj)
for (i = 0; i < sc->info->macs_num; i++) {
sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(>ftgmac100[i]),
sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
+
+if (ASPEED_IS_AST2600(sc->info->silicon_rev)) {
+sysbus_init_child_obj(obj, "mii[*]", >mii[i], sizeof(s->mii[i]),
+ TYPE_ASPEED_MII);
+object_property_add_const_link(OBJECT(>mii[i]), "nic",
+ OBJECT(>ftgmac100[i]),
+ _abort);
+}
}
sysbus_init_child_obj(obj, "xdma", OBJECT(>xdma), sizeof(s->xdma),
@@ -562,6 +574,19 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
sc->info->memmap[ASPEED_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(>ftgmac100[i]), 0,
aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
+
+
+if (ASPEED_IS_AST2600(sc->info->silicon_rev)) {
+object_property_set_bool(OBJECT(>mii[i]), true, "realized",
+ );
+if (err) {
+error_propagate(errp, err);
+return;
+}
+
+sysbus_mmio_map(SYS_BUS_DEVICE(>mii[i]), 0,
+sc->info->memmap[ASPEED_MII1 + i]);
+}
}
/* XDMA */
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 04c78e85170b..eb8b441461a1 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -15,6 +15,7 @@
#include "hw/irq.h"
#include "hw/net/ftgmac100.h"
#include "sysemu/dma.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "net/checksum.h"
@@ -1087,9 +1088,170 @@ static const TypeInfo ftgmac100_info = {
.class_init = ftgmac100_class_init,
};
+/*
+ * AST2600 MII controller
+ */
+#define ASPEED_MII_PHYCR_FIREBIT(31)
+#define ASPEED_MII_PHYCR_ST_22 BIT(28)
+#define ASPEED_MII_PHYCR_OP(x) ((x) & (ASPEED_MII_PHYCR_OP_WRITE | \
+ ASPEED_MII_PHYCR_OP_READ))
+#define ASPEED_MII_PHYCR_OP_WRITEBIT(26)
+#define ASPEED_MII_PHYCR_OP_READ BIT(27)
+#define ASPEED_MII_PHYCR_DATA(x) (x & 0x)
+#define ASPEED_MII_PHYCR_PHY(x) (((x) >> 21) & 0x1f)
+#define ASPEED_MII_PHYCR_REG(x) (((x) >> 16) & 0x1f)
+
+#define ASPEED_MII_PHYDATA_IDLE BIT(16)
+
+static void aspeed_mii_transition(AspeedMiiState *s, bool fire)
+{
+if (fire) {
+s->phycr |= ASPEED_MII_PHYCR_FIRE;
+s->phydata &= ~ASPEED_MII_PHYDATA_IDLE;
+} else {
+s->phycr &= ~ASPEED_MII_PHYCR_FIRE;
+s->phydata |=
[Qemu-devel] [RFC PATCH 09/15] hw: wdt_aspeed: Add AST2600 support
From: Joel Stanley
The AST2600 has four watchdogs, and they each have a 0x40 of registers.
When running as part of an ast2600 system we must check a different
offset for the system reset control register in the SCU.
Signed-off-by: Joel Stanley
[clg: - reworked mode integration into new objet class ]
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 2 +-
include/hw/watchdog/wdt_aspeed.h | 1 +
hw/watchdog/wdt_aspeed.c | 29 +
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index ba5bbb53e1a1..b427f2668a8a 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -27,7 +27,7 @@
#include "hw/sd/aspeed_sdhci.h"
#define ASPEED_SPIS_NUM 2
-#define ASPEED_WDTS_NUM 3
+#define ASPEED_WDTS_NUM 4
#define ASPEED_CPUS_NUM 2
#define ASPEED_MACS_NUM 2
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index 796342764e2e..dfedd7662dd1 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -18,6 +18,7 @@
OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
+#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
#define ASPEED_WDT_REGS_MAX(0x20 / 4)
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 9e241b7c8da4..6870dcf0c107 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -40,12 +40,14 @@
#define WDT_DRIVE_TYPE_MASK (0xFF << 24)
#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
#define WDT_OPEN_DRAIN_MAGIC(0x8A << 24)
+#define WDT_RESET_MASK1 (0x1c / 4)
#define WDT_TIMEOUT_STATUS (0x10 / 4)
#define WDT_TIMEOUT_CLEAR (0x14 / 4)
#define WDT_RESTART_MAGIC 0x4755
+#define AST2600_SCU_RESET_CONTROL1 (0x40 / 4)
#define SCU_RESET_CONTROL1 (0x04 / 4)
#defineSCU_RESET_SDRAM BIT(0)
@@ -74,6 +76,8 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset,
unsigned size)
return s->regs[WDT_CTRL];
case WDT_RESET_WIDTH:
return s->regs[WDT_RESET_WIDTH];
+case WDT_RESET_MASK1:
+return s->regs[WDT_RESET_MASK1];
case WDT_TIMEOUT_STATUS:
case WDT_TIMEOUT_CLEAR:
qemu_log_mask(LOG_UNIMP,
@@ -146,6 +150,11 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset,
uint64_t data,
s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask;
break;
+case WDT_RESET_MASK1:
+/* TODO: implement */
+s->regs[WDT_RESET_MASK1] = data;
+break;
+
case WDT_TIMEOUT_STATUS:
case WDT_TIMEOUT_CLEAR:
qemu_log_mask(LOG_UNIMP,
@@ -316,12 +325,32 @@ static const TypeInfo aspeed_2500_wdt_info = {
.class_init = aspeed_2500_wdt_class_init,
};
+static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
+
+dc->desc = "ASPEED 2600 Watchdog Controller";
+awc->offset = 0x40;
+awc->ext_pulse_width_mask = 0xf; /* TODO */
+awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
+awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
+}
+
+static const TypeInfo aspeed_2600_wdt_info = {
+.name = TYPE_ASPEED_2600_WDT,
+.parent = TYPE_ASPEED_WDT,
+.instance_size = sizeof(AspeedWDTState),
+.class_init = aspeed_2600_wdt_class_init,
+};
+
static void wdt_aspeed_register_types(void)
{
watchdog_add_model();
type_register_static(_wdt_info);
type_register_static(_2400_wdt_info);
type_register_static(_2500_wdt_info);
+type_register_static(_2600_wdt_info);
}
type_init(wdt_aspeed_register_types)
--
2.21.0
[Qemu-devel] [PATCH v6 1/4] block: Add zoned device model property
This commit adds Zoned Device Model (as defined in T10 ZBC and
T13 ZAC standards) as a block driver property, along with some
useful access functions.
A new backend driver permission, BLK_PERM_SUPPORT_HM_ZONED, is also
introduced. Only the drivers having this permission will be allowed
to open host managed zoned block devices.
No code is added yet to initialize or check the value of this new
property, therefore this commit doesn't change any functionality.
Signed-off-by: Dmitry Fomichev
---
block.c | 15 +++
include/block/block.h | 19 ++-
include/block/block_int.h | 3 +++
3 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/block.c b/block.c
index 874a29a983..69f565e1e9 100644
--- a/block.c
+++ b/block.c
@@ -4679,6 +4679,21 @@ void bdrv_get_geometry(BlockDriverState *bs, uint64_t
*nb_sectors_ptr)
*nb_sectors_ptr = nb_sectors < 0 ? 0 : nb_sectors;
}
+BdrvZonedModel bdrv_get_zoned_model(BlockDriverState *bs)
+{
+return bs->bl.zoned_model;
+}
+
+bool bdrv_is_hm_zoned(BlockDriverState *bs)
+{
+/*
+ * Host Aware zone devices are supposed to be able to work
+ * just like regular block devices. Thus, we only consider
+ * Host Managed devices to be zoned here.
+ */
+return bdrv_get_zoned_model(bs) == BDRV_ZONED_MODEL_HM;
+}
+
bool bdrv_is_sg(BlockDriverState *bs)
{
return bs->sg;
diff --git a/include/block/block.h b/include/block/block.h
index 124ad40809..28d065ed80 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -271,18 +271,33 @@ enum {
*/
BLK_PERM_GRAPH_MOD = 0x10,
+/**
+ * This permission is required to open host-managed zoned block devices.
+ */
+BLK_PERM_SUPPORT_HM_ZONED = 0x20,
+
BLK_PERM_ALL= 0x1f,
DEFAULT_PERM_PASSTHROUGH= BLK_PERM_CONSISTENT_READ
| BLK_PERM_WRITE
| BLK_PERM_WRITE_UNCHANGED
- | BLK_PERM_RESIZE,
+ | BLK_PERM_RESIZE
+ | BLK_PERM_SUPPORT_HM_ZONED,
DEFAULT_PERM_UNCHANGED = BLK_PERM_ALL & ~DEFAULT_PERM_PASSTHROUGH,
};
char *bdrv_perm_names(uint64_t perm);
+/*
+ * Known zoned device models.
+ */
+typedef enum {
+BDRV_ZONED_MODEL_NONE, /* Regular block device */
+BDRV_ZONED_MODEL_HA, /* Host-aware zoned block device */
+BDRV_ZONED_MODEL_HM, /* Host-managed zoned block device */
+} BdrvZonedModel;
+
/* disk I/O throttling */
void bdrv_init(void);
void bdrv_init_with_whitelist(void);
@@ -359,6 +374,8 @@ int64_t bdrv_get_allocated_file_size(BlockDriverState *bs);
BlockMeasureInfo *bdrv_measure(BlockDriver *drv, QemuOpts *opts,
BlockDriverState *in_bs, Error **errp);
void bdrv_get_geometry(BlockDriverState *bs, uint64_t *nb_sectors_ptr);
+BdrvZonedModel bdrv_get_zoned_model(BlockDriverState *bs);
+bool bdrv_is_hm_zoned(BlockDriverState *bs);
void bdrv_refresh_limits(BlockDriverState *bs, Error **errp);
int bdrv_commit(BlockDriverState *bs);
int bdrv_change_backing_file(BlockDriverState *bs,
diff --git a/include/block/block_int.h b/include/block/block_int.h
index 0422acdf1c..928cbae9a5 100644
--- a/include/block/block_int.h
+++ b/include/block/block_int.h
@@ -635,6 +635,9 @@ typedef struct BlockLimits {
/* maximum number of iovec elements */
int max_iov;
+
+/* Zoned device model. Zero value indicates a regular block device */
+BdrvZonedModel zoned_model;
} BlockLimits;
typedef struct BdrvOpBlocker BdrvOpBlocker;
--
2.21.0
[Qemu-devel] [RFC PATCH 13/15] aspeed: Parameterise number of MACs
From: Joel Stanley
To support the ast2600's four MACs allow SoCs to specify the number
they have, and create that many.
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 5 -
hw/arm/aspeed_soc.c | 7 ++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 74db48374531..30b67a09f13c 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -30,7 +30,7 @@
#define ASPEED_SPIS_NUM 2
#define ASPEED_WDTS_NUM 4
#define ASPEED_CPUS_NUM 2
-#define ASPEED_MACS_NUM 2
+#define ASPEED_MACS_NUM 4
typedef struct AspeedSoCState {
/*< private >*/
@@ -67,6 +67,7 @@ typedef struct AspeedSoCInfo {
uint64_t sram_size;
int spis_num;
int wdts_num;
+int macs_num;
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
@@ -117,6 +118,8 @@ enum {
ASPEED_I2C,
ASPEED_ETH1,
ASPEED_ETH2,
+ASPEED_ETH3,
+ASPEED_ETH4,
ASPEED_SDRAM,
ASPEED_XDMA,
};
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 80d7f206004c..8069de8d5a36 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -90,7 +90,9 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_SPI1] = 0x1E63,
[ASPEED_SPI2] = 0x1E641000,
[ASPEED_ETH1] = 0x1E66,
+[ASPEED_ETH3] = 0x1E67,
[ASPEED_ETH2] = 0x1E68,
+[ASPEED_ETH4] = 0x1E69,
[ASPEED_VIC] = 0x1E6C,
[ASPEED_SDMC] = 0x1E6E,
[ASPEED_SCU] = 0x1E6E2000,
@@ -190,6 +192,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.sram_size= 0x8000,
.spis_num = 1,
.wdts_num = 2,
+.macs_num = 2,
.irqmap = aspeed_soc_ast2400_irqmap,
.memmap = aspeed_soc_ast2400_memmap,
.num_cpus = 1,
@@ -200,6 +203,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.sram_size= 0x9000,
.spis_num = 2,
.wdts_num = 3,
+.macs_num = 2,
.irqmap = aspeed_soc_ast2500_irqmap,
.memmap = aspeed_soc_ast2500_memmap,
.num_cpus = 1,
@@ -210,6 +214,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.sram_size= 0x1,
.spis_num = 2,
.wdts_num = 4,
+.macs_num = 4,
.irqmap = aspeed_soc_ast2600_irqmap,
.memmap = aspeed_soc_ast2600_memmap,
.num_cpus = 2,
@@ -305,7 +310,7 @@ static void aspeed_soc_init(Object *obj)
OBJECT(>scu), _abort);
}
-for (i = 0; i < ASPEED_MACS_NUM; i++) {
+for (i = 0; i < sc->info->macs_num; i++) {
sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(>ftgmac100[i]),
sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
}
--
2.21.0
[Qemu-devel] [RFC PATCH 05/15] aspeed/timer: Add support for IRQ status register on the AST2600
The AST2600 timer replaces control register 2 with a interrupt status
register. It is set by hardware when an IRQ occurs and cleared by
software.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater
---
include/hw/timer/aspeed_timer.h | 1 +
hw/timer/aspeed_timer.c | 32 ++--
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index 69b1377af01e..948329893c0b 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -60,6 +60,7 @@ typedef struct AspeedTimerCtrlState {
uint32_t ctrl;
uint32_t ctrl2;
uint32_t ctrl3;
+uint32_t irq_sts;
AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
AspeedSCUState *scu;
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 7f73d0c75337..dbf8143f0457 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -160,7 +160,9 @@ static uint64_t calculate_next(struct AspeedTimer *t)
timer_del(>timer);
if (timer_overflow_interrupt(t)) {
+AspeedTimerCtrlState *s = timer_to_ctrl(t);
t->level = !t->level;
+s->irq_sts |= BIT(t->id);
qemu_set_irq(t->irq, t->level);
}
@@ -199,7 +201,9 @@ static void aspeed_timer_expire(void *opaque)
}
if (interrupt) {
+AspeedTimerCtrlState *s = timer_to_ctrl(t);
t->level = !t->level;
+s->irq_sts |= BIT(t->id);
qemu_set_irq(t->irq, t->level);
}
@@ -244,9 +248,6 @@ static uint64_t aspeed_timer_read(void *opaque, hwaddr
offset, unsigned size)
case 0x30: /* Control Register */
value = s->ctrl;
break;
-case 0x34: /* Control Register 2 */
-value = s->ctrl2;
-break;
case 0x00 ... 0x2c: /* Timers 1 - 4 */
value = aspeed_timer_get_value(>timers[(offset >> 4)], reg);
break;
@@ -438,9 +439,6 @@ static void aspeed_timer_write(void *opaque, hwaddr offset,
uint64_t value,
case 0x30:
aspeed_timer_set_ctrl(s, tv);
break;
-case 0x34:
-aspeed_timer_set_ctrl2(s, tv);
-break;
/* Timer Registers */
case 0x00 ... 0x2c:
aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS), reg, tv);
@@ -468,6 +466,9 @@ static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState
*s, hwaddr offset)
uint64_t value;
switch (offset) {
+case 0x34:
+value = s->ctrl2;
+break;
case 0x38:
case 0x3C:
default:
@@ -482,7 +483,12 @@ static uint64_t
aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset)
static void aspeed_2400_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
uint64_t value)
{
+const uint32_t tv = (uint32_t)(value & 0x);
+
switch (offset) {
+case 0x34:
+aspeed_timer_set_ctrl2(s, tv);
+break;
case 0x38:
case 0x3C:
default:
@@ -497,6 +503,9 @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState
*s, hwaddr offset)
uint64_t value;
switch (offset) {
+case 0x34:
+value = s->ctrl2;
+break;
case 0x38:
value = s->ctrl3 & BIT(0);
break;
@@ -517,6 +526,9 @@ static void aspeed_2500_timer_write(AspeedTimerCtrlState
*s, hwaddr offset,
uint8_t command;
switch (offset) {
+case 0x34:
+aspeed_timer_set_ctrl2(s, tv);
+break;
case 0x38:
command = (value >> 1) & 0xFF;
if (command == 0xAE) {
@@ -543,6 +555,9 @@ static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState
*s, hwaddr offset)
uint64_t value;
switch (offset) {
+case 0x34:
+value = s->irq_sts;
+break;
case 0x38:
case 0x3C:
default:
@@ -560,6 +575,9 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState
*s, hwaddr offset,
const uint32_t tv = (uint32_t)(value & 0x);
switch (offset) {
+case 0x34:
+s->irq_sts &= tv;
+break;
case 0x3C:
aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
break;
@@ -626,6 +644,7 @@ static void aspeed_timer_reset(DeviceState *dev)
s->ctrl = 0;
s->ctrl2 = 0;
s->ctrl3 = 0;
+s->irq_sts = 0;
}
static const VMStateDescription vmstate_aspeed_timer = {
@@ -650,6 +669,7 @@ static const VMStateDescription vmstate_aspeed_timer_state
= {
VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState),
VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState),
+VMSTATE_UINT32(irq_sts, AspeedTimerCtrlState),
VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer,
AspeedTimer),
--
2.21.0
[Qemu-devel] [RFC PATCH 11/15] hw/gpio: Add in AST2600 specific implementation
From: Rashmica Gupta
The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
addtional two sets of 1.8V gpios.
Signed-off-by: Rashmica Gupta
Reviewed-by: Cédric Le Goater
Signed-off-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 142 --
1 file changed, 137 insertions(+), 5 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 25fbfec3b84e..196e47c26284 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -169,6 +169,48 @@
#define GPIO_3_6V_MEM_SIZE 0x1F0
#define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2)
+/* AST2600 only - 1.8V gpios */
+/*
+ * The AST2600 has same 3.6V gpios as the AST2400 (memory offsets 0x0-0x198)
+ * and addtional 1.8V gpios (memory offsets 0x800-0x9D4).
+ */
+#define GPIO_1_8V_REG_OFFSET 0x800
+#define GPIO_1_8V_ABCD_DATA_VALUE ((0x800 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_DIRECTION ((0x804 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_ENABLE ((0x808 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_SENS_0 ((0x80C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_SENS_1 ((0x810 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_SENS_2 ((0x814 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_STATUS ((0x818 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_RESET_TOLERANT ((0x81C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DATA_VALUE((0x820 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DIRECTION ((0x824 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_ENABLE((0x828 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_SENS_0((0x82C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_SENS_1((0x830 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_SENS_2((0x834 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_STATUS((0x838 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_RESET_TOLERANT((0x83C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_DEBOUNCE_1 ((0x840 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_DEBOUNCE_2 ((0x844 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DEBOUNCE_1((0x848 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DEBOUNCE_2((0x84C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_DEBOUNCE_TIME_1 ((0x850 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_DEBOUNCE_TIME_2 ((0x854 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_DEBOUNCE_TIME_3 ((0x858 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_COMMAND_SRC_0 ((0x860 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_COMMAND_SRC_1 ((0x864 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_COMMAND_SRC_0 ((0x868 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_COMMAND_SRC_1 ((0x86C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_DATA_READ ((0x8C0 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DATA_READ ((0x8C4 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INPUT_MASK ((0x9D0 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INPUT_MASK((0x9D4 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_MEM_SIZE0x9D8
+#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \
+ GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE)
+
static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)
{
uint32_t falling_edge = 0, rising_edge = 0;
@@ -465,6 +507,39 @@ static const AspeedGPIOReg
aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = {
[GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask },
};
+static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = {
+/* 1.8V Set ABCD */
+[GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value},
+[GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction},
+[GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable},
+[GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0},
+[GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1},
+[GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2},
+[GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status},
+[GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant},
+[GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1},
+[GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2},
+[GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0},
+[GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1},
+[GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read},
+[GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask},
+/* 1.8V Set E */
+[GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value},
+[GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction},
+[GPIO_1_8V_E_INT_ENABLE] = {1,
[Qemu-devel] [PATCH v1 41/42] tests/docker: --disable-libssh on ubuntu1804 builds
Currently this stops the mega: make docker-test-build from working. Once the source is patched to deal with the case this workaround can be removed. Signed-off-by: Alex Bennée --- tests/docker/dockerfiles/ubuntu1804.docker | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/docker/dockerfiles/ubuntu1804.docker b/tests/docker/dockerfiles/ubuntu1804.docker index 44bbf0f77ae..883f9bcf31c 100644 --- a/tests/docker/dockerfiles/ubuntu1804.docker +++ b/tests/docker/dockerfiles/ubuntu1804.docker @@ -56,3 +56,6 @@ RUN apt-get update && \ DEBIAN_FRONTEND=noninteractive apt-get -y install $PACKAGES RUN dpkg -l $PACKAGES | sort > /packages.txt ENV FEATURES clang pyyaml sdl2 + +# https://bugs.launchpad.net/qemu/+bug/1838763 +ENV QEMU_CONFIGURE_OPTS --disable-libssh -- 2.20.1
[Qemu-devel] [RFC PATCH 04/15] aspeed/timer: Add support for AST2600
The AST2600 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
On the AST2600, it is not configurable via 0x38 (control register 3)
as it is on the AST2500.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater
---
include/hw/timer/aspeed_timer.h | 1 +
hw/timer/aspeed_timer.c | 51 +
2 files changed, 52 insertions(+)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index 1e0288ebc49f..69b1377af01e 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -30,6 +30,7 @@
#define TYPE_ASPEED_TIMER "aspeed.timer"
#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
+#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"
#define ASPEED_TIMER_NR_TIMERS 8
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index d70e78a0293e..7f73d0c75337 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -538,6 +538,40 @@ static void aspeed_2500_timer_write(AspeedTimerCtrlState
*s, hwaddr offset,
}
}
+static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState *s, hwaddr offset)
+{
+uint64_t value;
+
+switch (offset) {
+case 0x38:
+case 0x3C:
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+__func__, offset);
+value = 0;
+break;
+}
+return value;
+}
+
+static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
+uint64_t value)
+{
+const uint32_t tv = (uint32_t)(value & 0x);
+
+switch (offset) {
+case 0x3C:
+aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
+break;
+
+case 0x38:
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+__func__, offset);
+break;
+}
+}
+
static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id)
{
AspeedTimer *t = >timers[id];
@@ -674,11 +708,28 @@ static const TypeInfo aspeed_2500_timer_info = {
.class_init = aspeed_2500_timer_class_init,
};
+static void aspeed_2600_timer_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass);
+
+dc->desc = "ASPEED 2600 Timer";
+awc->read = aspeed_2600_timer_read;
+awc->write = aspeed_2600_timer_write;
+}
+
+static const TypeInfo aspeed_2600_timer_info = {
+.name = TYPE_ASPEED_2600_TIMER,
+.parent = TYPE_ASPEED_TIMER,
+.class_init = aspeed_2600_timer_class_init,
+};
+
static void aspeed_timer_register_types(void)
{
type_register_static(_timer_info);
type_register_static(_2400_timer_info);
type_register_static(_2500_timer_info);
+type_register_static(_2600_timer_info);
}
type_init(aspeed_timer_register_types)
--
2.21.0
[Qemu-devel] [RFC PATCH 08/15] watchdog/aspeed: Introduce an object class per SoC
It cleanups the current models for the Aspeed AST2400 and AST2500 SoCs
and prepares ground for future SoCs.
Signed-off-by: Cédric Le Goater
---
include/hw/watchdog/wdt_aspeed.h | 18 -
hw/arm/aspeed_soc.c | 9 ++-
hw/watchdog/wdt_aspeed.c | 122 ---
3 files changed, 86 insertions(+), 63 deletions(-)
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index 8c5691ce2047..796342764e2e 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -16,6 +16,8 @@
#define TYPE_ASPEED_WDT "aspeed.wdt"
#define ASPEED_WDT(obj) \
OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
+#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
+#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
#define ASPEED_WDT_REGS_MAX(0x20 / 4)
@@ -30,8 +32,20 @@ typedef struct AspeedWDTState {
AspeedSCUState *scu;
uint32_t pclk_freq;
-uint32_t silicon_rev;
-uint32_t ext_pulse_width_mask;
} AspeedWDTState;
+#define ASPEED_WDT_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AspeedWDTClass, (klass), TYPE_ASPEED_WDT)
+#define ASPEED_WDT_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AspeedWDTClass, (obj), TYPE_ASPEED_WDT)
+
+typedef struct AspeedWDTClass {
+SysBusDeviceClass parent_class;
+
+uint32_t offset;
+uint32_t ext_pulse_width_mask;
+uint32_t reset_ctrl_reg;
+void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
+} AspeedWDTClass;
+
#endif /* WDT_ASPEED_H */
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index aaf18d3e42f1..5c5fcb810944 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -214,10 +214,9 @@ static void aspeed_soc_init(Object *obj)
"max-ram-size", _abort);
for (i = 0; i < sc->info->wdts_num; i++) {
+snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
sysbus_init_child_obj(obj, "wdt[*]", OBJECT(>wdt[i]),
- sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
-qdev_prop_set_uint32(DEVICE(>wdt[i]), "silicon-rev",
-sc->info->silicon_rev);
+ sizeof(s->wdt[i]), typename);
object_property_add_const_link(OBJECT(>wdt[i]), "scu",
OBJECT(>scu), _abort);
}
@@ -384,13 +383,15 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
/* Watch dog */
for (i = 0; i < sc->info->wdts_num; i++) {
+AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(>wdt[i]);
+
object_property_set_bool(OBJECT(>wdt[i]), true, "realized", );
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(>wdt[i]), 0,
-sc->info->memmap[ASPEED_WDT] + i * 0x20);
+sc->info->memmap[ASPEED_WDT] + i * awc->offset);
}
/* Net */
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 9b932134172c..9e241b7c8da4 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -54,21 +54,6 @@ static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
}
-static bool is_ast2500(const AspeedWDTState *s)
-{
-switch (s->silicon_rev) {
-case AST2500_A0_SILICON_REV:
-case AST2500_A1_SILICON_REV:
-return true;
-case AST2400_A0_SILICON_REV:
-case AST2400_A1_SILICON_REV:
-default:
-break;
-}
-
-return false;
-}
-
static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
{
AspeedWDTState *s = ASPEED_WDT(opaque);
@@ -124,6 +109,7 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset,
uint64_t data,
unsigned size)
{
AspeedWDTState *s = ASPEED_WDT(opaque);
+AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
bool enable = data & WDT_CTRL_ENABLE;
offset >>= 2;
@@ -153,24 +139,13 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset,
uint64_t data,
}
break;
case WDT_RESET_WIDTH:
-{
-uint32_t property = data & WDT_POLARITY_MASK;
-
-if (property && is_ast2500(s)) {
-if (property == WDT_ACTIVE_HIGH_MAGIC) {
-s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH;
-} else if (property == WDT_ACTIVE_LOW_MAGIC) {
-s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;
-} else if (property == WDT_PUSH_PULL_MAGIC) {
-s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL;
-} else if (property == WDT_OPEN_DRAIN_MAGIC) {
-s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;
-}
+if (awc->reset_pulse) {
+awc->reset_pulse(s, data & WDT_POLARITY_MASK);
}
-s->regs[WDT_RESET_WIDTH] &= ~s->ext_pulse_width_mask;
-
[Qemu-devel] [PATCH v1 23/42] tests/docker: add debian-xtensa-cross to DEBIAN_PARTIAL_IMAGES
This should have been marked when the docker recipe was added to prevent it being used for cross compiling QEMU. Sort the DEBIAN_PARTIAL_IMAGE list while we are at it. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index f4e9dfc0120..8d7f9376578 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -115,10 +115,15 @@ docker-image-travis: NOUSER=1 docker-image-tricore-cross: docker-image-debian9 # These images may be good enough for building tests but not for test builds -DOCKER_PARTIAL_IMAGES += debian-alpha-cross debian-hppa-cross debian-m68k-cross debian-sh4-cross -DOCKER_PARTIAL_IMAGES += debian-sparc64-cross debian-mips64-cross debian-riscv64-cross -DOCKER_PARTIAL_IMAGES += debian-tricore-cross debian-powerpc-cross debian-ppc64-cross fedora-i386-cross -DOCKER_PARTIAL_IMAGES += fedora-cris-cross +DOCKER_PARTIAL_IMAGES += debian-alpha-cross +DOCKER_PARTIAL_IMAGES += debian-hppa-cross +DOCKER_PARTIAL_IMAGES += debian-m68k-cross debian-mips64-cross +DOCKER_PARTIAL_IMAGES += debian-powerpc-cross debian-ppc64-cross +DOCKER_PARTIAL_IMAGES += debian-riscv64-cross +DOCKER_PARTIAL_IMAGES += debian-sh4-cross debian-sparc64-cross +DOCKER_PARTIAL_IMAGES += debian-tricore-cross +DOCKER_PARTIAL_IMAGES += debian-xtensa-cross +DOCKER_PARTIAL_IMAGES += fedora-i386-cross fedora-cris-cross # Rules for building linux-user powered images # -- 2.20.1
[Qemu-devel] [RFC PATCH 00/15] aspeed: Add support for the AST2600 SoC
Hello, The most important Aspeed models are reworked with an object class to introduce the AST2600 variant. A model for the AST2600 SoC and a simple AST2600 EVB machine is proposed at the end of the series. It can boot the OpenBMC firmware image which is currently used for HW bringup. I would like to have some feedback on the approach taken to instantiate the correct type of a device model for a given SoC and also on the AST2600 SoC model itself as it has some significant difference with the previous. This series is based on the previous Aspeed series : http://patchwork.ozlabs.org/cover/1157492/ Thanks, C. Cédric Le Goater (9): aspeed/timer: Introduce an object class per SoC aspeed/timer: Add support for control register 3 aspeed/timer: Add support for AST2600 aspeed/timer: Add support for IRQ status register on the AST2600 aspeed/sdmc: Introduce an object class per SoC watchdog/aspeed: Introduce an object class per SoC aspeed/smc: Add support for the AST2600 SoC aspeed: add support for the AST2600 eval board aspeed: add support for the Aspeed MII controller of the AST2600 Joel Stanley (5): hw: aspeed_scu: Add AST2600 support aspeed/sdmc: Add AST2600 support hw: wdt_aspeed: Add AST2600 support aspeed: Parameterise number of MACs aspeed/soc: Add ASPEED Video stub Rashmica Gupta (1): hw/gpio: Add in AST2600 specific implementation include/hw/arm/aspeed_soc.h | 17 ++- include/hw/misc/aspeed_scu.h | 8 +- include/hw/misc/aspeed_sdmc.h| 20 ++- include/hw/net/ftgmac100.h | 17 +++ include/hw/ssi/aspeed_smc.h | 2 + include/hw/timer/aspeed_timer.h | 18 +++ include/hw/watchdog/wdt_aspeed.h | 19 ++- hw/arm/aspeed.c | 18 +++ hw/arm/aspeed_soc.c | 243 +++--- hw/gpio/aspeed_gpio.c| 142 +- hw/misc/aspeed_scu.c | 186 ++- hw/misc/aspeed_sdmc.c| 250 +++ hw/net/ftgmac100.c | 162 hw/ssi/aspeed_smc.c | 129 +++- hw/timer/aspeed_timer.c | 209 +++--- hw/watchdog/wdt_aspeed.c | 151 --- 16 files changed, 1403 insertions(+), 188 deletions(-) -- 2.21.0
[Qemu-devel] [RFC PATCH 01/15] hw: aspeed_scu: Add AST2600 support
From: Joel Stanley
AST2600 has extra registers. Increase the number of regs of the model
and introduce a new field in the class to customize the MemoryRegion
operations depending on the SoC model.
Signed-off-by: Joel Stanley
[clg: - improved commit log ]
- reworked mode integration into new objet class ]
Signed-off-by: Cédric Le Goater
---
include/hw/misc/aspeed_scu.h | 7 +-
hw/misc/aspeed_scu.c | 184 ++-
2 files changed, 185 insertions(+), 6 deletions(-)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 239e94fe2c47..1d7f7ffc1598 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -17,8 +17,10 @@
#define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU)
#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
+#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
+#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)
typedef struct AspeedSCUState {
/*< private >*/
@@ -27,7 +29,7 @@ typedef struct AspeedSCUState {
/*< public >*/
MemoryRegion iomem;
-uint32_t regs[ASPEED_SCU_NR_REGS];
+uint32_t regs[ASPEED_AST2600_SCU_NR_REGS];
uint32_t silicon_rev;
uint32_t hw_strap1;
uint32_t hw_strap2;
@@ -38,6 +40,7 @@ typedef struct AspeedSCUState {
#define AST2400_A1_SILICON_REV 0x02010303U
#define AST2500_A0_SILICON_REV 0x04000303U
#define AST2500_A1_SILICON_REV 0x04010303U
+#define AST2600_A0_SILICON_REV 0x05000303U
#define ASPEED_IS_AST2500(si_rev) si_rev) >> 24) & 0xff) == 0x04)
@@ -54,6 +57,8 @@ typedef struct AspeedSCUClass {
const uint32_t *resets;
uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg);
uint32_t apb_divider;
+uint32_t nr_regs;
+const MemoryRegionOps *ops;
} AspeedSCUClass;
#define ASPEED_SCU_PROT_KEY 0x1688A8A8
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 620b25c20476..4190adab8220 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -88,6 +88,33 @@
#define BMC_REV TO_REG(0x19C)
#define BMC_DEV_ID TO_REG(0x1A4)
+#define AST2600_PROT_KEY TO_REG(0x00)
+#define AST2600_SILICON_REV TO_REG(0x04)
+#define AST2600_SILICON_REV2 TO_REG(0x14)
+#define AST2600_SYS_RST_CTRL TO_REG(0x40)
+#define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44)
+#define AST2600_SYS_RST_CTRL2 TO_REG(0x50)
+#define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54)
+#define AST2600_CLK_STOP_CTRL TO_REG(0x80)
+#define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
+#define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
+#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94)
+#define AST2600_MPLL_EXT TO_REG(0x224)
+#define AST2600_EPLL_EXT TO_REG(0x244)
+#define AST2600_CLK_SEL TO_REG(0x300)
+#define AST2600_CLK_SEL2 TO_REG(0x304)
+#define AST2600_CLK_SEL3 TO_REG(0x310)
+#define AST2600_HW_STRAP1 TO_REG(0x500)
+#define AST2600_HW_STRAP1_CLR TO_REG(0x504)
+#define AST2600_HW_STRAP1_PROTTO_REG(0x508)
+#define AST2600_HW_STRAP2 TO_REG(0x510)
+#define AST2600_HW_STRAP2_CLR TO_REG(0x514)
+#define AST2600_HW_STRAP2_PROTTO_REG(0x518)
+#define AST2600_RNG_CTRL TO_REG(0x524)
+#define AST2600_RNG_DATA TO_REG(0x540)
+
+#define AST2600_CLK TO_REG(0x40)
+
#define SCU_IO_REGION_SIZE 0x1000
static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
@@ -178,7 +205,7 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr
offset, unsigned size)
AspeedSCUState *s = ASPEED_SCU(opaque);
int reg = TO_REG(offset);
-if (reg >= ARRAY_SIZE(s->regs)) {
+if (reg >= ASPEED_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
@@ -208,7 +235,7 @@ static void aspeed_scu_write(void *opaque, hwaddr offset,
uint64_t data,
AspeedSCUState *s = ASPEED_SCU(opaque);
int reg = TO_REG(offset);
-if (reg >= ARRAY_SIZE(s->regs)) {
+if (reg >= ASPEED_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
@@ -346,7 +373,7 @@ static void aspeed_scu_reset(DeviceState *dev)
AspeedSCUState *s = ASPEED_SCU(dev);
AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
-memcpy(s->regs, asc->resets, sizeof(s->regs));
+memcpy(s->regs, asc->resets, asc->nr_regs * 4);
s->regs[SILICON_REV] = s->silicon_rev;
s->regs[HW_STRAP1] = s->hw_strap1;
s->regs[HW_STRAP2] = s->hw_strap2;
@@ -358,6 +385,7 @@ static uint32_t aspeed_silicon_revs[] = {
AST2400_A1_SILICON_REV,
AST2500_A0_SILICON_REV,
AST2500_A1_SILICON_REV,
+AST2600_A0_SILICON_REV,
};
bool is_supported_silicon_rev(uint32_t
[Qemu-devel] [PATCH v1 20/42] tests/docker: move our ppc64 cross compile to Buster
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 4 ++--
tests/docker/dockerfiles/debian-ppc64-cross.docker | 7 +++
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index 93190b1e2a2..b6c04059502 100644
--- a/tests/docker/Makefile.include
+++ b/tests/docker/Makefile.include
@@ -104,11 +104,11 @@ docker-image-debian-hppa-cross: docker-image-debian10
docker-image-debian-m68k-cross: docker-image-debian10
docker-image-debian-mips64-cross: docker-image-debian10
docker-image-debian-powerpc-cross: docker-image-debian10
+docker-image-debian-ppc64-cross: docker-image-debian10
docker-image-debian-riscv64-cross: docker-image-debian10
docker-image-debian-sh4-cross: docker-image-debian10
docker-image-debian-sparc64-cross: docker-image-debian10
-docker-image-debian-ppc64-cross: docker-image-debian-sid
docker-image-travis: NOUSER=1
# Specialist build images, sometimes very limited tools
@@ -117,7 +117,7 @@ docker-image-tricore-cross: docker-image-debian9
# These images may be good enough for building tests but not for test builds
DOCKER_PARTIAL_IMAGES += debian-alpha-cross debian-hppa-cross
debian-m68k-cross debian-sh4-cross
DOCKER_PARTIAL_IMAGES += debian-sparc64-cross debian-mips64-cross
debian-riscv64-cross
-DOCKER_PARTIAL_IMAGES += debian-tricore-cross debian-powerpc-cross
fedora-i386-cross
+DOCKER_PARTIAL_IMAGES += debian-tricore-cross debian-powerpc-cross
debian-ppc64-cross fedora-i386-cross
DOCKER_PARTIAL_IMAGES += fedora-cris-cross
# Rules for building linux-user powered images
diff --git a/tests/docker/dockerfiles/debian-ppc64-cross.docker
b/tests/docker/dockerfiles/debian-ppc64-cross.docker
index e5757fe46ee..4bf88ab02dd 100644
--- a/tests/docker/dockerfiles/debian-ppc64-cross.docker
+++ b/tests/docker/dockerfiles/debian-ppc64-cross.docker
@@ -1,12 +1,11 @@
#
# Docker ppc64 cross-compiler target
#
-# This docker target builds on the debian sid base image which
-# contains cross compilers for Debian "ports" targets.
-FROM qemu:debian-sid
+# This docker target builds on the debian Buster base image.
+FROM qemu:debian10
RUN apt update && \
DEBIAN_FRONTEND=noninteractive eatmydata \
apt install -y --no-install-recommends \
gcc-powerpc64-linux-gnu \
- libc6-dev-ppc64-cross || { echo "Failed to build - see
debian-sid.docker notes"; exit 1; }
+ libc6-dev-ppc64-cross
--
2.20.1
[Qemu-devel] [PULL 08/13] target/openrisc: Check CPUCFG_OF32S for float insns
Make sure the OF32S insns are enabled before allowing execution.
Include the missing bit for cpu "any".
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.c | 2 +-
target/openrisc/translate.c | 84 -
2 files changed, 36 insertions(+), 50 deletions(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 9f566ad883..f3c8134531 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -131,7 +131,7 @@ static void openrisc_any_initfn(Object *obj)
cpu->env.avr = 0x0101; /* Architecture v1.1 */
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
-cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S |
+cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
CPUCFGR_AVRP | CPUCFGR_EVBARP;
/* 1Way, TLB_SIZE entries. */
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 341f923864..2f5c969f21 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -45,6 +45,7 @@ typedef struct DisasContext {
uint32_t mem_idx;
uint32_t tb_flags;
uint32_t delayed_branch;
+uint32_t cpucfgr;
/* If not -1, jmp_pc contains this value and so is a direct jump. */
target_ulong jmp_pc_imm;
@@ -140,30 +141,11 @@ static void gen_illegal_exception(DisasContext *dc)
dc->base.is_jmp = DISAS_NORETURN;
}
-/* not used yet, open it when we need or64. */
-/*#ifdef TARGET_OPENRISC64
-static void check_ob64s(DisasContext *dc)
+static bool check_of32s(DisasContext *dc)
{
-if (!(dc->flags & CPUCFGR_OB64S)) {
-gen_illegal_exception(dc);
-}
+return dc->cpucfgr & CPUCFGR_OF32S;
}
-static void check_of64s(DisasContext *dc)
-{
-if (!(dc->flags & CPUCFGR_OF64S)) {
-gen_illegal_exception(dc);
-}
-}
-
-static void check_ov64s(DisasContext *dc)
-{
-if (!(dc->flags & CPUCFGR_OV64S)) {
-gen_illegal_exception(dc);
-}
-}
-#endif*/
-
static TCGv cpu_R(DisasContext *dc, int reg)
{
if (reg == 0) {
@@ -1157,26 +1139,37 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a)
return true;
}
-static void do_fp2(DisasContext *dc, arg_da *a,
+static bool do_fp2(DisasContext *dc, arg_da *a,
void (*fn)(TCGv, TCGv_env, TCGv))
{
+if (!check_of32s(dc)) {
+return false;
+}
check_r0_write(dc, a->d);
fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a));
gen_helper_update_fpcsr(cpu_env);
+return true;
}
-static void do_fp3(DisasContext *dc, arg_dab *a,
+static bool do_fp3(DisasContext *dc, arg_dab *a,
void (*fn)(TCGv, TCGv_env, TCGv, TCGv))
{
+if (!check_of32s(dc)) {
+return false;
+}
check_r0_write(dc, a->d);
fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
gen_helper_update_fpcsr(cpu_env);
+return true;
}
-static void do_fpcmp(DisasContext *dc, arg_ab *a,
+static bool do_fpcmp(DisasContext *dc, arg_ab *a,
void (*fn)(TCGv, TCGv_env, TCGv, TCGv),
bool inv, bool swap)
{
+if (!check_of32s(dc)) {
+return false;
+}
if (swap) {
fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a));
} else {
@@ -1186,52 +1179,50 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a,
tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
}
gen_helper_update_fpcsr(cpu_env);
+return true;
}
static bool trans_lf_add_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_add_s);
-return true;
+return do_fp3(dc, a, gen_helper_float_add_s);
}
static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_sub_s);
-return true;
+return do_fp3(dc, a, gen_helper_float_sub_s);
}
static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_mul_s);
-return true;
+return do_fp3(dc, a, gen_helper_float_mul_s);
}
static bool trans_lf_div_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_div_s);
-return true;
+return do_fp3(dc, a, gen_helper_float_div_s);
}
static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_rem_s);
+return do_fp3(dc, a, gen_helper_float_rem_s);
return true;
}
static bool trans_lf_itof_s(DisasContext *dc, arg_da *a)
{
-do_fp2(dc, a, gen_helper_itofs);
-return true;
+return do_fp2(dc, a, gen_helper_itofs);
}
static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a)
{
-do_fp2(dc, a, gen_helper_ftois);
-return true;
+return do_fp2(dc, a, gen_helper_ftois);
}
static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a)
{
+if (!check_of32s(dc)) {
+return false;
+}
check_r0_write(dc, a->d);
gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d),
cpu_R(dc,
[Qemu-devel] [PULL 12/13] target/openrisc: Implement l.adrp
This was added to the 1.3 spec.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/disas.c | 1 +
target/openrisc/translate.c | 13 +
target/openrisc/insns.decode | 2 ++
3 files changed, 16 insertions(+)
diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
index e51cbb24c6..ce112640b9 100644
--- a/target/openrisc/disas.c
+++ b/target/openrisc/disas.c
@@ -98,6 +98,7 @@ INSN(sw, "%d(r%d), r%d", a->i, a->a, a->b)
INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b)
INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b)
INSN(nop,"")
+INSN(adrp, "r%d, %d", a->d, a->i)
INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i)
INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i)
INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 6e8bc23568..6addbac8d6 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -799,6 +799,19 @@ static bool trans_l_nop(DisasContext *dc, arg_l_nop *a)
return true;
}
+static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a)
+{
+if (!check_v1_3(dc)) {
+return false;
+}
+check_r0_write(dc, a->d);
+
+tcg_gen_movi_i32(cpu_R(dc, a->d),
+ (dc->base.pc_next & TARGET_PAGE_MASK) +
+ ((target_long)a->i << TARGET_PAGE_BITS));
+return true;
+}
+
static bool trans_l_addi(DisasContext *dc, arg_rri *a)
{
TCGv t0;
diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode
index 71e0d740db..0d6f7c29f8 100644
--- a/target/openrisc/insns.decode
+++ b/target/openrisc/insns.decode
@@ -102,6 +102,8 @@ l_maci 010011 - a:5 i:s16
l_movhi 000110 d:5 0 k:16
l_macrc 000110 d:5 1
+l_adrp 10 d:5 i:s21
+
# Arithmetic Instructions
--
2.17.1
[Qemu-devel] [PATCH v1 31/42] .travis.yml: Increase cache timeout from 3min to 20min
From: Philippe Mathieu-Daudé We are going to cache few gigabytes, increase the cache timeout to avoid build failures when uploading our cache. See https://docs.travis-ci.com/user/caching/#setting-the-timeout Signed-off-by: Philippe Mathieu-Daudé --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index 612caabc6cf..8c376d22239 100644 --- a/.travis.yml +++ b/.travis.yml @@ -6,6 +6,7 @@ language: c compiler: - gcc cache: + timeout: 1200 ccache: true -- 2.20.1
[Qemu-devel] [RFC PATCH 15/15] aspeed/soc: Add ASPEED Video stub
From: Joel Stanley
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_soc.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 9e06a6ad4fbd..ef5b93e5e9cf 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -99,6 +99,7 @@ enum {
ASPEED_SDMC,
ASPEED_SCU,
ASPEED_ADC,
+ASPEED_VIDEO,
ASPEED_SRAM,
ASPEED_SDHCI,
ASPEED_GPIO,
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index c3f99849b7f0..b9da49e16f2d 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -102,6 +102,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_SCU] = 0x1E6E2000,
[ASPEED_XDMA] = 0x1E6E7000,
[ASPEED_ADC] = 0x1E6E9000,
+[ASPEED_VIDEO] = 0x1E70,
[ASPEED_SDHCI] = 0x1E74,
[ASPEED_GPIO] = 0x1E78,
[ASPEED_GPIO_1_8V] = 0x1E780800,
@@ -371,6 +372,10 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
create_unimplemented_device("aspeed_soc.io",
sc->info->memmap[ASPEED_IOMEM],
ASPEED_SOC_IOMEM_SIZE);
+/* Video engine stub */
+create_unimplemented_device("aspeed.video", sc->info->memmap[ASPEED_VIDEO],
+0x1000);
+
if (s->num_cpus > sc->info->num_cpus) {
warn_report("%s: invalid number of CPUs %d, using default %d",
sc->info->name, s->num_cpus, sc->info->num_cpus);
--
2.21.0
[Qemu-devel] [PULL 03/13] target/openrisc: Cache R0 in DisasContext
Finish the race condition fix from the previous patch.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index d635a46f7e..341f923864 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -48,6 +48,9 @@ typedef struct DisasContext {
/* If not -1, jmp_pc contains this value and so is a direct jump. */
target_ulong jmp_pc_imm;
+
+/* The temporary corresponding to register 0 for this compilation. */
+TCGv R0;
} DisasContext;
static inline bool is_user(DisasContext *dc)
@@ -64,7 +67,6 @@ static inline bool is_user(DisasContext *dc)
static TCGv cpu_sr;
static TCGv cpu_regs[32];
-static TCGv cpu_R0;
static TCGv cpu_pc;
static TCGv jmp_pc;/* l.jr/l.jalr temp pc */
static TCGv cpu_ppc;
@@ -122,7 +124,6 @@ void openrisc_translate_init(void)
shadow_gpr[0][i]),
regnames[i]);
}
-cpu_R0 = cpu_regs[0];
}
static void gen_exception(DisasContext *dc, unsigned int excp)
@@ -165,7 +166,11 @@ static void check_ov64s(DisasContext *dc)
static TCGv cpu_R(DisasContext *dc, int reg)
{
-return cpu_regs[reg];
+if (reg == 0) {
+return dc->R0;
+} else {
+return cpu_regs[reg];
+}
}
/*
@@ -175,7 +180,7 @@ static TCGv cpu_R(DisasContext *dc, int reg)
static void check_r0_write(DisasContext *dc, int reg)
{
if (unlikely(reg == 0)) {
-cpu_regs[0] = cpu_R0;
+dc->R0 = cpu_regs[0];
}
}
@@ -747,7 +752,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)
to cpu_regs[0]. Since l.swa is quite often immediately followed by a
branch, don't bother reallocating; finish the TB using the "real" R0.
This also takes care of RB input across the branch. */
-cpu_regs[0] = cpu_R0;
+dc->R0 = cpu_regs[0];
lab_fail = gen_new_label();
lab_done = gen_new_label();
@@ -1292,9 +1297,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db,
CPUState *cs)
/* Allow the TCG optimizer to see that R0 == 0,
when it's true, which is the common case. */
if (dc->tb_flags & TB_FLAGS_R0_0) {
-cpu_regs[0] = tcg_const_tl(0);
+dc->R0 = tcg_const_tl(0);
} else {
-cpu_regs[0] = cpu_R0;
+dc->R0 = cpu_regs[0];
}
}
--
2.17.1
[Qemu-devel] [PULL 11/13] target/openrisc: Implement move to/from FPCSR
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 2 ++
target/openrisc/cpu.c| 1 +
target/openrisc/fpu_helper.c | 13 +
target/openrisc/machine.c| 11 +++
target/openrisc/sys_helper.c | 18 --
5 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 71c5959828..0ad02eab79 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -413,6 +413,8 @@ static inline void cpu_set_sr(CPUOpenRISCState *env,
uint32_t val)
env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO;
}
+void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val);
+
#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
#endif /* OPENRISC_CPU_H */
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index b931605e62..f96a69e278 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -55,6 +55,7 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.sr = SR_FO | SR_SM;
cpu->env.lock_addr = -1;
s->exception_index = -1;
+cpu_set_fpcsr(>env, 0);
#ifndef CONFIG_USER_ONLY
cpu->env.picmr = 0x;
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index 7bcef9dc53..59e1413279 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -61,6 +61,19 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
}
}
+void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val)
+{
+static const int rm_to_sf[] = {
+float_round_nearest_even,
+float_round_to_zero,
+float_round_up,
+float_round_down
+};
+
+env->fpcsr = val & 0x7ff;
+set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], >fp_status);
+}
+
uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
{
return int64_to_float64(val, >fp_status);
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 0a96404dc6..b92985d99b 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -121,10 +121,21 @@ static const VMStateDescription vmstate_env = {
}
};
+static int cpu_post_load(void *opaque, int version_id)
+{
+OpenRISCCPU *cpu = opaque;
+CPUOpenRISCState *env = >env;
+
+/* Update env->fp_status to match env->fpcsr. */
+cpu_set_fpcsr(env, env->fpcsr);
+return 0;
+}
+
const VMStateDescription vmstate_openrisc_cpu = {
.name = "cpu",
.version_id = 1,
.minimum_version_id = 1,
+.post_load = cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_CPU(),
VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index cf8e637b08..d9fe6c5948 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -37,8 +37,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
CPUState *cs = env_cpu(env);
target_ulong mr;
int idx;
+#endif
switch (spr) {
+#ifndef CONFIG_USER_ONLY
case TO_SPR(0, 11): /* EVBAR */
env->evbar = rb;
break;
@@ -179,10 +181,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong
spr, target_ulong rb)
}
cpu_openrisc_timer_update(cpu);
break;
-default:
+#endif
+
+case TO_SPR(0, 20): /* FPCSR */
+cpu_set_fpcsr(env, rb);
break;
}
-#endif
}
target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
@@ -193,8 +197,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
OpenRISCCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
int idx;
+#endif
switch (spr) {
+#ifndef CONFIG_USER_ONLY
case TO_SPR(0, 0): /* VR */
return env->vr;
@@ -303,12 +309,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
case TO_SPR(10, 1): /* TTCR */
cpu_openrisc_count_update(cpu);
return cpu_openrisc_count_get(cpu);
-
-default:
-break;
-}
#endif
+case TO_SPR(0, 20): /* FPCSR */
+return env->fpcsr;
+}
+
/* for rd is passed in, if rd unchanged, just keep it back. */
return rd;
}
--
2.17.1
[Qemu-devel] [RFC PATCH 10/15] aspeed/smc: Add support for the AST2600 SoC
The AST2600 SoC SMC controller is a SPI only controller now and has a
few extensions which we will need to take into account when SW
requires it.
- 4BYTE mode
- HCLK divider has changed (SPI Training)
- CE0-2 Read Timing Compensation registers
This is enough to support u-boot.
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/aspeed_smc.h | 2 +
hw/ssi/aspeed_smc.c | 129 +---
2 files changed, 123 insertions(+), 8 deletions(-)
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index 5176ff6bf95f..84f268de3091 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -49,6 +49,8 @@ typedef struct AspeedSMCController {
hwaddr dma_flash_mask;
hwaddr dma_dram_mask;
uint32_t nregs;
+uint32_t (*segment_to_reg)(const AspeedSegments *seg);
+void (*reg_to_segment)(uint32_t reg, AspeedSegments *seg);
} AspeedSMCController;
typedef struct AspeedSMCFlash {
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 9ffc7e01179a..1be53b5e53ac 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -54,10 +54,8 @@
/* CE Control Register */
#define R_CE_CTRL(0x04 / 4)
-#define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
-#define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
-#define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
-#define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
+
+#define CTRL_4B_AUTOREAD 4 /* 4B address Auto-Read command selection */
#define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
/* Interrupt Control and Status Register */
@@ -71,8 +69,11 @@
/* CEx Control Register */
#define R_CTRL0 (0x10 / 4)
+#define CTRL_IO_QPI (1 << 31)
+#define CTRL_IO_QUAD_DATA(1 << 30)
#define CTRL_IO_DUAL_DATA(1 << 29)
#define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */
+#define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */
#define CTRL_CMD_SHIFT 16
#define CTRL_CMD_MASK0xff
#define CTRL_DUMMY_HIGH_SHIFT14
@@ -84,7 +85,7 @@
#define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */
#define CTRL_CE_STOP_ACTIVE (1 << 2)
#define CTRL_CMD_MODE_MASK 0x3
-#define CTRL_READMODE 0x0
+#define CTRL_READMODE 0x0 /* AST2600: 4BYTE READ */
#define CTRL_FREADMODE 0x1
#define CTRL_WRITEMODE 0x2
#define CTRL_USERMODE 0x3
@@ -135,8 +136,11 @@
/* Misc Control Register #2 */
#define R_TIMINGS (0x94 / 4)
+#define R_CE0_READ_TIMING (0x94 / 4)
+#define R_CE1_READ_TIMING (0x98 / 4)
+#define R_CE2_READ_TIMING (0x9C / 4)
-/* SPI controller registers and bits */
+/* AST2400 SPI1 controller registers and bits */
#define R_SPI_CONF(0x00 / 4)
#define SPI_CONF_ENABLE_W0 0
#define R_SPI_CTRL0 (0x4 / 4)
@@ -212,6 +216,36 @@ static const AspeedSegments aspeed_segments_ast2500_spi2[]
= {
{ 0x3A00, 96 * 1024 * 1024 }, /* end address is readonly */
};
+/*
+ * AST2600 definitions
+ */
+#define ASPEED26_SOC_FMC_FLASH_BASE 0x2000
+#define ASPEED26_SOC_SPI_FLASH_BASE 0x3000
+#define ASPEED26_SOC_SPI2_FLASH_BASE 0x5000
+
+static const AspeedSegments aspeed_segments_ast2600_fmc[] = {
+{ 0x2000, 128 * 1024 * 1024 }, /* start address is readonly */
+{ 0x0, 0 }, /* disabled */
+{ 0x0, 0 }, /* disabled */
+};
+
+static const AspeedSegments aspeed_segments_ast2600_spi1[] = {
+{ 0x3000, 128 * 1024 * 1024 }, /* start address is readonly */
+{ 0x0, 0 }, /* disabled */
+};
+
+static const AspeedSegments aspeed_segments_ast2600_spi2[] = {
+{ 0x5000, 128 * 1024 * 1024 }, /* start address is readonly */
+{ 0x0, 0 }, /* disabled */
+{ 0x0, 0 }, /* disabled */
+};
+
+static uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg);
+static void aspeed_smc_reg_to_segment(uint32_t reg, AspeedSegments *seg);
+
+static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSegments *seg);
+static void aspeed_2600_smc_reg_to_segment(uint32_t reg, AspeedSegments *seg);
+
static const AspeedSMCController controllers[] = {
{
.name = "aspeed.smc-ast2400",
@@ -226,6 +260,8 @@ static const AspeedSMCController controllers[] = {
.flash_window_size = 0x600,
.has_dma = false,
.nregs = ASPEED_SMC_R_SMC_MAX,
+.segment_to_reg= aspeed_smc_segment_to_reg,
+.reg_to_segment= aspeed_smc_reg_to_segment,
}, {
.name = "aspeed.fmc-ast2400",
.r_conf= R_CONF,
@@ -241,6 +277,8 @@ static const AspeedSMCController controllers[] = {
.dma_flash_mask= 0x0FFC,
.dma_dram_mask = 0x1FFC,
.nregs = ASPEED_SMC_R_MAX,
+.segment_to_reg= aspeed_smc_segment_to_reg,
+
[Qemu-devel] [RFC PATCH 07/15] aspeed/sdmc: Add AST2600 support
From: Joel Stanley
The AST2600 SDMC controller is slightly different from its predecessor
(DRAM training). Max memory is now 2G on the AST2600.
Signed-off-by: Joel Stanley
[clg: - improved commit log ]
- reworked mode integration into new objet class ]
Signed-off-by: Cédric Le Goater
---
include/hw/misc/aspeed_sdmc.h | 1 +
hw/misc/aspeed_scu.c | 2 +
hw/misc/aspeed_sdmc.c | 82 +++
3 files changed, 85 insertions(+)
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
index 81156320c497..5dbde59fe777 100644
--- a/include/hw/misc/aspeed_sdmc.h
+++ b/include/hw/misc/aspeed_sdmc.h
@@ -15,6 +15,7 @@
#define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC)
#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
+#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
#define ASPEED_SDMC_NR_REGS (0x174 >> 2)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 4190adab8220..df76bd58a1bb 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -99,6 +99,7 @@
#define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
#define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94)
+#define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
#define AST2600_MPLL_EXT TO_REG(0x224)
#define AST2600_EPLL_EXT TO_REG(0x244)
#define AST2600_CLK_SEL TO_REG(0x300)
@@ -599,6 +600,7 @@ static const uint32_t
ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
[AST2600_SYS_RST_CTRL2] = 0xFFFC,
[AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
[AST2600_CLK_STOP_CTRL2]= 0xFFF0FFF0,
+[AST2600_SDRAM_HANDSHAKE] = 0x0040, /* SoC completed DRAM init */
};
static void aspeed_ast2600_scu_reset(DeviceState *dev)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 60c99e773488..f3a63a2e01db 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -28,6 +28,7 @@
/* Control/Status Register #1 (ast2500) */
#define R_STATUS1 (0x60 / 4)
#define PHY_BUSY_STATE BIT(0)
+#define PHY_PLL_LOCK_STATUS BIT(4)
#define R_ECC_TEST_CTRL (0x70 / 4)
#define ECC_TEST_FINISHED BIT(12)
@@ -85,6 +86,11 @@
#define ASPEED_SDMC_AST2500_512MB 0x2
#define ASPEED_SDMC_AST2500_1024MB 0x3
+#define ASPEED_SDMC_AST2600_256MB 0x0
+#define ASPEED_SDMC_AST2600_512MB 0x1
+#define ASPEED_SDMC_AST2600_1024MB 0x2
+#define ASPEED_SDMC_AST2600_2048MB 0x3
+
#define ASPEED_SDMC_AST2500_READONLY_MASK \
(ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT |\
@@ -186,6 +192,28 @@ static int ast2500_rambits(AspeedSDMCState *s)
return ASPEED_SDMC_AST2500_512MB;
}
+static int ast2600_rambits(AspeedSDMCState *s)
+{
+switch (s->ram_size >> 20) {
+case 256:
+return ASPEED_SDMC_AST2600_256MB;
+case 512:
+return ASPEED_SDMC_AST2600_512MB;
+case 1024:
+return ASPEED_SDMC_AST2600_1024MB;
+case 2048:
+return ASPEED_SDMC_AST2600_2048MB;
+default:
+break;
+}
+
+/* use a common default */
+warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M",
+s->ram_size);
+s->ram_size = 512 << 20;
+return ASPEED_SDMC_AST2600_512MB;
+}
+
static void aspeed_sdmc_reset(DeviceState *dev)
{
AspeedSDMCState *s = ASPEED_SDMC(dev);
@@ -340,11 +368,65 @@ static const TypeInfo aspeed_2500_sdmc_info = {
.class_init = aspeed_2500_sdmc_class_init,
};
+static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t
data)
+{
+uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) |
+ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
+ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s));
+
+/* Make sure readonly bits are kept (use ast2500 mask) */
+data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
+
+return data | fixed_conf;
+}
+
+static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
+ uint32_t data)
+{
+switch (reg) {
+case R_CONF:
+data = aspeed_2600_sdmc_compute_conf(s, data);
+break;
+case R_STATUS1:
+/* Will never return 'busy'. 'lock status' is always set */
+data &= ~PHY_BUSY_STATE;
+data |= PHY_PLL_LOCK_STATUS;
+break;
+case R_ECC_TEST_CTRL:
+/* Always done, always happy */
+data |= ECC_TEST_FINISHED;
+data &= ~ECC_TEST_FAIL;
+break;
+default:
+break;
+}
+
+s->regs[reg] = data;
+}
+
+static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
+
+dc->desc = "ASPEED 2600 SDRAM Memory Controller";
[Qemu-devel] [PULL 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
These registers are read-only and implementation specific.
Initiailize VR for the first time; take the OR1200 values
from the verilog source.
Note that moving fields within CPUOpenRISCState does not
affect migration.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 8
target/openrisc/cpu.c| 23 ---
target/openrisc/sys_helper.c | 4 ++--
3 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 755282f95d..18d7445e74 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -260,10 +260,6 @@ typedef struct CPUOpenRISCState {
target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */
target_long sr_ov; /* the SR_OV bit (in the sign bit only) */
uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */
-uint32_t vr; /* Version register */
-uint32_t upr; /* Unit presence register */
-uint32_t dmmucfgr;/* DMMU configure register */
-uint32_t immucfgr;/* IMMU configure register */
uint32_t esr; /* Exception supervisor register */
uint32_t evbar; /* Exception vector base address register */
uint32_t pmr; /* Power Management Register */
@@ -283,7 +279,11 @@ typedef struct CPUOpenRISCState {
struct {} end_reset_fields;
/* Fields from here on are preserved across CPU reset. */
+uint32_t vr; /* Version register */
+uint32_t upr; /* Unit presence register */
uint32_t cpucfgr; /* CPU configure register */
+uint32_t dmmucfgr;/* DMMU configure register */
+uint32_t immucfgr;/* IMMU configure register */
#ifndef CONFIG_USER_ONLY
QEMUTimer *timer;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f19e482a55..d9f447e90c 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -56,13 +56,6 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.lock_addr = -1;
s->exception_index = -1;
-cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
- UPR_PMP;
-cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
- | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
-cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
- | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
-
#ifndef CONFIG_USER_ONLY
cpu->env.picmr = 0x;
cpu->env.picsr = 0x;
@@ -117,15 +110,31 @@ static void or1200_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
+cpu->env.vr = 0x1308;
+cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
CPUCFGR_EVBARP;
+
+/* 1Way, TLB_SIZE entries. */
+cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
+ | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
+cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
+ | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
static void openrisc_any_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
+cpu->env.vr = 0x1300;
+cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
+
+/* 1Way, TLB_SIZE entries. */
+cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
+ | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
+cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
+ | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index d20f48b659..a2b1f52294 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -199,13 +199,13 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
return env->vr;
case TO_SPR(0, 1): /* UPR */
-return env->upr;/* TT, DM, IM, UP present */
+return env->upr;
case TO_SPR(0, 2): /* CPUCFGR */
return env->cpucfgr;
case TO_SPR(0, 3): /* DMMUCFGR */
-return env->dmmucfgr;/* 1Way, 64 entries */
+return env->dmmucfgr;
case TO_SPR(0, 4): /* IMMUCFGR */
return env->immucfgr;
--
2.17.1
[Qemu-devel] [PATCH v1 25/42] tests/docker: avoid $SHELL invoke bash directly
On some images SHELL is pointing at a limited /bin/sh which doesn't understand noprofile/norc. Given the run script is running bash just invoke it directly. Signed-off-by: Alex Bennée --- tests/docker/run | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/docker/run b/tests/docker/run index 1014871fec0..8edc7026ee3 100755 --- a/tests/docker/run +++ b/tests/docker/run @@ -62,7 +62,7 @@ echo "* Prepared to run command:" echo " $CMD" echo "* Hit Ctrl-D to continue, or type 'exit 1' to abort" echo -$SHELL --noprofile --norc +env bash --noprofile --norc if "$CMD"; then exit 0 @@ -72,7 +72,7 @@ elif test -n "$DEBUG"; then echo "* Hit Ctrl-D to exit" echo # Force error after shell exits -$SHELL --noprofile --norc && exit 1 +env bash --noprofile --norc && exit 1 else exit 1 fi -- 2.20.1
[Qemu-devel] [RFC PATCH 06/15] aspeed/sdmc: Introduce an object class per SoC
Use class handlers and class constants to differentiate the
characteristics of the memory controller and remove the 'silicon_rev'
property.
Signed-off-by: Cédric Le Goater
---
include/hw/misc/aspeed_sdmc.h | 19 +++-
hw/arm/aspeed_soc.c | 5 +-
hw/misc/aspeed_sdmc.c | 168 +-
3 files changed, 122 insertions(+), 70 deletions(-)
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
index b3c926acae90..81156320c497 100644
--- a/include/hw/misc/aspeed_sdmc.h
+++ b/include/hw/misc/aspeed_sdmc.h
@@ -13,6 +13,8 @@
#define TYPE_ASPEED_SDMC "aspeed.sdmc"
#define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC)
+#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
+#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
#define ASPEED_SDMC_NR_REGS (0x174 >> 2)
@@ -24,12 +26,21 @@ typedef struct AspeedSDMCState {
MemoryRegion iomem;
uint32_t regs[ASPEED_SDMC_NR_REGS];
-uint32_t silicon_rev;
-uint32_t ram_bits;
uint64_t ram_size;
uint64_t max_ram_size;
-uint32_t fixed_conf;
-
} AspeedSDMCState;
+#define ASPEED_SDMC_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AspeedSDMCClass, (klass), TYPE_ASPEED_SDMC)
+#define ASPEED_SDMC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AspeedSDMCClass, (obj), TYPE_ASPEED_SDMC)
+
+typedef struct AspeedSDMCClass {
+SysBusDeviceClass parent_class;
+
+uint64_t max_ram_size;
+uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
+void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
+} AspeedSDMCClass;
+
#endif /* ASPEED_SDMC_H */
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 26e03486f9b7..aaf18d3e42f1 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -205,10 +205,9 @@ static void aspeed_soc_init(Object *obj)
sizeof(s->spi[i]), typename);
}
+snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
sysbus_init_child_obj(obj, "sdmc", OBJECT(>sdmc), sizeof(s->sdmc),
- TYPE_ASPEED_SDMC);
-qdev_prop_set_uint32(DEVICE(>sdmc), "silicon-rev",
- sc->info->silicon_rev);
+ typename);
object_property_add_alias(obj, "ram-size", OBJECT(>sdmc),
"ram-size", _abort);
object_property_add_alias(obj, "max-ram-size", OBJECT(>sdmc),
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index cb13c63ec848..60c99e773488 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -110,6 +110,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr,
uint64_t data,
unsigned int size)
{
AspeedSDMCState *s = ASPEED_SDMC(opaque);
+AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
addr >>= 2;
@@ -130,41 +131,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr,
uint64_t data,
return;
}
-if (addr == R_CONF) {
-/* Make sure readonly bits are kept */
-switch (s->silicon_rev) {
-case AST2400_A0_SILICON_REV:
-case AST2400_A1_SILICON_REV:
-data &= ~ASPEED_SDMC_READONLY_MASK;
-data |= s->fixed_conf;
-break;
-case AST2500_A0_SILICON_REV:
-case AST2500_A1_SILICON_REV:
-data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
-data |= s->fixed_conf;
-break;
-default:
-g_assert_not_reached();
-}
-}
-if (s->silicon_rev == AST2500_A0_SILICON_REV ||
-s->silicon_rev == AST2500_A1_SILICON_REV) {
-switch (addr) {
-case R_STATUS1:
-/* Will never return 'busy' */
-data &= ~PHY_BUSY_STATE;
-break;
-case R_ECC_TEST_CTRL:
-/* Always done, always happy */
-data |= ECC_TEST_FINISHED;
-data &= ~ECC_TEST_FAIL;
-break;
-default:
-break;
-}
-}
-
-s->regs[addr] = data;
+asc->write(s, addr, data);
}
static const MemoryRegionOps aspeed_sdmc_ops = {
@@ -222,44 +189,21 @@ static int ast2500_rambits(AspeedSDMCState *s)
static void aspeed_sdmc_reset(DeviceState *dev)
{
AspeedSDMCState *s = ASPEED_SDMC(dev);
+AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
memset(s->regs, 0, sizeof(s->regs));
/* Set ram size bit and defaults values */
-s->regs[R_CONF] = s->fixed_conf;
+s->regs[R_CONF] = asc->compute_conf(s, 0);
}
static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AspeedSDMCState *s = ASPEED_SDMC(dev);
+AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
-if (!is_supported_silicon_rev(s->silicon_rev)) {
-error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
-s->silicon_rev);
-return;
-}
-
-switch (s->silicon_rev) {
-case
[Qemu-devel] [PULL 01/13] target/openrisc: Add DisasContext parameter to check_r0_write
We will need this context in the next patch.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 96 +++--
1 file changed, 49 insertions(+), 47 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index b189c506c5..8d72edf9b7 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -163,14 +163,16 @@ static void check_ov64s(DisasContext *dc)
}
#endif*/
-/* We're about to write to REG. On the off-chance that the user is
- writing to R0, re-instate the architectural register. */
-#define check_r0_write(reg) \
-do {\
-if (unlikely(reg == 0)) { \
-cpu_R[0] = cpu_R0; \
-} \
-} while (0)
+/*
+ * We're about to write to REG. On the off-chance that the user is
+ * writing to R0, re-instate the architectural register.
+ */
+static void check_r0_write(DisasContext *dc, int reg)
+{
+if (unlikely(reg == 0)) {
+cpu_R[0] = cpu_R0;
+}
+}
static void gen_ove_cy(DisasContext *dc)
{
@@ -436,98 +438,98 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv
srcb)
static bool trans_l_add(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_addc(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sub(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_and(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_or(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_xor(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sll(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_srl(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sra(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_ror(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_exths(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
}
static bool trans_l_extbs(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
}
static bool trans_l_exthz(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
}
static bool trans_l_extbz(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
}
@@ -536,7 +538,7 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
{
TCGv zero;
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
zero = tcg_const_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[a->d], cpu_sr_f, zero,
cpu_R[a->a], cpu_R[a->b]);
@@ -546,7 +548,7 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
static bool trans_l_ff1(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1);
tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1);
return true;
@@ -554,7 +556,7 @@ static bool trans_l_ff1(DisasContext *dc, arg_da *a)
static bool trans_l_fl1(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS);
tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]);
return true;
@@ -562,28 +564,28 @@ static bool
[Qemu-devel] [RFC PATCH 03/15] aspeed/timer: Add support for control register 3
The AST2500 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
This models the behaviour expected by the AST2500 while maintaining
the same behaviour for the AST2400.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater
---
include/hw/timer/aspeed_timer.h | 1 +
hw/timer/aspeed_timer.c | 19 +++
2 files changed, 20 insertions(+)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index a791fee276f4..1e0288ebc49f 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -58,6 +58,7 @@ typedef struct AspeedTimerCtrlState {
uint32_t ctrl;
uint32_t ctrl2;
+uint32_t ctrl3;
AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
AspeedSCUState *scu;
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index c78bc1bd2d25..d70e78a0293e 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -498,6 +498,8 @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState
*s, hwaddr offset)
switch (offset) {
case 0x38:
+value = s->ctrl3 & BIT(0);
+break;
case 0x3C:
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
@@ -511,9 +513,24 @@ static uint64_t
aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset)
static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
uint64_t value)
{
+const uint32_t tv = (uint32_t)(value & 0x);
+uint8_t command;
+
switch (offset) {
case 0x38:
+command = (value >> 1) & 0xFF;
+if (command == 0xAE) {
+s->ctrl3 = 0x1;
+} else if (command == 0xEA) {
+s->ctrl3 = 0x0;
+}
+break;
case 0x3C:
+if (s->ctrl3 & BIT(0)) {
+aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
+}
+break;
+
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
@@ -574,6 +591,7 @@ static void aspeed_timer_reset(DeviceState *dev)
}
s->ctrl = 0;
s->ctrl2 = 0;
+s->ctrl3 = 0;
}
static const VMStateDescription vmstate_aspeed_timer = {
@@ -597,6 +615,7 @@ static const VMStateDescription vmstate_aspeed_timer_state
= {
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState),
+VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState),
VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer,
AspeedTimer),
--
2.21.0
[Qemu-devel] [RFC PATCH 02/15] aspeed/timer: Introduce an object class per SoC
It prepares ground for register differences between SoCs.
Signed-off-by: Cédric Le Goater
---
include/hw/timer/aspeed_timer.h | 15 +
hw/arm/aspeed_soc.c | 3 +-
hw/timer/aspeed_timer.c | 107
3 files changed, 113 insertions(+), 12 deletions(-)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index 1fb949e16710..a791fee276f4 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -28,6 +28,9 @@
#define ASPEED_TIMER(obj) \
OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
#define TYPE_ASPEED_TIMER "aspeed.timer"
+#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
+#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
+
#define ASPEED_TIMER_NR_TIMERS 8
typedef struct AspeedTimer {
@@ -60,4 +63,16 @@ typedef struct AspeedTimerCtrlState {
AspeedSCUState *scu;
} AspeedTimerCtrlState;
+#define ASPEED_TIMER_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AspeedTimerClass, (klass), TYPE_ASPEED_TIMER)
+#define ASPEED_TIMER_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AspeedTimerClass, (obj), TYPE_ASPEED_TIMER)
+
+typedef struct AspeedTimerClass {
+SysBusDeviceClass parent_class;
+
+uint64_t (*read)(AspeedTimerCtrlState *s, hwaddr offset);
+void (*write)(AspeedTimerCtrlState *s, hwaddr offset, uint64_t value);
+} AspeedTimerClass;
+
#endif /* ASPEED_TIMER_H */
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index c3821a562733..26e03486f9b7 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -182,8 +182,9 @@ static void aspeed_soc_init(Object *obj)
sysbus_init_child_obj(obj, "rtc", OBJECT(>rtc), sizeof(s->rtc),
TYPE_ASPEED_RTC);
+snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
sysbus_init_child_obj(obj, "timerctrl", OBJECT(>timerctrl),
- sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
+ sizeof(s->timerctrl), typename);
object_property_add_const_link(OBJECT(>timerctrl), "scu",
OBJECT(>scu), _abort);
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 2bda826882d9..c78bc1bd2d25 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -253,13 +253,8 @@ static uint64_t aspeed_timer_read(void *opaque, hwaddr
offset, unsigned size)
case 0x40 ... 0x8c: /* Timers 5 - 8 */
value = aspeed_timer_get_value(>timers[(offset >> 4) - 1], reg);
break;
-/* Illegal */
-case 0x38:
-case 0x3C:
default:
-qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-__func__, offset);
-value = 0;
+value = ASPEED_TIMER_GET_CLASS(s)->read(s, offset);
break;
}
trace_aspeed_timer_read(offset, size, value);
@@ -453,12 +448,8 @@ static void aspeed_timer_write(void *opaque, hwaddr
offset, uint64_t value,
case 0x40 ... 0x8c:
aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv);
break;
-/* Illegal */
-case 0x38:
-case 0x3C:
default:
-qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
-__func__, offset);
+ASPEED_TIMER_GET_CLASS(s)->write(s, offset, value);
break;
}
}
@@ -472,6 +463,64 @@ static const MemoryRegionOps aspeed_timer_ops = {
.valid.unaligned = false,
};
+static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset)
+{
+uint64_t value;
+
+switch (offset) {
+case 0x38:
+case 0x3C:
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+__func__, offset);
+value = 0;
+break;
+}
+return value;
+}
+
+static void aspeed_2400_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
+uint64_t value)
+{
+switch (offset) {
+case 0x38:
+case 0x3C:
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+__func__, offset);
+break;
+}
+}
+
+static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset)
+{
+uint64_t value;
+
+switch (offset) {
+case 0x38:
+case 0x3C:
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+__func__, offset);
+value = 0;
+break;
+}
+return value;
+}
+
+static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
+uint64_t value)
+{
+switch (offset) {
+case 0x38:
+case 0x3C:
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+__func__, offset);
+break;
+}
+}
+
static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id)
{
AspeedTimer *t = >timers[id];
@@
[Qemu-devel] [PATCH v1 26/42] tests/docker: add debian-amd64-cross for non-x86 hosts
When building on a non-x86 host we need to setup the x86 build like any other cross compiler. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 6 + .../dockerfiles/debian-amd64-cross.docker | 22 +++ 2 files changed, 28 insertions(+) create mode 100644 tests/docker/dockerfiles/debian-amd64-cross.docker diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index 2c8cb790ad0..cb0961a69e4 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -87,7 +87,13 @@ endif # Enforce dependencies for composite images docker-image-debian9-mxe: docker-image-debian9 +ifeq ($(ARCH),x86_64) docker-image-debian-amd64: docker-image-debian9 +DOCKER_PARTIAL_IMAGES += debian-amd64-cross +else +docker-image-debian-amd64-cross: docker-image-debian10 +DOCKER_PARTIAL_IMAGES += debian-amd64 +endif docker-image-debian-armel-cross: docker-image-debian9 docker-image-debian-armhf-cross: docker-image-debian9 docker-image-debian-mips-cross: docker-image-debian9 diff --git a/tests/docker/dockerfiles/debian-amd64-cross.docker b/tests/docker/dockerfiles/debian-amd64-cross.docker new file mode 100644 index 000..5d890419251 --- /dev/null +++ b/tests/docker/dockerfiles/debian-amd64-cross.docker @@ -0,0 +1,22 @@ +# +# Docker x86_64 cross target +# +# This docker target is used on non-x86_64 machines which need the +# x86_64 cross compilers installed. +# +FROM qemu:debian10 +MAINTAINER Alex Bennée + +# Add the foreign architecture we want and install dependencies +RUN dpkg --add-architecture amd64 +RUN apt update && \ +DEBIAN_FRONTEND=noninteractive eatmydata \ +apt install -y --no-install-recommends \ +crossbuild-essential-amd64 +RUN apt update && \ +DEBIAN_FRONTEND=noninteractive eatmydata \ +apt build-dep -yy -a amd64 --arch-only qemu + +# Specify the cross prefix for this image (see tests/docker/common.rc) +ENV QEMU_CONFIGURE_OPTS --cross-prefix=x86_64-linux-gnu- +ENV DEF_TARGET_LIST x86_64-softmmu,x86_64-linux-user,i386-softmmu,i386-linux-user -- 2.20.1
[Qemu-devel] [PULL 10/13] target/openrisc: Implement unordered fp comparisons
These were added to the 1.3 spec. For OF32S, validate AVR.
But OF64A32 is itself new to 1.3 so no extra check needed.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/helper.h | 4 ++
target/openrisc/disas.c | 24 ++
target/openrisc/fpu_helper.c | 20 +
target/openrisc/translate.c | 85
target/openrisc/insns.decode | 12 +
5 files changed, 145 insertions(+)
diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h
index 94b823580e..d847814a28 100644
--- a/target/openrisc/helper.h
+++ b/target/openrisc/helper.h
@@ -52,6 +52,10 @@ DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl,
env, i64, i64)
FOP_CMP(eq)
FOP_CMP(lt)
FOP_CMP(le)
+FOP_CMP(un)
+FOP_CMP(ueq)
+FOP_CMP(ule)
+FOP_CMP(ult)
#undef FOP_CMP
/* interrupt */
diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
index 4de5c632de..e51cbb24c6 100644
--- a/target/openrisc/disas.c
+++ b/target/openrisc/disas.c
@@ -166,6 +166,12 @@ FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfge, s, "r%d, r%d", a->a, a->b)
FP_INSN(sflt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfle, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfun, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfueq, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfuge, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfugt, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfule, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfult, s, "r%d, r%d", a->a, a->b)
FP_INSN(add, d, "r%d,r%d, r%d,r%d, r%d,r%d",
a->d, a->d + a->dp + 1,
@@ -222,3 +228,21 @@ FP_INSN(sflt, d, "r%d,r%d, r%d,r%d",
FP_INSN(sfle, d, "r%d,r%d, r%d,r%d",
a->a, a->a + a->ap + 1,
a->b, a->b + a->bp + 1)
+FP_INSN(sfun, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfueq, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfuge, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfugt, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfule, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfult, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index 9d7dfc0fb9..7bcef9dc53 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -135,4 +135,24 @@ target_ulong helper_float_ ## name ## _s(CPUOpenRISCState
*env, \
FLOAT_CMP(le, le)
FLOAT_CMP(lt, lt)
FLOAT_CMP(eq, eq_quiet)
+FLOAT_CMP(un, unordered_quiet)
#undef FLOAT_CMP
+
+#define FLOAT_UCMP(name, expr) \
+target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
+ uint64_t fdt0, uint64_t fdt1)\
+{ \
+int r = float64_compare_quiet(fdt0, fdt1, >fp_status); \
+return expr; \
+} \
+target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
+ uint32_t fdt0, uint32_t fdt1)\
+{ \
+int r = float32_compare_quiet(fdt0, fdt1, >fp_status); \
+return expr; \
+}
+
+FLOAT_UCMP(ueq, r == float_relation_equal || r == float_relation_unordered)
+FLOAT_UCMP(ult, r == float_relation_less || r == float_relation_unordered)
+FLOAT_UCMP(ule, r != float_relation_greater)
+#undef FLOAT_UCMP
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index b8ef485903..6e8bc23568 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -46,6 +46,7 @@ typedef struct DisasContext {
uint32_t tb_flags;
uint32_t delayed_branch;
uint32_t cpucfgr;
+uint32_t avr;
/* If not -1, jmp_pc contains this value and so is a direct jump. */
target_ulong jmp_pc_imm;
@@ -141,6 +142,11 @@ static void gen_illegal_exception(DisasContext *dc)
dc->base.is_jmp = DISAS_NORETURN;
}
+static bool check_v1_3(DisasContext *dc)
+{
+return dc->avr >= 0x0103;
+}
+
static bool check_of32s(DisasContext *dc)
{
return dc->cpucfgr & CPUCFGR_OF32S;
@@ -1265,6 +1271,54 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a)
return do_fpcmp(dc, a, gen_helper_float_le_s, false, false);
}
+static bool trans_lf_sfueq_s(DisasContext *dc, arg_ab *a)
+{
+if (!check_v1_3(dc)) {
+return false;
+}
+return do_fpcmp(dc, a, gen_helper_float_ueq_s, false, false);
+}
+
+static bool trans_lf_sfult_s(DisasContext *dc, arg_ab *a)
+{
+if (!check_v1_3(dc)) {
+return false;
+}
+
[Qemu-devel] [PATCH v1 38/42] .travis.yml: Cache Linux/GCC 'non-debug profile' jobs together
From: Philippe Mathieu-Daudé
These jobs build different components but use the same
host features. Put them in the same cache bucket.
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 13 +
1 file changed, 13 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index ab4ee425e4f..63cbf41e573 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -101,15 +101,18 @@ matrix:
include:
- env:
- CONFIG="--disable-system --static"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
# we split the system builds as it takes a while to build them all
- env:
- CONFIG="--disable-user --target-list=${MAIN_SOFTMMU_TARGETS}"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
- env:
- CONFIG="--disable-user --target-list-exclude=${MAIN_SOFTMMU_TARGETS}"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
# Just build tools and run minimal unit and softfloat checks
@@ -117,6 +120,8 @@ matrix:
- BASE_CONFIG="--enable-tools"
- CONFIG="--disable-user --disable-system"
- TEST_CMD="make check-unit check-softfloat -j3"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
+
- env:
- CONFIG="--enable-debug --enable-debug-tcg --disable-user"
@@ -136,6 +141,7 @@ matrix:
# Module builds are mostly of interest to major distros
- env:
- CONFIG="--enable-modules --target-list=${MAIN_SOFTMMU_TARGETS}"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
# Alternate coroutines implementations are only really of interest to KVM
users
@@ -155,6 +161,7 @@ matrix:
- BUILD_DIR="out-of-tree/build/dir" SRC_DIR="../../.."
- BASE_CONFIG="--enable-tools --enable-docs"
- CONFIG="--target-list=x86_64-softmmu,aarch64-linux-user"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
addons:
apt:
packages:
@@ -196,6 +203,7 @@ matrix:
# We manually include builds which we disable "make check" for
- env:
- CONFIG="--without-default-devices --disable-user"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
- TEST_CMD=""
@@ -239,6 +247,7 @@ matrix:
# Python builds
- env:
- CONFIG="--target-list=x86_64-softmmu"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
language: python
python:
- "3.4"
@@ -246,6 +255,7 @@ matrix:
- env:
- CONFIG="--target-list=x86_64-softmmu"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
language: python
python:
- "3.6"
@@ -312,8 +322,11 @@ matrix:
- env:
- CONFIG="--disable-system"
- TEST_CMD="make -j3 check-tcg V=1"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
+
# Run check-tcg against softmmu targets
- env:
-
CONFIG="--target-list=xtensa-softmmu,arm-softmmu,aarch64-softmmu,alpha-softmmu"
- TEST_CMD="make -j3 check-tcg V=1"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default"
--
2.20.1
[Qemu-devel] [PATCH v1 28/42] tests/docker: add more images to PARTIAL_IMAGES when not on x86_64
This prevents us trying to do builds which we can't complete. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 9 + 1 file changed, 9 insertions(+) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index cb0961a69e4..46f95320e54 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -104,6 +104,15 @@ docker-image-debian-s390x-cross: docker-image-debian9 docker-image-debian-win32-cross: docker-image-debian9-mxe docker-image-debian-win64-cross: docker-image-debian9-mxe +# For non-x86 hosts not all cross-compilers have been packaged +ifneq ($(ARCH),x86_64) +DOCKER_PARTIAL_IMAGES += debian-mips-cross debian-mipsel-cross debian-mips64el-cross +DOCKER_PARTIAL_IMAGES += debian-ppc64el-cross +DOCKER_PARTIAL_IMAGES += debian-s390x-cross +DOCKER_PARTIAL_IMAGES += debian-win32-cross debian-win64-cross +DOCKER_PARTIAL_IMAGES += fedora travis +endif + docker-image-debian-alpha-cross: docker-image-debian10 docker-image-debian-arm64-cross: docker-image-debian10 docker-image-debian-hppa-cross: docker-image-debian10 -- 2.20.1
[Qemu-devel] [PULL 13/13] target/openrisc: Update cpu "any" to v1.3
Now that the two updates from v1.3 are implemented, update the "any" cpu to enable it. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f96a69e278..506aec6bfb 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -129,7 +129,7 @@ static void openrisc_any_initfn(Object *obj) cpu->env.vr = 0x1340; /* Obsolete VER + UVRP for new SPRs */ cpu->env.vr2 = 0; /* No version specific id */ -cpu->env.avr = 0x0101; /* Architecture v1.1 */ +cpu->env.avr = 0x0103; /* Architecture v1.3 */ cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | -- 2.17.1
[Qemu-devel] [PULL 07/13] target/openrisc: Fix lf.ftoi.s
The specification of this insn is round-to-zero.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index b9d2ebbb8c..4cc5b297c5 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -78,7 +78,7 @@ uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)
uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
{
-return float32_to_int32(val, >fp_status);
+return float32_to_int32_round_to_zero(val, >fp_status);
}
#define FLOAT_CALC(name) \
--
2.17.1
[Qemu-devel] [PATCH v1 21/42] tests/docker: drop debian-sid image
Debian Sid was only ever a stop gap and thanks to the much better
cross compiler in the Buster release we don't need it any more. Send
it on its merry way.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
tests/docker/dockerfiles/debian-sid.docker | 41 --
2 files changed, 1 insertion(+), 42 deletions(-)
delete mode 100644 tests/docker/dockerfiles/debian-sid.docker
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index b6c04059502..59fbebbe2e6 100644
--- a/tests/docker/Makefile.include
+++ b/tests/docker/Makefile.include
@@ -6,7 +6,7 @@ DOCKER_SUFFIX := .docker
DOCKER_FILES_DIR := $(SRC_PATH)/tests/docker/dockerfiles
DOCKER_DEPRECATED_IMAGES := debian
# we don't run tests on intermediate images (used as base by another image)
-DOCKER_PARTIAL_IMAGES := debian debian8 debian9 debian10 debian8-mxe
debian-ports debian-sid debian-bootstrap
+DOCKER_PARTIAL_IMAGES := debian debian8 debian9 debian10 debian8-mxe
debian-ports debian-bootstrap
DOCKER_IMAGES := $(filter-out $(DOCKER_DEPRECATED_IMAGES),$(sort $(notdir
$(basename $(wildcard $(DOCKER_FILES_DIR)/*.docker)
DOCKER_TARGETS := $(patsubst %,docker-image-%,$(DOCKER_IMAGES))
# Use a global constant ccache directory to speed up repetitive builds
diff --git a/tests/docker/dockerfiles/debian-sid.docker
b/tests/docker/dockerfiles/debian-sid.docker
deleted file mode 100644
index 513459ca7f8..000
--- a/tests/docker/dockerfiles/debian-sid.docker
+++ /dev/null
@@ -1,41 +0,0 @@
-#
-# Debian Sid Base
-#
-# A number of our guests exist as ports only. We can either use the
-# ports repo or get everything from Sid. However Sid is a rolling
-# distro which may be broken at any particular time. If you are
-# unlucky and try and build your images while gcc is in the process of
-# being uploaded this can fail. Your only recourse is to try again in
-# a few hours when the repos have re-synced. Once built however you
-# won't be affected by repo changes unless the docker recipies are
-# updated and trigger a re-build.
-#
-
-# This must be earlier than the snapshot date we are aiming for
-FROM debian:sid-20181011-slim
-
-# Use a snapshot known to work (see http://snapshot.debian.org/#Usage)
-ENV DEBIAN_SNAPSHOT_DATE "20181030"
-RUN sed -i "s%^deb \(https\?://\)deb.debian.org/debian/\? \(.*\)%deb
[check-valid-until=no]
\1snapshot.debian.org/archive/debian/${DEBIAN_SNAPSHOT_DATE} \2%"
/etc/apt/sources.list
-
-# Use a snapshot known to work (see http://snapshot.debian.org/#Usage)
-ENV DEBIAN_SNAPSHOT_DATE "20181030"
-RUN sed -i "s%^deb \(https\?://\)deb.debian.org/debian/\? \(.*\)%deb
[check-valid-until=no]
\1snapshot.debian.org/archive/debian/${DEBIAN_SNAPSHOT_DATE} \2%"
/etc/apt/sources.list
-
-# Duplicate deb line as deb-src
-RUN cat /etc/apt/sources.list | sed "s/^deb\ /deb-src /" >>
/etc/apt/sources.list
-
-# Install common build utilities
-RUN apt update && \
-DEBIAN_FRONTEND=noninteractive apt install -yy eatmydata && \
-DEBIAN_FRONTEND=noninteractive eatmydata \
-apt install -y --no-install-recommends \
-bison \
-build-essential \
-ca-certificates \
-flex \
-git \
-pkg-config \
-psmisc \
-python \
-texinfo || { echo "Failed to build - see debian-sid.docker notes";
exit 1; }
--
2.20.1
[Qemu-devel] [PATCH v1 33/42] .travis.yml: Cache Avocado cache
From: Philippe Mathieu-Daudé Avocado tests download artifacts from various sources. These sources sometime have network issues resulting in build failures. Cache Avocado cache to reduce build failure. See https://docs.travis-ci.com/user/caching/#arbitrary-directories Signed-off-by: Philippe Mathieu-Daudé --- .travis.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis.yml b/.travis.yml index d51125c9569..8d2e89da533 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,6 +9,8 @@ cache: timeout: 1200 ccache: true pip: true + directories: + - $HOME/avocado/data/cache addons: -- 2.20.1
[Qemu-devel] [PULL 09/13] target/openrisc: Add support for ORFPX64A32
This is hardware support for double-precision floating-point using
pairs of 32-bit registers. Fix latent bugs in the heretofore unused
helper_itofd and helper_ftoid. Include the bit for cpu "any".
Change the default cpu for linux-user to "any".
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
linux-user/openrisc/target_elf.h | 2 +-
target/openrisc/helper.h | 2 +
target/openrisc/cpu.c| 2 +-
target/openrisc/disas.c | 56
target/openrisc/fpu_helper.c | 14 +-
target/openrisc/translate.c | 230 +++
target/openrisc/insns.decode | 31 +
7 files changed, 333 insertions(+), 4 deletions(-)
diff --git a/linux-user/openrisc/target_elf.h b/linux-user/openrisc/target_elf.h
index 40ceb025c9..265ecd3079 100644
--- a/linux-user/openrisc/target_elf.h
+++ b/linux-user/openrisc/target_elf.h
@@ -9,6 +9,6 @@
#define OPENRISC_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
-return "or1200";
+return "any";
}
#endif
diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h
index 96d79a8113..94b823580e 100644
--- a/target/openrisc/helper.h
+++ b/target/openrisc/helper.h
@@ -30,6 +30,8 @@ DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_RWG, i32, env, i32)
DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_RWG, i32, env, i32)
+DEF_HELPER_FLAGS_2(stod, TCG_CALL_NO_RWG, i64, env, i32)
+DEF_HELPER_FLAGS_2(dtos, TCG_CALL_NO_RWG, i32, env, i64)
DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f3c8134531..b931605e62 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -132,7 +132,7 @@ static void openrisc_any_initfn(Object *obj)
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
- CPUCFGR_AVRP | CPUCFGR_EVBARP;
+ CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;
/* 1Way, TLB_SIZE entries. */
cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
index 7091832347..4de5c632de 100644
--- a/target/openrisc/disas.c
+++ b/target/openrisc/disas.c
@@ -166,3 +166,59 @@ FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfge, s, "r%d, r%d", a->a, a->b)
FP_INSN(sflt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfle, s, "r%d, r%d", a->a, a->b)
+
+FP_INSN(add, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sub, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(mul, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(div, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(rem, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(madd, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+
+FP_INSN(itof, d, "r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1)
+FP_INSN(ftoi, d, "r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1)
+
+FP_INSN(stod, d, "r%d,r%d, r%d",
+a->d, a->d + a->dp + 1, a->a)
+FP_INSN(dtos, d, "r%d r%d,r%d",
+a->d, a->a, a->a + a->ap + 1)
+
+FP_INSN(sfeq, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfne, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfgt, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfge, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sflt, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfle, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index 4cc5b297c5..9d7dfc0fb9 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -63,7 +63,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
{
-return int32_to_float64(val, >fp_status);
+return int64_to_float64(val, >fp_status);
}
uint32_t HELPER(itofs)(CPUOpenRISCState *env,
[Qemu-devel] [PATCH v1 32/42] .travis.yml: Cache Python PIP packages
From: Philippe Mathieu-Daudé We always install the same packages ever and ever, cache them. See https://docs.travis-ci.com/user/caching/#pip-cache Signed-off-by: Philippe Mathieu-Daudé --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index 8c376d22239..d51125c9569 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,6 +8,7 @@ compiler: cache: timeout: 1200 ccache: true + pip: true addons: -- 2.20.1
[Qemu-devel] [PULL 06/13] target/openrisc: Add VR2 and AVR special processor registers
Update the CPUCFG bits to arch v1.3.
Include support for AVRP for cpu "any".
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 11 +++
target/openrisc/cpu.c| 8 ++--
target/openrisc/sys_helper.c | 6 ++
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 18d7445e74..71c5959828 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -96,11 +96,12 @@ enum {
CPUCFGR_OF32S = (1 << 7),
CPUCFGR_OF64S = (1 << 8),
CPUCFGR_OV64S = (1 << 9),
-/* CPUCFGR_ND = (1 << 10), */
-/* CPUCFGR_AVRP = (1 << 11), */
+CPUCFGR_ND = (1 << 10),
+CPUCFGR_AVRP = (1 << 11),
CPUCFGR_EVBARP = (1 << 12),
-/* CPUCFGR_ISRP = (1 << 13), */
-/* CPUCFGR_AECSRP = (1 << 14), */
+CPUCFGR_ISRP = (1 << 13),
+CPUCFGR_AECSRP = (1 << 14),
+CPUCFGR_OF64A32S = (1 << 15),
};
/* DMMU configure register */
@@ -280,6 +281,8 @@ typedef struct CPUOpenRISCState {
/* Fields from here on are preserved across CPU reset. */
uint32_t vr; /* Version register */
+uint32_t vr2; /* Version register 2 */
+uint32_t avr; /* Architecture version register */
uint32_t upr; /* Unit presence register */
uint32_t cpucfgr; /* CPU configure register */
uint32_t dmmucfgr;/* DMMU configure register */
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index d9f447e90c..9f566ad883 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -126,9 +126,13 @@ static void openrisc_any_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
-cpu->env.vr = 0x1300;
+cpu->env.vr = 0x1340; /* Obsolete VER + UVRP for new SPRs */
+cpu->env.vr2 = 0; /* No version specific id */
+cpu->env.avr = 0x0101; /* Architecture v1.1 */
+
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
-cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
+cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S |
+ CPUCFGR_AVRP | CPUCFGR_EVBARP;
/* 1Way, TLB_SIZE entries. */
cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index a2b1f52294..cf8e637b08 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -210,6 +210,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
case TO_SPR(0, 4): /* IMMUCFGR */
return env->immucfgr;
+case TO_SPR(0, 9): /* VR2 */
+return env->vr2;
+
+case TO_SPR(0, 10): /* AVR */
+return env->avr;
+
case TO_SPR(0, 11): /* EVBAR */
return env->evbar;
--
2.17.1
[Qemu-devel] [PATCH v1 35/42] .travis.yml: Enable ccache on OSX
From: Philippe Mathieu-Daudé
By default, ccache is not installed on macOS environments.
See https://docs.travis-ci.com/user/caching/#ccache-on-macos
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 5a878ae6ae9..2dd26486abc 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -45,6 +45,7 @@ addons:
- gcovr
homebrew:
packages:
+ - ccache
- glib
- pixman
- gnu-sed
@@ -80,6 +81,7 @@ git:
before_script:
+ - if [ "$TRAVIS_OS_NAME" == "osx" ] ; then export
PATH="/usr/local/opt/ccache/libexec:$PATH" ; fi
- command -v ccache && ccache --zero-stats
- mkdir -p ${BUILD_DIR} && cd ${BUILD_DIR}
- ${SRC_DIR}/configure ${BASE_CONFIG} ${CONFIG} || { cat config.log && exit
1; }
--
2.20.1
[Qemu-devel] [PULL 02/13] target/openrisc: Replace cpu register array with a function
The writes to cpu_R[0] are now a race across threads, now that we
do code generation in parallel. Stage the change by introducing
a function to return the temp for R0.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 213
1 file changed, 116 insertions(+), 97 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 8d72edf9b7..d635a46f7e 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -63,7 +63,7 @@ static inline bool is_user(DisasContext *dc)
#include "decode.inc.c"
static TCGv cpu_sr;
-static TCGv cpu_R[32];
+static TCGv cpu_regs[32];
static TCGv cpu_R0;
static TCGv cpu_pc;
static TCGv jmp_pc;/* l.jr/l.jalr temp pc */
@@ -117,12 +117,12 @@ void openrisc_translate_init(void)
offsetof(CPUOpenRISCState, mac),
"mac");
for (i = 0; i < 32; i++) {
-cpu_R[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUOpenRISCState,
- shadow_gpr[0][i]),
- regnames[i]);
+cpu_regs[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUOpenRISCState,
+ shadow_gpr[0][i]),
+ regnames[i]);
}
-cpu_R0 = cpu_R[0];
+cpu_R0 = cpu_regs[0];
}
static void gen_exception(DisasContext *dc, unsigned int excp)
@@ -163,6 +163,11 @@ static void check_ov64s(DisasContext *dc)
}
#endif*/
+static TCGv cpu_R(DisasContext *dc, int reg)
+{
+return cpu_regs[reg];
+}
+
/*
* We're about to write to REG. On the off-chance that the user is
* writing to R0, re-instate the architectural register.
@@ -170,7 +175,7 @@ static void check_ov64s(DisasContext *dc)
static void check_r0_write(DisasContext *dc, int reg)
{
if (unlikely(reg == 0)) {
-cpu_R[0] = cpu_R0;
+cpu_regs[0] = cpu_R0;
}
}
@@ -439,98 +444,98 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv
srcb)
static bool trans_l_add(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_addc(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_sub(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_and(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_or(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_xor(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_sll(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_shl_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_srl(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_shr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_sra(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_sar_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_ror(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_rotr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_exths(DisasContext *dc, arg_da *a)
{
check_r0_write(dc, a->d);
-tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]);
+tcg_gen_ext16s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a));
return true;
}
static bool trans_l_extbs(DisasContext *dc, arg_da *a)
{
check_r0_write(dc, a->d);
-tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]);
+
[Qemu-devel] [PULL 04/13] target/openrisc: Make VR and PPC read-only
These SPRs are read-only. The writes can simply be ignored,
as we already do for other read-only (or missing) registers.
There is no reason to mask the value in env->vr.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 3 ---
target/openrisc/sys_helper.c | 10 +-
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 561f0f7fad..755282f95d 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -68,9 +68,6 @@ enum {
(reg) |= ((v & 0x1f) << 2);\
} while (0)
-/* Version Register */
-#define SPR_VR 0x003F
-
/* Interrupt */
#define NR_IRQS 32
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 1053409a04..d20f48b659 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -39,10 +39,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
int idx;
switch (spr) {
-case TO_SPR(0, 0): /* VR */
-env->vr = rb;
-break;
-
case TO_SPR(0, 11): /* EVBAR */
env->evbar = rb;
break;
@@ -62,10 +58,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
cpu_set_sr(env, rb);
break;
-case TO_SPR(0, 18): /* PPC */
-env->ppc = rb;
-break;
-
case TO_SPR(0, 32): /* EPCR */
env->epcr = rb;
break;
@@ -204,7 +196,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
switch (spr) {
case TO_SPR(0, 0): /* VR */
-return env->vr & SPR_VR;
+return env->vr;
case TO_SPR(0, 1): /* UPR */
return env->upr;/* TT, DM, IM, UP present */
--
2.17.1
[Qemu-devel] [PATCH v1 19/42] tests/docker: move our riscv64 cross compile to Buster
Now Buster is released we can stop relying on the movable feast that is Sid for our cross-compiler for building tests. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include| 2 +- tests/docker/dockerfiles/debian-riscv64-cross.docker | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index 896c1c5a601..93190b1e2a2 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -104,10 +104,10 @@ docker-image-debian-hppa-cross: docker-image-debian10 docker-image-debian-m68k-cross: docker-image-debian10 docker-image-debian-mips64-cross: docker-image-debian10 docker-image-debian-powerpc-cross: docker-image-debian10 +docker-image-debian-riscv64-cross: docker-image-debian10 docker-image-debian-sh4-cross: docker-image-debian10 docker-image-debian-sparc64-cross: docker-image-debian10 -docker-image-debian-riscv64-cross: docker-image-debian-sid docker-image-debian-ppc64-cross: docker-image-debian-sid docker-image-travis: NOUSER=1 diff --git a/tests/docker/dockerfiles/debian-riscv64-cross.docker b/tests/docker/dockerfiles/debian-riscv64-cross.docker index 221697f9d11..5e2d6ddb600 100644 --- a/tests/docker/dockerfiles/debian-riscv64-cross.docker +++ b/tests/docker/dockerfiles/debian-riscv64-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -- 2.20.1
[Qemu-devel] [PATCH v1 12/42] tests/docker: move our powerpc cross compile to Buster
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include| 2 +-
tests/docker/dockerfiles/debian-powerpc-cross.docker | 8 +++-
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index 48c22ae40c0..7c1ff677a13 100644
--- a/tests/docker/Makefile.include
+++ b/tests/docker/Makefile.include
@@ -99,6 +99,7 @@ docker-image-debian-win32-cross: docker-image-debian9-mxe
docker-image-debian-win64-cross: docker-image-debian9-mxe
docker-image-debian-arm64-cross: docker-image-debian10
+docker-image-debian-powerpc-cross: docker-image-debian10
docker-image-debian-alpha-cross: docker-image-debian-sid
docker-image-debian-hppa-cross: docker-image-debian-sid
@@ -107,7 +108,6 @@ docker-image-debian-sh4-cross: docker-image-debian-sid
docker-image-debian-sparc64-cross: docker-image-debian-sid
docker-image-debian-mips64-cross: docker-image-debian-sid
docker-image-debian-riscv64-cross: docker-image-debian-sid
-docker-image-debian-powerpc-cross: docker-image-debian-sid
docker-image-debian-ppc64-cross: docker-image-debian-sid
docker-image-travis: NOUSER=1
diff --git a/tests/docker/dockerfiles/debian-powerpc-cross.docker
b/tests/docker/dockerfiles/debian-powerpc-cross.docker
index 5d08fad7cd3..89dd4fbf870 100644
--- a/tests/docker/dockerfiles/debian-powerpc-cross.docker
+++ b/tests/docker/dockerfiles/debian-powerpc-cross.docker
@@ -1,14 +1,12 @@
#
# Docker powerpc cross-compiler target
#
-# This docker target builds on the debian sid base image which
-# contains cross compilers for Debian "ports" targets. The original
-# Jessie based no longer builds.
+# This docker target builds on the debian Buster base image.
#
-FROM qemu:debian-sid
+FROM qemu:debian10
RUN apt update && \
DEBIAN_FRONTEND=noninteractive eatmydata \
apt install -y --no-install-recommends \
gcc-powerpc-linux-gnu \
-libc6-dev-powerpc-cross || { echo "Failed to build - see
debian-sid.docker notes"; exit 1; }
+libc6-dev-powerpc-cross
--
2.20.1
Re: [Qemu-devel] [PATCH] numa: Introduce MachineClass::auto_enable_numa for implicit NUMA node
On Wed, Sep 04, 2019 at 02:22:39PM +0800, Tao Xu wrote:
> On 9/4/2019 1:52 AM, Eduardo Habkost wrote:
> > On Mon, Aug 05, 2019 at 03:13:02PM +0800, Tao Xu wrote:
> > > Add MachineClass::auto_enable_numa field. When it is true, a NUMA node
> > > is expected to be created implicitly.
> > >
> > > Acked-by: David Gibson
> > > Suggested-by: Igor Mammedov
> > > Suggested-by: Eduardo Habkost
> > > Signed-off-by: Tao Xu
> >
> > This introduces spurious warnings when running qemu-system-ppc64.
> > See:
> > https://lore.kernel.org/qemu-devel/CAFEAcA-AvFS2cbDH-t5SxgY9hA=lgl81_8dn-vh193vtv9w...@mail.gmail.com/
> >
> > To reproduce it, just run 'qemu-system-ppc64 -machine pseries'
> > without any -numa arguments.
> >
> > I have removed this patch from machine-next so it won't block the
> > existing pull request.
> >
> I got it. If default splitting of RAM between nodes is
> deprecated, this patch can't reuse the splitting code. I agree with droping
> this patch.
Probably all we need to fix this issue is to replace
NumaNodeOptions node = { };
with
NumaNodeOptions node = { .size = ram_size };
in the auto_enable_numa block.
Do you plan to send v2?
--
Eduardo
[Qemu-devel] [PULL 00/13] target/openrisc updates
The following changes since commit a8b5ad8e1faef0d1bb3e550530328e8ec76fe87c: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2019-09-04 17:22:34 +0100) are available in the Git repository at: https://github.com/rth7680/qemu.git tags/pull-or1k-20190904 for you to fetch changes up to 9e3bab08d3e3f5808cc35a59af1912bfb6fe96fd: target/openrisc: Update cpu "any" to v1.3 (2019-09-04 13:01:56 -0700) Updates for arch v1.3. Richard Henderson (13): target/openrisc: Add DisasContext parameter to check_r0_write target/openrisc: Replace cpu register array with a function target/openrisc: Cache R0 in DisasContext target/openrisc: Make VR and PPC read-only target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init target/openrisc: Add VR2 and AVR special processor registers target/openrisc: Fix lf.ftoi.s target/openrisc: Check CPUCFG_OF32S for float insns target/openrisc: Add support for ORFPX64A32 target/openrisc: Implement unordered fp comparisons target/openrisc: Implement move to/from FPCSR target/openrisc: Implement l.adrp target/openrisc: Update cpu "any" to v1.3 linux-user/openrisc/target_elf.h | 2 +- target/openrisc/cpu.h| 24 +- target/openrisc/helper.h | 6 + target/openrisc/cpu.c| 30 +- target/openrisc/disas.c | 81 + target/openrisc/fpu_helper.c | 49 ++- target/openrisc/machine.c| 11 + target/openrisc/sys_helper.c | 38 ++- target/openrisc/translate.c | 716 +-- target/openrisc/insns.decode | 45 +++ 10 files changed, 774 insertions(+), 228 deletions(-)
[Qemu-devel] [PATCH v1 14/42] tests/docker: move our HPPA cross compile to Buster
Now Buster is released we can stop relying on the movable feast that is Sid for our cross-compiler for building tests. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 2 +- tests/docker/dockerfiles/debian-hppa-cross.docker | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index e7379f1d732..ba5a624eaec 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -100,9 +100,9 @@ docker-image-debian-win64-cross: docker-image-debian9-mxe docker-image-debian-alpha-cross: docker-image-debian10 docker-image-debian-arm64-cross: docker-image-debian10 +docker-image-debian-hppa-cross: docker-image-debian10 docker-image-debian-powerpc-cross: docker-image-debian10 -docker-image-debian-hppa-cross: docker-image-debian-sid docker-image-debian-m68k-cross: docker-image-debian-sid docker-image-debian-sh4-cross: docker-image-debian-sid docker-image-debian-sparc64-cross: docker-image-debian-sid diff --git a/tests/docker/dockerfiles/debian-hppa-cross.docker b/tests/docker/dockerfiles/debian-hppa-cross.docker index ee6d9a24ce8..5c68b2d3304 100644 --- a/tests/docker/dockerfiles/debian-hppa-cross.docker +++ b/tests/docker/dockerfiles/debian-hppa-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -- 2.20.1
[Qemu-devel] [PATCH v1 29/42] configure: check if --no-pie is supported first
For whatever reason this doesn't trigger normally but because
compile_prog uses QEMU_CFLAGS we end up trying to build a -pie
--no-pie build which confuses compilers on some non-x86 hosts.
Signed-off-by: Alex Bennée
---
configure | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/configure b/configure
index 7860bbc3121..30aad233d17 100755
--- a/configure
+++ b/configure
@@ -2021,6 +2021,12 @@ static THREAD int tls_var;
int main(void) { return tls_var; }
EOF
+ # check we support --no-pie first...
+ if compile_prog "-Werror -fno-pie" "-no-pie"; then
+CFLAGS_NOPIE="-fno-pie"
+LDFLAGS_NOPIE="-nopie"
+ fi
+
if compile_prog "-fPIE -DPIE" "-pie"; then
QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS"
LDFLAGS="-pie $LDFLAGS"
@@ -2036,11 +2042,6 @@ EOF
pie="no"
fi
fi
-
- if compile_prog "-Werror -fno-pie" "-nopie"; then
-CFLAGS_NOPIE="-fno-pie"
-LDFLAGS_NOPIE="-nopie"
- fi
fi
##
--
2.20.1
[Qemu-devel] [PATCH v1 16/42] tests/docker: move our sparc64 cross compile to Buster
Now Buster is released we can stop relying on the movable feast that is Sid for our cross-compiler for building tests. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include| 2 +- tests/docker/dockerfiles/debian-sparc64-cross.docker | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index 62f2733eb66..50c5e64212a 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -103,9 +103,9 @@ docker-image-debian-arm64-cross: docker-image-debian10 docker-image-debian-hppa-cross: docker-image-debian10 docker-image-debian-m68k-cross: docker-image-debian10 docker-image-debian-powerpc-cross: docker-image-debian10 +docker-image-debian-sparc64-cross: docker-image-debian10 docker-image-debian-sh4-cross: docker-image-debian-sid -docker-image-debian-sparc64-cross: docker-image-debian-sid docker-image-debian-mips64-cross: docker-image-debian-sid docker-image-debian-riscv64-cross: docker-image-debian-sid docker-image-debian-ppc64-cross: docker-image-debian-sid diff --git a/tests/docker/dockerfiles/debian-sparc64-cross.docker b/tests/docker/dockerfiles/debian-sparc64-cross.docker index 7a2c2ab19c2..31fd34f120b 100644 --- a/tests/docker/dockerfiles/debian-sparc64-cross.docker +++ b/tests/docker/dockerfiles/debian-sparc64-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -- 2.20.1
[Qemu-devel] [PATCH v1 27/42] tests/docker: use --arch-only for installing deps
The Debian QEMU packages require a bunch of cross compilers for building firmware which aren't available on all host architectures. Using --arch-only skips this particular requirement and allows us to install just the dependencies we need. Signed-off-by: Alex Bennée --- tests/docker/dockerfiles/debian-arm64-cross.docker| 2 +- tests/docker/dockerfiles/debian-armel-cross.docker| 2 +- tests/docker/dockerfiles/debian-armhf-cross.docker| 2 +- tests/docker/dockerfiles/debian-mips-cross.docker | 6 +++--- tests/docker/dockerfiles/debian-mips64el-cross.docker | 2 +- tests/docker/dockerfiles/debian-mipsel-cross.docker | 2 +- tests/docker/dockerfiles/debian-ppc64el-cross.docker | 2 +- tests/docker/dockerfiles/debian-s390x-cross.docker| 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) diff --git a/tests/docker/dockerfiles/debian-arm64-cross.docker b/tests/docker/dockerfiles/debian-arm64-cross.docker index 55045ff5d5a..09ca0a1ba79 100644 --- a/tests/docker/dockerfiles/debian-arm64-cross.docker +++ b/tests/docker/dockerfiles/debian-arm64-cross.docker @@ -13,7 +13,7 @@ RUN apt update && \ crossbuild-essential-arm64 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -apt build-dep -yy -a arm64 qemu +apt build-dep -yy -a arm64 --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=aarch64-linux-gnu- diff --git a/tests/docker/dockerfiles/debian-armel-cross.docker b/tests/docker/dockerfiles/debian-armel-cross.docker index 363a162a253..15378f8ea2c 100644 --- a/tests/docker/dockerfiles/debian-armel-cross.docker +++ b/tests/docker/dockerfiles/debian-armel-cross.docker @@ -11,7 +11,7 @@ RUN dpkg --add-architecture armel && \ apt update && \ apt install -yy crossbuild-essential-armel && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -apt build-dep -yy -a armel qemu +apt build-dep -yy -a armel --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=arm-linux-gnueabi- diff --git a/tests/docker/dockerfiles/debian-armhf-cross.docker b/tests/docker/dockerfiles/debian-armhf-cross.docker index d5365881e79..4a20af6fe1a 100644 --- a/tests/docker/dockerfiles/debian-armhf-cross.docker +++ b/tests/docker/dockerfiles/debian-armhf-cross.docker @@ -13,7 +13,7 @@ RUN apt update && \ crossbuild-essential-armhf RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -apt build-dep -yy -a armhf qemu +apt build-dep -yy -a armhf --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=arm-linux-gnueabihf- diff --git a/tests/docker/dockerfiles/debian-mips-cross.docker b/tests/docker/dockerfiles/debian-mips-cross.docker index a54efa7253a..08a8e1c29cc 100644 --- a/tests/docker/dockerfiles/debian-mips-cross.docker +++ b/tests/docker/dockerfiles/debian-mips-cross.docker @@ -1,9 +1,9 @@ # # Docker mips cross-compiler target # -# This docker target builds on the debian Stretch base image. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian9 +FROM qemu:debian10 MAINTAINER Philippe Mathieu-Daudé @@ -16,7 +16,7 @@ RUN apt update && \ RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -apt build-dep -yy -a mips qemu +apt build-dep -yy -a mips --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=mips-linux-gnu- diff --git a/tests/docker/dockerfiles/debian-mips64el-cross.docker b/tests/docker/dockerfiles/debian-mips64el-cross.docker index a1481e16e2c..2fca1124053 100644 --- a/tests/docker/dockerfiles/debian-mips64el-cross.docker +++ b/tests/docker/dockerfiles/debian-mips64el-cross.docker @@ -17,7 +17,7 @@ RUN dpkg --add-architecture mips64el && \ RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -apt build-dep -yy -a mips64el qemu +apt build-dep -yy -a mips64el --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=mips64el-linux-gnuabi64- diff --git a/tests/docker/dockerfiles/debian-mipsel-cross.docker b/tests/docker/dockerfiles/debian-mipsel-cross.docker index 88accad2692..4abf7832ac6 100644 --- a/tests/docker/dockerfiles/debian-mipsel-cross.docker +++ b/tests/docker/dockerfiles/debian-mipsel-cross.docker @@ -16,7 +16,7 @@ RUN apt update && \ RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -apt build-dep -yy -a mipsel qemu +apt build-dep -yy -a mipsel --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=mipsel-linux-gnu- diff --git a/tests/docker/dockerfiles/debian-ppc64el-cross.docker b/tests/docker/dockerfiles/debian-ppc64el-cross.docker index
[Qemu-devel] [PATCH v1 05/42] tests/tcg: cleanup Makefile inclusions
From: Paolo Bonzini
Rename Makefile.probe to Makefile.prereqs and make it actually
define rules for the tests.
Rename Makefile to Makefile.target, since it is not a toplevel
makefile.
Rename Makefile.include to Makefile.qemu and disentangle it
from the QEMU Makefile.target, so that it is invoked recursively
by tests/Makefile.include. Tests are now placed in
tests/tcg/$(TARGET).
Drop the usage of TARGET_BASE_ARCH, which is ignored by everything except
x86_64 and aarch64. Fix x86 tests by using -cpu max and, while
at it, standardize on QEMU_OPTS for aarch64 tests too.
Signed-off-by: Paolo Bonzini
Message-Id: <20190807143523.15917-3-pbonz...@redhat.com>
---
Makefile.target | 3 --
tests/Makefile.include| 23 +
.../tcg/{Makefile.probe => Makefile.prereqs} | 5 +-
tests/tcg/{Makefile.include => Makefile.qemu} | 48 +++
tests/tcg/{Makefile => Makefile.target} | 13 ++---
tests/tcg/aarch64/Makefile.target | 12 +++--
tests/tcg/arm/Makefile.softmmu-target | 4 --
tests/tcg/i386/Makefile.softmmu-target| 8
tests/tcg/i386/Makefile.target| 13 ++---
tests/tcg/x86_64/Makefile.softmmu-target | 36 ++
tests/tcg/x86_64/Makefile.target | 7 +--
11 files changed, 100 insertions(+), 72 deletions(-)
rename tests/tcg/{Makefile.probe => Makefile.prereqs} (92%)
rename tests/tcg/{Makefile.include => Makefile.qemu} (52%)
rename tests/tcg/{Makefile => Makefile.target} (92%)
create mode 100644 tests/tcg/x86_64/Makefile.softmmu-target
diff --git a/Makefile.target b/Makefile.target
index 933b27453a1..5e916230c43 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -39,9 +39,6 @@ endif
PROGS=$(QEMU_PROG) $(QEMU_PROGW)
STPFILES=
-# Makefile Tests
-include $(SRC_PATH)/tests/tcg/Makefile.include
-
config-target.h: config-target.h-timestamp
config-target.h-timestamp: config-target.mak
diff --git a/tests/Makefile.include b/tests/Makefile.include
index f5ac09549ca..8400656b9d3 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -1062,23 +1062,28 @@ RUN_TCG_TARGET_RULES=$(patsubst %,run-tcg-tests-%,
$(TARGET_DIRS))
ifeq ($(HAVE_USER_DOCKER),y)
# Probe for the Docker Builds needed for each build
$(foreach PROBE_TARGET,$(TARGET_DIRS), \
- $(eval -include $(SRC_PATH)/tests/tcg/Makefile.probe) \
- $(if $(DOCKER_PREREQ), \
- $(eval build-tcg-tests-$(PROBE_TARGET): $(DOCKER_PREREQ
+ $(eval -include $(SRC_PATH)/tests/tcg/Makefile.prereqs))
endif
build-tcg-tests-%:
- $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \
- SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" guest-tests, \
+ $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) \
+ -f $(SRC_PATH)/tests/tcg/Makefile.qemu \
+ SRC_PATH=$(SRC_PATH) \
+ V="$(V)" TARGET_DIR="$*/" guest-tests, \
"BUILD", "TCG tests for $*")
-run-tcg-tests-%: % build-tcg-tests-%
- $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \
- SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" run-guest-tests, \
+run-tcg-tests-%: build-tcg-tests-% %/all
+ $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) \
+ -f $(SRC_PATH)/tests/tcg/Makefile.qemu \
+ SRC_PATH=$(SRC_PATH) SPEED="$(SPEED)" \
+ V="$(V)" TARGET_DIR="$*/" run-guest-tests, \
"RUN", "TCG tests for $*")
clean-tcg-tests-%:
- $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)"
TARGET_DIR="$*/" clean-guest-tests,)
+ $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) \
+ -f $(SRC_PATH)/tests/tcg/Makefile.qemu \
+ SRC_PATH=$(SRC_PATH) TARGET_DIR="$*/" clean-guest-tests, \
+ "RUN", "TCG tests for $*")
.PHONY: build-tcg
build-tcg: $(BUILD_TCG_TARGET_RULES)
diff --git a/tests/tcg/Makefile.probe b/tests/tcg/Makefile.prereqs
similarity index 92%
rename from tests/tcg/Makefile.probe
rename to tests/tcg/Makefile.prereqs
index 9dc654663d6..53b01962e1d 100644
--- a/tests/tcg/Makefile.probe
+++ b/tests/tcg/Makefile.prereqs
@@ -8,20 +8,19 @@
# each target.
# First we need the target makefile which tells us the target architecture
+CROSS_CC_GUEST:=
-include $(BUILD_DIR)/$(PROBE_TARGET)/config-target.mak
# Then we load up the target architecture makefiles which tell us
# about the compilers
-CROSS_CC_GUEST:=
DOCKER_IMAGE:=
-DOCKER_PREREQ:=
-include $(SRC_PATH)/tests/tcg/$(TARGET_BASE_ARCH)/Makefile.include
-include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.include
ifndef CROSS_CC_GUEST
ifneq ($(DOCKER_IMAGE),)
-DOCKER_PREREQ:=docker-image-$(DOCKER_IMAGE)
+build-tcg-tests-$(PROBE_TARGET): docker-image-$(DOCKER_IMAGE)
endif
endif
diff --git a/tests/tcg/Makefile.include b/tests/tcg/Makefile.qemu
similarity index
[Qemu-devel] [PATCH v1 39/42] .travis.yml: Cache Linux/Clang jobs together
From: Philippe Mathieu-Daudé
These jobs build different components but use the same
host features. Put them in the same cache bucket.
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 63cbf41e573..17aca3cd9c8 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -173,11 +173,13 @@ matrix:
# Test with Clang for compile portability (Travis uses clang-5.0)
- env:
- CONFIG="--disable-system"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-clang-default"
compiler: clang
- env:
- CONFIG="--disable-user --target-list=${MAIN_SOFTMMU_TARGETS}"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-clang-default"
compiler: clang
@@ -190,6 +192,7 @@ matrix:
- env:
- CONFIG="--disable-user --target-list-exclude=${MAIN_SOFTMMU_TARGETS}"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-clang-default"
compiler: clang
--
2.20.1
[Qemu-devel] [PATCH v1 10/42] tests/docker: add Buster to DOCKER_PARTIAL_IMAGES
We need to add additional packages to the base images to be able to build QEMU so lets avoid building with it. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index cf535cbd196..89881fb5f5d 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -6,7 +6,7 @@ DOCKER_SUFFIX := .docker DOCKER_FILES_DIR := $(SRC_PATH)/tests/docker/dockerfiles DOCKER_DEPRECATED_IMAGES := debian # we don't run tests on intermediate images (used as base by another image) -DOCKER_PARTIAL_IMAGES := debian debian8 debian9 debian8-mxe debian-ports debian-sid debian-bootstrap +DOCKER_PARTIAL_IMAGES := debian debian8 debian9 debian10 debian8-mxe debian-ports debian-sid debian-bootstrap DOCKER_IMAGES := $(filter-out $(DOCKER_DEPRECATED_IMAGES),$(sort $(notdir $(basename $(wildcard $(DOCKER_FILES_DIR)/*.docker) DOCKER_TARGETS := $(patsubst %,docker-image-%,$(DOCKER_IMAGES)) # Use a global constant ccache directory to speed up repetitive builds -- 2.20.1
[Qemu-devel] [PATCH v1 36/42] .travis.yml: Document how the build matrix use caches
From: Philippe Mathieu-Daudé We will set the CACHE_NAME variable to improve the caching of various jobs using the same characteristics. Document it first. See https://docs.travis-ci.com/user/caching/#caches-and-build-matrices Signed-off-by: Philippe Mathieu-Daudé --- .travis.yml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/.travis.yml b/.travis.yml index 2dd26486abc..ab3e4ebaadf 100644 --- a/.travis.yml +++ b/.travis.yml @@ -6,6 +6,12 @@ language: c compiler: - gcc cache: + # There is one cache per branch and compiler version. + # characteristics of each job are used to identify the cache: + # - OS name (currently, linux, osx, or windows) + # - OS distribution (for Linux, xenial, trusty, or precise) + # - macOS image name (e.g., xcode7.2) + # - Names and values of visible environment variables set in .travis.yml or Settings panel timeout: 1200 ccache: true pip: true -- 2.20.1
[Qemu-devel] [PATCH v1 00/42] current testing/next queue (podman, docker, ci)
Hi All, Here is the current status of my testing/next queue. It brings together a number of different series as well as some CI fixes that may be coming in view different trees. So in order we have: Some fixes to for podman. This is a relatively new alternative to docker and it works well but needs a little tweak to ensure we can also use it from cross compiling check-tcg tests. Paolo's tcg Makefile disentanglement which reduces some of the Makefile hackage by having a tcg check specific configure step. I've made a few minor tweaks to the configure script to fix up -static handling and setting of make variables. There is then a set of clean-ups to the dockerfiles whhich allow them to default a target list in the dockerfile environment which can then be overridden. I then update a bunch of the images to buster which allows us to drop the rather hokey sid based approach we were using. The next major chunk is Phillipe's caching changes which make a considerable difference when constantly rebuild the same tree, especially if all you are messing around with is ancillary scripts. Finally there are a few more CI fixes including one slightly hacky change to deal with variation in python3 implementations. Please review ;-) Alex Bennée (27): configure: clean-up container cross compile detect tests/docker: fix "cc" command to work with podman tests/tcg: add .gitignore for in source builds tests/docker: move DEF_TARGET_LIST setting to common.rc tests/docker: set DEF_TARGET_LIST for some containers tests/docker: add Buster to DOCKER_PARTIAL_IMAGES tests/docker: move our arm64 cross compile to Buster tests/docker: move our powerpc cross compile to Buster tests/docker: move our Alpha cross compile to Buster tests/docker: move our HPPA cross compile to Buster tests/docker: move our m68k cross compile to Buster tests/docker: move our sparc64 cross compile to Buster tests/docker: move our sh4 cross compile to Buster tests/docker: move our mips64 cross compile to Buster tests/docker: move our riscv64 cross compile to Buster tests/docker: move our ppc64 cross compile to Buster tests/docker: drop debian-sid image tests/docker: drop powerpc-user image for QEMU cross builds tests/docker: add debian-xtensa-cross to DEBIAN_PARTIAL_IMAGES tests/docker: add debian9-mxe to DEBIAN_PARTIAL_IMAGES tests/docker: avoid $SHELL invoke bash directly tests/docker: add debian-amd64-cross for non-x86 hosts tests/docker: use --arch-only for installing deps tests/docker: add more images to PARTIAL_IMAGES when not on x86_64 configure: check if --no-pie is supported first tests/docker: --disable-libssh on ubuntu1804 builds tests/docker: don't always encoding for subprocess.check_output Cleber Rosa (1): Fedora images: use URLs from stable "archives.fedoraproject.org" Paolo Bonzini (3): tests/tcg: use EXTRA_CFLAGS everywhere tests/tcg: cleanup Makefile inclusions tests/tcg: move configuration to a sub-shell script Philippe Mathieu-Daudé (10): .travis.yml: Enable multiple caching features .travis.yml: Increase cache timeout from 3min to 20min .travis.yml: Cache Python PIP packages .travis.yml: Cache Avocado cache .travis.yml: Improve ccache use .travis.yml: Enable ccache on OSX .travis.yml: Document how the build matrix use caches .travis.yml: Cache Linux/GCC 'debug profile' jobs together .travis.yml: Cache Linux/GCC 'non-debug profile' jobs together .travis.yml: Cache Linux/Clang jobs together Thomas Huth (1): hw/misc: Mark most objects as "common" code to speed up compilation a litte bit .travis.yml | 39 ++- Makefile | 1 + Makefile.target | 3 - configure | 168 ++--- hw/misc/Makefile.objs | 90 +++ qemu-doc.texi | 6 +- tests/Makefile.include| 25 +- tests/acceptance/boot_linux_console.py| 25 +- tests/acceptance/linux_initrd.py | 5 +- tests/docker/Makefile.include | 61 +++-- tests/docker/common.rc| 4 + tests/docker/docker.py| 51 ++-- .../dockerfiles/debian-alpha-cross.docker | 7 +- .../dockerfiles/debian-amd64-cross.docker | 22 ++ .../dockerfiles/debian-arm64-cross.docker | 7 +- .../dockerfiles/debian-armel-cross.docker | 3 +- .../dockerfiles/debian-armhf-cross.docker | 3 +- .../debian-buster-arm64-cross.docker | 16 -- .../dockerfiles/debian-hppa-cross.docker | 5 +- .../dockerfiles/debian-m68k-cross.docker | 5 +- .../dockerfiles/debian-mips-cross.docker | 7 +- .../dockerfiles/debian-mips64-cross.docker| 5 +- .../dockerfiles/debian-mips64el-cross.docker | 3 +- .../dockerfiles/debian-mipsel-cross.docker| 2 +-
[Qemu-devel] [PATCH v1 42/42] tests/docker: don't always encoding for subprocess.check_output
This was only added in Python 3.6 and not all the build hosts have that recent a python3. However those that do will complain if everything isn't properly utf-8 clean: ./tests/docker/docker.py --engine auto build qemu:debian-amd64 tests/docker/dockerfiles/debian-amd64.docker --add-current-user Sending build context to Docker daemon 3.584kB Step 1/16 : FROM qemu:debian9 pull access denied for qemu, repository does not exist or may require 'docker login' Traceback (most recent call last): File "./tests/docker/docker.py", line 659, in sys.exit(main()) File "./tests/docker/docker.py", line 655, in main return args.cmdobj.run(args, argv) File "./tests/docker/docker.py", line 452, in run extra_files_cksum=cksum) File "./tests/docker/docker.py", line 306, in build_image quiet=quiet) File "./tests/docker/docker.py", line 231, in _do_check return subprocess.check_call(self._command + cmd, **kwargs) File "/usr/lib/python3.4/subprocess.py", line 561, in check_call raise CalledProcessError(retcode, cmd) subprocess.CalledProcessError: Command '['docker', 'build', '-t', 'qemu:debian-amd64', '-f', '/tmp/docker_buildjvzs88tf/tmpyvtj7ub0.docker', '/tmp/docker_buildjvzs88tf']' returned non-zero exit status 1 Error in atexit._run_exitfuncs: Traceback (most recent call last): File "./tests/docker/docker.py", line 258, in _kill_instances return self._do_kill_instances(True) File "./tests/docker/docker.py", line 239, in _do_kill_instances labels = json.loads(resp)[0]["Config"]["Labels"] File "/usr/lib/python3.4/json/__init__.py", line 312, in loads s.__class__.__name__)) TypeError: the JSON object must be str, not 'bytes' make: *** [docker-image-debian-amd64] Error 1 Signed-off-by: Alex Bennée --- tests/docker/docker.py | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tests/docker/docker.py b/tests/docker/docker.py index 8f391eb278b..e5b7632464b 100755 --- a/tests/docker/docker.py +++ b/tests/docker/docker.py @@ -258,10 +258,16 @@ class Docker(object): return self._do_kill_instances(True) def _output(self, cmd, **kwargs): -return subprocess.check_output(self._command + cmd, - stderr=subprocess.STDOUT, - encoding='utf-8', - **kwargs) +if sys.version_info[1] >= 6: +return subprocess.check_output(self._command + cmd, + stderr=subprocess.STDOUT, + encoding='utf-8', + **kwargs) +else: +return subprocess.check_output(self._command + cmd, + stderr=subprocess.STDOUT, + **kwargs) + def inspect_tag(self, tag): try: -- 2.20.1
[Qemu-devel] [PATCH v1 06/42] tests/tcg: move configuration to a sub-shell script
From: Paolo Bonzini
Avoid the repeated inclusions of config-target.mak, which have
risks of namespace pollution, and instead build minimal configuration
files in a configuration script. The same configuration files can
also be included in Makefile and Makefile.qemu
Signed-off-by: Paolo Bonzini
Message-Id: <20190807143523.15917-4-pbonz...@redhat.com>
[AJB: s/docker/container/, rm last bits from configure]
Signed-off-by: Alex Bennée
---
Makefile | 1 +
configure | 157 ++-
tests/Makefile.include | 8 +-
tests/tcg/Makefile.prereqs | 18 +--
tests/tcg/Makefile.qemu| 51 +++
tests/tcg/Makefile.target | 8 +-
tests/tcg/aarch64/Makefile.include | 8 -
tests/tcg/alpha/Makefile.include | 2 -
tests/tcg/arm/Makefile.include | 8 -
tests/tcg/configure.sh | 234 +
tests/tcg/cris/Makefile.include| 6 -
tests/tcg/hppa/Makefile.include| 2 -
tests/tcg/i386/Makefile.include| 9 --
tests/tcg/m68k/Makefile.include| 2 -
tests/tcg/mips/Makefile.include| 20 ---
tests/tcg/ppc/Makefile.include | 10 --
tests/tcg/riscv/Makefile.include | 10 --
tests/tcg/s390x/Makefile.include | 2 -
tests/tcg/sh4/Makefile.include | 4 -
tests/tcg/sparc64/Makefile.include | 2 -
tests/tcg/xtensa/Makefile.include | 11 --
21 files changed, 282 insertions(+), 291 deletions(-)
delete mode 100644 tests/tcg/aarch64/Makefile.include
delete mode 100644 tests/tcg/alpha/Makefile.include
delete mode 100644 tests/tcg/arm/Makefile.include
create mode 100755 tests/tcg/configure.sh
delete mode 100644 tests/tcg/cris/Makefile.include
delete mode 100644 tests/tcg/hppa/Makefile.include
delete mode 100644 tests/tcg/i386/Makefile.include
delete mode 100644 tests/tcg/m68k/Makefile.include
delete mode 100644 tests/tcg/mips/Makefile.include
delete mode 100644 tests/tcg/ppc/Makefile.include
delete mode 100644 tests/tcg/riscv/Makefile.include
delete mode 100644 tests/tcg/s390x/Makefile.include
delete mode 100644 tests/tcg/sh4/Makefile.include
delete mode 100644 tests/tcg/sparc64/Makefile.include
delete mode 100644 tests/tcg/xtensa/Makefile.include
diff --git a/Makefile b/Makefile
index ae17a830678..b3528617e48 100644
--- a/Makefile
+++ b/Makefile
@@ -717,6 +717,7 @@ endef
distclean: clean
rm -f config-host.mak config-host.h* config-host.ld $(DOCS)
qemu-options.texi qemu-img-cmds.texi qemu-monitor.texi qemu-monitor-info.texi
+ rm -f tests/tcg/config-*.mak
rm -f config-all-devices.mak config-all-disas.mak config.status
rm -f $(SUBDIR_DEVICES_MAK)
rm -f po/*.mo tests/qemu-iotests/common.env
diff --git a/configure b/configure
index 94845fc5101..7860bbc3121 100755
--- a/configure
+++ b/configure
@@ -495,27 +495,10 @@ qed="yes"
parallels="yes"
sheepdog="yes"
libxml2=""
-container="no"
debug_mutex="no"
libpmem=""
default_devices="yes"
-# cross compilers defaults, can be overridden with --cross-cc-ARCH
-cross_cc_aarch64="aarch64-linux-gnu-gcc"
-cross_cc_aarch64_be="$cross_cc_aarch64"
-cross_cc_cflags_aarch64_be="-mbig-endian"
-cross_cc_arm="arm-linux-gnueabihf-gcc"
-cross_cc_cflags_armeb="-mbig-endian"
-cross_cc_i386="i386-pc-linux-gnu-gcc"
-cross_cc_cflags_i386=""
-cross_cc_ppc="powerpc-linux-gnu-gcc"
-cross_cc_cflags_ppc="-m32"
-cross_cc_ppc64="powerpc-linux-gnu-gcc"
-cross_cc_cflags_ppc64="-m64"
-cross_cc_ppc64le="powerpc64le-linux-gnu-gcc"
-
-enabled_cross_compilers=""
-
supported_cpu="no"
supported_os="no"
bogus_os="no"
@@ -548,9 +531,12 @@ for opt do
;;
--cross-cc-cflags-*) cc_arch=${opt#--cross-cc-flags-}; cc_arch=${cc_arch%%=*}
eval "cross_cc_cflags_${cc_arch}=\$optarg"
+ cross_cc_vars="$cross_cc_vars cross_cc_cflags_${cc_arch}"
;;
--cross-cc-*) cc_arch=${opt#--cross-cc-}; cc_arch=${cc_arch%%=*}
+cc_archs="$cc_archs $cc_arch"
eval "cross_cc_${cc_arch}=\$optarg"
+cross_cc_vars="$cross_cc_vars cross_cc_${cc_arch}"
;;
esac
done
@@ -745,42 +731,34 @@ ARCH=
case "$cpu" in
ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64)
supported_cpu="yes"
-eval "cross_cc_${cpu}=\$host_cc"
;;
ppc64le)
ARCH="ppc64"
supported_cpu="yes"
-cross_cc_ppc64le=$host_cc
;;
i386|i486|i586|i686|i86pc|BePC)
cpu="i386"
supported_cpu="yes"
-cross_cc_i386=$host_cc
;;
x86_64|amd64)
cpu="x86_64"
supported_cpu="yes"
-cross_cc_x86_64=$host_cc
;;
armv*b|armv*l|arm)
cpu="arm"
supported_cpu="yes"
-cross_cc_arm=$host_cc
;;
aarch64)
cpu="aarch64"
supported_cpu="yes"
-cross_cc_aarch64=$host_cc
;;
mips*)
cpu="mips"
supported_cpu="yes"
-cross_cc_mips=$host_cc
;;
sparc|sun4[cdmuv])
cpu="sparc"
supported_cpu="yes"
-cross_cc_sparc=$host_cc
;;
*)
# This
[Qemu-devel] [PATCH v1 40/42] Fedora images: use URLs from stable "archives.fedoraproject.org"
From: Cleber Rosa
The LinuxInitrd.test_with_2gib_file_should_work_with_linux_v4_16 test,
from tests/acceptance/linux_initrd.py, is currently failing to fetch
the "vmlinuz" file. The reason for the failure is that the Fedora
project retires older versions from the "dl.fedoraproject.org" URL,
and keeps them in "archives.fedoraproject.org". As an added note,
that test uses a Fedora 28 image, because of the specific Linux kernel
version requirements of the test.
For the sake of stability, let's use URLs from the archived and
supposedely ever stable URLs. The good news is that the currently
supported versions are also hosted on the later. This change limits
itself to change the URLs, while keeping the fetched files the same
(as can be evidenced by the unchanged hashes).
Documentation and the "vm tests" fedora definition were also updated.
Signed-off-by: Cleber Rosa
Reviewed-by: Yash Mankad
Message-Id: <20190904005218.12536-1-cr...@redhat.com>
Signed-off-by: Alex Bennée
---
qemu-doc.texi | 6 +++---
tests/acceptance/boot_linux_console.py | 25 +++--
tests/acceptance/linux_initrd.py | 5 +++--
tests/vm/fedora| 2 +-
4 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 577d1e83764..37795f86fb6 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -440,15 +440,15 @@ of .
Example: boot from a remote Fedora 20 live ISO image
@example
-qemu-system-x86_64 --drive
media=cdrom,file=http://dl.fedoraproject.org/pub/fedora/linux/releases/20/Live/x86_64/Fedora-Live-Desktop-x86_64-20-1.iso,readonly
+qemu-system-x86_64 --drive
media=cdrom,file=https://archives.fedoraproject.org/pub/archive/fedora/linux/releases/20/Live/x86_64/Fedora-Live-Desktop-x86_64-20-1.iso,readonly
-qemu-system-x86_64 --drive
media=cdrom,file.driver=http,file.url=http://dl.fedoraproject.org/pub/fedora/linux/releases/20/Live/x86_64/Fedora-Live-Desktop-x86_64-20-1.iso,readonly
+qemu-system-x86_64 --drive
media=cdrom,file.driver=http,file.url=http://archives.fedoraproject.org/pub/archive/fedora/linux/releases/20/Live/x86_64/Fedora-Live-Desktop-x86_64-20-1.iso,readonly
@end example
Example: boot from a remote Fedora 20 cloud image using a local overlay for
writes, copy-on-read, and a readahead of 64k
@example
-qemu-img create -f qcow2 -o backing_file='json:@{"file.driver":"http",,
"file.url":"https://dl.fedoraproject.org/pub/fedora/linux/releases/20/Images/x86_64/Fedora-x86_64-20-20131211.1-sda.qcow2;,,
"file.readahead":"64k"@}' /tmp/Fedora-x86_64-20-20131211.1-sda.qcow2
+qemu-img create -f qcow2 -o backing_file='json:@{"file.driver":"http",,
"file.url":"http://archives.fedoraproject.org/pub/archive/fedora/linux/releases/20/Images/x86_64/Fedora-x86_64-20-20131211.1-sda.qcow2;,,
"file.readahead":"64k"@}' /tmp/Fedora-x86_64-20-20131211.1-sda.qcow2
qemu-system-x86_64 -drive
file=/tmp/Fedora-x86_64-20-20131211.1-sda.qcow2,copy-on-read=on
@end example
diff --git a/tests/acceptance/boot_linux_console.py
b/tests/acceptance/boot_linux_console.py
index 2504ef01507..8a9a314ab49 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -76,8 +76,9 @@ class BootLinuxConsole(Test):
:avocado: tags=arch:x86_64
:avocado: tags=machine:pc
"""
-kernel_url = ('https://download.fedoraproject.org/pub/fedora/linux/'
-
'releases/29/Everything/x86_64/os/images/pxeboot/vmlinuz')
+kernel_url = ('https://archives.fedoraproject.org/pub/archive/fedora'
+ '/linux/releases/29/Everything/x86_64/os/images/pxeboot'
+ '/vmlinuz')
kernel_hash = '23bebd2680757891cf7adedb033532163a792495'
kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
@@ -250,8 +251,9 @@ class BootLinuxConsole(Test):
:avocado: tags=arch:aarch64
:avocado: tags=machine:virt
"""
-kernel_url = ('https://download.fedoraproject.org/pub/fedora/linux/'
-
'releases/29/Everything/aarch64/os/images/pxeboot/vmlinuz')
+kernel_url = ('https://archives.fedoraproject.org/pub/archive/fedora'
+ '/linux/releases/29/Everything/aarch64/os/images/pxeboot'
+ '/vmlinuz')
kernel_hash = '8c73e469fc6ea06a58dc83a628fc695b693b8493'
kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
@@ -271,8 +273,9 @@ class BootLinuxConsole(Test):
:avocado: tags=arch:arm
:avocado: tags=machine:virt
"""
-kernel_url = ('https://download.fedoraproject.org/pub/fedora/linux/'
-
'releases/29/Everything/armhfp/os/images/pxeboot/vmlinuz')
+kernel_url = ('https://archives.fedoraproject.org/pub/archive/fedora'
+ '/linux/releases/29/Everything/armhfp/os/images/pxeboot'
+ '/vmlinuz')
[Qemu-devel] [PATCH v1 01/42] hw/misc: Mark most objects as "common" code to speed up compilation a litte bit
From: Thomas Huth Most of the code in hw/misc/ does not directly depend on CPU-specific code. Mark it as "common" so that the code can be shared between e.g. qemu-system-arm and qemu-system-aarch64, or between the various mips flavours, instead of recompiling it for each and every target again and again. Signed-off-by: Thomas Huth Message-Id: <20190902162638.28142-1-th...@redhat.com> --- hw/misc/Makefile.objs | 90 +-- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index e4aad707fb4..a1506809660 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -26,57 +26,57 @@ common-obj-$(CONFIG_PUV3) += puv3_pm.o common-obj-$(CONFIG_MACIO) += macio/ -obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o +common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o -obj-$(CONFIG_REALVIEW) += arm_sysctl.o -obj-$(CONFIG_NSERIES) += cbus.o -obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o -obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o exynos4210_rng.o -obj-$(CONFIG_IMX) += imx_ccm.o -obj-$(CONFIG_IMX) += imx31_ccm.o -obj-$(CONFIG_IMX) += imx25_ccm.o -obj-$(CONFIG_IMX) += imx6_ccm.o -obj-$(CONFIG_IMX) += imx6ul_ccm.o +common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o +common-obj-$(CONFIG_NSERIES) += cbus.o +common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o +common-obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o exynos4210_rng.o +common-obj-$(CONFIG_IMX) += imx_ccm.o +common-obj-$(CONFIG_IMX) += imx31_ccm.o +common-obj-$(CONFIG_IMX) += imx25_ccm.o +common-obj-$(CONFIG_IMX) += imx6_ccm.o +common-obj-$(CONFIG_IMX) += imx6ul_ccm.o obj-$(CONFIG_IMX) += imx6_src.o -obj-$(CONFIG_IMX) += imx7_ccm.o -obj-$(CONFIG_IMX) += imx2_wdt.o -obj-$(CONFIG_IMX) += imx7_snvs.o -obj-$(CONFIG_IMX) += imx7_gpr.o -obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o -obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o -obj-$(CONFIG_MAINSTONE) += mst_fpga.o -obj-$(CONFIG_OMAP) += omap_clk.o -obj-$(CONFIG_OMAP) += omap_gpmc.o -obj-$(CONFIG_OMAP) += omap_l4.o -obj-$(CONFIG_OMAP) += omap_sdrc.o -obj-$(CONFIG_OMAP) += omap_tap.o -obj-$(CONFIG_RASPI) += bcm2835_mbox.o -obj-$(CONFIG_RASPI) += bcm2835_property.o -obj-$(CONFIG_RASPI) += bcm2835_rng.o -obj-$(CONFIG_SLAVIO) += slavio_misc.o -obj-$(CONFIG_ZYNQ) += zynq_slcr.o -obj-$(CONFIG_ZYNQ) += zynq-xadc.o -obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o +common-obj-$(CONFIG_IMX) += imx7_ccm.o +common-obj-$(CONFIG_IMX) += imx2_wdt.o +common-obj-$(CONFIG_IMX) += imx7_snvs.o +common-obj-$(CONFIG_IMX) += imx7_gpr.o +common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o +common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o +common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o +common-obj-$(CONFIG_OMAP) += omap_clk.o +common-obj-$(CONFIG_OMAP) += omap_gpmc.o +common-obj-$(CONFIG_OMAP) += omap_l4.o +common-obj-$(CONFIG_OMAP) += omap_sdrc.o +common-obj-$(CONFIG_OMAP) += omap_tap.o +common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o +common-obj-$(CONFIG_RASPI) += bcm2835_property.o +common-obj-$(CONFIG_RASPI) += bcm2835_rng.o +common-obj-$(CONFIG_SLAVIO) += slavio_misc.o +common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o +common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o +common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) += mips_cpc.o obj-$(CONFIG_MIPS_ITU) += mips_itu.o -obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o -obj-$(CONFIG_MPS2_SCC) += mps2-scc.o +common-obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o +common-obj-$(CONFIG_MPS2_SCC) += mps2-scc.o -obj-$(CONFIG_TZ_MPC) += tz-mpc.o -obj-$(CONFIG_TZ_MSC) += tz-msc.o -obj-$(CONFIG_TZ_PPC) += tz-ppc.o -obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o +common-obj-$(CONFIG_TZ_MPC) += tz-mpc.o +common-obj-$(CONFIG_TZ_MSC) += tz-msc.o +common-obj-$(CONFIG_TZ_PPC) += tz-ppc.o +common-obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o -obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o -obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o -obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o +common-obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o +common-obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o +common-obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o -obj-$(CONFIG_PVPANIC) += pvpanic.o -obj-$(CONFIG_AUX) += auxbus.o -obj-$(CONFIG_ASPEED_SOC) += aspeed_xdma.o -obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o -obj-$(CONFIG_MSF2) += msf2-sysreg.o -obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o +common-obj-$(CONFIG_PVPANIC) += pvpanic.o +common-obj-$(CONFIG_AUX) += auxbus.o +common-obj-$(CONFIG_ASPEED_SOC) += aspeed_xdma.o +common-obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o +common-obj-$(CONFIG_MSF2) += msf2-sysreg.o +common-obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o -obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o +common-obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o -- 2.20.1
[Qemu-devel] [PATCH v1 09/42] tests/docker: set DEF_TARGET_LIST for some containers
You can assume the failures most people are interested in are the cross-compile failures that are specific to the cross compile target. Set DEF_TARGET_LIST based on what we use for shippable, the user can always override by calling with TARGET_LIST set. Signed-off-by: Alex Bennée --- tests/docker/dockerfiles/debian-arm64-cross.docker| 1 + tests/docker/dockerfiles/debian-armel-cross.docker| 1 + tests/docker/dockerfiles/debian-armhf-cross.docker| 1 + tests/docker/dockerfiles/debian-mips-cross.docker | 1 + tests/docker/dockerfiles/debian-mips64el-cross.docker | 1 + tests/docker/dockerfiles/debian-ppc64el-cross.docker | 1 + tests/docker/dockerfiles/debian-s390x-cross.docker| 1 + 7 files changed, 7 insertions(+) diff --git a/tests/docker/dockerfiles/debian-arm64-cross.docker b/tests/docker/dockerfiles/debian-arm64-cross.docker index 7c2cc93daf8..6b59ef0843a 100644 --- a/tests/docker/dockerfiles/debian-arm64-cross.docker +++ b/tests/docker/dockerfiles/debian-arm64-cross.docker @@ -17,6 +17,7 @@ RUN apt update && \ # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=aarch64-linux-gnu- +ENV DEF_TARGET_LIST aarch64-softmmu,aarch64-linux-user RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-armel-cross.docker b/tests/docker/dockerfiles/debian-armel-cross.docker index d866fe5d75b..363a162a253 100644 --- a/tests/docker/dockerfiles/debian-armel-cross.docker +++ b/tests/docker/dockerfiles/debian-armel-cross.docker @@ -15,6 +15,7 @@ RUN dpkg --add-architecture armel && \ # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=arm-linux-gnueabi- +ENV DEF_TARGET_LIST arm-softmmu,arm-linux-user,armeb-linux-user RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-armhf-cross.docker b/tests/docker/dockerfiles/debian-armhf-cross.docker index 2b8627673c3..d5365881e79 100644 --- a/tests/docker/dockerfiles/debian-armhf-cross.docker +++ b/tests/docker/dockerfiles/debian-armhf-cross.docker @@ -17,6 +17,7 @@ RUN apt update && \ # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=arm-linux-gnueabihf- +ENV DEF_TARGET_LIST arm-softmmu,arm-linux-user,armeb-linux-user RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-mips-cross.docker b/tests/docker/dockerfiles/debian-mips-cross.docker index 3c4d6f9ec1f..a54efa7253a 100644 --- a/tests/docker/dockerfiles/debian-mips-cross.docker +++ b/tests/docker/dockerfiles/debian-mips-cross.docker @@ -20,6 +20,7 @@ RUN apt update && \ # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=mips-linux-gnu- +ENV DEF_TARGET_LIST mips-softmmu,mipsel-linux-user # Install extra libraries to increase code coverage RUN apt update && \ diff --git a/tests/docker/dockerfiles/debian-mips64el-cross.docker b/tests/docker/dockerfiles/debian-mips64el-cross.docker index 34b0b828957..a1481e16e2c 100644 --- a/tests/docker/dockerfiles/debian-mips64el-cross.docker +++ b/tests/docker/dockerfiles/debian-mips64el-cross.docker @@ -21,6 +21,7 @@ RUN apt update && \ # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=mips64el-linux-gnuabi64- +ENV DEF_TARGET_LIST mips64el-softmmu,mips64el-linux-user # Install extra libraries to increase code coverage RUN apt update && \ diff --git a/tests/docker/dockerfiles/debian-ppc64el-cross.docker b/tests/docker/dockerfiles/debian-ppc64el-cross.docker index fc056d7bc35..f10883c8188 100644 --- a/tests/docker/dockerfiles/debian-ppc64el-cross.docker +++ b/tests/docker/dockerfiles/debian-ppc64el-cross.docker @@ -16,6 +16,7 @@ RUN apt update && \ # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=powerpc64le-linux-gnu- +ENV DEF_TARGET_LIST ppc64-softmmu,ppc64-linux-user,ppc64abi32-linux-user # Install extra libraries to increase code coverage RUN apt update && \ diff --git a/tests/docker/dockerfiles/debian-s390x-cross.docker b/tests/docker/dockerfiles/debian-s390x-cross.docker index 6732f9ec789..efa346007d6 100644 --- a/tests/docker/dockerfiles/debian-s390x-cross.docker +++ b/tests/docker/dockerfiles/debian-s390x-cross.docker @@ -21,6 +21,7 @@ RUN apt update && \ # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=s390x-linux-gnu- +ENV DEF_TARGET_LIST s390x-softmmu,s390x-linux-user # Install extra libraries to increase code coverage RUN apt update && \ -- 2.20.1
[Qemu-devel] [PATCH v1 24/42] tests/docker: add debian9-mxe to DEBIAN_PARTIAL_IMAGES
Another image that can't be used directly to build QEMU. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index 8d7f9376578..2c8cb790ad0 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -6,7 +6,7 @@ DOCKER_SUFFIX := .docker DOCKER_FILES_DIR := $(SRC_PATH)/tests/docker/dockerfiles DOCKER_DEPRECATED_IMAGES := debian # we don't run tests on intermediate images (used as base by another image) -DOCKER_PARTIAL_IMAGES := debian debian8 debian9 debian10 debian8-mxe debian-ports debian-bootstrap +DOCKER_PARTIAL_IMAGES := debian debian8 debian9 debian10 debian8-mxe debian9-mxe debian-ports debian-bootstrap DOCKER_IMAGES := $(filter-out $(DOCKER_DEPRECATED_IMAGES),$(sort $(notdir $(basename $(wildcard $(DOCKER_FILES_DIR)/*.docker) DOCKER_TARGETS := $(patsubst %,docker-image-%,$(DOCKER_IMAGES)) # Use a global constant ccache directory to speed up repetitive builds -- 2.20.1
[Qemu-devel] [PATCH v1 17/42] tests/docker: move our sh4 cross compile to Buster
Now Buster is released we can stop relying on the movable feast that is Sid for our cross-compiler for building tests. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include| 2 +- tests/docker/dockerfiles/debian-sh4-cross.docker | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index 50c5e64212a..e946aae14fa 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -103,9 +103,9 @@ docker-image-debian-arm64-cross: docker-image-debian10 docker-image-debian-hppa-cross: docker-image-debian10 docker-image-debian-m68k-cross: docker-image-debian10 docker-image-debian-powerpc-cross: docker-image-debian10 +docker-image-debian-sh4-cross: docker-image-debian10 docker-image-debian-sparc64-cross: docker-image-debian10 -docker-image-debian-sh4-cross: docker-image-debian-sid docker-image-debian-mips64-cross: docker-image-debian-sid docker-image-debian-riscv64-cross: docker-image-debian-sid docker-image-debian-ppc64-cross: docker-image-debian-sid diff --git a/tests/docker/dockerfiles/debian-sh4-cross.docker b/tests/docker/dockerfiles/debian-sh4-cross.docker index 29983b2d75b..9d7663764e4 100644 --- a/tests/docker/dockerfiles/debian-sh4-cross.docker +++ b/tests/docker/dockerfiles/debian-sh4-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -- 2.20.1
Re: [Qemu-devel] Cryptic errors from PIP install if missing openssl-devel
On Sat, Aug 31, 2019 at 11:48:34AM +1000, David Gibson wrote:
> On Fri, Aug 30, 2019 at 02:56:48PM -0300, Eduardo Habkost wrote:
> > On Thu, Aug 29, 2019 at 11:31:25AM +1000, David Gibson wrote:
> > > If I attempt to run "make check-acceptance" on my POWER9, RHEL8.1
> > > machine when the openssl-devel package isn't installed, I get the
> > > following very cryptic error:
> > >
> > > VENV/home/dwg/qemu/build/rhel8/tests/venv
> > > PIP /home/dwg/qemu/tests/requirements.txt
> > > Command "/home/dwg/qemu/build/rhel8/tests/venv/bin/python -u -c "import
> > > setuptools,
> > > tokenize;__file__='/tmp/pip-build-la4el5r5/cryptography/setup.py';f=getattr(tokenize,
> > > 'open', open)(__file__);code=f.read().replace('\r\n',
> > > '\n');f.close();exec(compile(code, __file__, 'exec'))" install --record
> > > /tmp/pip-1efs22iz-record/install-record.txt
> > > --single-version-externally-managed --compile --install-headers
> > > /home/dwg/qemu/build/rhel8/tests/venv/include/site/python3.6/cryptography"
> > > failed with error code 1 in /tmp/pip-build-la4el5r5/cryptography/
> > >
> > > Using V=1 doesn't give any more useful information, and it's not
> > > (easily) possible to manually re-run the given command since it relies
> > > on things in /tmp that are removed once the attempt finishes.
> >
> > V=1 is supposed to show the actual pip command being run. I see
> > it here:
> >
> > $ make check-venv V=1
> > [...]
> > python3 -B -m venv --system-site-packages
> > /home/ehabkost/rh/proj/virt/qemu/tests/venv
> > * /home/ehabkost/rh/proj/virt/qemu/tests/venv/bin/python -m pip -q install
> > -r /home/ehabkost/rh/proj/virt/qemu/tests/requirements.txt
> > You are using pip version 19.0.3, however version 19.2.3 is available.
> > You should consider upgrading via the 'pip install --upgrade pip' command.
> > touch /home/ehabkost/rh/proj/virt/qemu/tests/venv
> >
> > Can you reproduce the problem if you re-run the pip command?
>
> Yes, I can, but it's basically just the same error without any extra
> information.
>
> > > I only figured out it was openssl-devel being missing that was the
> > > problem by (mostly) guesswork. It would be really great if we could
> > > generate a more helpful error here.
> >
> > I don't think there's much we can do about it, as the error is generated by
> > a
> > package being built by pip.
> >
> > There's one thing we can do to make it slightly better: not passing `-q` to
> > pip
> > if running with V=1, so people can see which packages are being installed
> > and
> > which one is generating the error.
>
> That sounds like a good start to me.
>
> > > In addition, if I rerun "make check-acceptance" it no longer even
> > > attempts the PIP install, since tests/venv already exists in my build
> > > environment. It then sort of works, but I think it might be hitting
> > > other errors because of the missing python packages. Sorry that's a
> > > bit vague - I also seem to be getting unrelated errors that I'm still
> > > trying to figure out.
> >
> > This sounds like a bug and we need to fix it.
>
> I agree.
Hi David,
I've pushed a branch here (most of the commits have already been sent
separately):
https://github.com/clebergnu/qemu/tree/ppc64
I've tested on a RHEL 8 ppc64le Power 9, and it seems to work for me.
My steps for building QEMU:
- Configured with: '/home/cleber/src/qemu/configure' '--enable-slirp=git'
'--python=/usr/bin/python3'
'--target-list=x86_64-softmmu,ppc64-softmmu,arm-softmmu,aarch64-softmmu,mips-softmmu,mipsel-softmmu,mips64-softmmu,mips64el-softmmu,sh4-softmmu,s390x-softmmu,alpha-softmmu,m68k-softmmu,riscv64-softmmu'
- make
- make check-acceptance
Would you be able to test if that branch works smoothly for you?
Thanks,
- Cleber.
>
> --
> David Gibson | I'll have my music baroque, and my code
> david AT gibson.dropbear.id.au| minimalist, thank you. NOT _the_
> _other_
> | _way_ _around_!
> http://www.ozlabs.org/~dgibson
[Qemu-devel] [PATCH v1 04/42] tests/tcg: use EXTRA_CFLAGS everywhere
From: Paolo Bonzini For i386 specifically, this allows using the host GCC to compile the i386 tests. But, it should really be done for all targets, unless we want to pass $(EXTRA_CFLAGS) directly as part of $(CC). Signed-off-by: Paolo Bonzini Message-Id: <20190807143523.15917-2-pbonz...@redhat.com> --- tests/tcg/aarch64/Makefile.softmmu-target | 4 ++-- tests/tcg/alpha/Makefile.softmmu-target | 4 ++-- tests/tcg/arm/Makefile.softmmu-target | 2 +- tests/tcg/i386/Makefile.softmmu-target| 4 ++-- tests/tcg/minilib/Makefile.target | 2 +- tests/tcg/xtensa/Makefile.softmmu-target | 4 ++-- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index 2e560e4d08e..4c4aaf61dd3 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -22,11 +22,11 @@ LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc .PRECIOUS: $(CRT_OBJS) %.o: $(CRT_PATH)/%.S - $(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@ # Build and link the tests %: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) memory: CFLAGS+=-DCHECK_UNALIGNED=1 diff --git a/tests/tcg/alpha/Makefile.softmmu-target b/tests/tcg/alpha/Makefile.softmmu-target index 3c0f34cc692..09193a62d68 100644 --- a/tests/tcg/alpha/Makefile.softmmu-target +++ b/tests/tcg/alpha/Makefile.softmmu-target @@ -22,11 +22,11 @@ LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc .PRECIOUS: $(CRT_OBJS) %.o: $(CRT_PATH)/%.S - $(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@ # Build and link the tests %: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) memory: CFLAGS+=-DCHECK_UNALIGNED=0 diff --git a/tests/tcg/arm/Makefile.softmmu-target b/tests/tcg/arm/Makefile.softmmu-target index 49d48d8a1c3..2deb06e6e46 100644 --- a/tests/tcg/arm/Makefile.softmmu-target +++ b/tests/tcg/arm/Makefile.softmmu-target @@ -18,7 +18,7 @@ CFLAGS+=-Wl,--build-id=none -x assembler-with-cpp LDFLAGS+=-nostdlib -N -static %: %.S %.ld - $(CC) $(CFLAGS) $(ASFLAGS) $< -o $@ $(LDFLAGS) -T $(ARM_SRC)/$@.ld + $(CC) $(CFLAGS) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) -T $(ARM_SRC)/$@.ld # Specific Test Rules diff --git a/tests/tcg/i386/Makefile.softmmu-target b/tests/tcg/i386/Makefile.softmmu-target index 0a4364868ce..cee342017e5 100644 --- a/tests/tcg/i386/Makefile.softmmu-target +++ b/tests/tcg/i386/Makefile.softmmu-target @@ -32,11 +32,11 @@ TESTS+=$(MULTIARCH_TESTS) .PRECIOUS: $(CRT_OBJS) %.o: $(CRT_PATH)/%.S - $(CC) $(CFLAGS) -c $< -o $@ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ # Build and link the tests %: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) memory: CFLAGS+=-DCHECK_UNALIGNED=1 diff --git a/tests/tcg/minilib/Makefile.target b/tests/tcg/minilib/Makefile.target index 3ed8077d0f9..c821d2806a9 100644 --- a/tests/tcg/minilib/Makefile.target +++ b/tests/tcg/minilib/Makefile.target @@ -18,4 +18,4 @@ MINILIB_INC=-isystem $(SYSTEM_MINILIB_SRC) .PRECIOUS: $(MINILIB_OBJS) %.o: $(SYSTEM_MINILIB_SRC)/%.c - $(CC) $(CFLAGS) -c $< -o $@ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ diff --git a/tests/tcg/xtensa/Makefile.softmmu-target b/tests/tcg/xtensa/Makefile.softmmu-target index 8212d96b81d..9530cac2ad9 100644 --- a/tests/tcg/xtensa/Makefile.softmmu-target +++ b/tests/tcg/xtensa/Makefile.softmmu-target @@ -34,9 +34,9 @@ $(XTENSA_USABLE_TESTS): linker.ld macros.inc $(CRT) Makefile.softmmu-target # special rule for common blobs %.o: %.S - $(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) -c $< -o $@ + $(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ %: %.S - $(CC) $(XTENSA_INC) $(ASFLAGS) $< -o $@ $(LDFLAGS) $(NOSTDFLAGS) $(CRT) + $(CC) $(XTENSA_INC) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(NOSTDFLAGS) $(CRT) endif -- 2.20.1
[Qemu-devel] [PATCH v1 13/42] tests/docker: move our Alpha cross compile to Buster
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
tests/docker/dockerfiles/debian-alpha-cross.docker | 7 +++
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index 7c1ff677a13..e7379f1d732 100644
--- a/tests/docker/Makefile.include
+++ b/tests/docker/Makefile.include
@@ -98,10 +98,10 @@ docker-image-debian-s390x-cross: docker-image-debian9
docker-image-debian-win32-cross: docker-image-debian9-mxe
docker-image-debian-win64-cross: docker-image-debian9-mxe
+docker-image-debian-alpha-cross: docker-image-debian10
docker-image-debian-arm64-cross: docker-image-debian10
docker-image-debian-powerpc-cross: docker-image-debian10
-docker-image-debian-alpha-cross: docker-image-debian-sid
docker-image-debian-hppa-cross: docker-image-debian-sid
docker-image-debian-m68k-cross: docker-image-debian-sid
docker-image-debian-sh4-cross: docker-image-debian-sid
diff --git a/tests/docker/dockerfiles/debian-alpha-cross.docker
b/tests/docker/dockerfiles/debian-alpha-cross.docker
index 23444342f03..74bcabfdb12 100644
--- a/tests/docker/dockerfiles/debian-alpha-cross.docker
+++ b/tests/docker/dockerfiles/debian-alpha-cross.docker
@@ -1,13 +1,12 @@
#
# Docker cross-compiler target
#
-# This docker target builds on the debian sid base image which
-# contains cross compilers for Debian "ports" targets.
+# This docker target builds on the debian Buster base image.
#
-FROM qemu:debian-sid
+FROM qemu:debian10
RUN apt update && \
DEBIAN_FRONTEND=noninteractive eatmydata \
apt install -y --no-install-recommends \
gcc-alpha-linux-gnu \
-libc6.1-dev-alpha-cross || { echo "Failed to build - see
debian-sid.docker notes"; exit 1; }
+libc6.1-dev-alpha-cross
--
2.20.1
[Qemu-devel] [PATCH v1 15/42] tests/docker: move our m68k cross compile to Buster
Now Buster is released we can stop relying on the movable feast that is Sid for our cross-compiler for building tests. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include | 2 +- tests/docker/dockerfiles/debian-m68k-cross.docker | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index ba5a624eaec..62f2733eb66 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -101,9 +101,9 @@ docker-image-debian-win64-cross: docker-image-debian9-mxe docker-image-debian-alpha-cross: docker-image-debian10 docker-image-debian-arm64-cross: docker-image-debian10 docker-image-debian-hppa-cross: docker-image-debian10 +docker-image-debian-m68k-cross: docker-image-debian10 docker-image-debian-powerpc-cross: docker-image-debian10 -docker-image-debian-m68k-cross: docker-image-debian-sid docker-image-debian-sh4-cross: docker-image-debian-sid docker-image-debian-sparc64-cross: docker-image-debian-sid docker-image-debian-mips64-cross: docker-image-debian-sid diff --git a/tests/docker/dockerfiles/debian-m68k-cross.docker b/tests/docker/dockerfiles/debian-m68k-cross.docker index 4311c9cf86d..25edc80e9a3 100644 --- a/tests/docker/dockerfiles/debian-m68k-cross.docker +++ b/tests/docker/dockerfiles/debian-m68k-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ -- 2.20.1
[Qemu-devel] [PATCH v4 65/69] target/arm: Convert T16, load (literal)
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 42 ++
target/arm/t16.decode | 4
2 files changed, 6 insertions(+), 40 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d409afd55f..4f4c77fc89 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -982,14 +982,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s,
TCGv_i32 val, \
TCGv_i32 a32, int index)\
{\
gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
-}\
-static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \
- TCGv_i32 val, \
- TCGv_i32 a32, int index, \
- ISSInfo issinfo) \
-{\
-gen_aa32_ld##SUFF(s, val, a32, index); \
-disas_set_da_iss(s, OPC, issinfo); \
}
#define DO_GEN_ST(SUFF, OPC) \
@@ -997,14 +989,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s,
TCGv_i32 val, \
TCGv_i32 a32, int index)\
{\
gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
-}\
-static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \
- TCGv_i32 val, \
- TCGv_i32 a32, int index, \
- ISSInfo issinfo) \
-{\
-gen_aa32_st##SUFF(s, val, a32, index); \
-disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \
}
static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
@@ -1053,9 +1037,7 @@ static inline void gen_aa32_st64(DisasContext *s,
TCGv_i64 val,
gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
}
-DO_GEN_LD(8s, MO_SB)
DO_GEN_LD(8u, MO_UB)
-DO_GEN_LD(16s, MO_SW)
DO_GEN_LD(16u, MO_UW)
DO_GEN_LD(32u, MO_UL)
DO_GEN_ST(8, MO_UB)
@@ -10754,11 +10736,10 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
-uint32_t val, rd;
+uint32_t val;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
-TCGv_i32 addr;
if (disas_t16(s, insn)) {
return;
@@ -10768,26 +10749,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
switch (insn >> 12) {
case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */
case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
-goto illegal_op;
-case 4:
-if (insn & (1 << 11)) {
-rd = (insn >> 8) & 7;
-/* load pc-relative. Bit 1 of PC is ignored. */
-addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4);
-tmp = tcg_temp_new_i32();
-gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
- rd | ISSIs16Bit);
-tcg_temp_free_i32(addr);
-store_reg(s, rd, tmp);
-break;
-}
-
-/*
- * - Data-processing (two low registers), in decodetree
- * - data processing extended, branch and exchange, in decodetree
- */
-goto illegal_op;
-
+case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */
case 5: /* load/store register offset, in decodetree */
case 6: /* load/store word immediate offset, in decodetree */
case 7: /* load/store byte immediate offset, in decodetree */
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 79a1d66d6c..0b4da411e0 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -113,6 +113,10 @@ LDRH_ri 10001 . ... ... @ldst_ri_2
STR_ri 10010 ... @ldst_spec_i rn=13
LDR_ri 10011 ... @ldst_spec_i rn=13
+# Load (PC-relative)
+
+LDR_ri 01001 ... @ldst_spec_i rn=15
+
# Add PC/SP (immediate)
ADR 10100 rd:3 imm=%imm8_0x4
--
2.17.1
Re: [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
On Sat, Aug 31, 2019 at 7:54 PM Bin Meng wrote: > > As of today, the QEMU 'sifive_u' machine is a special target that does > not boot the upstream OpenSBI/U-Boot firmware images built for the real > SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform > "qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced > in the OpenSBI doc as its payload, but that does not boot at all due > to various issues in current QEMU 'sifive_u' machine codes. > > This series aims to improve the emulation fidelity of sifive_u machine, > so that the upstream OpenSBI, U-Boot and kernel images built for the > SiFive HiFive Unleashed board can be used out of the box without any > special hack. > > The major changes include: > - Heterogeneous harts creation supported, so that we can create a CPU > that exactly mirrors the real hardware: 1 E51 + 4 U54. > - Implemented a PRCI model for FU540 > - Implemented an OTP model for FU540, primarily used for storing serial > number of the board > - Fixed GEM support that was seriously broken on sifive_u > - Synced device tree with upstream Linux kernel on sifive_u > > OpenSBI v0.4 image built for sifive/fu540 is included as the default > bios image for 'sifive_u' machine. > > The series is tested against OpenSBI v0.4 image for sifive/fu540 > paltform, U-Boot v2019.10-rc1 image for sifive_fu540_defconfig, > and Linux kernel v5.3-rc3 image with the following patch: > > macb: Update compatibility string for SiFive FU540-C000 [1] > > OpenSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well. > Boot Linux 64-bit defconfig image, verified that system console on > the serial 0 and ping host work pretty well. > > An OpenSBI patch [2] was sent to drop the special "qemu/sifive_u" platform > support in OpenSBI. The original plan was to get the drop patch applied > after this QEMU series is merged. However after discussion in the OpenSBI > mailing list, it seems the best option for us is to let OpenSBI continue > shipping the special "qemu/sifive_u" platform support to work with QEMU > version <= 4.1 and deprecate the support sometime in the future. A patch > will need to be sent to OpenSBI mailing list to update its document. > > v4 is now rebased on Palmer's QEMU RISC-V repo "for-master" branch. > Dropped the following v3 patch that was already done by someone else. > - riscv: sifive_u: Generate an aliases node in the device tree > - riscv: sifive_u: Support loading initramfs I'm having trouble applying this. Do you mind sharing a public git branch? Alistair > > The following v3 patch was dropped too due to a different cluster approach > suggested by Richard Henderson is used in v4: > - riscv: hart: Support heterogeneous harts population > > [1]: https://patchwork.kernel.org/patch/11050003/ > [2]: http://lists.infradead.org/pipermail/opensbi/2019-August/000335.html > > Changes in v7: > - use `s->hartid_base + idx` directly > > Changes in v6: > - use s->hartid_base directly, instead of an extra variable > - generate u cpus unconditionally (not test ms->smp.cpus > 1) > since the minimal required number of cpu is now 2, due to > this patch is reordered > - fix incorrectly indented comment lines > - remove unneeded brackets around assignment > > Changes in v5: > - new patch to change to use qemu_log_mask(LOG_GUEST_ERROR,...) instead > in various sifive models > - new patch to remove the unnecessary include of target/riscv/cpu.h > - change to use defines instead of enums > - change to use qemu_log_mask(LOG_GUEST_ERROR,...) in sifive_u_prci > - creating a 32-bit val variable and using that instead of casting > everywhere in sifive_u_prci_write() > - move all register initialization to sifive_u_prci_reset() function > - drop sifive_u_prci_create() > - s/codes that worked/code that works/g > - create sifive_u_prci block directly in the machine codes, instead > of calling sifive_u_prci_create() > - change to use defines instead of enums > - change to use qemu_log_mask(LOG_GUEST_ERROR,...) in sifive_u_otp > - creating a 32-bit val variable and using that instead of casting > everywhere in sifive_u_otp_write() > - move all register initialization to sifive_u_otp_reset() function > - drop sifive_u_otp_create() > - create sifive_u_otp block directly in the machine codes, instead > of calling sifive_u_otp_create() > - add the missing "local-mac-address" property in the ethernet node > > Changes in v4: > - remove 2 more "linux,phandle" instances in sifive_u.c and spike.c > after rebasing on Palmer's QEMU RISC-V tree > - change create_fdt() to return void in sifive_u.c too, after rebasing > on Palmer's QEMU RISC-V tree > - new patch to remove executable attribute of opensbi images > - prefix all macros/variables/functions with SIFIVE_E/sifive_e > in the sifive_e_prci driver > - new patch to add a "hartid-base" property to RISC-V hart array > - changed to create clusters for each cpu type > - prefix all macros/variables/functions with
[Qemu-devel] [PATCH v1 30/42] .travis.yml: Enable multiple caching features
From: Philippe Mathieu-Daudé Using the 'multiple caching features' means explode the YAML array, thus it eases the git workflow (it is easier to move patches around). See https://docs.travis-ci.com/user/caching#enabling-multiple-caching-features Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-Id: <20170809202712.6951-4-f4...@amsat.org> --- .travis.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 92b00927d4f..612caabc6cf 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,7 +5,8 @@ dist: xenial language: c compiler: - gcc -cache: ccache +cache: + ccache: true addons: -- 2.20.1
[Qemu-devel] [PATCH v1 11/42] tests/docker: move our arm64 cross compile to Buster
Now Buster is released we can unify our cross build images for both QEMU and tests. Signed-off-by: Alex Bennée --- tests/docker/Makefile.include| 5 ++--- .../docker/dockerfiles/debian-arm64-cross.docker | 4 ++-- .../dockerfiles/debian-buster-arm64-cross.docker | 16 tests/tcg/configure.sh | 2 +- 4 files changed, 5 insertions(+), 22 deletions(-) delete mode 100644 tests/docker/dockerfiles/debian-buster-arm64-cross.docker diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index 89881fb5f5d..48c22ae40c0 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -86,13 +86,10 @@ docker-binfmt-image-debian-%: $(DOCKER_FILES_DIR)/debian-bootstrap.docker endif # Enforce dependencies for composite images -docker-image-debian: docker-image-debian9 docker-image-debian9-mxe: docker-image-debian9 docker-image-debian-amd64: docker-image-debian9 docker-image-debian-armel-cross: docker-image-debian9 docker-image-debian-armhf-cross: docker-image-debian9 -docker-image-debian-arm64-cross: docker-image-debian9 -docker-image-debian-buster-arm64-cross: docker-image-debian10 docker-image-debian-mips-cross: docker-image-debian9 docker-image-debian-mipsel-cross: docker-image-debian9 docker-image-debian-mips64el-cross: docker-image-debian9 @@ -101,6 +98,8 @@ docker-image-debian-s390x-cross: docker-image-debian9 docker-image-debian-win32-cross: docker-image-debian9-mxe docker-image-debian-win64-cross: docker-image-debian9-mxe +docker-image-debian-arm64-cross: docker-image-debian10 + docker-image-debian-alpha-cross: docker-image-debian-sid docker-image-debian-hppa-cross: docker-image-debian-sid docker-image-debian-m68k-cross: docker-image-debian-sid diff --git a/tests/docker/dockerfiles/debian-arm64-cross.docker b/tests/docker/dockerfiles/debian-arm64-cross.docker index 6b59ef0843a..55045ff5d5a 100644 --- a/tests/docker/dockerfiles/debian-arm64-cross.docker +++ b/tests/docker/dockerfiles/debian-arm64-cross.docker @@ -1,9 +1,9 @@ # # Docker arm64 cross-compiler target # -# This docker target builds on the debian Stretch base image. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian9 +FROM qemu:debian10 # Add the foreign architecture we want and install dependencies RUN dpkg --add-architecture arm64 diff --git a/tests/docker/dockerfiles/debian-buster-arm64-cross.docker b/tests/docker/dockerfiles/debian-buster-arm64-cross.docker deleted file mode 100644 index 52787edcc2c..000 --- a/tests/docker/dockerfiles/debian-buster-arm64-cross.docker +++ /dev/null @@ -1,16 +0,0 @@ -# -# Docker arm64 cross-compiler target -# -# This docker target builds on the Debian's Buster base image. There -# are no QEMU pre-requistes so this image can only be used to build -# test cases. -# -FROM qemu:debian10 - -# Add the foreign architecture we want and install dependencies -RUN dpkg --add-architecture arm64 -RUN apt update && \ -DEBIAN_FRONTEND=noninteractive apt install -yy eatmydata && \ -DEBIAN_FRONTEND=noninteractive eatmydata \ -apt-get install -y --no-install-recommends \ -crossbuild-essential-arm64 diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 5f794b664b8..2a351a00048 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -95,7 +95,7 @@ for target in $target_list; do case $target in aarch64-*) # We don't have any bigendian build tools so we only use this for AArch64 - container_image=debian-buster-arm64-cross + container_image=debian-arm64-cross container_cross_cc=aarch64-linux-gnu-gcc ;; alpha-*) -- 2.20.1
[Qemu-devel] [PATCH v1 03/42] tests/docker: fix "cc" command to work with podman
Podman requires a little bit of additional magic to the uid mapping
which was already done for the normal RunCommand. We simplify the
logic by pushing it directly into the Docker::run method to avoid
instantiating an extra Docker() object and ensure the CC command
always runs as the current user.
Signed-off-by: Alex Bennée
---
tests/docker/docker.py | 30 +++---
tests/tcg/Makefile.include | 2 +-
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/tests/docker/docker.py b/tests/docker/docker.py
index e23209f71ee..8f391eb278b 100755
--- a/tests/docker/docker.py
+++ b/tests/docker/docker.py
@@ -318,10 +318,20 @@ class Docker(object):
return False
return checksum == _text_checksum(_dockerfile_preprocess(dockerfile))
-def run(self, cmd, keep, quiet):
+def run(self, cmd, keep, quiet, as_user=False):
label = uuid.uuid1().hex
if not keep:
self._instances.append(label)
+
+if as_user:
+uid = os.getuid()
+cmd = [ "-u", str(uid) ] + cmd
+# podman requires a bit more fiddling
+if self._command[0] == "podman":
+cmd = [ "--uidmap", "%d:0:1" % uid,
+"--uidmap", "0:1:%d" % uid,
+"--uidmap", "%d:%d:64536" % (uid + 1, uid + 1)] + cmd
+
ret = self._do_check(["run", "--label",
"com.qemu.instance.uuid=" + label] + cmd,
quiet=quiet)
@@ -364,15 +374,8 @@ class RunCommand(SubCommand):
help="Run container using the current user's uid")
def run(self, args, argv):
-if args.run_as_current_user:
-uid = os.getuid()
-argv = [ "-u", str(uid) ] + argv
-docker = Docker()
-if docker._command[0] == "podman":
-argv = [ "--uidmap", "%d:0:1" % uid,
- "--uidmap", "0:1:%d" % uid,
- "--uidmap", "%d:%d:64536" % (uid + 1, uid + 1)] + argv
-return Docker().run(argv, args.keep, quiet=args.quiet)
+return Docker().run(argv, args.keep, quiet=args.quiet,
+as_user=args.run_as_current_user)
class BuildCommand(SubCommand):
@@ -556,8 +559,6 @@ class CcCommand(SubCommand):
help="The docker image in which to run cc")
parser.add_argument("--cc", default="cc",
help="The compiler executable to call")
-parser.add_argument("--user",
-help="The user-id to run under")
parser.add_argument("--source-path", "-s", nargs="*", dest="paths",
help="""Extra paths to (ro) mount into container
for
reading sources""")
@@ -571,11 +572,10 @@ class CcCommand(SubCommand):
if args.paths:
for p in args.paths:
cmd += ["-v", "%s:%s:ro,z" % (p, p)]
-if args.user:
-cmd += ["-u", args.user]
cmd += [args.image, args.cc]
cmd += argv
-return Docker().command("run", cmd, args.quiet)
+return Docker().run(cmd, False, quiet=args.quiet,
+as_user=True)
class CheckCommand(SubCommand):
diff --git a/tests/tcg/Makefile.include b/tests/tcg/Makefile.include
index 73b5626fc5f..210f8428237 100644
--- a/tests/tcg/Makefile.include
+++ b/tests/tcg/Makefile.include
@@ -41,7 +41,7 @@ ifneq ($(DOCKER_IMAGE),)
# We also need the Docker make rules to depend on
include $(SRC_PATH)/tests/docker/Makefile.include
-DOCKER_COMPILE_CMD="$(DOCKER_SCRIPT) cc --user $(shell id -u) \
+DOCKER_COMPILE_CMD="$(DOCKER_SCRIPT) cc \
--cc $(DOCKER_CROSS_COMPILER) \
-i qemu:$(DOCKER_IMAGE) \
-s $(SRC_PATH) -- "
--
2.20.1
[Qemu-devel] [PATCH v4 55/69] target/arm: Convert T16 adjust sp (immediate)
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 15 ++-
target/arm/t16.decode | 9 +
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 73c8863134..8399a2c1f6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10765,19 +10765,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
/* misc */
op = (insn >> 8) & 0xf;
switch (op) {
-case 0:
-/*
- * 0b1011___
- * - ADD (SP plus immediate)
- * - SUB (SP minus immediate)
- */
-tmp = load_reg(s, 13);
-val = (insn & 0x7f) * 4;
-if (insn & (1 << 7))
-val = -(int32_t)val;
-tcg_gen_addi_i32(tmp, tmp, val);
-store_sp_checked(s, tmp);
-break;
+case 0: /* add/sub (sp, immediate), in decodetree */
+goto illegal_op;
case 2: /* sign/zero extend. */
ARCH(6);
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 5a570484e3..b425b86795 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -156,6 +156,15 @@ ADD_rrri0100 0100 . ...@addsub_2h
s=0
CMP_xrri0100 0101 . ...@addsub_2h s=1
MOV_rxri0100 0110 . ...@addsub_2h s=0
+# Adjust SP (immediate)
+
+%imm7_0x4 0:7 !function=times_4
+@addsub_sp_i . ... \
+_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4
+
+ADD_rri 1011 0 ... @addsub_sp_i
+SUB_rri 1011 1 ... @addsub_sp_i
+
# Branch and exchange
@branchr . rm:4 ...
--
2.17.1
[Qemu-devel] [PATCH v1 08/42] tests/docker: move DEF_TARGET_LIST setting to common.rc
We might as well not repeat ourselves. At the same time allow it to be
overridden which we will use later from docker targets.
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
tests/docker/common.rc | 4
tests/docker/test-build | 1 -
tests/docker/test-mingw | 1 -
tests/docker/test-quick | 1 -
4 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/tests/docker/common.rc b/tests/docker/common.rc
index 4011561587a..512202b0a19 100755
--- a/tests/docker/common.rc
+++ b/tests/docker/common.rc
@@ -11,6 +11,10 @@
# or (at your option) any later version. See the COPYING file in
# the top-level directory.
+# This might be set by ENV of a docker container... it is always
+# overriden by TARGET_LIST if the user sets it.
+DEF_TARGET_LIST=${DEF_TARGET_LIST:-"x86_64-softmmu,aarch64-softmmu"}
+
requires()
{
for c in $@; do
diff --git a/tests/docker/test-build b/tests/docker/test-build
index 22766cfacc0..2b2a7832f15 100755
--- a/tests/docker/test-build
+++ b/tests/docker/test-build
@@ -15,7 +15,6 @@
cd "$BUILD_DIR"
-DEF_TARGET_LIST="x86_64-softmmu,aarch64-softmmu"
TARGET_LIST=${TARGET_LIST:-$DEF_TARGET_LIST} \
build_qemu
install_qemu
diff --git a/tests/docker/test-mingw b/tests/docker/test-mingw
index fdb1c2c879d..c30eb654eb7 100755
--- a/tests/docker/test-mingw
+++ b/tests/docker/test-mingw
@@ -16,7 +16,6 @@
requires mingw dtc
cd "$BUILD_DIR"
-DEF_TARGET_LIST="x86_64-softmmu,aarch64-softmmu"
for prefix in x86_64-w64-mingw32- i686-w64-mingw32-; do
TARGET_LIST=${TARGET_LIST:-$DEF_TARGET_LIST} \
diff --git a/tests/docker/test-quick b/tests/docker/test-quick
index eee59c55fba..feee44b2476 100755
--- a/tests/docker/test-quick
+++ b/tests/docker/test-quick
@@ -15,7 +15,6 @@
cd "$BUILD_DIR"
-DEF_TARGET_LIST="x86_64-softmmu,aarch64-softmmu"
TARGET_LIST=${TARGET_LIST:-$DEF_TARGET_LIST} \
build_qemu
check_qemu
--
2.20.1
[Qemu-devel] [PATCH v1 07/42] tests/tcg: add .gitignore for in source builds
This hides the new build artefacts from the re-organised TCG tests when you are doing an in-source build. Signed-off-by: Alex Bennée --- tests/tcg/.gitignore | 5 + 1 file changed, 5 insertions(+) create mode 100644 tests/tcg/.gitignore diff --git a/tests/tcg/.gitignore b/tests/tcg/.gitignore new file mode 100644 index 000..84d7541b286 --- /dev/null +++ b/tests/tcg/.gitignore @@ -0,0 +1,5 @@ +# These are build artefacts which only appear when you are doing +# builds directly in the source tree. +config-*.mak +*-softmmu/ +*-linux-user/ -- 2.20.1
[Qemu-devel] [PATCH v4 50/69] target/arm: Convert T16 load/store multiple
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 48 --
target/arm/t16.decode | 8 +++
2 files changed, 17 insertions(+), 39 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d8a4c7bf99..f9d4b619fa 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10092,6 +10092,14 @@ static bool trans_LDM_t32(DisasContext *s,
arg_ldst_block *a)
return do_ldm(s, a, 2);
}
+static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
+{
+/* Writeback is conditional on the base register not being loaded. */
+a->w = !(a->list & (1 << a->rn));
+/* BitCount(list) < 1 is UNPREDICTABLE */
+return do_ldm(s, a, 1);
+}
+
/*
* Branch, branch with link
*/
@@ -10869,6 +10877,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
case 8: /* load/store halfword immediate offset, in decodetree */
case 9: /* load/store from stack, in decodetree */
case 10: /* add PC/SP (immediate), in decodetree */
+case 12: /* load/store multiple, in decodetree */
goto illegal_op;
case 11:
@@ -11092,45 +11101,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
}
break;
-case 12:
-{
-/* load/store multiple */
-TCGv_i32 loaded_var = NULL;
-rn = (insn >> 8) & 0x7;
-addr = load_reg(s, rn);
-for (i = 0; i < 8; i++) {
-if (insn & (1 << i)) {
-if (insn & (1 << 11)) {
-/* load */
-tmp = tcg_temp_new_i32();
-gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
-if (i == rn) {
-loaded_var = tmp;
-} else {
-store_reg(s, i, tmp);
-}
-} else {
-/* store */
-tmp = load_reg(s, i);
-gen_aa32_st32(s, tmp, addr, get_mem_index(s));
-tcg_temp_free_i32(tmp);
-}
-/* advance to the next address */
-tcg_gen_addi_i32(addr, addr, 4);
-}
-}
-if ((insn & (1 << rn)) == 0) {
-/* base reg not in list: base register writeback */
-store_reg(s, rn, addr);
-} else {
-/* base reg in list: if load, complete it now */
-if (insn & (1 << 11)) {
-store_reg(s, rn, loaded_var);
-}
-tcg_temp_free_i32(addr);
-}
-break;
-}
case 13:
/* conditional branch or swi */
cond = (insn >> 8) & 0xf;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 71b3e8f02e..a7a437f930 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -26,6 +26,7 @@
!extern rd imm
_rr !extern p w u rn rt rm shimm shtype
_ri !extern p w u rn rt imm
+_block !extern rn i b u w list
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -109,3 +110,10 @@ LDR_ri 10011 ...
@ldst_spec_i rn=13
ADR 10100 rd:3 imm=%imm8_0x4
ADD_rri 10101 rd:3 \
_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
+
+# Load/store multiple
+
+@ldstm . rn:3 list:8 _block i=1 b=0 u=0 w=1
+
+STM 11000 ... @ldstm
+LDM_t16 11001 ... @ldstm
--
2.17.1
[Qemu-devel] [PATCH v4 68/69] target/arm: Clean up disas_thumb_insn
Now that everything is converted, remove the rest of
the legacy decode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 27 ++-
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a99a5c2eef..2412dde631 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10770,32 +10770,9 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
-if (disas_t16(s, insn)) {
-return;
+if (!disas_t16(s, insn)) {
+unallocated_encoding(s);
}
-/* fall back to legacy decoder */
-
-switch (insn >> 12) {
-case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */
-case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
-case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */
-case 5: /* load/store register offset, in decodetree */
-case 6: /* load/store word immediate offset, in decodetree */
-case 7: /* load/store byte immediate offset, in decodetree */
-case 8: /* load/store halfword immediate offset, in decodetree */
-case 9: /* load/store from stack, in decodetree */
-case 10: /* add PC/SP (immediate), in decodetree */
-case 11: /* misc, in decodetree */
-case 12: /* load/store multiple, in decodetree */
-case 13: /* conditional branch or swi, in decodetree */
-case 14:
-case 15:
-/* branches, in decodetree */
-goto illegal_op;
-}
-return;
-illegal_op:
-unallocated_encoding(s);
}
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
--
2.17.1
[Qemu-devel] [PATCH v1 02/42] configure: clean-up container cross compile detect
The introduction of podman support inadvertently broke configure's
detect of the container support as the configure probe didn't specify
an engine type. To fix this in docker.py:
- only (re)set USE_ENGINE if --engine is specified
- enhance the output so docker is no longer just yes
In the configure script we can at least start cleaning up the
detecting and naming of variables. To avoid too much churn the
conversion of the various make DOCKER_foo variables has been left for
future clean-ups.
Signed-off-by: Alex Bennée
---
configure | 10 +-
tests/docker/docker.py | 7 ---
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/configure b/configure
index 95134c0180b..94845fc5101 100755
--- a/configure
+++ b/configure
@@ -495,7 +495,7 @@ qed="yes"
parallels="yes"
sheepdog="yes"
libxml2=""
-docker="no"
+container="no"
debug_mutex="no"
libpmem=""
default_devices="yes"
@@ -5894,14 +5894,14 @@ EOF
fi
##
-# Docker and cross-compiler support
+# Container based cross-compiler support
#
# This is specifically for building test
# cases for foreign architectures, not
# cross-compiling QEMU itself.
-if has "docker"; then
-docker=$($python $source_path/tests/docker/docker.py probe)
+if has "docker" || has "podman"; then
+container=$($python $source_path/tests/docker/docker.py probe)
fi
##
@@ -6474,7 +6474,7 @@ echo "qed support $qed"
echo "parallels support $parallels"
echo "sheepdog support $sheepdog"
echo "capstone $capstone"
-echo "docker$docker"
+echo "container support $container"
echo "libpmem support $libpmem"
echo "libudev $libudev"
echo "default devices $default_devices"
diff --git a/tests/docker/docker.py b/tests/docker/docker.py
index 4bba29e104e..e23209f71ee 100755
--- a/tests/docker/docker.py
+++ b/tests/docker/docker.py
@@ -536,9 +536,9 @@ class ProbeCommand(SubCommand):
try:
docker = Docker()
if docker._command[0] == "docker":
-print("yes")
+print("docker")
elif docker._command[0] == "sudo":
-print("sudo")
+print("sudo docker")
elif docker._command[0] == "podman":
print("podman")
except Exception:
@@ -651,7 +651,8 @@ def main():
cmd.args(subp)
subp.set_defaults(cmdobj=cmd)
args, argv = parser.parse_known_args()
-USE_ENGINE = args.engine
+if args.engine:
+USE_ENGINE = args.engine
return args.cmdobj.run(args, argv)
--
2.20.1
[Qemu-devel] [PATCH v4 49/69] target/arm: Convert T16 add pc/sp (immediate)
Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +--- target/arm/t16.decode | 7 +++ 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4ae73d1c92..d8a4c7bf99 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10868,19 +10868,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 7: /* load/store byte immediate offset, in decodetree */ case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ +case 10: /* add PC/SP (immediate), in decodetree */ goto illegal_op; -case 10: -/* - * 0b1010___ - * - Add PC/SP (immediate) - */ -rd = (insn >> 8) & 7; -val = (insn & 0xff) * 4; -tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val); -store_reg(s, rd, tmp); -break; - case 11: /* misc */ op = (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 1cf79789ac..71b3e8f02e 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ _rrr_shr !extern s rn rd rm rs shty _rri_rot !extern s rn rd imm rot _ !extern s rd rn rm ra + !extern rd imm _rr !extern p w u rn rt rm shimm shtype _ri !extern p w u rn rt imm @@ -102,3 +103,9 @@ LDRH_ri 10001 . ... ... @ldst_ri_2 STR_ri 10010 ... @ldst_spec_i rn=13 LDR_ri 10011 ... @ldst_spec_i rn=13 + +# Add PC/SP (immediate) + +ADR 10100 rd:3 imm=%imm8_0x4 +ADD_rri 10101 rd:3 \ +_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP -- 2.17.1
[Qemu-devel] [PATCH v4 66/69] target/arm: Convert T16, Unconditional branch
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 9 ++---
target/arm/t16.decode | 6 ++
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4f4c77fc89..3238ccbf1e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10736,7 +10736,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
-uint32_t val;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -10780,12 +10779,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
gen_bx(s, tmp);
break;
}
-/* unconditional branch */
-val = read_pc(s);
-offset = ((int32_t)insn << 21) >> 21;
-val += offset << 1;
-gen_jmp(s, val);
-break;
+/* unconditional branch, in decodetree */
+goto illegal_op;
case 15:
/* thumb_insn_is_16bit() ensures we can't get here for
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 0b4da411e0..a4c89dba61 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -266,3 +266,9 @@ LDM_t16 1011 110 . \
SVC 1101 imm:8
B_cond_thumb 1101 cond:4 imm=%imm8_0x2
}
+
+# Unconditional Branch
+
+%imm11_0x2 0:s11 !function=times_2
+
+B 11100 ...imm=%imm11_0x2
--
2.17.1
[Qemu-devel] [PATCH v4 48/69] target/arm: Convert T16 load/store (immediate offset)
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 94 +++---
target/arm/t16.decode | 33 +++
2 files changed, 38 insertions(+), 89 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 789abe9b87..4ae73d1c92 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10863,97 +10863,13 @@ static void disas_thumb_insn(DisasContext *s,
uint32_t insn)
*/
goto illegal_op;
-case 5:
-/* load/store register offset, in decodetree */
+case 5: /* load/store register offset, in decodetree */
+case 6: /* load/store word immediate offset, in decodetree */
+case 7: /* load/store byte immediate offset, in decodetree */
+case 8: /* load/store halfword immediate offset, in decodetree */
+case 9: /* load/store from stack, in decodetree */
goto illegal_op;
-case 6:
-/* load/store word immediate offset */
-rd = insn & 7;
-rn = (insn >> 3) & 7;
-addr = load_reg(s, rn);
-val = (insn >> 4) & 0x7c;
-tcg_gen_addi_i32(addr, addr, val);
-
-if (insn & (1 << 11)) {
-/* load */
-tmp = tcg_temp_new_i32();
-gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
-store_reg(s, rd, tmp);
-} else {
-/* store */
-tmp = load_reg(s, rd);
-gen_aa32_st32(s, tmp, addr, get_mem_index(s));
-tcg_temp_free_i32(tmp);
-}
-tcg_temp_free_i32(addr);
-break;
-
-case 7:
-/* load/store byte immediate offset */
-rd = insn & 7;
-rn = (insn >> 3) & 7;
-addr = load_reg(s, rn);
-val = (insn >> 6) & 0x1f;
-tcg_gen_addi_i32(addr, addr, val);
-
-if (insn & (1 << 11)) {
-/* load */
-tmp = tcg_temp_new_i32();
-gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
-store_reg(s, rd, tmp);
-} else {
-/* store */
-tmp = load_reg(s, rd);
-gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
-tcg_temp_free_i32(tmp);
-}
-tcg_temp_free_i32(addr);
-break;
-
-case 8:
-/* load/store halfword immediate offset */
-rd = insn & 7;
-rn = (insn >> 3) & 7;
-addr = load_reg(s, rn);
-val = (insn >> 5) & 0x3e;
-tcg_gen_addi_i32(addr, addr, val);
-
-if (insn & (1 << 11)) {
-/* load */
-tmp = tcg_temp_new_i32();
-gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd |
ISSIs16Bit);
-store_reg(s, rd, tmp);
-} else {
-/* store */
-tmp = load_reg(s, rd);
-gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
-tcg_temp_free_i32(tmp);
-}
-tcg_temp_free_i32(addr);
-break;
-
-case 9:
-/* load/store from stack */
-rd = (insn >> 8) & 7;
-addr = load_reg(s, 13);
-val = (insn & 0xff) * 4;
-tcg_gen_addi_i32(addr, addr, val);
-
-if (insn & (1 << 11)) {
-/* load */
-tmp = tcg_temp_new_i32();
-gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd |
ISSIs16Bit);
-store_reg(s, rd, tmp);
-} else {
-/* store */
-tmp = load_reg(s, rd);
-gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
-tcg_temp_free_i32(tmp);
-}
-tcg_temp_free_i32(addr);
-break;
-
case 10:
/*
* 0b1010___
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 83fe4363c7..1cf79789ac 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -24,6 +24,7 @@
_rri_rot !extern s rn rd imm rot
_ !extern s rd rn rm ra
_rr !extern p w u rn rt rm shimm shtype
+_ri !extern p w u rn rt imm
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr
LDRH_rr 0101 101 ... ... ... @ldst_rr
LDRB_rr 0101 110 ... ... ... @ldst_rr
LDRSH_rr 0101 111 ... ... ... @ldst_rr
+
+# Load/store word/byte (immediate offset)
+
+%imm5_6x4 6:5 !function=times_4
+
+@ldst_ri_1 . imm:5 rn:3 rt:3 \
+_ri p=1 w=0 u=1
+@ldst_ri_4 . . rn:3 rt:3 \
+_ri p=1 w=0 u=1 imm=%imm5_6x4
+
+STR_ri 01100 . ... ... @ldst_ri_4
+LDR_ri 01101 . ... ... @ldst_ri_4
+STRB_ri 01110 . ... ... @ldst_ri_1
+LDRB_ri 0 . ... ... @ldst_ri_1
+
+# Load/store halfword (immediate offset)
+
+%imm5_6x2 6:5
[Qemu-devel] [PATCH v4 62/69] target/arm: Convert T16, Conditional branches, Supervisor call
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 26 +++---
target/arm/t16.decode | 12
2 files changed, 15 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ed52018c17..a4844992d5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10721,7 +10721,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
-uint32_t val, op, rm, rd, shift, cond;
+uint32_t val, op, rm, rd, shift;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -10860,28 +10860,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
}
break;
-case 13:
-/* conditional branch or swi */
-cond = (insn >> 8) & 0xf;
-if (cond == 0xe)
-goto undef;
-
-if (cond == 0xf) {
-/* swi */
-gen_set_pc_im(s, s->base.pc_next);
-s->svc_imm = extract32(insn, 0, 8);
-s->base.is_jmp = DISAS_SWI;
-break;
-}
-/* generate a conditional jump to next instruction */
-arm_skip_unless(s, cond);
-
-/* jump to the offset */
-val = read_pc(s);
-offset = ((int32_t)insn << 24) >> 24;
-val += offset << 1;
-gen_jmp(s, val);
-break;
+case 13: /* conditional branch or swi, in decodetree */
+goto illegal_op;
case 14:
if (insn & (1 << 11)) {
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 55fadce223..cbc64f4e48 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -28,11 +28,13 @@
!extern rd rm
!extern rd imm
!extern rm
+ !extern imm
_rr !extern p w u rn rt rm shimm shtype
_ri !extern p w u rn rt imm
_block !extern rn i b u w list
!extern E
!extern mode imod M A I F
+ !extern cond imm
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -231,3 +233,13 @@ STM 1011 010 . \
_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
LDM_t16 1011 110 . \
_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
+
+# Conditional branches, Supervisor call
+
+%imm8_0x2 0:s8 !function=times_2
+
+{
+ UDF 1101 1110
+ SVC 1101 imm:8
+ B_cond_thumb 1101 cond:4 imm=%imm8_0x2
+}
--
2.17.1
