This method is used to determine the name of the irq backend's node in the
device tree, so that we can find its phandle (after SLOF may have modified
it from the phandle we initially gave it).
But, in the two cases the only difference between the node name is the
presence of a unit address. Searc
There are a number of ics_simple_*() functions that aren't actually
specific to TYPE_XICS_SIMPLE at all, and are equally valid on
TYPE_XICS_BASE. Rename them to ics_*() accordingly.
Signed-off-by: David Gibson
Reviewed-by: Cédric Le Goater
Reviewed-by: Greg Kurz
---
hw/intc/trace-events | 6
Currently spapr_qirq() used to find the qemu_irq for an spapr global irq
number, redirects through the SpaprIrq::qirq method. But the array of
qemu_irqs is allocated in the PAPR layer, not the backends, and so the
method implementations all return the same thing, just differing in the
preliminary
Every caller of spapr_vio_qirq() immediately calls qemu_irq_pulse() with
the result, so we might as well just fold that into the helper.
Signed-off-by: David Gibson
---
hw/char/spapr_vty.c| 3 +--
hw/net/spapr_llan.c| 3 +--
hw/ppc/spapr_vio.c | 3 +--
include/hw/ppc/spap
Currently TYPE_XICS_BASE and TYPE_XICS_SIMPLE have their own reset methods,
using the standard technique for having the subtype call the supertype's
methods before doing its own thing.
But TYPE_XICS_SIMPLE is the only subtype of TYPE_XICS_BASE ever
instantiated, so there's no point having the spli
This is a first batch of a number of cleanups to the handling of IRQs
in spapr. It includes some cleanups to both the XICS and XIVE
interrupt controller backends, as well as more to the common spapr irq
handling infrastructure.
These are first steps towards even more cleanups that should make the
We create a subtype of TYPE_ICS specifically for sPAPR. For now all this
does is move the setup of the PAPR specific hcalls and RTAS calls to
the realize() function for this, rather than requiring the PAPR code to
explicitly call xics_spapr_init(). In future it will have some more
function.
Sign
Both the XICS and XIVE interrupt backends have a "nr-irqs" property, but
it means slightly different things. For XICS (or, strictly, the ICS) it
indicates the number of "real" external IRQs. Those start at XICS_IRQ_BASE
(0x1000) and don't include the special IPI vector. For XIVE, however, it
inc
Currently ics_reject(), ics_resend() and ics_eoi() indirect through
class methods. But there's only one implementation of each method,
the one in TYPE_ICS_SIMPLE. TYPE_ICS_BASE has no implementation, but
it's never instantiated, and has no other subtypes.
So clean up by eliminating the method an
No point having a two-line helper that's used exactly once, and not likely
to be used anywhere else in future.
Signed-off-by: David Gibson
---
hw/ppc/spapr_pci.c | 3 ++-
include/hw/pci-host/spapr.h | 7 ---
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/spapr
Interface instances should never be directly dereferenced. So, the common
practice is to make them incomplete types to make sure no-one does that.
XICSFrabric, however, had a dummy type which is less safe.
Signed-off-by: David Gibson
---
include/hw/ppc/xics.h | 4 +---
1 file changed, 1 inserti
TYPE_ICS_SIMPLE is the only subtype of TYPE_ICS_BASE that's ever
instantiated, and the only one we're ever likely to want. The
existence of different classes is just a hang over from when we
(misguidedly) had separate subtypes for the KVM and non-KVM version of
the device.
So, collapse the two cl
Eric Blake writes:
> On 9/24/19 8:28 AM, Markus Armbruster wrote:
>> We track source locations with a dict of the form
>>
>> {'file': FNAME, 'line': LINENO, parent': PARENT}
>>
>> where PARENT is None for the main file, and the include directive's
>> source location for included files.
>>
On Wed, 25 Sep 2019 11:31:30 +0530
Aravinda Prasad wrote:
>
>
> On Wednesday 25 September 2019 07:00 AM, David Gibson wrote:
> > On Wed, Sep 18, 2019 at 01:42:34PM +0530, Aravinda Prasad wrote:
> >> Upon a machine check exception (MCE) in a guest address space,
> >> KVM causes a guest exit to e
Markus Armbruster writes:
> Eric Blake writes:
>
>> On 9/24/19 8:28 AM, Markus Armbruster wrote:
>>> Split check_flags() off check_keys() and have check_exprs() call it
>>> later, so its error messages gain an "in definition" line. Tweak the
>>> error messages.
>>>
>>> Checking values in a fun
On Wednesday 25 September 2019 07:09 AM, David Gibson wrote:
> On Wed, Sep 18, 2019 at 01:42:51PM +0530, Aravinda Prasad wrote:
>> This patch includes migration support for machine check
>> handling. Especially this patch blocks VM migration
>> requests until the machine check error handling is
Philippe Mathieu-Daudé writes:
> On 9/24/19 2:44 PM, Sergio Lopez wrote:
>> qboot is a minimalist x86 firmware for booting Linux kernels. It does
>> the mininum amount of work required for the task, and it's able to
>> boot both PVH images and bzImages without relying on option roms.
>>
>> This
On Wednesday 25 September 2019 07:03 AM, David Gibson wrote:
> On Wed, Sep 18, 2019 at 01:42:43PM +0530, Aravinda Prasad wrote:
>> This patch adds support in QEMU to handle "ibm,nmi-register"
>> and "ibm,nmi-interlock" RTAS calls.
>>
>> The machine check notification address is saved when the
>>
On 25/09/2019 03:46, David Gibson wrote:
> On Tue, Sep 24, 2019 at 04:06:02PM +0200, Cédric Le Goater wrote:
>> On 24/09/2019 13:41, David Gibson wrote:
>>> On Tue, Sep 24, 2019 at 07:31:44AM +0200, Cédric Le Goater wrote:
On 24/09/2019 06:59, David Gibson wrote:
> TYPE_ICS_SIMPLE is the o
On Wednesday 25 September 2019 07:00 AM, David Gibson wrote:
> On Wed, Sep 18, 2019 at 01:42:34PM +0530, Aravinda Prasad wrote:
>> Upon a machine check exception (MCE) in a guest address space,
>> KVM causes a guest exit to enable QEMU to build and pass the
>> error to the guest in the PAPR defi
Philippe Mathieu-Daudé writes:
> Hi Sergio,
>
> On 9/24/19 2:44 PM, Sergio Lopez wrote:
>> Extract PVH related functions from pc.c, and put them in pvh.c, so
>> they can be shared with other components.
>>
>> Signed-off-by: Sergio Lopez
>> ---
>> hw/i386/Makefile.objs | 1 +
>> hw/i386/pc.c
Michael S. Tsirkin writes:
> On Tue, Sep 24, 2019 at 02:44:33PM +0200, Sergio Lopez wrote:
>> +static void microvm_fix_kernel_cmdline(MachineState *machine)
>> +{
>> +X86MachineState *x86ms = X86_MACHINE(machine);
>> +BusState *bus;
>> +BusChild *kid;
>> +char *cmdline;
>> +
>> +
OK, thank you all :)
Jason Wang writes:
> On 2019/9/24 下午11:35, Philippe Mathieu-Daudé wrote:
>> Hi Fan,
>>
>> you forgot to Cc the maintainers (doing that for you):
>>
>> ./scripts/get_maintainer.pl -f net/colo-compare.c
>> Zhang Chen (supporter:COLO Proxy)
>> Li Zhijian (supporter:COLO Proxy
Paolo Bonzini writes:
> On 24/09/19 14:44, Sergio Lopez wrote:
>> microvm.option-roms=bool (Set off to disable loading option ROMs)
>
> Please make this x-option-roms
OK.
>> microvm.isa-serial=bool (Set off to disable the instantiation an ISA serial
>> port)
>> microvm.rtc=bool (Set off to di
Peter Maydell writes:
> On Tue, 24 Sep 2019 at 14:25, Sergio Lopez wrote:
>>
>> Microvm is a machine type inspired by both NEMU and Firecracker, and
>> constructed after the machine model implemented by the latter.
>>
>> It's main purpose is providing users a minimalist machine type free
>> fro
Alex, thank you for these hints. Let me add one more:
docs/devel/testing.rst section "Docker based tests".
Does it contain your hints already? If not, it may need an update.
Paolo Bonzini writes:
> On 24/09/19 14:44, Sergio Lopez wrote:
>> +Microvm is a machine type inspired by both NEMU and Firecracker, and
>> +constructed after the machine model implemented by the latter.
>
> I would say it's inspired by Firecracker only. The NEMU virt machine
> had virtio-pci an
On Wednesday 25 September 2019 06:42 AM, David Gibson wrote:
> On Wed, Sep 18, 2019 at 01:42:17PM +0530, Aravinda Prasad wrote:
>> Introduce the KVM capability KVM_CAP_PPC_FWNMI so that
>> the KVM causes guest exit with NMI as exit reason
>> when it encounters a machine check exception on the
>>
John Snow writes:
> Signed-off-by: John Snow
> ---
> qemu-options.hx | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/qemu-options.hx b/qemu-options.hx
> index 2a04ca6ac5..629a7b1186 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx
> @@ -1192,7 +1192,7 @@ Instead o
On Wed, Sep 25, 2019 at 12:49 PM wrote:
>
> From: Guo Ren
>
nits: the title is probably better to be rephrased to: Ignore reserved
bits when calculating PPN for RV64
> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> need to ignore them. They can not be a part of ppn.
On Tue, Sep 24, 2019 at 9:48 PM wrote:
>
> From: Guo Ren
>
> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> need to ignore them. They can not be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>4.4 Sv39: Page-Based 39-bit
Hi,
> +microvm.kernel-cmdline=bool (Set off to disable adding virtio-mmio devices
> to the kernel cmdline)
Hmm, is that the long-term plan? IMO the virtio-mmio devices should be
discoverable somehow. ACPI, or device-tree, or fw_cfg, or ...
> +As no current FW is able to boot from a block de
From: Guo Ren
Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They can not be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit
On 2019/9/24 下午11:35, Philippe Mathieu-Daudé wrote:
> Hi Fan,
>
> you forgot to Cc the maintainers (doing that for you):
>
> ./scripts/get_maintainer.pl -f net/colo-compare.c
> Zhang Chen (supporter:COLO Proxy)
> Li Zhijian (supporter:COLO Proxy)
> Jason Wang (maintainer:Network device ba...)
On 2019/9/25 上午12:20, Adrian Moreno wrote:
> That way the state can be correctly restored when the device is opened
> again. This might happen if the backend is restarted.
>
> Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1738768
> Reported-by: Pei Zhang
> Fixes: 6ab79a20af3a (do not call
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Tuesday, September 24, 2019 7:35 PM
> To: Anup Patel ; Peter Maydell
> ; Palmer Dabbelt ; Alistair
> Francis ; Sagar Karandikar
> ; Bastian Koppelmann paderborn.de>
> Cc: Atish Patra ; qemu-ri...@nongnu.org; qemu-
> de...@nongn
On 2019/9/24 上午10:02, Tian, Kevin wrote:
From: Jason Wang [mailto:jasow...@redhat.com]
Sent: Friday, September 20, 2019 9:19 AM
On 2019/9/20 上午6:54, Tian, Kevin wrote:
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Thursday, September 19, 2019 7:14 PM
On 19/09/19 09:16, Tian, Kevin w
On Tue, Sep 24, 2019 at 10:47:51AM -0400, Igor Mammedov wrote:
> s390 was trying to solve limited KVM memslot size issue by abusing
> memory_region_allocate_system_memory(), which breaks API contract
> where the function might be called only once.
>
> Beside an invalid use of API, the approach als
On Tue, Sep 24, 2019 at 10:47:50AM -0400, Igor Mammedov wrote:
[...]
> @@ -2877,6 +2912,7 @@ static bool kvm_accel_has_memory(MachineState *ms,
> AddressSpace *as,
>
> for (i = 0; i < kvm->nr_as; ++i) {
> if (kvm->as[i].as == as && kvm->as[i].ml) {
> +size = MIN(kvm_m
On Tue, Sep 24, 2019 at 04:06:02PM +0200, Cédric Le Goater wrote:
> On 24/09/2019 13:41, David Gibson wrote:
> > On Tue, Sep 24, 2019 at 07:31:44AM +0200, Cédric Le Goater wrote:
> >> On 24/09/2019 06:59, David Gibson wrote:
> >>> TYPE_ICS_SIMPLE is the only subtype of TYPE_ICS_BASE that's ever
> >
On Wed, Sep 18, 2019 at 01:42:34PM +0530, Aravinda Prasad wrote:
> Upon a machine check exception (MCE) in a guest address space,
> KVM causes a guest exit to enable QEMU to build and pass the
> error to the guest in the PAPR defined rtas error log format.
>
> This patch builds the rtas error log,
On Wed, Sep 18, 2019 at 01:42:17PM +0530, Aravinda Prasad wrote:
> Introduce the KVM capability KVM_CAP_PPC_FWNMI so that
> the KVM causes guest exit with NMI as exit reason
> when it encounters a machine check exception on the
> address belonging to a guest. Without this capability
> enabled, KVM
On Wed, Sep 18, 2019 at 01:42:43PM +0530, Aravinda Prasad wrote:
> This patch adds support in QEMU to handle "ibm,nmi-register"
> and "ibm,nmi-interlock" RTAS calls.
>
> The machine check notification address is saved when the
> OS issues "ibm,nmi-register" RTAS call.
>
> This patch also handles
On Wed, Sep 18, 2019 at 01:42:51PM +0530, Aravinda Prasad wrote:
> This patch includes migration support for machine check
> handling. Especially this patch blocks VM migration
> requests until the machine check error handling is
> complete as these errors are specific to the source
> hardware and
On 9/24/19 6:01 PM, John Snow wrote:
> This parameter has been deprecated since 2.12.0 and is eligible for
> removal. Remove this parameter as it is actually completely ignored;
> let's not give false hope.
>
> Signed-off-by: John Snow
> ---
> qemu-deprecated.texi | 20 +++-
> qa
Patchew URL: https://patchew.org/QEMU/20190924123334.30645-1-arm...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190924123334.30645-1-arm...@redhat.com
Subject: [PULL 00/37] QAPI patches for 2019-09-24
On Tue, Sep 24, 2019 at 4:35 PM Alistair Francis wrote:
>
> On Tue, Sep 24, 2019 at 1:04 PM Palmer Dabbelt wrote:
> >
> > On Tue, 24 Sep 2019 11:29:25 PDT (-0700), alistai...@gmail.com wrote:
> > > On Mon, Jun 24, 2019 at 11:21 AM Joel Sing wrote:
> > >>
> > >> On 19-06-17 16:52:44, Richard Hend
在 2019/9/25 上午8:21, Alistair Francis 写道:
On Tue, Sep 24, 2019 at 5:13 PM Guo Ren wrote:
在 2019年9月25日，上午7:33，Alistair Francis 写道：
On Tue, Sep 24, 2019 at 12:58 AM wrote:
From: Guo Ren
Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They can
On Tue, Sep 24, 2019 at 2:32 AM Philippe Mathieu-Daudé
wrote:
>
> On 9/23/19 11:46 PM, Peter Maydell wrote:
> > On Fri, 20 Sep 2019 at 23:23, Alistair Francis wrote:
> >> On Thu, Sep 19, 2019 at 10:15 PM Bin Meng wrote:
> >>> I don't think we should mirror what is used on ARM virt board to
> >>>
On Mon, Sep 23, 2019 at 2:46 PM Peter Maydell wrote:
>
> On Fri, 20 Sep 2019 at 23:23, Alistair Francis wrote:
> > On Thu, Sep 19, 2019 at 10:15 PM Bin Meng wrote:
> > > I don't think we should mirror what is used on ARM virt board to
> > > create 2 flash for sifive_u. For ARM virt, there are 2
> 在 2019年9月25日，上午7:33，Alistair Francis 写道：
>
> On Tue, Sep 24, 2019 at 12:58 AM wrote:
>>
>> From: Guo Ren
>>
>> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
>> need to ignore them. They can not be a part of ppn.
>>
>> 1: The RISC-V Instruction Set Manual, Volum
On Tue, Sep 24, 2019 at 5:13 PM Guo Ren wrote:
>
>
> > 在 2019年9月25日，上午7:33，Alistair Francis 写道：
> >
> > On Tue, Sep 24, 2019 at 12:58 AM wrote:
> >>
> >> From: Guo Ren
> >>
> >> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> >> need to ignore them. They can not be a
On Tue, Sep 24, 2019 at 11:02:08AM +0100, Dr. David Alan Gilbert wrote:
>* Wei Yang (richardw.y...@linux.intel.com) wrote:
>> All pages, either partially sent or partially dirty, will be discarded in
>> postcopy_send_discard_bm_ram(), since we update the unsentmap to be
>> unsentmap = unsentmap | d
From: John Snow
debian-sid is listed as a partial image, so we cannot run tests against it.
Since it isn't used by any other testable image, remove it for now as it
is prone to bitrot.
Signed-off-by: John Snow
Message-Id: <20190923181140.7235-6-js...@redhat.com>
Signed-off-by: Alex Bennée
---
Richard Henderson writes:
> It does not require going through the whole I/O path
> in order to discard a write.
>
> Reviewed-by: David Hildenbrand
> Signed-off-by: Richard Henderson
> ---
> include/exec/cpu-all.h| 5 -
> include/exec/cpu-common.h | 1 -
> accel/tcg/cputlb.c
I'm going to be honest, here. There's actually no real reason to remove
this now, but we could, so I'm going to.
Also, in terms of the API serving as documentation, it's nicer to not
pretend this is an option that does anything, so out it goes.
This will serve as a little smoke test to see what h
Signed-off-by: John Snow
---
qemu-options.hx | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 2a04ca6ac5..629a7b1186 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1192,7 +1192,7 @@ Instead of @option{-fda}, @option{-fdb}, you can
This is broadly similar to the existing fcvt test for ARM but using
the generic float testing framework. We should be able to pare down
the ARM fcvt test case to purely half-precision with or without the
Alt HP provision.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
tests/tcg/a
On 9/24/19 2:05 PM, Mark Cave-Ayland wrote:
> With the full patchset applied you'll see that get_dfp64() and friends are
> in exactly the same form you show above, and if I swap the arguments then
> the compiler does actually complain, although somewhat cryptically.
Oh, good. I'll finish reading t
On Tue, Sep 24, 2019 at 1:04 PM Palmer Dabbelt wrote:
>
> On Tue, 24 Sep 2019 11:29:25 PDT (-0700), alistai...@gmail.com wrote:
> > On Mon, Jun 24, 2019 at 11:21 AM Joel Sing wrote:
> >>
> >> On 19-06-17 16:52:44, Richard Henderson wrote:
> >> > On 6/16/19 12:19 PM, Joel Sing wrote:
> >> > > +
On Tue, Sep 24, 2019 at 12:58 AM wrote:
>
> From: Guo Ren
>
> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> need to ignore them. They can not be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>4.4 Sv39: Page-Based 39-bi
Patchew URL:
https://patchew.org/QEMU/95b2f9d76104ee09b43159528b35b96eb01bbd8c.1569329826.git.tgole...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id:
95b2f9d76104ee09b43159528b35b96eb01bbd8c.1569329826.git
On Tue, 24 Sep 2019 10:25:15 +0200
Eric Auger wrote:
> This series allows the memory_region_register_iommu_notifier()
> to fail. As of now, when a MAP notifier is attempted to be
> registered along with SMMUv3 or AMD IOMMU, we exit in the IOMMU
> MR notify_flag_changed() callback.
>
> In case of
On 9/24/19 8:35 AM, Mark Cave-Ayland wrote:
> There are several places in dfp_helper.c that access the decimal number
> representations in struct PPC_DFP via HI_IDX and LO_IDX defines which are set
> at the top of dfp_helper.c according to the host endian.
>
> However we can instead switch to usin
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Wednesday, September 25, 2019 2:03 AM
>
> On Tue, 24 Sep 2019 02:19:15 +
> "Tian, Kevin" wrote:
>
> > > From: Tian, Kevin
> > > Sent: Friday, September 13, 2019 7:00 AM
> > >
> > > > From: Alex Williamson [mailto:alex.willia
On 9/24/19 8:35 AM, Mark Cave-Ayland wrote:
> Now that the parameters to both set_dfp64() and set_dfp128() are exactly the
> same, there is no need for an explicit if() statement to determine which
> function should be called based upon size. Instead we can simply use the
> preprocessor to generate
On 9/24/19 8:35 AM, Mark Cave-Ayland wrote:
> Since commit ef96e3ae96 "target/ppc: move FP and VMX registers into aligned
> vsr
> register array" FP registers are no longer stored consecutively in memory and
> so
> the current method of combining FP register pairs into DFP numbers is
> incorrect
This parameter has been deprecated since 2.12.0 and is eligible for
removal. Remove this parameter as it is actually completely ignored;
let's not give false hope.
Signed-off-by: John Snow
---
qemu-deprecated.texi | 20 +++-
qapi/block-core.json | 6 +-
blockdev.c
On 9/24/19 8:35 AM, Mark Cave-Ayland wrote:
> Switch over all accesses to the decimal numbers held in struct PPC_DFP from
> using HI_IDX and LO_IDX to using the VsrD() macro instead. Not only does this
> allow the compiler to ensure that the various dfp_* functions are being passed
> a ppc_vsr_t ra
On 9/24/19 8:35 AM, Mark Cave-Ayland wrote:
> The existing functions (now incorrectly) assume that the MSB and LSB of DFP
> numbers are stored as consecutive 64-bit words in memory. Instead of accessing
> the DFP numbers directly, introduce set_dfp{64,128}() helper functions to ease
> the switch to
On 9/24/19 8:35 AM, Mark Cave-Ayland wrote:
> Most of the DFP helper functions call decimal{64,128}FromNumber() just before
> returning in order to convert the decNumber stored in dfp.t64 back to a
> Decimal{64,128} to write back to the FP registers.
>
> Introduce new dfp_finalize_decimal{64,128}(
The slirp sub-module complains about not being able to find the glib
library on cross-compiles because it is using the default pkg-config
tool (which isn't installed in our cross-build docker images).
Preserve PKG_CONFIG in our host config and pass it down to slirp.
Signed-off-by: Alex Bennée
Rev
On Tue, Sep 24, 2019 at 11:03:38AM +0200, Christian Schoenebeck wrote:
> > Yes, the resulting mail would be correct, in the sense that it could be
> > applied just fine by git-am. But I think it would be uglier. IOW, I
> > consider the presence of the in-body From to be a clue that something
> > i
These were missed in the recent de-tangling so have been updated to be
more actuate. I've also built up ARM_TESTS in a manner similar to
AARCH64_TESTS for better consistency.
Signed-off-by: Alex Bennée
Reviewed-by: Peter Maydell
---
tests/tcg/Makefile.target | 7 +--
tests/tcg/aarc
From: John Snow
We don't have a debian8-mxe dockerfile anymore.
Fixes: 67bd36beda1ae
Signed-off-by: John Snow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190923181140.7235-2-js...@redhat.com>
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
1 file changed, 1 insert
From: Philippe Mathieu-Daudé
The WHPX build is broken since commit 12e9493df92 which removed the
"hw/boards.h" where MachineState is declared:
$ ./configure \
--enable-hax --enable-whpx
$ make x86_64-softmmu/all
[...]
CC x86_64-softmmu/target/i386/whpx-all.o
target/i386/wh
Richard Henderson writes:
> The memory_region_tb_read tracepoint is unreachable, since notdirty
> is supposed to apply only to writes. The memory_region_tb_write
> tracepoint is mis-named, because notdirty is not only used for TB
> invalidation. It is also used for e.g. VGA RAM updates and mi
On 24/09/2019 20:21, Richard Henderson wrote:
> On 9/24/19 8:35 AM, Mark Cave-Ayland wrote:
>> +static void get_dfp64(uint64_t *dst, uint64_t *dfp)
>> +{
>> +dst[0] = dfp[0];
>> +}
>> +
>> +static void get_dfp128(uint64_t *dst, uint64_t *dfp)
>> +{
>> +dst[0] = dfp[HI_IDX];
>> +dst[1]
On 9/24/19 3:09 PM, Vladimir Sementsov-Ogievskiy wrote:
> If we want append hint to errp, we must use ERRP_FUNCTION_BEGIN macro.
> Otherwise hint will not be appended in case of errp == &fatal_err
> (program will exit before error_append_hint() call). Fix such cases.
>
Copy-and-pasted, but if you
On 9/24/19 8:35 AM, Mark Cave-Ayland wrote:
> struct PPC_DFP {
> CPUPPCState *env;
> -uint64_t t64[2], a64[2], b64[2];
> +ppc_vsr_t vt, va, vb;
This I don't think is a good idea. It's not a vsr_t.
I think this step would be clearer with
union {
decimal64 d;
uint64_t i;
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
Message-Id: <20190920113329.16787-4-phi...@redhat.com>
---
.shippable.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.shippable.yml b/.shippable.yml
index bbc6f88510f..01b33bd034e 100644
--
From: John Snow
There isn't a debian.dockerfile anymore,
so perform some ghost-busting.
Signed-off-by: John Snow
Message-Id: <20190923181140.7235-4-js...@redhat.com>
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff
From: Philippe Mathieu-Daudé
To build WHPX (Windows Hypervisor) binaries, we need the WHPX
headers provided by the Windows SDK.
Add a script that fetches the required MSI/CAB files from the
latest SDK (currently 10.0.18362.1).
Headers are accessible under /opt/win10sdk/include.
Set the QEMU_CO
From: John Snow
debian-ports is listed as a partial image, so we cannot run tests against it.
Since it isn't used by any other testable image, remove it for now as it
is prone to bitrot.
Signed-off-by: John Snow
Message-Id: <20190923181140.7235-5-js...@redhat.com>
Signed-off-by: Alex Bennée
--
On 9/24/19 3:09 PM, Vladimir Sementsov-Ogievskiy wrote:
> If we want append hint to errp, we must use ERRP_FUNCTION_BEGIN macro.
> Otherwise hint will not be appended in case of errp == &fatal_err
> (program will exit before error_append_hint() call). Fix such cases.
>
> This commit (together with
From: John Snow
debian8 partial base is also not consumed by any image, so remove it.
For QEMU's development cycle, we only support debian9 (stretch) and
debian10 (buster).
Signed-off-by: John Snow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190923181140.7235-3-js...@redhat.com>
Signed-
On 24/09/2019 16:35, Mark Cave-Ayland wrote:
> Switch over all accesses to the decimal numbers held in struct PPC_DFP from
> using HI_IDX and LO_IDX to using the VsrD() macro instead. Not only does this
> allow the compiler to ensure that the various dfp_* functions are being passed
> a ppc_vsr_t r
From: John Snow
As part of the push to drop python2 support, replace any explicit python2
dependencies with python3 versions.
For centos, python2 still exists as an implicit dependency, but by adding
python3 we will be able to build even if the configure script begins to
require python 3.5+.
Te
From: John Snow
When it was based on debian8 which uses python-minimal, it needed this.
It no longer does.
Goodbye, python2.7.
Signed-off-by: John Snow
Message-Id: <20190918222546.11696-1-js...@redhat.com>
[AJB: fixed up commit message]
Signed-off-by: Alex Bennée
---
tests/docker/dockerfiles
Despite our attempts in 4d26c7fef4 to keep this going it still gets in
the way of "make docker-test-build" completing because of course we
can't build a modern QEMU with the image. Let's put the thing out of
it's misery and remove it.
People who really care about building on powerpc can still use
Now we have fixed the signal delivary bug we can remove this horrible
hack from the system.
Cc: Richard Henderson
Signed-off-by: Alex Bennée
---
v2
- drop un-needed cflags
---
tests/tcg/multiarch/Makefile.target | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/
From: John Snow
Oops; there's no argv here.
Signed-off-by: John Snow
Message-Id: <20190913193821.17756-1-js...@redhat.com>
Signed-off-by: Alex Bennée
Reviewed-by: Cleber Rosa
Tested-by: Cleber Rosa
---
tests/docker/docker.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
There was in the clean-up code caused by attempting to inspect images
which finished before we got there. Clean up the clean up code by:
- only track the one instance at a time
- use --filter for docker ps instead of doing it by hand
- just call docker rm -f to be done with it
- use uuid.u
It was pointed out we haven't documented the check-tcg part of the
build system. Attempt to rectify that now.
Signed-off-by: Alex Bennée
---
docs/devel/testing.rst | 62 ++
1 file changed, 62 insertions(+)
diff --git a/docs/devel/testing.rst b/docs/devel/
This adds two new tests that re-use the memory test to check basic
record replay functionality is still working. We have to define our
own runners rather than using the default pattern as we want to change
the test name but re-use the memory binary.
We declare the test binaries as PHONY as they do
On 9/24/19 3:08 PM, Vladimir Sementsov-Ogievskiy wrote:
> If we want append hint to errp, we must use ERRP_FUNCTION_BEGIN macro.
> Otherwise hint will not be appended in case of errp == &fatal_err
> (program will exit before error_append_hint() call). Fix such cases.
>
> This commit (together with
From: "Dr. David Alan Gilbert"
Various parts of the migration code do different things when they're
in postcopy mode; prior to this patch this has been 'postcopy-active'.
This patch extends 'in_postcopy' to include 'postcopy-paused' and
'postcopy-recover'.
In particular, when you set the max-pos
We were incorrectly using the 64-bit AIX ABI instead of the 32-bit
SYSV ABI for setting NIP for the signal handler.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
---
v2
- change to wording
---
linux-user/ppc/signal.c | 4 +++-
1 file changed, 3 inserti
From: Richard Henderson
Remove a redundant masking of ignore. Once that's gone it is
obvious that the system-mode inner test is redundant with the
outer test. Move the fpcr_exc_enable masking up and tidy.
No functional change.
Signed-off-by: Richard Henderson
Signed-off-by: Alex Bennée
Mess
From: Richard Henderson
Since we're converting the swcr to fpcr format for exceptions,
it's trivial to add FPCR_DNZ to the set of fpcr bits overriden.
No functional change.
Signed-off-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20190921043256.4575-5-richard.hender...@linaro.o
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